ADV7280AWBCPZ

10-Bit, 4× Oversampled SDTV Video Decoder with Deinterlacer ADV7280A Data Sheet FEATURES GENERAL DESCRIPTION Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit ADC, 4× oversampling per channel for CVBS, Y/C, and YPrPb modes Analog video input channels with on-chip antialiasing filter ADV7280A: up to 4 input channels ADV7280A-M: up to 8 input channels Video input support for CVBS (composite), S-Video (Y/C), and YPrPb (component) NTSC/PAL/SECAM autodetection Up to 1.47 V common-mode input range solution Excellent common-mode noise rejection capabilities 5-line adaptive 2D comb filter and CTI video enhancement Integrated AGC with adaptive peak white mode Fast switching capability Integrated I2P video output converter (deinterlacer) ACE Downdither (8-bit to 6-bit) Rovi copy protection detection MIPI CSI-2 output interface (ADV7280A-M) 8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, or field synchronization (ADV7280A) Full featured VBI data slicer with WST support Power-down mode available 2-wire, I2C-compatible serial interface Qualified for automotive applications −40°C to +105°C temperature grade 32-lead, 5 mm × 5 mm, RoHS compliant LFCSP The ADV7280A1 has the same pinout as and is software compatible with the ADV7280 with the exception of an updated IDENT code. The mobile industry processor interface (MIPI®) model of the ADV7280A (ADV7280A-M) has the same pinout and is software compatible with the ADV7280-M with the exception of an updated IDENT code. All features, functionality, and specifications are shared by the ADV7280A and the ADV7280A-M, unless otherwise noted. The ADV7280A is a versatile one-chip, multiformat video decoder that automatically detects standard analog baseband video signals and converts them into YCrCb 4:2:2 component video data streams. The analog input of the ADV7280A is designed for singleended input video signals. It features an input mux (4-channel on ADV7280A, 8-channel on ADV7280A-M) and a single 10-bit analog-to-digital converter (ADC). The standard definition processor (SDP) in the ADV7280A automatically detects PAL, NTSC and SECAM standards in the form of composite, S-Video (Y/C) and component. The analog video is converted into a 4:2:2 component video data stream that is output either via an 8-bit ITU-R BT.656 standard compatible interface (ADV7280A) or via a MIPI CSI-2 Tx (hereafter referred to as MIPI Tx) interface (ADV7280A-M). The ADV7280A also features a deinterlacer for interlaced to progressive (I2P) conversion. The ADV7280A is provided in a space-saving LFCSP surfacemount, RoHS compliant package. The ADV7280A is offered in an automotive grade rated over the −40°C to +105°C temperature range, as well as a −40°C to +85°C temperature range, making the device ideal for automotive, industrial, and consumer applications. APPLICATIONS Advanced driver assistance Automotive infotainment DVRs for video security Media players The ADV7280A must be configured in accordance with the I2C writes provided in the evaluation board script files available at www.analog.com/ADV7280A. 1 Protected by U.S. Patent 5,784,120. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7280A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Universal Power Supply (ADV7280A Only) .......................... 15 Applications ....................................................................................... 1 Crystal Oscillator Design .............................................................. 16 General Description ......................................................................... 1 Input Network ................................................................................. 17 Revision History ............................................................................... 2 Applications Information .............................................................. 18 Functional Block Diagrams ............................................................. 3 Input Configuration ................................................................... 18 Specifications..................................................................................... 4 Adaptive Contrast Enhancement (ACE) ................................. 18 Electrical Specifications ............................................................... 4 I2P Function ................................................................................ 18 Video Specifications ..................................................................... 5 ITU-R BT.656 Tx Configuration (ADV7280A Only) ........... 19 Analog Specifications ................................................................... 6 MIPI Tx Output (ADV7280A-M Only) .................................. 19 Clock and I C Timing Specifications ......................................... 6 I2C Port Description................................................................... 20 MIPI Tx Video Output and Timing Specifications (ADV7280A-M Only) .................................................................. 7 Register Maps .................................................................................. 21 Pixel Port Timing Specifications (ADV7280A Only).............. 9 Analog Interface Inputs ............................................................. 23 Absolute Maximum Ratings.......................................................... 10 Power Supply Decoupling ......................................................... 23 Thermal Resistance .................................................................... 10 VREFN and VREFP Pins .......................................................... 23 ESD Caution ................................................................................ 10 Digital Outputs ........................................................................... 23 Pin Configurations and Function Descriptions ......................... 11 Exposed Metal Pad ..................................................................... 23 Theory of Operation ...................................................................... 13 Digital Inputs .............................................................................. 23 Analog Front End ....................................................................... 13 MIPI Tx Outputs (ADV7280A-M Only) ................................ 23 Standard Definition Processor (SDP) ...................................... 13 Typical Circuit Connections ......................................................... 24 Power Supply Sequencing .............................................................. 15 Outline Dimensions ....................................................................... 26 Optimal Power-Up Sequence.................................................... 15 Ordering Guide .......................................................................... 26 Simplified Power-Up Sequence ................................................ 15 Automotive Products ................................................................. 26 2 PCB Layout Recommendations.................................................... 23 Power-Down Sequence .............................................................. 15 REVISION HISTORY 5/2018—Rev. 0 to Rev. A Changes to General Description Section ...................................... 1 9/2017—Revision 0: Initial Version Rev. A | Page 2 of 26 Data Sheet ADV7280A FUNCTIONAL BLOCK DIAGRAMS CLOCK PROCESSING BLOCK ADLLT PROCESSING 10-BIT ADC DIGITAL PROCESSING BLOCK AIN3 AIN4 AA FILTER AA FILTER VS/FIELD/SFL 2D COMB + SHA VBI SLICER ADC – COLOR DEMOD AA FILTER HS I2P ACE DOWN DITHER I2C/CONTROL REFERENCE 8-BIT PIXEL DATA P7 TO P0 INTRQ 16162-001 ANALOG VIDEO INPUTS MUX BLOCK AIN1 AIN2 AA FILTER LLC FIFO PLL XTALN OUTPUT BLOCK ADV7280A XTALP SCLK SDATA ALSB RESET PWRDWN Figure 1. ADV7280A Functional Block Diagram ADV7280A-M CLKP CLOCK PROCESSING BLOCK XTALP PLL ADLLT PROCESSING 10-BIT ADC DIGITAL PROCESSING BLOCK MIPI Tx XTALN D0P AA FILTER 2D COMB + SHA ADC – VBI SLICER COLOR DEMOD AA FILTER I2P ACE DOWN DITHER I2C/CONTROL REFERENCE SCLK SDATA ALSB RESET PWRDWN Figure 2. ADV7280A-M Functional Block Diagram Rev. A | Page 3 of 26 GPO0 GPO1 GPO2 INTRQ 16162-002 AA FILTER OUTPUT BLOCK AA FILTER FIFO D0N MUX BLOCK ANALOG VIDEO INPUTS AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 CLKN ADV7280A Data Sheet SPECIFICATIONS ELECTRICAL SPECIFICATIONS PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at the operating temperature range, unless otherwise noted. MVDD only applies to the ADV7280A-M. Table 1. Parameter STATIC PERFORMANCE ADC Resolution Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Symbol Test Conditions/Comments N INL DNL CVBS mode CVBS mode VIH Input Low Voltage VIL Input Leakage Current IIN Input Capacitance CRYSTAL INPUT Input High Voltage Input Low Voltage DIGITAL OUTPUTS Output High Voltage CIN Output Low Voltage VOL High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 1, 2, 3 Digital Input/Output (I/O) Power Supply DVDDIO = 3.3 V DVDDIO = 1.8 V, ADV7280A only DVDDIO = 3.3 V DVDDIO = 1.8 V, ADV7280A only RESET pin SDATA, SCLK pins PWRDWN, ALSB pins Min Typ −10 −10 −10 1.2 VOH DVDDIO = 3.3 V, ISOURCE = 0.4 mA DVDDIO = 1.8 V, ISOURCE = 0.4 mA, ADV7280A only DVDDIO = 3.3 V, ISINK = 3.2 mA DVDDIO = 1.8 V, ISINK = 1.6 mA, ADV7280A only 2.4 1.4 PLL Supply Current MIPI Tx Supply Current Analog Supply Current Single-Ended CVBS Input Y/C Input YPrPb Input Digital Supply Current Single-Ended CVBS Input Y/C Input YPrPb Input IPVDD IMVDD IAVDD Bits LSB LSB 0.8 0.4 +10 +15 +50 10 V V V V µA µA µA pF 0.4 V V V V ILEAK COUT PVDD AVDD DVDD MVDD IDVDDIO 10 2 1.2 XTALN pin XTALN pin PLL Power Supply Analog Power Supply Digital Power Supply MIPI Transmitter (Tx) Power Supply Digital I/O Supply Current Unit 2 ±0.6 VIH VIL DVDDIO Max 0.4 0.2 V V 10 20 µA pF ADV7280A-M 2.97 3.3 3.63 V ADV7280A 1.62 1.71 1.71 1.71 1.71 3.3 1.8 1.8 1.8 1.8 1.5 5 12 14 3.63 1.89 1.89 1.89 1.89 V V V V V mA mA mA mA ADV7280A-M only ADV7280A-M ADV7280A ADV7280A-M only 47 60 75 mA mA mA 70 70 70 mA mA mA IDVDD Rev. A | Page 4 of 26 Data Sheet Parameter POWER-DOWN CURRENTS1 Digital I/O Supply PLL Supply Analog Supply Digital Supply MIPI Tx Supply Total Power Dissipation in Power-Down Mode CRYSTAL OSCILLATOR1 Transconductance ADV7280A Symbol Test Conditions/Comments IDVDDIO_PD DVDDIO = 3.3 V, ADV7280A-M DVDDIO = 3.3 V, ADV7280A IPVDD_PD IAVDD_PD IDVDD_PD IMVDD_PD Min ADV7280A-M only gM Typ Max Unit 73 84 46 0.2 420 4.5 1 µA µA µA µA µA µA mW 30 mA/V Guaranteed by characterization. Typical current consumption values are measured with nominal voltage supply levels and a Society of Motion Picture and Television Engineers (SMPTE) bar test pattern. 3 All specifications apply when the I2P core is activated, unless otherwise stated. 1 2 VIDEO SPECIFICATIONS PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. MVDD only applies to the ADV7280A-M. Table 2. Parameter NONLINEAR SPECIFICATIONS 1 Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS Signal-to-Noise Ratio, Unweighted Analog Front End (AFE) Crosstalk Common-Mode Rejection Ratio 2 LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range Subcarrier Lock Range Color Lock-In Time Synchronization Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed 3 Fast Switch Speed 4 LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy Symbol Test Conditions/Comments Min DP DG LNL CVBS input, modulated five-step CVBS input, modulated five-step CVBS input, five-step 0.9 0.5 2.0 Degrees % % SNR Luma ramp Luma flat field 57.1 58 60 73 dB dB dB dB CMRR Typ −5 40 fSC Max +5 70 Unit 2 100 100 % Hz kHz Lines % % Fields Lines ms 1 1 % % ±1.3 60 20 5 200 200 CVBS, 1 V input These specifications apply for all CVBS input types (NTSC, PAL, and SECAM). The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Network section). The CMRR measurement was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz. 3 Autodetection switch speed is the time required for the ADV7280/ADV7280-M to detect which video format is present at its input, for example, PAL I or NTSC M. 4 Fast switch speed is the time required for the ADV7280/ADV7280-M to switch from one analog input to another, for example, switching from AIN1 to AIN2. 1 2 Rev. A | Page 5 of 26 ADV7280A Data Sheet ANALOG SPECIFICATIONS PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. MVDD only applies to the ADV7280A-M. Table 3. Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current Test Conditions/Comments Min Typ Max 0.1 10 0.4 0.4 10 10 Clamps switched off Unit µF MΩ mA mA µA µA CLOCK AND I2C TIMING SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. MVDD only applies to the ADV7280A-M. Table 4. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDATA Setup Time SCLK and SDATA Rise Times SCLK and SDATA Fall Times Setup Time (Stop Condition) RESET INPUT RESET Pulse Width Symbol Min Typ Max Unit ±50 MHz ppm 28.63636 400 t1 t2 t3 t4 t5 t6 t7 t8 kHz µs µs µs µs ns ns ns µs 0.6 1.3 0.6 0.6 100 300 300 0.6 5 ms t5 t3 t3 SDATA t2 t4 t7 Figure 3. I C Timing Diagram 2 Rev. A | Page 6 of 26 t8 16162-003 t1 t6 SCLK Data Sheet ADV7280A MIPI Tx VIDEO OUTPUT AND TIMING SPECIFICATIONS (ADV7280A-M ONLY) PVDD, AVDD, DVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. The ADV7282A MIPI Tx conforms to the MIPI D-PHY Version 1.00.00 specification by characterization. The MIPI Tx clock lane of the ADV7280A-M remains in high speed mode even when the data lane enters low power (LP) mode. For this reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements were performed with the ADV7280A-M operating in progressive mode and with a nominal 432 Mbps output data rate. Specifications guaranteed by characterization. Table 5. Parameter UNIT INTERVAL Interlaced Output Progressive Output DATA LANE LP MIPI Tx DC SPECIFICATIONS 1 Thevenin Output High Level Thevenin Output Low Level DATA LANE LP MIPI Tx AC SPECIFICATIONS1 Rise Time, 15% to 85% Fall Time, 85% to 15% Rise Time, 30% to 85% Data Lane LP Slew Rate vs. Load Capacitance (CLOAD) Maximum Slew Rate over Entire Vertical Edge Region Symbol UI Minimum Slew Rate 400 mV ≤ VOUT ≤ 930 mV 400 mV ≤ VOUT ≤ 700 mV 700 mV ≤ VOUT ≤ 930 mV Min Typ Max 4.63 2.31 VOH VOL Minimum Slew Rate 400 mV ≤ VOUT ≤ 930 mV 400 mV ≤ VOUT ≤ 700 mV 700 mV ≤ VOUT ≤ 930 mV Pulse Width of LP Exclusive OR Clock Period of LP Exclusive-OR Clock CLOCK LANE LP MIPI Tx DC SPECIFICATIONS1 Thevenin Output High Level Thevenin Output Low Level CLOCK LANE LP MIPI Tx AC SPECIFICATIONS1 Rise Time, 15% to 85% Fall Time, 85% to 15% Clock Lane LP Slew Rate Maximum Slew Rate over Entire Vertical Edge Region Test Conditions/Comments 1.1 −50 ns ns 1.3 +50 V mV 25 25 35 ns ns ns Rising edge 150 mV/ns Falling edge 150 mV/ns Falling edge Rising edge Rising edge First clock pulse after stop state or last pulse before stop state All other clock pulses VOH VOL 1.2 0 Unit 30 30 >0 40 mV/ns mV/ns mV/ns ns 20 90 ns ns 1.1 −50 1.3 +50 V mV 25 25 ns ns Rising edge 150 mV/ns Falling edge 150 mV/ns Falling edge Rising edge Rising edge Rev. A | Page 7 of 26 30 30 >0 1.2 0 mV/ns mV/ns mV/ns ADV7280A Parameter DATA LANE HIGH SPEED MIPI Tx SIGNALING REQUIREMENTS LP to High Speed Transition Stage Data Sheet Symbol Test Conditions/Comments See Figure 4 Min t9 Time that the D0P pin is at VOL and the D0N pin is at VOH Time that the D0P and D0N pins are at VOL t10 plus the high speed zero period 50 t10 t11 High Speed Differential Voltage Swing Differential Voltage Mismatch Single-Ended Output High Voltages Static Common-Mode Voltage Level Static Common-Mode Voltage Mismatch Dynamic Common Level Variations 50 MHz to 450 MHz Above 450 MHz Rise Time, 20% to 80% Fall Time, 80% to 20% High Speed to LP Transition Stage |V1| t12 t13 t14 t15 CLOCK LANE HIGH SPEED MIPI Tx SIGNALING REQUIREMENTS LP to High Speed Transition Stage 2 High Speed Differential Voltage Swing Differential Voltage Mismatch Single-Ended Output High Voltages Static Common-Mode Voltage Level Static Common-Mode Voltage Mismatch Dynamic Common Level Variations 50 MHz to 450 MHz Above 450 MHz Rise Time, 20% to 80% Fall Time, 80% to 20% HIGH SPEED MIPI Tx CLOCK TO DATA LANE TIMING REQUIREMENTS Data to Clock Skew 1 2 t9 Time that the ADV7280A-M drives the flipped last data bit after sending the last payload data bit of a high speed transmission burst Post end of transmission rise time (30% to 85%) Time from start of t12 to start of low power state following a high speed transmission burst Time that a low power state is transmitted after a high speed transmission burst See Figure 4 Time that the CLKP pin is at VOL and the CLKN pin is at VOH Time that the CLKP and CLKN pins are at VOL Clock high speed zero period |V2| Typ Unit ns 40 + (4 × UI) 85 + (6 × UI) 145 + (10 × UI) ns ns 140 200 150 200 0.15 0.15 60 + (4 × UI) 270 10 360 250 5 mV p-p mV mV mV mV 25 15 0.3 × UI 0.3 × UI mV mV ns ns ns 35 ns 105 + (12 × UI) ns 100 ns 50 ns 38 95 ns 270 10 360 250 5 ns mV p-p mV mV mV mV 0.15 0.15 25 15 0.3 × UI 0.3 × UI mV mV ns ns 0.35 × UI 0.65 × UI ns 300 140 500 200 150 200 These measurements were performed with CLOAD = 50 pF. The clock lane remains in high speed mode throughout normal operation. These results apply only to the ADV7280-M during startup. Rev. A | Page 8 of 26 Max Data Sheet ADV7280A |V2| CLKP/CLKN D0P/D0N t10 t9 t11 VOH |V1| VOL t13 TRANSMIT FIRST DATA BIT LOW POWER TO HIGH SPEED TRANSITION HIGH SPEED ZERO START OF TRANSMISSION SEQUENCE HIGH SPEED DATA TRANSMISSION t12 t15 HIGH SPEED TRAIL HIGH SPEED TO LOW POWER TRANSITION 16162-005 t14 Figure 4. ADV7280A-M Output Timing Diagram (Conforms with MIPI CSI-2 Specification) PIXEL PORT TIMING SPECIFICATIONS (ADV7280A ONLY) AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. Table 6. Parameter CLOCK OUTPUTS LLC Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transitional Time Symbol Test Conditions/Comments Min t9:t10 Typ 45:55 t11 Negative clock edge to start of valid data (tSETUP = t10 − t11) End of valid data to negative clock edge (tHOLD = t9 − t12) t12 t10 t9 OUTPUT LLC t11 16162-004 t12 OUTPUTS P0 TO P7, HS, VS/FIELD/SFL Figure 5. ADV7280A Pixel Port and Control Output Timing Diagram Rev. A | Page 9 of 26 Max Unit 55:45 % duty cycle 3.8 ns 6.9 ns ADV7280A Data Sheet ABSOLUTE MAXIMUM RATINGS Table 7. Parameter1 AVDD to GND DVDD to GND PVDD to GND MVDD to GND2 DVDDIO to GND PVDD to DVDD MVDD to DVDD2 AVDD to DVDD Digital Inputs Voltage Digital Outputs Voltage Analog Inputs to Ground Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 2.2 V 2.2 V 2.2 V 2.2 V 4V −0.9 V to +0.9 V −0.9 V to +0.9 V −0.9 V to +0.9 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to AVDD + 0.3 V 125°C −65°C to +150°C JEDEC J-STD-020 THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure as per JEDEC JESD51. ΨJT is the junction to top thermal characterization parameter measured on a standard test board, as per JEDEC JESD51, allowing the heat generated in the ADV7280A die to flow normally along preferred thermal conduction paths that more closely represent the thermal flows in a typical application board. Table 8. Thermal Resistance Package CP-32-121 1 The absolute maximum ratings assume that the DGND pins and the exposed pad of the ADV7280A are connected together to a common ground plane (GND). This is part of the recommended layout scheme. See the PCB Layout Recommendations section for more information. The absolute maximum ratings are stated in relation to this common ground plane. 2 MVDD only applies to the ADV7280A-M. 1 θJA 39.6 ΨJT 0.86 Unit °C/W JEDEC JESD51 2s2p 4-layer PCB with two signal layers and two buried solid ground planes (GND), and with via nine thermal vias connecting the exposed pad to the ground plane (GND). ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 10 of 26 Data Sheet ADV7280A 32 31 30 29 28 27 26 25 LLC PWRDWN HS VS/FIELD/SFL SCLK SDATA ALSB RESET PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADV7280A TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 INTRQ AIN4 AIN3 AVDD VREFN VREFP AIN2 AIN1 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED, TOGETHER WITH THE DGND PINS, TO A COMMON GROUND PLANE (GND). 16162-006 P3 9 P2 10 P1 11 P0 12 DVDD 13 XTALP 14 XTALN 15 PVDD 16 DGND DVDDIO DVDD DGND P7 P6 P5 P4 Figure 6. ADV7280A Pin Configuration Table 9. Pin Function Descriptions, ADV7280A Pin No. 1, 4 2 3, 13 5 to 12 14 Mnemonic DGND DVDDIO DVDD P7 to P0 XTALP Type Ground Power Power Output Output 15 XTALN Input 16 17, 18, 22, 23 19 20 21 24 PVDD AIN1 to AIN4 VREFP VREFN AVDD INTRQ Power Input Output Output Power Output 25 RESET Input 26 ALSB Input 27 28 29 SDATA SCLK VS/FIELD/SFL Input/output Input Output 30 31 32 HS PWRDWN LLC Output Input Output EPAD (EP) Description Ground for Digital Supply. Digital I/O Power Supply (1.8 V or 3.3 V). Digital Power Supply (1.8 V). Video Pixel Output Ports. Output Pin for the Crystal Oscillator Amplifier. Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280A. The crystal used with the ADV7280A must be a fundamental mode crystal. Input Pin for the Crystal Oscillator Amplifier. The crystal used with the ADV7280A must be a fundamental mode crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280A, the output of the oscillator is fed into the XTALN pin. PLL Power Supply (1.8 V). Analog Video Input Channels. Positive Internal Voltage Reference Output. Negative Internal Voltage Reference Output. Analog Power Supply (1.8 V). Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video. System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to reset the ADV7280A circuitry. Address Least Significant Bit. This pin selects the I2C write address for the ADV7280A. When ALSB is set to Logic 0, the write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42. I2C Port Serial Data Input/Output. I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier Frequency Lock. When configured for the SFL function, this pin provides a serial output stream that can be used to lock the subcarrier frequency when the ADV7280A decoder is connected to any Analog Devices, Inc., digital video encoder. Horizontal Synchronization Output Signal. Power-Down. A logic low on this pin places the ADV7280A in power-down mode. Line Locked Clock for Output Pixel Data. The clock output is nominally 27 MHz, but it increases or decreases according to the video line length. Exposed Ground Pad. The exposed pad must be connected, together with the DGND pins, to a common ground plane (GND). Rev. A | Page 11 of 26 Data Sheet 32 31 30 29 28 27 26 25 PWRDWN SCLK SDATA ALSB RESET AIN8 AIN7 AIN6 ADV7280A 1 2 3 4 5 6 7 8 ADV7280A-M TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 AIN5 AIN4 AIN3 AVDD VREFN VREFP AIN2 AIN1 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED, TOGETHER WITH THE DGND PINS, TO A COMMON GROUND PLANE (GND). 16162-007 D0P D0N CLKP CLKN MVDD XTALP XTALN PVDD 9 10 11 12 13 14 15 16 DGND DVDDIO DVDD DGND INTRQ GPO2 GPO1 GPO0 Figure 7. ADV7280A-M Pin Configuration Table 10. Pin Function Descriptions, ADV7280A-M Pin No. 1, 4 2 3 5 Mnemonic DGND DVDDIO DVDD INTRQ Type Ground Power Power Output 6 to 8 Output 9 10 11 12 13 14 GPO2 to GPO0 D0P D0N CLKP CLKN MVDD XTALP 15 XTALN Input 16 17, 18, 22, 23, 24, 25, 26, 27 19 20 21 28 PVDD AIN1 to AIN8 Power Input VREFP VREFN AVDD RESET Output Output Power Input 29 ALSB Input 30 31 32 SDATA SCLK PWRDWN EPAD (EP) Input/output Input Input Output Output Output Output Power Output Description Ground for Digital Supply. Digital I/O Power Supply (3.3 V). Digital Power Supply (1.8 V). Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video. General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices. Positive MIPI Differential Data Output. Negative MIPI Differential Data Output. Positive MIPI Differential Clock Output. Negative MIPI Differential Clock Output. MIPI Digital Power Supply (1.8 V). Output Pin for the Crystal Oscillator Amplifier. Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280A-M. The crystal used with the ADV7280A-M must be a fundamental mode crystal. Input Pin for the Crystal Oscillator Amplifier. The crystal used with the ADV7280A-M must be a fundamental mode crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280A-M, the output of the oscillator is fed into the XTALN pin. PLL Power Supply (1.8 V). Analog Video Input Channels. Positive Internal Voltage Reference Output. Negative Internal Voltage Reference Output. Analog Power Supply (1.8 V). System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to reset the ADV7280A-M circuitry. Address Least Significant Bit. This pin selects the I2C write address for the ADV7280A-M. When ALSB is set to Logic 0, the write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42. I2C Port Serial Data Input/Output. I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. Power-Down. A logic low on this pin places the ADV7280A-M in power-down mode. Exposed Ground Pad. The exposed pad must be connected, together with the DGND pins, to a common ground plane (GND). Rev. A | Page 12 of 26 Data Sheet ADV7280A THEORY OF OPERATION The ADV7280A is a versatile one-chip, multiformat video decoder that automatically detects standard analog baseband video signals and converts them into a YCrCb 4:2:2 component video data stream. The ADV7280A supports video signals compatible with worldwide NTSC, PAL and SECAM standards. that are determined by the video input format to be processed. These clock rates ensure 4× oversampling per channel for CVBS, Y/C, and YPrPb modes. The analog front ends of the ADV7280A are designed for single-ended input video signals. They feature an input mux (4-channel for ADV7280A, 8-channel for ADV7280A-M) and a single 10-bit ADC. The analog video inputs accept single-ended video signals as well as S-Video (Y/C) and YPbPr video signals, supporting a wide range of automotive and consumer video sources. Input Format CVBS S-Video (Y/C)2 YPrPb2 The incoming analog video is converted into a digital 8-bit YCrCb 4:2:2 video stream that is output either via a digital 8-bit ITU-R BT.656 video stream (ADV7280A) or via a MIPI CSI-2 interface (ADV7280A-M). External horizontal sync (HS), vertical sync (VS), and field sync signals are available for the ITU-R BT.656 interface to provide timing references for LCD controllers and other video ASICs. STANDARD DEFINITION PROCESSOR (SDP) Table 11. ADC Clock Rates 1 2 ADC Clock Rate (MHz)1 57.27 114 172 Oversampling Rate per Channel 4× 4× 4× Based on a 28.63636 MHz clock input to the ADV7280A. Configuration writes are required for the different S-Video (Y/C) and YPrPb modes. The SDP in the ADV7280A is capable of decoding a large selection of baseband video signals in composite (both single-ended and differential), S-Video (Y/C), and component formats. The video standards supported by the video processor include • PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N, PAL Nc, PAL 60 NTSC J, NTSC M, NTSC 4.43 SECAM B, SECAM D, SECAM G, SECAM K, SECAM L The ADV7280A features an advanced I2P function to convert interlaced input video to a progressive video output with no requirement for external memory. The I2P conversion uses edge adaptive technology to minimize video defects on low angle lines. • • The ADV7280A also offers a downdither mode, adaptive contrast enhancement (ACE), and general-purpose outputs (ADV7280A-M only). The ADV7280A has a five-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available in the ADV7280A. The ADV7280A is programmed via a 2-wire, serial bidirectional port (I2C compatible) and can communicate with other devices via a hardware interrupt pin, INTRQ. The ADV7280A is fabricated in a low power 1.8 V CMOS process and are provided in a space-saving LFCSP surface-mount, RoHS compliant package. The ADV7280A is available in an automotive grade rated over the −40°C to +105°C temperature range, as well as a −40°C to +85°C temperature range, making them ideal for automotive, industrial, and consumer applications. ANALOG FRONT END The AFE of the ADV7280A is composed of an input mux, a set of four antialiasing filters, and a single 10-bit ADC. The input mux (4-channel for ADV7280A, 8-channel for ADV7280A-M) enables multiple composite video signals to be applied to the SDP and is software controlled. The external resistor divider is required before each analog input channel to ensure that the input signal is kept within the range of the ADC. Current and voltage clamps in the circuit ensure that the video signal remains within the range on the ADC. The single 10-bit ADC digitizes the analog video before it is applied to the SDP. Table 11 shows the three ADC clocking rates The SDP in the ADV7280A can automatically detect the video standard and process it accordingly. The ADV7280A implements a patented Adaptive Digital Line Length Tracking (ADLLT™) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7280A to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs, VCD players, and camcorders. The ADV7280A contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The ADV7280A features an automatic gain control (AGC) algorithm to ensure that the optimum luma gain is selected as the input video varies in brightness. ACE is an algorithm that automatically varies the contrast level applied across an image to enhance the picture detail visible. This automatic variation enables the contrast in the dark areas of an image to be increased without saturating the bright areas, which is particularly useful in automotive applications where it can be important to be able to clearly discern objects in shaded areas. Downdithering from eight bits to six bits enables ease of design for standard LCD panels. Rev. A | Page 13 of 26 ADV7280A Data Sheet The SDP can handle a variety of vertical blanking interval (VBI) data services, such as closed captioning (CCAP), wide screen signaling (WSS), copy generation management system (CGMS), and teletext data slicing for world standard teletext (WST). Data is transmitted via the 8-bit video output port as ancillary data packets (ANC). The ADV7280A is fully Rovi™ (formerly Macrovision® and now rebranded as TiVo upon acquisition of the same) compliant; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The SDP is fully robust to all Rovi signal inputs. Rev. A | Page 14 of 26 Data Sheet ADV7280A POWER SUPPLY SEQUENCING OPTIMAL POWER-UP SEQUENCE asserted, wait a further 5 ms before initiating I2C communication with the ADV7280A. The optimal power-up sequence for the ADV7280A is guaranteed by production testing. The optimal power-up sequence for the ADV7280A is to first power up the 3.3 V DVDDIO supply, followed by the 1.8 V supplies: DVDD, PVDD, AVDD, and MVDD (for the ADV7280A-M). While the supplies are being established, take care to ensure that a lower rated supply does not go above a higher rated supply level. During power-up, all supplies must adhere to the specifications listed in the Absolute Maximum Ratings section. When powering up the ADV7280A, follow these steps. During power-up, all supplies must adhere to the specifications listed in the Absolute Maximum Ratings section. The ADV7280A supplies can be deasserted simultaneously as long as DVDDIO does not go below a lower rated supply. 5. 6. Assert the PWRDWN and RESET pins (pull the pins low). Power up the DVDDIO supply. After DVDDIO is fully asserted, power up the 1.8 V supplies. After the 1.8 V supplies are fully asserted, pull the PWRDWN pin high. Wait 5 ms and then pull the RESET pin high. After all power supplies and the PWRDWN and RESET pins are powered up and stable, wait an additional 5 ms before initiating I2C communication with the ADV7280A. SIMPLIFIED POWER-UP SEQUENCE UNIVERSAL POWER SUPPLY (ADV7280A ONLY) The ADV7280A-M model requires a DVDDIO supply at a nominal value of 3.3 V. The ADV7280A, however, can operate with a DVDDIO supply at a nominal value of 1.8 V. Therefore, it is possible to power up all the supplies for the ADV7280A (DVDD, PVDD, AVDD, and DVDDIO) to 1.8 V. When DVDDIO is at a nominal value of 1.8 V, power up the ADV7280A as follows: 1. The simplified power-up sequence is guaranteed by characterization. Alternatively, the ADV7280A can be powered up by asserting all supplies and the PWRDWN pin simultaneously. During this operation, the RESET pin must remain low. After the supplies and PWRDWN are fully asserted, wait for at least 5 ms before bringing the RESET pin high. After the RESET pin is fully VOLTAGE 3.3V 1.8V 3.3V SUPPLY 2. 3. Follow the power-up sequence described in the Optimal Power-Up Sequence section, but power up the DVDDIO supply to 1.8 V instead of 3.3 V. Also, power up the PWRDWN and RESET pins to 1.8 V instead of 3.3 V. Set the drive strengths of the digital outputs of the ADV7280A to their maximum setting. Connect any pull-up resistors connected to pins on the ADV7280A (such as the SCLK and SDATA pins) to 1.8 V instead of 3.3 V. PWRDWN PIN 1.8V SUPPLIES PWRDWN PIN POWER-UP 3.3V SUPPLY POWER-UP RESET PIN 1.8V SUPPLIES POWER-UP RESET PIN POWER-UP 5ms RESET OPERATION Figure 8. Optimal Power-Up Sequence Rev. A | Page 15 of 26 5ms WAIT TIME 16162-008 1. 2. 3. 4. POWER-DOWN SEQUENCE ADV7280A Data Sheet CRYSTAL OSCILLATOR DESIGN The ADV7280A needs a stable and accurate clock source to guarantee their operation. This clock is typically provided by a crystal resonator (XTAL) but can also be provided by a clock oscillator. The required circuitry for an XTAL is illustrated in Figure 16. A damping resistor (RDAMP) is required on the output of the ADV7280A XTAL amplifier (XTALP). The purpose of this damping resistor is to limit the current flowing through the XTAL and to limit the voltage across the XTAL amplifier. To define the appropriate value of the damping resistor RDAMP (see the Typical Circuit Connections section), consult the accompanying calculator tool (visit the design resources section at www.analog.com/ADV7280A to download). The other components in the XTAL circuit must be chosen carefully; for example, incorrectly selected load capacitors may result in an offset to the crystal oscillation frequency. For more information on such considerations, see the AN-1260 Application Note, Crystal Design Considerations for Video Decoders, HDMI Receivers, and Transceivers. After the XTAL circuit is defined, it is recommended to consult with the XTAL vendor to ensure that the design operates with sufficient margin across all conditions. The evaluation of the ADV7280A was completed using an XTAL with typical characteristics (see Table 12). Table 12. Reference XTAL Characteristics Characteristic Package Nominal Frequency Mode of Oscillation Frequency Calibration (at 25°C) Frequency Temperature Stability Tolerance Operating Temperature Range Maximum Equivalent Series Resistance Load Capacitance Drive Level Shunt Capacitance (Maximum) Aging per Year Value 3.2 × 2.5 × 0.8 28.63636 Fundamental ±20 ±50 Unit mm MHz ppm ppm −40 to +125 25 °C Ω 12 200 5 ±3 pF µW pF ppm The values in Table 12 are provided for reference only. It is recommended to characterize the operation of the XTAL circuit thoroughly across the operating temperature range of the application, in conjunction with the XTAL vendor, prior to releasing any new design. Rev. A | Page 16 of 26 Data Sheet ADV7280A INPUT NETWORK An input network (external resistor and capacitor circuit) is required on the AINx input pins of the decoder. Figure 9 shows the input network to use on each AINx input pin of the ADV7280A when any of the following video input formats is used: Single-ended CVBS S-Video (Y/C) YPrPb INPUT CONNECTOR VIDEO INPUT FROM SOURCE EXT ESD 24Ω 100nF AIN1 OF ADV7280A 51Ω Figure 9. Input Network 16162-009 • • • The 24 Ω and 51 Ω resistors supply the 75 Ω end termination required for the analog video input. These resistors also create a resistor divider with a gain of 0.68. The resistor divider attenuates the amplitude of the input analog video and scales the input to the ADC range of the ADV7280A. This resistor divider allows an input range to the ADV7280A of up to 1.47 V p-p. Amplifiers within the ADC restore the amplitude of the input signal so that SNR performance is maintained. The 100 nF ac coupling capacitor removes the dc bias of the analog input video before it is fed into the AINx pin of the ADV7280A. The clamping circuitry within the ADV7280A restores the dc bias of the input signal to the optimal level before it is fed into the ADC of the ADV7280A. Rev. A | Page 17 of 26 ADV7280A Data Sheet APPLICATIONS INFORMATION INPUT CONFIGURATION The input format of the ADV7280A is specified using the INSEL[4:0] bits (see Table 13). These bits also configure the SDP core to process CVBS, S-Video (Y/C), or component (YPrPb) format. The INSEL[4:0] bits are located in the user sub map of the register space at Address 0x00, Bits[4:0]. For more information about the registers, see the Register Maps section. The INSEL[4:0] bits specify predefined analog input routing schemes, eliminating the need for manual mux programming and allowing the user to route the various video signal types to the decoder. For example, if the CVBS input is selected, the remaining channels are powered down. ADAPTIVE CONTRAST ENHANCEMENT (ACE) The ADV7280A can increase the contrast of an image depending on the content of the picture, allowing bright areas to be made brighter and dark areas to be made darker. The optional ACE feature enables the contrast within dark areas to be increased without significantly affecting the bright areas. The ACE feature is particularly useful in automotive applications, where it can be important to discern objects in shaded areas. The ACE function is disabled by default. To enable the ACE function, execute the register writes shown in Table 14. To disable the ACE function, execute the register writes shown in Table 15. I2P FUNCTION The advanced I2P function allows the ADV7280A to convert an interlaced video input into a progressive video output. This function is performed without the need for external memory. The ADV7280A uses edge adaptive technology to minimize video defects on low angle lines. The I2P function is disabled by default. To enable the I2P function, use the recommended scripts from Analog Devices, Inc., available at www.analog.com/ADV7280A. Table 13. Input Format Specified by the INSEL[4:0] Bits INSEL[4:0] Bit Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 to 11111 Video Format CVBS CVBS CVBS CVBS CVBS CVBS CVBS CVBS S-Video (Y/C) S-Video (Y/C) S-Video (Y/C) S-Video (Y/C) YPrPb YPrPb Reserved Analog Inputs ADV7280A ADV7280A-M CVBS input on AIN1 CVBS input on AIN1 CVBS input on AIN2 CVBS input on AIN2 CVBS input on AIN3 CVBS input on AIN3 CVBS input on AIN4 CVBS input on AIN4 Reserved CVBS input on AIN5 Reserved CVBS input on AIN6 Reserved CVBS input on AIN7 Reserved CVBS input on AIN8 Y input on AIN1; C input on AIN2 Y input on AIN1; C input on AIN2 Y input on AIN3; C input on AIN4 Y input on AIN3; C input on AIN4 Reserved Y input on AIN5; C input on AIN6 Reserved Y input on AIN7; C input on AIN8 Y input on AIN1; Pb input on AIN2; Pr input on AIN3 Y input on AIN1; Pb input on AIN2; Pr input on AIN3 Reserved Y input on AIN4; Pb input on AIN5; Pr input on AIN6 Reserved Reserved Table 14. Register Writes to Enable the ACE Function Register Map User Sub Map (0x40 or 0x42) User Sub Map 2 (0x40 or 0x42) User Sub Map 2 (0x40 or 0x42) Register Address 0x0E 0x80 0x0E Register Write 0x40 0x80 0x00 Description Enter User Sub Map 2 Enable ACE Reenter user sub map Register Write 0x40 0x00 0x00 Description Enter User Sub Map 2 Disable ACE Reenter user sub map Table 15. Register Writes to Disable the ACE Function Register Map User Sub Map (0x40 or 0x42) User Sub Map 2 (0x40 or 0x42) User Sub Map 2 (0x40 or 0x42) Register Address 0x0E 0x80 0x0E Rev. A | Page 18 of 26 Data Sheet ADV7280A ITU-R BT.656 Tx CONFIGURATION (ADV7280A ONLY) MIPI Tx OUTPUT (ADV7280A-M ONLY) The decoder in the ADV7280A-M outputs an ITU-R BT.656 data stream. The ITU-R BT.656 data stream is connected into a CSI-2 Tx module. Data from the CSI-2 Tx module is fed into a D-PHY physical layer and output serially from the device. The ADV7280A receives analog video and outputs digital video according to the ITU-R BT.656 specification. The ADV7280A outputs the ITU-R BT.656 video data stream over the P0 to P7 data pins and has an LLC pin and two synchronization pins (HS and VS/FIELD/SFL). The output of the ADV7280A-M consists of a single data channel on the D0P and D0N lanes and a clock channel on the CLKP and CLKN lanes. Video data is output over the P0 to P7 pins in YCrCb 4:2:2 format. Synchronization signals are automatically embedded in the video data signal in accordance with the ITU-R BT.656 specification. Video data is output over the data lanes in high speed mode. The data lanes enter low power mode during the horizontal and vertical blanking periods. The LLC output is used to clock the output data on the P0 to P7 pins at a nominal frequency of 27 MHz. The clock lanes clock the output video. After the ADV7280A-M is programmed, the clock lanes exit low power mode and remain in high speed mode until the device is reset or powered down. The two synchronization pins (HS and VS/FIELD/SFL) output a variety of synchronization signals such as horizontal sync, vertical sync, field sync, and color subcarrier frequency lock (SFL) sync. The majority of these synchronization signals are already embedded in the video data. Therefore, the use of the synchronization pins is optional. The ADV7280A-M outputs video data in an 8-bit, YCrCb, 4:2:2 format. When the I2P core is disabled, the video data is output in an interlaced format at a nominal data rate of 216 Mbps. When the I2P core is enabled, the video data is output in a progressive format at a nominal data rate of 432 Mbps (see the I2P Function section for more information). ADV7280A VIDEO DECODER P0 P1 P2 P3 ANALOG VIDEO INPUT ANALOG FRONT END STANDARD DEFINITION PROCESSOR ITU-R BT.656 DATA STREAM P4 P5 P6 P7 LLC VS/FIELD/SFL (OPTIONAL) 16162-018 HS (OPTIONAL) Figure 10. ITU-R BT.656 Output Stage of the ADV7280A D0P (1 BIT) CSI Tx DATA OUTPUT (8 BITS) VIDEO DECODER ITU-R BT.656 DATA STREAM CSI-2 Tx DATA LANE LP SIGNALS (2 BITS) D0N (1 BIT) D-PHY Tx CLOCK LANE LP SIGNALS (2 BITS) CLKP (1 BIT) CLKN (1 BIT) 16162-011 ANALOG VIDEO INPUT Figure 11. MIPI CSI-2 Output Stage of the ADV7280A-M Rev. A | Page 19 of 26 ADV7280A Data Sheet I2C PORT DESCRIPTION 4. The ADV7280A supports a 2-wire, I2C-compatible serial interface. Two inputs, serial data (SDATA) and serial clock (SCLK), carry information between the ADV7280A and the system I2C master controller. The I2C port of the ADV7280A allows the user to set up and configure the decoder and to read back captured VBI data. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADV7280A has a variety of possible I2C slave addresses and subaddresses (see the Register Maps section). The main map of the ADV7280A has four possible slave addresses for read and write operations, depending on the logic level of the ALSB pin (see Table 16). The ADV7280A acts as standard I2C slave devices on the bus. The data on the SDATA pin is eight bits long, supporting the 7-bit address plus the R/W bit. The device has subaddresses to enable access to the internal registers; therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register individually without updating all the registers. Table 16. Main Map I2C Addresses R/W Bit 0 1 0 1 Slave Address 0x40 (write) 0x41 (read) 0x42 (write) 0x43 (read) The ALSB pin controls Bit 1 of the slave address. By changing the logic level of the ALSB pin, it is possible to control two ADV7280A devices in an application without using the same I2C slave address. The LSB (Bit 0) specifies either a read or write operation: Logic 1 corresponds to a read operation, and Logic 0 corresponds to a write operation. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLK high period, issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7280A does not issue an acknowledge, and returns to the idle condition. To control the device on the bus, use the following protocol: 2. 3. The master initiates a data transfer by establishing a start condition, defined as a high to low transition on SDATA while SCLK remains high, and indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge (ACK) bit. If the highest subaddress is exceeded in auto-increment mode, take one of the following actions:   In read mode, the register contents of the highest subaddress continue to output until the master device issues a no acknowledge, indicating the end of a read. A no acknowledge condition occurs when the SDATA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into a subaddress register. A no acknowledge is issued by the ADV7280A, and the device returns to the idle condition. SDATA SCLK S 1–7 8 9 1–7 8 9 1–7 START ADDR R/W ACK SUBADDRESS ACK DATA 8 9 P ACK STOP Figure 12. Bus Data Transfer WRITE SEQUENCE S SLAVE ADDR A(S) SUBADDRESS A(S) LSB = 0 READ SEQUENCE A(S) DATA A(S) P LSB = 1 S SLAVE ADDR A(S) SUBADDRESS A(S) S S = START BIT P = STOP BIT DATA SLAVE ADDR A(S) A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER DATA A(M) A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER Figure 13. Read and Write Sequence Rev. A | Page 20 of 26 DATA A(M) P 16162-013 1. 16162-012 ALSB Pin 0 0 1 1 All other devices withdraw from the bus and maintain an idle condition. In the idle condition, the device monitors the SDATA and SCLK lines for the start condition and the correct transmitted address. Data Sheet ADV7280A REGISTER MAPS The ADV7280A contains two register maps: the main map, the video postprocessor (VPP) map, and the CSI map. The main register map contains three sub maps: the user sub map, the interrupt/VDP sub map, and User Sub Map 2 (see Figure 14). For more information about the ADV7280A registers, see the ADV7280A/ADV7281A/ADV7282A Device Manual. Main Map Interrupt/VDP Sub Map The interrupt/VDP sub map contains registers that program internal interrupts, control the INTRQ pin, and decode VBI data. The interrupt/VDP sub map has the same I2C slave address as the main map. To access the interrupt/VDP sub map, set the SUB_USR_EN[1:0] bits in the user sub map (Address 0x0E, Bits[6:5]) to 01. User Sub Map 2 The I2C slave address of the main map of the ADV7280A is set by the ALSB pin (see Table 16). The main map allows the user to program the I2C slave addresses of the VPP and CSI maps. The three sub maps are accessed by writing to the SUB_USR_EN[1:0] bits (Address 0x0E, Bits[6:5]) within the user sub map (see Figure 14 and Table 17). User Sub Map 2 contains registers that control the ACE, downdither, and fast lock functions. It also contains controls that set the acceptable input luma and chroma limits before the ADV7280A enters free run and color kill modes. User Sub Map The user sub map contains registers that program the AFE and digital core of the ADV7280A. The user sub map has the same I2C slave address as the main map. To access the user sub map, set the SUB_USR_EN[1:0] bits in the user sub map (Address 0x0E, Bits[6:5]) to 00. User Sub Map 2 has the same I2C slave address as the main map. To access User Sub Map 2, set the SUB_USR_EN[1:0] bits in the user sub map (Address 0x0E, Bits[6:5]) to 10. MAIN MAP VPP MAP CSI MAP DEVICE ADDRESS DEVICE ADDRESS DEVICE ADDRESS ALSB PIN HIGH WRITE: 0x42 READ: 0x43 0x0E[6:5] = 00 0x0E[6:5] = 01 0x0E[6:5] = 10 USER SUB MAP INTERRUPT/VDP SUB MAP USER SUB MAP 2 WRITE: 0x84 (RECOMMENDED READ: 0x85 SETTINGS) VPP MAP DEVICE ADDRESS IS PROGRAMMABLE AND SET BY REGISTER 0xFD IN THE USER SUB MAP WRITE: 0x88 (RECOMMENDED READ: 0x89 SETTINGS) CSI MAP ADDRESS IS PROGRAMMABLE AND SET BY REGISTER 0xFE IN THE USER SUB MAP 16162-014 ALSB PIN LOW WRITE: 0x40 READ: 0x41 Figure 14. Register Map and Sub Map Access Table 17. I2C Register Map and Sub Map Addresses ALSB Pin 0 0 0 0 0 0 1 1 1 1 1 1 X1 X1 X1 X1 1 R/W Bit 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) Slave Address 0x40 0x41 0x40 0x41 0x40 0x41 0x42 0x43 0x42 0x43 0x42 0x43 0x84 0x85 0x88 0x89 SUB_USR_EN[1:0] Bits (Address 0x0E, Bits[6:5]) 00 00 01 01 10 10 00 00 01 01 10 10 XX1 XX1 XX1 XX1 X and XX mean don’t care. A | Page 21 of 26 Register Map or Sub Map User sub map User sub map Interrupt/VDP sub map Interrupt/VDP sub map User Sub Map 2 User Sub Map 2 User sub map User sub map Interrupt/VDP sub map Interrupt/VDP sub map User Sub Map 2 User Sub Map 2 VPP map VPP map CSI map (ADV7280A-M only) CSI map (ADV7280A-M only) ADV7280A Data Sheet VPP Map default value for the CSI map address is 0x00; however, the CSI map cannot be accessed until the I2C slave address is reset. The recommended I2C slave address for the CSI map is 0x88. The VPP map contains registers that control the I P core (interlaced to progressive converter). 2 The VPP map has a programmable I2C slave address, which is programmed using Register 0xFD in the user sub map. The default value for the VPP map address is 0x00; however, the VPP map cannot be accessed until the I2C slave address is reset. The recommended I2C slave address for the VPP map is 0x84. To reset the I2C slave address of the CSI map, write to the CSI_TX_SLAVE_ADDR[7:1] bits in the user sub map (Address 0xFE, Bits[7:1]). Set these bits to a value of 0x88 (I2C write address; I2C read address is 0x89). To reset the I2C slave address of the VPP map, write to the VPP_SLAVE_ADDR[7:1] bits in the user sub map (Address 0xFD, Bits[7:1]). Set these bits to a value of 0x84 (I2C write address; I2C read address is 0x85). The user sub map is available by default. The other two sub maps are accessed using the SUB_USR_EN[1:0] bits. When programming of the interrupt/VDP map or User Sub Map 2 is completed, it is necessary to write to the SUB_USR_EN[1:0] bits to return to the user sub map. CSI Map (ADV7280A-M Only) SUB_USR_EN[1:0] Bits, Address 0x0E, Bits[6:5] The CSI map contains registers that control the MIPI CSI-2 output stream from the ADV7280A-M. The CSI map has a programmable I2C slave address, which is programmed using Register 0xFE in the user sub map. The Rev. A | Page 22 of 26 Data Sheet ADV7280A PCB LAYOUT RECOMMENDATIONS The ADV7280A is a high precision, high speed, mixed-signal device. To achieve maximum performance from the device, it is important to use a well designed PCB. This section provides guidelines for designing a PCB for use with the ADV7280A. VREFN AND VREFP PINS ANALOG INTERFACE INPUTS DIGITAL OUTPUTS When routing the analog interface inputs on the PCB, keep track lengths to a minimum. Use 75 Ω trace impedances when possible; trace impedances other than 75 Ω increase the chance of reflections. POWER SUPPLY DECOUPLING It is recommended that each power supply pin be decoupled with 100 nF and 10 nF capacitors. The basic principle is to place a decoupling capacitor within approximately 0.5 cm of the PVDD, AVDD, DVDD, and MVDD pins. Avoid placing the decoupling capacitors on the opposite side of the PCB from the ADV7280A because doing so introduces inductive vias in the path. Place the decoupling capacitors between the power plane and the power pin. Current flows from the power plane to the capacitor and then to the power pin. Do not apply the power connection between the capacitor and the power pin. The best approach is to place a via near, or beneath, the decoupling capacitor pads down to the power plane (see Figure 15). VIA TO SUPPLY SUPPLY 10nF VIA TO GND The ADV7280A digital outputs are INTRQ, LLC, HS, VS/FIELD/SFL, and P0 to P7. The ADV7280A-M digital outputs are INTRQ and GPO0 to GPO2. Minimize the trace length that the digital outputs must drive. Longer traces have higher capacitance, requiring more current and, in turn, causing more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a 30 Ω to 50 Ω series resistor can suppress reflections, reduce electromagnetic interference (EMI), and reduce current spikes inside the ADV7280A. If using series resistors, place them as close as possible to the pins of the ADV7280A. However, try not to add vias or extra length to the output trace in an attempt to place the resistors closer. If possible, limit the capacitance that each digital output must drive to less than 15 pF. This recommendation can be easily accommodated by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside the ADV7280A, creating more digital noise on the power supplies. EXPOSED METAL PAD 16162-015 GROUND 100nF Place the circuit associated with the VREFN and VREFP pins as close as possible to the ADV7280A and on the same side of the PCB as the device. Figure 15. Recommended Power Supply Decoupling Ensure that the power supplies connected to the ADV7280A, PVDD and MVDD (MVDD only applies to the ADV7280A-M model) in particular, are well regulated and filtered. For optimum performance of the ADV7280A, it is recommended to isolate each supply and to use decoupling on each pin, located as physically close to the ADV7280A package as possible. Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). This disparity can result in a measurable change in the voltage supplied to the analog supply regulator, which can, in turn, produce changes in the regulated analog supply voltage. This problem can be mitigated by regulating the analog supply, or at least the PVDD supply, from a different, cleaner power source, for example, from a 12 V supply. Using a single ground plane for the entire board is also recommended. Experience has shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. The ADV7280A has an exposed metal pad on the bottom of the package. This pad must be soldered to ground. The exposed pad is used for proper heat dissipation, noise suppression, and mechanical strength. DIGITAL INPUTS The digital inputs of the ADV7280A are designed to work with 1.8 V signals (3.3 V for DVDDIO) and are not tolerant of 5 V signals. Extra components are required if 5 V logic signals must be applied to the decoder. MIPI Tx OUTPUTS (ADV7280A-M ONLY) It is recommended that the MIPI Tx output traces be kept as short as possible and on the same side of the PCB as the ADV7280A-M device. It is also recommended that a solid plane (preferably a ground plane) be placed on the layer adjacent to the MIPI Tx traces to provide a solid reference plane. MIPI Tx transmission operates in both differential and singleended modes. During high speed transmission, the pair of outputs operates in differential mode; in low power mode, the pair operates as two independent single-ended traces. Therefore, it is recommended that each output pair be routed as two loosely coupled 50 Ω single-ended traces to reduce the risk of crosstalk between the two traces in low power mode. A | Page 23 of 26 ADV7280A Data Sheet TYPICAL CIRCUIT CONNECTIONS See the XTAL data sheet (from the XTAL vendor), the AN-1260 Application Note, and the calculator tool (visit the design resources section at www.analog.com/ADV7280A to download) for the correct values for C1, C2, and RDAMP. Figure 16 provides an example of how to connect the ADV7280A. Figure 17 provides an example of how to connect the ADV7280A-M. 0.1µF Y 24Ω AIN1 51Ω DVDD _1.8V DVDDIO _3.3V AVDD _1.8V 0.1µF Pb 24Ω AIN2 0.1µF 51Ω 10nF 0.1µF 0.1µF 0.1µF 10nF 10nF 10nF 0.1µF Pr 24Ω AIN3 51Ω PVDD _1.8V DVDDIO _3.3V DVDD _1.8V 10nF 18 AIN2 22 AIN3 23 AIN4 AIN2 AIN4 LOCATE VREFP AND VREFN CAPACITOR AS CLOSE AS POSSIBLE TO THE ADV7280A AND ON THE SAME SIDE OF THE PCB AS THE ADV7280A 19 VREFP 20 VREFN 16 21 3 AIN3 P0 TO P7 PVDD AIN1 AVDD 17 AIN1 DVDD 51Ω DVDD AIN4 13 0.1µF 2 24Ω 0.1µF AVDD _1.8V CVBS INPUT EXAMPLE DVDDIO COMPONENT ANALOG VIDEO INPUT EXAMPLE For detailed schematics of the ADV7280A evaluation boards, visit the ADV7280A product page at www.analog.com/ADV7280A. P0 P1 P2 P3 P4 P5 P6 P7 12 11 10 9 8 7 6 5 LLC 32 INTRQ 24 P0 P1 P2 P3 P4 P5 P6 P7 YCrCb 8-BIT ITU-R BT.656 DATA 0.1µF XTAL CIRCUIT 14 C1 XTALP RDAMP 15 INTRQ ADV7280A 28.63636MHz C2 LLC XTALN VS/FIELD/SFL 29 HS 30 VS/FIELD/SFL HS LOCATE AS CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV7280A DVDDIO 4kΩ 26 ALSB 31 PWRDWN 25 RESET 28 SCLK 27 SDATA 1 SDATA Figure 16. Typical Connection Diagram, ADV7280A Rev. A | Page 24 of 26 16162-016 SCLK DGND RESET 4 PWRDWN DGND ALSB TIED HIGH: I2C ADDRESS = 0x42 ALSB TIED LOW: I2C ADDRESS = 0x40 Data Sheet ADV7280A 0.1µF 24Ω AIN1 51Ω COMPONENT VIDEO INPUT 0.1µF 24Ω AIN2 51Ω 0.1µF AIN3 24Ω 51Ω D VDD_1.8V DVDDIO _3.3V 0.1µF SINGLEENDED CVBS INPUT 24Ω 0.1µF 10nF PVDD _1.8V A IN5 0.1µF 24 AIN5 51Ω AIN6 0.1µF AIN8 24Ω AIN7 AIN8 51Ω 13 MVDD PVDD D0P D0N 9 10 D0P D0N AIN3 AIN4 CLKP 11 CLKP AIN5 CLKN 12 CLKN 25 AIN6 26 AIN7 27 AIN8 ADV7280A-M XTAL CIRCUIT 14 C1 16 21 AVDD AIN2 23 AIN4 AIN7 AIN1 22 AIN3 24Ω 17 18 3 AIN2 DVDD AIN6 10nF 2 AIN1 0.1µF 24Ω 0.1µF AVDD_1.8V DVDDIO 24Ω MVDD_1.8V DVDD_1.8V 0.1µF 51Ω GPO2 GPO1 GPO0 6 7 8 GPO2 GPO1 GPO0 RDAMP 28.63636MHz 15 INTRQ 5 INTRQ C2 LOCATE AS CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV7280A-M DVDDIO 4kΩ LOCATE VREFN AND VREFP CAPACITOR AS CLOSE AS POSSIBLE TO THE ADV7280A-M AND ON THE SAME SIDE OF THE PCB AS THE ADV7280A-M 29 ALSB 19 ALSB TIED HIGH: I2 C ADDRESS = 0x42 ALSB TIED LOW: I2 C ADDRESS = 0x40 VREFP 0.1µF SCLK SDATA PWRDWN 28 RESET 31 SCLK 30 SDATA DGND RESET 20 16162-017 4 PWRDWN VREFN DGND 32 1 S-VIDEO INPUT 10nF 51Ω 51Ω SINGLEENDED CVBS INPUT 10nF AIN4 D VDDIO_3.3V SINGLEENDED CVBS INPUT MVDD _1.8V 0.1µF 0.1µF 10nF 0.1µF AVDD _1.8V Figure 17. Typical Connection Diagram, ADV7280A-M A | Page 25 of 26 ADV7280A Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.75 3.60 SQ 3.55 EXPOSED PAD 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 08-16-2010-B PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADV7280AWBCPZ ADV7280AWBCPZ-RL ADV7280AWBCPZ-M ADV7280AWBCPZ-M-RL ADV7280ABCPZ-M ADV7280ABCPZ-M-RL EVAL-ADV7280AEBZ EVAL-ADV7280AMEBZ 1 2 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board for the ADV7280A Evaluation Board for the ADV7280A-M Package Option CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADV7280AW models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2017–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16162-0-5/18(A) Rev. A | Page 26 of 26