Data Sheet
10-Bit, 4× Oversampled SDTV Video
Decoder with Differential Inputs
ADV7281
FEATURES
GENERAL DESCRIPTION
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit analog-to-digital converter (ADC), 4× oversampling
per channel for CVBS, Y/C, and YPrPb modes
Analog video input channels with on-chip antialiasing filter
ADV7281: up to 4 input channels
ADV7281-M: up to 6 input channels
ADV7281-MA: up to 8 input channels
Video input support for CVBS (composite), Y/C (S-Video),
and YPrPb (component)
Fully differential, pseudo differential, and single-ended
CVBS video input support
NTSC/PAL/SECAM autodetection
Short-to-battery (STB) diagnostics on 2 video inputs
(ADV7281 and ADV7281-M only)
Up to 4 V common-mode input range solution
Excellent common-mode noise rejection capabilities
5-line adaptive 2D comb filter and CTI video enhancement
Adaptive Digital Line Length Tracking (ADLLT), signal
processing, and enhanced FIFO management provide
mini-time base correction (TBC) functionality
Integrated automatic gain control (AGC) with adaptive
peak white mode
Fast switching capability
Adaptive contrast enhancement (ACE)
Down dither (8-bit to 6-bit)
Rovi (Macrovision) copy protection detection
MIPI CSI-2 output interface (ADV7281-M and ADV7281-MA)
8-bit ITU-R BT.656 YCrCb 4:2:2 output (ADV7281)
Full featured vertical blanking interval (VBI) data slicer
Power-down mode available
2-wire, I2C-compatible serial interface
Qualified for automotive applications
−40°C to +105°C temperature grade
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
The ADV7281/ADV7281-M/ADV7281-MA are versatile
one-chip, multiformat video decoders. The ADV7281/
ADV7281-M/ADV7281-MA automatically detect standard
analog baseband video signals compatible with worldwide
NTSC, PAL, and SECAM standards in the form of composite,
S-Video, and component video.
The ADV7281 converts the analog video signals into a YCrCb
4:2:2 video data stream that is compatible with the 8-bit ITU-R
BT.656 interface standard.
The ADV7281-M/ADV7281-MA convert the analog video
signals into an 8-bit YCrCb 4:2:2 video data stream that is
output over a mobile industry processor interface (MIPI®)
CSI-2 interface.
The analog video inputs of the ADV7281/ADV7281-M/
ADV7281-MA accept single-ended, pseudo differential, and
fully differential signals. The ADV7281 provides four analog
inputs and two STB diagnostic pins. The ADV7281-M provides
six analog inputs, two STB diagnostic pins, and three generalpurpose outputs. The ADV7281-MA provides eight analog
inputs and three general-purpose outputs.
The ADV7281/ADV7281-M/ADV7281-MA are programmed
via a 2-wire, serial bidirectional port (I2C compatible) and
are fabricated in a 1.8 V CMOS process. The ADV7281/
ADV7281-M/ADV7281-MA are provided in space-saving
LFCSP surface-mount, RoHS-compliant packages. The
ADV7281/ADV7281-M/ADV7281-MA are rated over the
−40°C to +105°C temperature range. This makes the ADV7281/
ADV7281-M/ADV7281-MA ideal for automotive applications.
APPLICATIONS
Smartphone/multimedia handsets
Automotive infotainment
DVRs for video security
Media players
Rev. B
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ADV7281
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Networks ............................................................................... 17
Applications ....................................................................................... 1
Single-Ended Input Network .................................................... 17
General Description ......................................................................... 1
Differential Input Network ....................................................... 17
Revision History ............................................................................... 2
Short-to-Battery Protection ...................................................... 17
Functional Block Diagrams ............................................................. 3
Input Configuration ....................................................................... 18
Specifications..................................................................................... 4
Electrical Specifications ............................................................... 4
Short-to-Battery (STB) Diagnostics (ADV7281/ADV7281-M
Only) ................................................................................................ 19
Video Specifications ..................................................................... 5
Programming the STB Diagnostic Function .......................... 19
Analog Specifications ................................................................... 6
Adaptive Contrast Enhancement (ACE) ..................................... 21
Clock and I2C Timing Specifications ......................................... 6
ITU-R BT.656 Tx Configuration (ADV7281 Only) .................. 22
MIPI Video Output Specifications (ADV7281-M and
ADV7281-MA Only) ................................................................... 7
MIPI CSI-2 Output ........................................................................ 23
Pixel Port Timing Specifications (ADV7281 Only) ................. 9
Register Maps .............................................................................. 25
Absolute Maximum Ratings.......................................................... 10
PCB Layout Recommendations.................................................... 27
Thermal Resistance .................................................................... 10
Analog Interface Inputs ............................................................. 27
Reflow Solder .............................................................................. 10
Power Supply Decoupling ......................................................... 27
ESD Caution ................................................................................ 10
VREFN and VREFP Pins .......................................................... 27
Pin Configurations and Function Descriptions ......................... 11
Digital Outputs ........................................................................... 27
Theory of Operation ...................................................................... 14
Exposed Metal Pad ..................................................................... 28
Analog Front End (AFE) ........................................................... 14
Digital Inputs .............................................................................. 28
Standard Definition Processor (SDP) ...................................... 15
Power Supply Sequencing .............................................................. 16
MIPI Outputs (D0P, D0N, CLKP, CLKN) ADV7281-M/
ADV7281-MA only .................................................................... 28
Optimal Power-Up Sequence.................................................... 16
Typical Circuit Connections ......................................................... 29
Simplified Power-Up Sequence ................................................ 16
Outline Dimensions ....................................................................... 32
Power-Down Sequence .............................................................. 16
Ordering Guide .......................................................................... 32
DVDDIO Supply Voltage ................................................................ 16
Automotive Products ................................................................. 32
I2C Port Description ....................................................................... 24
REVISION HISTORY
4/14—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changed Single-Ended CVBS Input from 35 mA to 47 mA ...... 4
Changes to Table 7 .......................................................................... 10
Changes to Theory of Operation Section .................................... 14
Changes to DVDDIO Supply Voltage ................................................ 16
Changes to Short-to-Battery Protection Section ........................ 17
Changes to Ordering Guide .......................................................... 32
11/13—Rev. 0 to Rev. A
Changes to Features and General Description Sections.............. 1
Added Figure 1; Renumbered Sequentially .................................. 3
Changes to Table 1 ............................................................................ 4
Added Pixel Port Timing Specifications (ADV7281 Only)
Section ................................................................................................ 9
Added Endnote 1; Table 7 ............................................................. 10
Added Figure 7 and Table 9 .......................................................... 11
Changes to Theory of Operation Section.................................... 14
Changes to Optimal Power-Up Sequence Section and DVDDIO
Supply Voltage Section................................................................... 16
Changes to Table 13 ....................................................................... 18
Changes to Programming the STB Diagnostic Function
Section.............................................................................................. 19
Added ITU-R BT.656 Tx Configuration (ADV7281 Only)
Section.............................................................................................. 22
Changes to Register Maps Section ............................................... 25
Changes to Power Supply Decoupling Section and Digital
Outputs Section .............................................................................. 27
Changes to Typical Circuit Connections Section ...................... 29
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
8/13—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
ADV7281
FUNCTIONAL BLOCK DIAGRAMS
ADV7281
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
LCC
2D COMB
+
SHA
AA
FILTER
ADC
VBI SLICER
–
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
DIAG1
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
8-BIT
PIXEL DATA
P0 TO P7
INTRQ
11633-200
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
XTALN
SCLK SDATA ALSB RESET PWRDWN
DIAG2
Figure 1. ADV7281 Functional Block Diagram
ADV7281-M
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
MIPI
Tx
XTALN
CLKN
D0P
2D COMB
+
SHA
AA
FILTER
ADC
VBI SLICER
–
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
DIAG1
ACE
DOWN
DITHER
GPO0
GPO1
GPO2
I2C/CONTROL
REFERENCE
INTRQ
11633-001
AIN5
AIN6
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
D0N
SCLK SDATA ALSB RESET PWRDWN
DIAG2
Figure 2. ADV7281-M Functional Block Diagram
ADV7281-MA
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
MIPI
Tx
ADLLT PROCESSING
XTALN
CLKN
D0P
AA
FILTER
2D COMB
+
SHA
AA
FILTER
DIGITAL
PROCESSING
BLOCK
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
SCLK SDATA ALSB RESET PWRDWN
Figure 3. ADV7281-MA Functional Block Diagram
Rev. B | Page 3 of 32
GPO0
GPO1
GPO2
INTRQ
11633-002
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
FILTER
OUTPUT BLOCK
10-BIT ADC
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
FIFO
D0N
ADV7281
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
ADC Resolution
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage
Symbol
Test Conditions/Comments
N
INL
DNL
CVBS mode
CVBS mode
VIH
Input Low Voltage
VIL
Input Leakage Current
IIN
DVDDIO = 3.3 V
DVDDIO = 1.8 V, ADV7281 only
DVDDIO = 3.3 V
DVDDIO = 1.8 V, ADV7281 only
RESET pin
SDATA, SCLK pins
PWRDWN, ALSB pins
Min
−10
−10
−10
VIH
VIL
XTALN pin
XTALN pin
1.2
VOH
2.4
1.4
Output Low Voltage
VOL
DVDDIO = 3.3 V, ISOURCE = 0.4 mA
DVDDIO = 1.8 V, ISOURCE = 0.4 mA,
ADV7281 only
DVDDIO = 3.3 V, ISINK = 3.2 mA
DVDDIO = 1.8 V, ISINK = 1.6 mA,
ADV7281 only
PLL Power Supply
Analog Power Supply
Digital Power Supply
MIPI Tx Power Supply
Digital I/O Supply Current
PVDD
AVDD
DVDD
MVDD
IDVDDIO
PLL Supply Current
MIPI Tx Supply Current
Analog Supply Current
Single-Ended CVBS Input
Differential CVBS Input
IPVDD
IMVDD
IAVDD
Y/C Input
YPrPb Input
Digital Supply Current
Single-Ended CVBS Input
Differential CVBS Input
ADV7281-M/ADV7281-MA only
ADV7281-M/ADV7281-MA
ADV7281
ADV7281-M/ADV7281-MA only
Fully differential and pseudo
differential CVBS
10
Bits
LSB
LSB
2.97
1.62
1.71
1.71
1.71
1.71
0.8
0.4
+10
+15
+50
10
V
V
V
V
µA
µA
µA
pF
0.4
V
V
V
V
ILEAK
COUT
ADV7281-M/ADV7281-MA
ADV7281
Unit
2
1.2
CIN
DVDDIO
Max
2
±0.6
Input Capacitance
CRYSTAL INPUT
Input High Voltage
Input Low Voltage
DIGITAL OUTPUTS
Output High Voltage
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS1, 2
Digital I/O Power Supply
Typ
3.3
3.3
1.8
1.8
1.8
1.8
1.5
5
12
14
0.4
0.2
V
V
10
20
µA
pF
3.63
3.63
1.89
1.89
1.89
1.89
V
V
V
V
V
V
mA
mA
mA
mA
47
69
mA
mA
60
75
mA
mA
60
60
mA
mA
60
60
mA
mA
IDVDD
Fully differential and pseudo
differential CVBS
Y/C Input
YPrPb Input
Rev. B | Page 4 of 32
Data Sheet
Parameter
POWER-DOWN CURRENTS1
Digital I/O Supply Power-Down
Current
PLL Supply Power-Down Current
Analog Supply Power-Down Current
Digital Supply Power-Down Current
MIPI Tx Supply Power-Down Current
Total Power Dissipation
in Power-Down Mode
1
2
ADV7281
Symbol
Test Conditions/Comments
IDVDDIO_PD
DVDDIO = 3.3 V, ADV7281-M/
ADV7281-MA
DVDDIO = 3.3 V, ADV7281
IPVDD_PD
IAVDD_PD
IDVDD_PD
IMVDD_PD
Min
ADV7281-M and ADV7281-MA only
Typ
Max
Unit
73
μA
84
46
0.2
420
4.5
1
μA
μA
μA
μA
μA
mW
Guaranteed by characterization.
Typical current consumption values are measured with nominal voltage supply levels and an SMPTE bar test pattern.
VIDEO SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 2.
Parameter
NONLINEAR SPECIFICATIONS1
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted
Analog Front-End Crosstalk
Common-Mode Rejection Ratio2
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
fSC Subcarrier Lock Range
Color Lock-In Time
Synchronization Depth Range
Color Burst Range
Vertical Lock Time
Autodetection Switch Speed3
Fast Switch Speed4
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
Symbol
Test Conditions/Comments
Min
DP
DG
LNL
CVBS input, modulated 5-step
CVBS input, modulated 5-step
CVBS input, 5-step
0.9
0.5
2.0
Degrees
%
%
SNR
Luma ramp
Luma flat field
57.1
58
60
73
dB
dB
dB
dB
CMRR
Typ
−5
40
Max
+5
70
Unit
2
100
100
%
Hz
kHz
Lines
%
%
Fields
Lines
ms
1
1
%
%
±1.3
60
20
5
200
200
CVBS, 1 V input
1
These specifications apply for all CVBS input types (NTSC, PAL, and SECAM), as well as for single-ended and differential CVBS inputs.
The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Networks section). The CMRR measurement
was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
3
Autodetection switch speed is the time required for the ADV7281/ADV7281-M/ADV7281-MA to detect which video format is present at its input, for example, PAL I or
NTSC M.
4
Fast switch speed is the time required for the ADV7281/ADV7281-M/ADV7281-MA to switch from one analog input (single-ended or differential) to another, for
example, switching from AIN1 to AIN2.
2
Rev. B | Page 5 of 32
ADV7281
Data Sheet
ANALOG SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7281-M/ADV7281-MA.
Table 3.
Parameter
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
Test Conditions/Comments
Min
Typ
Max
0.1
10
0.4
0.4
10
10
Clamps switched off
Unit
μF
MΩ
mA
mA
μA
μA
CLOCK AND I2C TIMING SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7281-M/ADV7281-MA.
Table 4.
Parameter
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Times
SCLK and SDATA Fall Times
Setup Time (Stop Condition)
RESET INPUT
RESET Pulse Width
Symbol
Min
Typ
Max
Unit
±50
MHz
ppm
28.63636
400
t1
t2
t3
t4
t5
t6
t7
t8
kHz
μs
μs
μs
μs
ns
ns
ns
μs
0.6
1.3
0.6
0.6
100
300
300
0.6
5
ms
t3
t5
t3
SDATA
t2
t4
t7
2
Figure 4. I C Timing Diagram
Rev. B | Page 6 of 32
t8
11633-003
t1
t6
SCLK
Data Sheet
ADV7281
MIPI VIDEO OUTPUT SPECIFICATIONS (ADV7281-M AND ADV7281-MA ONLY)
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
The CSI-2 clock lane of the ADV7281-M/ADV7281-MA remains in high speed (HS) mode even when the data lane enters low power (LP)
mode. For this reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated,
all high speed measurements were performed with the ADV7281-M/ADV7281-MA operating in interlaced mode and with a nominal
216 Mbps output data rate. Specifications guaranteed by characterization.
Table 5.
Parameter
UNIT INTERVAL
Interlaced Output
DATA LANE LP TX DC SPECIFICATIONS1
Thevenin Output High Level
Thevenin Output Low Level
DATA LANE LP TX AC SPECIFICATIONS1
Rise Time, 15% to 85%
Fall Time, 85% to 15%
Rise Time, 30% to 85%
Data Lane LP Slew Rate vs. CLOAD
Maximum Slew Rate over Entire
Vertical Edge Region
Symbol
UI
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV
400 mV ≤ VOUT ≤ 700 mV
700 mV ≤ VOUT ≤ 930 mV
DATA LANE HS TX SIGNALING
REQUIREMENTS
Low Power to High Speed Transition
Stage
VOH
VOL
1.1
−50
Typ
Max
t9
t11
|V1|
ns
V
mV
25
25
35
ns
ns
ns
Rising edge
150
mV/ns
Falling edge
150
mV/ns
VOH
VOL
1.2
0
Unit
1.3
+50
Falling edge
Rising edge
Rising edge
First clock pulse after stop state or
last pulse before stop state
All other clock pulses
t10
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
Static Common-Mode Voltage Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz
Above 450 MHz
Min
4.63
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV
400 mV ≤ VOUT ≤ 700 mV
700 mV ≤ VOUT ≤ 930 mV
Pulse Width of LP Exclusive-OR Clock
Period of LP Exclusive-OR Clock
CLOCK LANE LP TX DC SPECIFICATIONS1
Thevenin Output High Level
Thevenin Output Low Level
CLOCK LANE LP TX AC SPECIFICATIONS1
Rise Time, 15% to 85%
Fall Time, 85% to 15%
Clock Lane LP Slew Rate
Maximum Slew Rate over Entire
Vertical Edge Region
Test Conditions/Comments
30
30
>0
40
mV/ns
mV/ns
mV/ns
ns
20
90
ns
ns
1.1
−50
1.2
0
1.3
+50
V
mV
25
25
ns
ns
Rising edge
150
mV/ns
Falling edge
150
mV/ns
Falling edge
Rising edge
Rising edge
See Figure 5
30
30
>0
mV/ns
mV/ns
mV/ns
Time that the D0P pin is at VOL and
the D0N pin is at VOH
Time that the D0P and D0N pins
are at VOL
t10 plus the HS-zero period
50
ns
Rev. B | Page 7 of 32
40 + (4 × UI)
145 + (10 × UI)
140
200
150
200
85 + (6 × UI)
ns
270
10
360
250
5
ns
mV p-p
mV
mV
mV
mV
25
15
mV
mV
ADV7281
Data Sheet
Parameter
Rise Time, 20% to 80%
Fall Time, 80% to 20%
High Speed to Low Power Transition
Stage
Symbol
Test Conditions/Comments
t12
Time that the ADV7281-M/
ADV7281-MA drive the flipped last
data bit after sending the last
payload data bit of an HS
transmission burst
Post-end-of-transmission rise time
(30% to 85%)
Time from start of t12 to start of low
power state following an HS
transmission burst
Time that a low power state is
transmitted after an HS transmission burst
See Figure 5
t13
t14
t15
CLOCK LANE HS TX SIGNALING
REQUIREMENTS
Low Power to High Speed Transition
Stage2
Time that the CLKP pin is at VOL and
the CLKN pin is at VOH
Time that the CLKP and CLKN pins
are at VOL
Clock HS-zero period
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
Static Common-Mode Voltage Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz
Above 450 MHz
Rise Time, 20% to 80%
Fall Time, 80% to 20%
HS TX CLOCK TO DATA LANE TIMING
REQUIREMENTS
Data to Clock Skew
2
Typ
Max
0.3 × UI
0.3 × UI
Unit
ns
ns
ns
35
ns
105 + (12 × UI)
ns
100
ns
50
ns
38
95
ns
270
10
360
250
5
ns
mV p-p
mV
mV
mV
mV
0.15
0.15
25
15
0.3 × UI
0.3 × UI
mV
mV
ns
ns
0.35 × UI
0.65 × UI
ns
300
140
500
200
150
200
These measurements were performed with CLOAD = 50 pF.
The clock lane remains in high speed mode throughout normal operation. These results apply only to the ADV7281-M/ADV7281-MA during startup.
|V2|
CLKP/CLKN
D0P/D0N
t9
t10
t11
VOH
|V1|
VOL
t13
TRANSMIT FIRST
DATA BIT
t14
LOW POWER
TO
HIGH SPEED
TRANSITION
HS-ZERO
START OF
TRANSMISSION
SEQUENCE
HIGH SPEED DATA
TRANSMISSION
t12
t15
HS-TRAIL
HIGH SPEED
TO
LOW POWER
TRANSITION
Figure 5. ADV7281-M/ADV7281-MA Output Timing Diagram (Conforms with MIPI CSI-2 Specification)
Rev. B | Page 8 of 32
11633-004
1
|V2|
Min
0.15
0.15
60 + (4 × UI)
Data Sheet
ADV7281
PIXEL PORT TIMING SPECIFICATIONS (ADV7281 ONLY)
AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 6.
Parameter
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
Symbol
Test Conditions/Comments
Min
t16:t17
Typ
45:55
t18
Negative clock edge to start of valid data
(tSETUP = t17 − t18)
End of valid data to negative clock edge
(tHOLD = t16 − t19)
t19
t16
t17
OUTPUT LLC
t18
11633-201
t19
OUTPUTS P0 TO P7
Figure 6. ADV7281 Pixel Port and Control Output Timing Diagram
Rev. B | Page 9 of 32
Max
Unit
55:45
% duty cycle
3.8
ns
6.9
ns
ADV7281
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter1
AVDD to GND
DVDD to GND
PVDD to GND
MVDD to GND1
DVDDIO to GND
PVDD to DVDD
MVDD to DVDD2
AVDD to DVDD
Digital Inputs Voltage
Digital Outputs Voltage
Analog Inputs to Ground
Maximum Junction Temperature
(TJ max)
Storage Temperature Range
Infrared Reflow Soldering
(20 sec)
Rating
2.2 V
2.2 V
2.2 V
2.2 V
4V
−0.9 V to +0.9 V
−0.9 V to +0.9 V
−0.9 V to +0.9 V
GND − 0.3 V to DVDDIO + 0.3 V
GND − 0.3 V to DVDDIO + 0.3 V
GND − 0.3 V to AVDD + 0.3 V
140°C
THERMAL RESISTANCE
−65°C to +150°C
260°C
The ADV7281/ADV7281-M/ADV7281-MA are Pb-free,
environmentally friendly products. They are manufactured using
the most up-to-date materials and processes. The coating on the
leads of each device is 100% pure Sn electroplate. The devices
are suitable for Pb-free applications and can withstand surfacemount soldering at up to 255°C (±5°C).
The Absolute Maximum Ratings assume that DGND pins and the exposed
pad of the ADV7281/ADV7281-M/ADV7281-MA are connected together
to a common ground plane (GND). This is part of the recommended layout
scheme. See PCB Layout Recommendations for more information. The
Absolute Maximum Ratings are stated in relation to this common ground
plane.
2
MVDD applies to the ADV7281-M and ADV7281-MA only.
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The thermal resistance values in Table 8 are specified for the
device soldered onto a 4-layer printed circuit board (PCB) with
a common ground plane and with the exposed pad of the device
connected to DGND. The values in Table 8 are maximum values.
Table 8. Thermal Resistance for the 32-Lead LFCSP
Thermal Characteristic
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal
Resistance
Symbol
θJA
Value
32.5
Unit
°C/W
θJC
2.3
°C/W
REFLOW SOLDER
In addition, the ADV7281/ADV7281-M/ADV7281-MA are
backward-compatible with conventional SnPb soldering
processes. This means that the electroplated Sn coating can
be soldered with Sn/Pb solder pastes at conventional reflow
temperatures of 220°C to 235°C.
ESD CAUTION
These devices are high performance integrated circuits with
an ESD rating of
