ADV7282WBCPZ

10-Bit, 4× Oversampled SDTV Video Decoder with Differential Inputs and Deinterlacer ADV7282 Data Sheet FEATURES GENERAL DESCRIPTION Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit analog-to-digital converter (ADC), 4× oversampling per channel for CVBS, Y/C, and YPrPb modes ADV7282: 4 analog video input channels with on-chip antialiasing filter ADV7282-M: 6 analog video input channels with on-chip antialiasing filter Video input support for CVBS (composite), Y/C (S-Video), and YPrPb (component) Fully differential, pseudo differential, and single-ended CVBS video input support NTSC/PAL/SECAM autodetection Short-to-battery (STB) diagnostics on 2 video inputs Up to 4 V common-mode input range solution Excellent common-mode noise rejection capabilities 5-line adaptive 2D comb filter and CTI video enhancement Adaptive Digital Line Length Tracking (ADLLT), signal processing, and enhanced FIFO management provide mini-time base correction (TBC) functionality Integrated automatic gain control (AGC) with adaptive peak white mode Fast switching capability Integrated interlaced-to-progressive (I2P) video output converter (deinterlacer) Adaptive contrast enhancement (ACE) Down dither (8-bit to 6-bit) Rovi (Macrovision) copy protection detection 8-bit ITU-R BT.656 YCrCb 4:2:2 output (ADV7282) MIPI CSI-2 output interface (ADV7282-M only) Full featured vertical blanking interval (VBI) data slicer with world system teletext (WST) support Power-down mode available 2-wire, I2C-compatible serial interface Qualified for automotive applications −40°C to +105°C temperature grade 32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP The ADV7282/ADV7282-M are versatile one-chip, multiformat video decoders. The ADV7282/ADV7282-M automatically detects standard analog baseband video signals compatible with worldwide NTSC, PAL, and SECAM standards in the form of composite, S-Video, and component video. The ADV7282 converts the analog video signals into a YCrCb 4:2:2 video data stream that is compatible with the 8-bit ITU-R BT.656 interface standard. The ADV7282-M converts the analog video signals into an 8-bit YCrCb 4:2:2 video data stream that is output over a mobile industry processor interface (MIPI®) CSI-2 interface. The analog video inputs of the ADV7282/ADV7282-M accept single-ended, pseudo differential, and fully differential signals. The ADV7282/ADV7282-M contain a deinterlacer (I2P converter) and short to battery detection capability with two STB diagnostic pins. The ADV7282 provides four analog inputs. The ADV7282-M provides six analog inputs and three generalpurpose outputs. The ADV7282/ADV7282-M are programmed via a 2-wire, serial bidirectional port (I2C compatible) and is fabricated in a 1.8 V CMOS process. The ADV7282/ADV7282-M are provided in space-saving, RoHS compliant LFCSP surface-mount packages. The ADV7282/ADV7282-M are rated over the −40°C to +105°C temperature range. This makes the ADV7282/ADV7282-M ideal for automotive applications. APPLICATIONS Smartphone/multimedia handsets Automotive infotainment DVRs for video security Media players Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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Technical Support www.analog.com ADV7282 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Single-Ended Input Network .................................................... 16 Applications ....................................................................................... 1 Differential Input Network ....................................................... 16 General Description ......................................................................... 1 Short-to-Battery Protection ...................................................... 16 Revision History ............................................................................... 2 Input Configuration ....................................................................... 17 Functional Block Diagrams ............................................................. 3 Short-to-Battery (STB) Diagnostics ............................................. 18 Specifications..................................................................................... 4 Programming the STB Diagnostic Function .......................... 18 Electrical Specifications ............................................................... 4 Adaptive Contrast Enhancement (ACE) ..................................... 20 Video Specifications ..................................................................... 5 I2P Function.................................................................................... 21 Analog Specifications ................................................................... 6 ITU-R BT.656 Tx Configuration (ADV7282 Only) .................. 22 Clock and I C Timing Specifications ......................................... 6 MIPI CSI-2 Output (ADV7282-M Only) ................................... 23 MIPI Video Output Specifications (ADV7282-M Only) ........ 7 I2C Port Description ....................................................................... 24 Pixel Port Timing Specifications (ADV7282 Only) ................. 9 Register Maps .............................................................................. 25 Absolute Maximum Ratings.......................................................... 10 PCB Layout Recommendations.................................................... 27 Thermal Resistance .................................................................... 10 Analog Interface Inputs ............................................................. 27 Reflow Solder .............................................................................. 10 Power Supply Decoupling ......................................................... 27 ESD Caution ................................................................................ 10 VREFN and VREFP Pins .......................................................... 27 Pin Configuration and Function Descriptions ........................... 11 Digital Outputs ........................................................................... 27 Theory of Operation ...................................................................... 13 Exposed Metal Pad ..................................................................... 27 Analog Front End (AFE) ........................................................... 13 Digital Inputs .............................................................................. 27 Standard Definition Processor (SDP) ...................................... 14 Power Supply Sequencing .............................................................. 15 MIPI Outputs (D0P, D0N, CLKP, CLKN) ADV7282-M Only .............................................................................................. 27 Optimal Power-Up Sequence.................................................... 15 Typical Circuit Connection ........................................................... 28 Simplified Power-Up Sequence ................................................ 15 Outline Dimensions ....................................................................... 30 Power-Down Sequence .............................................................. 15 Ordering Guide .......................................................................... 30 DVDDIO Supply Voltage ................................................................ 15 Automotive Products ................................................................. 30 2 Input Networks ............................................................................... 16 REVISION HISTORY 3/14—Rev. A to Rev. B Changes to General Description .................................................... 1 Change to Single CVBS Input, Analog Supply Current, Power Requirements Parameter, Table 1 ................................................... 4 Changes to Table 7 .......................................................................... 10 Changes to Theory of Operation Section .................................... 13 Changes to DVDDIO Supply Voltage Section .................................. 15 Changes to Short-to-Battery Protection Section ........................ 16 Changes to Ordering Guide .......................................................... 30 11/13—Rev. 0 to Rev. A Changes to Features Section and General Description Section ... 1 Added Figure 1; Renumbered Sequentially .................................. 3 Changes to Table 1 ............................................................................ 4 Added Pixel Port Timing Specifications (ADV7282 Only) Section ................................................................................................ 9 Added Endnote 1; Table 7 ............................................................. 10 Added Figure 6 and Table 9 .......................................................... 11 Changes to Theory of Operation Section.................................... 13 Changes to DVDDIO Supply Voltage Section.................................. 15 Changes to Table 12 ....................................................................... 17 Changes to Programming the STB Diagnostic Function Section.............................................................................................. 18 Added ITU-R BT.656 Tx Configuration (ADV7282 Only) Section.............................................................................................. 22 Changes to Register Maps Section ............................................... 25 Changes to Power Supply Decoupling Section and Digital Outputs Section .............................................................................. 27 Changes to Typical Circuit Connections Section ...................... 28 Changes to Ordering Guide .......................................................... 30 8/13—Revision 0: Initial Version Rev. B | Page 2 of 32 Data Sheet ADV7282 FUNCTIONAL BLOCK DIAGRAMS ADV7282 CLOCK PROCESSING BLOCK XTALP PLL ADLLT PROCESSING 10-BIT ADC DIGITAL PROCESSING BLOCK LLC 2D COMB + SHA AA FILTER ADC – VBI SLICER COLOR DEMOD AA FILTER DIAGNOSTICS DIAG1 I2P ACE DOWN DITHER INTRQ I2C/CONTROL REFERENCE 8-BIT PIXEL DATA P0 TO P7 11534-200 AA FILTER OUTPUT BLOCK AIN3 AIN4 AA FILTER MUX BLOCK DIFFERENTIAL OR SINGLE-ENDED ANALOG VIDEO INPUTS AIN1 AIN2 FIFO XTALN SCLK SDATA ALSB RESET PWRDWN DIAG2 Figure 1. ADV7282 Functional Block Diagram ADV7282-M CLKP CLOCK PROCESSING BLOCK XTALP PLL MIPI Tx ADLLT PROCESSING XTALN CLKN D0P AIN5 AIN6 AA FILTER 2D COMB + SHA AA FILTER DIGITAL PROCESSING BLOCK ADC – VBI SLICER COLOR DEMOD AA FILTER DIAGNOSTICS DIAG1 DIAG2 I2P ACE DOWN DITHER I2C/CONTROL REFERENCE SCLK SDATA ALSB RESET PWRDWN Figure 2. ADV7282-M Functional Block Diagram Rev. B | Page 3 of 32 GPO0 GPO1 GPO2 INTRQ 11534-001 AIN3 AIN4 MUX BLOCK DIFFERENTIAL OR SINGLE-ENDED ANALOG VIDEO INPUTS AA FILTER OUTPUT BLOCK 10-BIT ADC AIN1 AIN2 FIFO D0N ADV7282 Data Sheet SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Note that MVDD only applies to the ADV7282-M. Table 1. Parameter STATIC PERFORMANCE ADC Resolution Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Symbol Test Conditions/Comments N INL DNL CVBS mode CVBS mode VIH Input Low Voltage VIL Input Leakage Current IIN Input Capacitance CRYSTAL INPUT Input High Voltage Input Low Voltage DIGITAL OUTPUTS Output High Voltage CIN Output Low Voltage VOL High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 1, 2, 3 Digital I/O Power Supply Typ −10 −10 −10 1.2 VOH DVDDIO = 3.3 V, ISOURCE = 0.4 mA DVDDIO = 1.8 V, ISOURCE = 0.4 mA, ADV7282 only DVDDIO = 3.3 V, ISINK = 3.2 mA DVDDIO = 1.8 V, ISINK = 1.6 mA, ADV7282 only 2.4 1.4 PVDD AVDD DVDD MVDD IDVDDIO PLL Supply Current MIPI Tx Supply Current Analog Supply Current Single-Ended CVBS Input Differential CVBS Input IPVDD IMVDD IAVDD ADV7282-M only ADV7282-M ADV7282 ADV7282-M only Fully differential and pseudo differential CVBS 10 Bits LSB LSB 2.97 1.62 1.71 1.71 1.71 1.71 0.8 0.4 +10 +15 +50 10 V V V V µA µA µA pF 0.4 V V V V ILEAK COUT ADV7282-M ADV7282 Unit 2 1.2 XTALN pin XTALN pin DVDDIO Max 2 ±0.6 VIH VIL PLL Power Supply Analog Power Supply Digital Power Supply MIPI Tx Power Supply Digital I/O Supply Current Y/C Input YPrPb Input Digital Supply Current Single-Ended CVBS Input Differential CVBS Input DVDDIO = 3.3 V DVDDIO = 1.8 V, ADV7282 only DVDDIO = 3.3 V DVDDIO = 1.8 V, ADV7282 only RESET pin SDATA, SCLK pins PWRDWN, ALSB pins Min 3.3 3.3 1.8 1.8 1.8 1.8 1.5 5 12 14 0.4 0.2 V V 10 20 µA pF 3.63 3.63 1.89 1.89 1.89 1.89 V V V V V V mA mA mA mA 47 69 mA mA 60 75 mA mA 70 70 mA mA 70 70 mA mA IDVDD Fully differential and pseudo differential CVBS Y/C Input YPrPb Input Rev. B | Page 4 of 32 Data Sheet Parameter POWER-DOWN CURRENTS1 Digital I/O Supply Power-Down Current PLL Supply Power-Down Current Analog Supply Power-Down Current Digital Supply Power-Down Current MIPI Tx Supply Power-Down Current Total Power Dissipation in Power-Down Mode ADV7282 Symbol Test Conditions/Comments Min IDVDDIO_PD IPVDD_PD IAVDD_PD IDVDD_PD IMVDD_PD Typ Max 73 46 0.2 420 4.5 1 Unit µA µA µA µA µA mW Guaranteed by characterization. Typical current consumption values are measured with nominal voltage supply levels and an SMPTE bar test pattern. 3 All specifications apply when the I2P core is activated, unless otherwise stated. 1 2 VIDEO SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7282-M. Table 2. Parameter NONLINEAR SPECIFICATIONS 1 Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS Signal-to-Noise Ratio, Unweighted Analog Front-End Crosstalk Common-Mode Rejection Ratio 2 LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range fSC Subcarrier Lock Range Color Lock-In Time Synchronization Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed 3 Fast Switch Speed 4 LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy Symbol Test Conditions/Comments Min DP DG LNL CVBS input, modulated 5-step CVBS input, modulated 5-step CVBS input, 5-step 0.9 0.5 2.0 Degrees % % SNR Luma ramp Luma flat field 57.1 58 60 73 dB dB dB dB CMRR Typ −5 40 Max +5 70 Unit 2 100 100 % Hz kHz Lines % % Fields Lines ms 1 1 % % ±1.3 60 20 5 200 200 CVBS, 1 V input These specifications apply for all CVBS input types (NTSC, PAL, and SECAM), as well as for single-ended and differential CVBS inputs. The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Networks section). The CMRR measurement was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz. 3 Autodetection switch speed is the time required for the ADV7282/ADV7282-M to detect which video format is present at its input, for example, PAL I or NTSC M. 4 Fast switch speed is the time required for the ADV7282/ADV7282-M to switch from one analog input (single-ended or differential) to another, for example, switching from AIN1 to AIN2. 1 2 Rev. B | Page 5 of 32 ADV7282 Data Sheet ANALOG SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7282-M. Table 3. Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current Test Conditions/Comments Min Typ Max 0.1 10 0.4 0.4 10 10 Clamps switched off Unit µF MΩ mA mA µA µA CLOCK AND I2C TIMING SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7282-M. Table 4. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDATA Setup Time SCLK and SDATA Rise Times SCLK and SDATA Fall Times Setup Time (Stop Condition) RESET INPUT RESET Pulse Width Symbol Min Typ Max Unit ±50 MHz ppm 28.63636 400 t1 t2 t3 t4 t5 t6 t7 t8 kHz µs µs µs µs ns ns ns µs 0.6 1.3 0.6 0.6 100 300 300 0.6 5 ms t3 t5 t3 SDATA t2 t4 t7 2 Figure 3. I C Timing Diagram Rev. B | Page 6 of 32 t8 11534-002 t1 t6 SCLK Data Sheet ADV7282 MIPI VIDEO OUTPUT SPECIFICATIONS (ADV7282-M ONLY) AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. The CSI-2 clock lane of the ADV7282-M remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements were performed with the ADV7282-M operating in progressive mode and with a nominal 432 Mbps output data rate. Specifications guaranteed by characterization. Table 5. Parameter UNIT INTERVAL Interlaced Output Progressive Output DATA LANE LP TX DC SPECIFICATIONS 1 Thevenin Output High Level Thevenin Output Low Level DATA LANE LP TX AC SPECIFICATIONS1 Rise Time, 15% to 85% Fall Time, 85% to 15% Rise Time, 30% to 85% Data Lane LP Slew Rate vs. CLOAD Maximum Slew Rate over Entire Vertical Edge Region Symbol UI Minimum Slew Rate 400 mV ≤ VOUT ≤ 930 mV 400 mV ≤ VOUT ≤ 700 mV 700 mV ≤ VOUT ≤ 930 mV DATA LANE HS TX SIGNALING REQUIREMENTS Low Power to High Speed Transition Stage VOH VOL 1.1 −50 Typ Max t9 t11 |V1| ns ns V mV 25 25 35 ns ns ns Rising edge 150 mV/ns Falling edge 150 mV/ns VOH VOL 1.2 0 Unit 1.3 +50 Falling edge Rising edge Rising edge First clock pulse after stop state or last pulse before stop state All other clock pulses t10 High Speed Differential Voltage Swing Differential Voltage Mismatch Single-Ended Output High Voltages Static Common-Mode Voltage Level Static Common-Mode Voltage Mismatch Dynamic Common Level Variations 50 MHz to 450 MHz Above 450 MHz Min 4.63 2.31 Minimum Slew Rate 400 mV ≤ VOUT ≤ 930 mV 400 mV ≤ VOUT ≤ 700 mV 700 mV ≤ VOUT ≤ 930 mV Pulse Width of LP Exclusive-OR Clock Period of LP Exclusive-OR Clock CLOCK LANE LP TX DC SPECIFICATIONS1 Thevenin Output High Level Thevenin Output Low Level CLOCK LANE LP TX AC SPECIFICATIONS1 Rise Time, 15% to 85% Fall Time, 85% to 15% Clock Lane LP Slew Rate Maximum Slew Rate over Entire Vertical Edge Region Test Conditions/Comments 30 30 >0 40 mV/ns mV/ns mV/ns ns 20 90 ns ns 1.1 −50 1.2 0 1.3 +50 V mV 25 25 ns ns Rising edge 150 mV/ns Falling edge 150 mV/ns Falling edge Rising edge Rising edge See Figure 4 30 30 >0 mV/ns mV/ns mV/ns Time that the D0P pin is at VOL and the D0N pin is at VOH Time that the D0P and D0N pins are at VOL t10 plus the HS-zero period 50 ns Rev. B | Page 7 of 32 40 + (4 × UI) 145 + (10 × UI) 140 200 150 200 85 + (6 × UI) ns 270 10 360 250 5 ns mV p-p mV mV mV mV 25 15 mV mV ADV7282 Data Sheet Parameter Rise Time, 20% to 80% Fall Time, 80% to 20% High Speed to Low Power Transition Stage Symbol Test Conditions/Comments t12 Time that the ADV7282-M drives the flipped last data bit after sending the last payload data bit of an HS transmission burst Post-end-of-transmission rise time (30% to 85%) Time from start of t12 to start of low power state following an HS transmission burst Time that a low power state is transmitted after an HS transmission burst See Figure 4 t13 t14 t15 CLOCK LANE HS TX SIGNALING REQUIREMENTS Low Power to High Speed Transition Stage 2 Time that the CLKP pin is at VOL and the CLKN pin is at VOH Time that the CLKP and CLKN pins are at VOL Clock HS-zero period High Speed Differential Voltage Swing Differential Voltage Mismatch Single-Ended Output High Voltages Static Common-Mode Voltage Level Static Common-Mode Voltage Mismatch Dynamic Common Level Variations 50 MHz to 450 MHz Above 450 MHz Rise Time, 20% to 80% Fall Time, 80% to 20% HS TX CLOCK TO DATA LANE TIMING REQUIREMENTS Data to Clock Skew 2 Typ Max 0.3 × UI 0.3 × UI Unit ns ns ns 35 ns 105 + (12 × UI) ns 100 ns 50 ns 38 95 ns 270 10 360 250 5 ns mV p-p mV mV mV mV 0.15 0.15 25 15 0.3 × UI 0.3 × UI mV mV ns ns 0.35 × UI 0.65 × UI ns 300 140 500 200 150 200 These measurements were performed with CLOAD = 50 pF. The clock lane remains in high speed mode throughout normal operation. These results apply only to the ADV7282-M during startup. |V2| CLKP/CLKN D0P/D0N t9 t10 t11 VOH |V1| VOL t13 TRANSMIT FIRST DATA BIT t14 LOW POWER TO HIGH SPEED TRANSITION HS-ZERO START OF TRANSMISSION SEQUENCE HIGH SPEED DATA TRANSMISSION Figure 4. ADV7282-M Output Timing Diagram (Conforms with MIPI CSI-2 Specification) Rev. B | Page 8 of 32 t12 t15 HS-TRAIL HIGH SPEED TO LOW POWER TRANSITION 11534-003 1 |V2| Min 0.15 0.15 60 + (4 × UI) Data Sheet ADV7282 PIXEL PORT TIMING SPECIFICATIONS (ADV7282 ONLY) AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. Table 6. Parameter CLOCK OUTPUTS LLC Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transitional Time Symbol Test Conditions/Comments Min t16:t17 Typ 45:55 t18 Negative clock edge to start of valid data (tSETUP = t17 − t18) End of valid data to negative clock edge (tHOLD = t16 − t19) t19 t17 t16 OUTPUT LLC t18 11534-201 t19 OUTPUTS P0 TO P7 Figure 5. ADV7282 Pixel Port and Control Output Timing Diagram Rev. B | Page 9 of 32 Max Unit 55:45 % duty cycle 3.8 ns 6.9 ns ADV7282 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 7. Parameter1 AVDD to GND DVDD to GND PVDD to GND MVDD to GND2 DVDDIO to GND PVDD to DVDD MVDD to DVDD2 AVDD to DVDD Digital Inputs Voltage Digital Outputs Voltage Analog Inputs to Ground Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 2.2 V 2.2 V 2.2 V 2.2 V 4V −0.9 V to +0.9 V −0.9 V to +0.9 V −0.9 V to +0.9 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to AVDD + 0.3 V 140°C −65°C to +150°C 260°C The Absolute Maximum Ratings assumes that DGND pins and the exposed pad of the ADV7282/ADV7282-M are connected together to a common ground plane (GND). This is part of the recommended layout scheme. See PCB Layout Recommendations section for more information. The Absolute Maximum Ratings are stated in relation to this common ground plane. 2 MVDD applies to the ADV7282-M only. 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The thermal resistance values in Table 8 are specified for the device soldered onto a 4-layer printed circuit board (PCB) with a common ground plane and with the exposed pad of the device connected to DGND. The values in Table 8 are maximum values. Table 8. Thermal Resistance for the 32-Lead LFCSP Thermal Characteristic Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Symbol θJA Value 32.5 Unit °C/W θJC 2.3 °C/W REFLOW SOLDER The ADV7282/ADV7282-M is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can withstand surface-mount soldering at up to 255°C (±5°C). In addition, the ADV7282/ADV7282-M is backwardcompatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C. ESD CAUTION This device is a high performance integrated circuit with an ESD rating of