ADV7340

Multiformat Video Encoder, Six 12-Bit Noise Shaped Video® DACS ADV7340/ADV7341 FEATURES 74.25 MHz 20-/30-bit high definition input support Compliant with SMPTE 274 M (1080i), 296 M (720p), and 240 M (1035i) 6 Noise Shaped Video (NSV)12-bit video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 YCrCb (ED and HD) 4:4:4 RGB (SD, ED, and HD) Multiformat video output support Composite (CVBS) and S-Video (Y/C) Component YPrPb (SD, ED, and HD) Component RGB (SD, ED, and HD) Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Simultaneous SD and ED/HD operation EIA/CEA-861B compliance support Programmable features Luma and chroma filter responses Vertical blanking interval (VBI) Subcarrier frequency (FSC) and phase Luma delay Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern generation On-board voltage reference (optional external input) Serial MPU interface with dual I2C® and SPI® compatibility 3.3 V analog operation 1.8 V digital operation 3.3 V I/O operation Temperature range: −40°C to +85°C APPLICATIONS DVD recorders and players High definition Blu-ray DVD players HD-DVD players FUNCTIONAL BLOCK DIAGRAM DGND (2) VDD (2) SCL/ SDA/ ALSB/ MOSI SCLK SPI_SS SFL/ MISO AGND VAA GND_IO VDD_IO VBI DATA SERVICE INSERTION MPU PORT SUBCARRIER FREQUENCY LOCK (SFL) ADV7340/ADV7341 12-BIT DAC 1 DAC 1 10-BIT SD VIDEO DATA 4:2:2 TO 4:4:4 HD DDR DEINTERLEAVE ADD BURST PROGRAMMABLE CHROMINANCE FILTER RGB MULTIPLEXER RGB/YCrCb TO YUV MATRIX ADD SYNC PROGRAMMABLE LUMINANCE FILTER YUV TO YCrCb/ RGB SIN/COS DDS BLOCK 16× FILTER 12-BIT DAC 2 12-BIT DAC 3 12-BIT DAC 4 12-BIT DAC 5 DAC 2 16× FILTER DAC 3 R G/B 20-BIT ED/HD VIDEO DATA RGB ASYNC BYPASS YCbCr DAC 4 ED/HD INPUT DEINTERLEAVE PROGRAMMABLE HDTV FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL HDTV TEST PATTERN GENERATOR YCbCr TO RGB MATRIX DAC 5 4× FILTER 12-BIT DAC 6 DAC 6 POWER MANAGEMENT CONTROL VIDEO TIMING GENERATOR 16x/4x OVERSAMPLING DAC PLL REFERENCE AND CABLE DETECT RSET (2) P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC CLKIN (2) PVDD PGND EXT_LF (2) VREF COMP (2) Figure 1. Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights. Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 06398-001 ADV7340/ADV7341 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Detailed Features .............................................................................. 4 General Description ......................................................................... 4 Specifications..................................................................................... 5 Power Supply and Voltage Specifications.................................. 5 Voltage Reference Specifications ................................................ 5 Input Clock Specifications .......................................................... 5 Analog Output Specifications..................................................... 6 Digital Input/Output Specifications........................................... 6 Digital Timing Specifications ..................................................... 7 MPU Port Timing Specifications ............................................... 8 Power Specifications .................................................................... 8 Video Performance Specifications ............................................. 9 Timing Diagrams............................................................................ 10 Absolute Maximum Ratings.......................................................... 18 Thermal Resistance .................................................................... 18 ESD Caution................................................................................ 18 Pin Configuration and Function Descriptions........................... 19 Typical Performance Characteristics ........................................... 21 MPU Port Description................................................................... 26 I2C Operation.............................................................................. 26 SPI Operation.............................................................................. 27 Register Map Access....................................................................... 28 Register Programming............................................................... 28 Subaddress Register (SR7 to SR0) ............................................ 28 Input Configuration ....................................................................... 45 Standard Definition Only.......................................................... 45 Enhanced Definition/High Definition Only .......................... 46 Simultaneous Standard Definition and Enhanced Definition/High Definition....................................................... 46 Enhanced Definition Only (at 54 MHz) ................................. 47 Output Configuration .................................................................... 48 Features ............................................................................................ 49 Output Oversampling ................................................................ 49 ED/HD Nonstandard Timing Mode........................................ 49 ED/HD Timing Reset ................................................................ 50 SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and Timing Reset ....................................................................... 50 SD VCR FF/RW Sync ................................................................ 51 Vertical Blanking Interval ......................................................... 51 SD Subcarrier Frequency Registers.......................................... 51 SD Noninterlaced Mode............................................................ 52 SD Square Pixel Mode ............................................................... 52 Filters............................................................................................ 53 ED/HD Test Pattern Color Controls ....................................... 54 Color Space Conversion Matrix ............................................... 54 SD Luma and Color Control..................................................... 55 SD Hue Adjust Control.............................................................. 56 SD Brightness Detect ................................................................. 56 SD Brightness Control............................................................... 56 SD Input Standard Auto Detection.......................................... 56 Double Buffering ........................................................................ 57 Programmable DAC Gain Control .......................................... 57 Gamma Correction .................................................................... 57 ED/HD Sharpness Filter and Adaptive Filter Controls........ 59 ED/HD Sharpness Filter and Adaptive Filter Application Examples...................................................................................... 60 SD Digital Noise Reduction...................................................... 61 SD Active Video Edge Control ................................................. 62 External Horizontal and Vertical Synchronization Control ........................................................... 64 Low Power Mode........................................................................ 65 Cable Detection .......................................................................... 65 DAC Auto Power-Down............................................................ 65 Pixel and Control Port Readback............................................. 65 Reset Mechanism........................................................................ 65 Printed Circuit Board Layout and Design .................................. 66 DAC Configurations.................................................................. 66 Voltage Reference ....................................................................... 66 Video Output Buffer and Optional Output Filter.................. 66 Printed Circuit Board (PCB) Layout ....................................... 67 Typical Application Circuit....................................................... 69 Appendix 1—Copy Generation Management System .............. 70 SD CGMS .................................................................................... 70 ED CGMS.................................................................................... 70 HD CGMS................................................................................... 70 CGMS CRC Functionality ........................................................ 70 Rev. 0 | Page 2 of 88 ADV7340/ADV7341 Appendix 2—SD Wide Screen Signaling .....................................73 Appendix 3—SD Closed Captioning............................................74 Appendix 4—Internal Test Pattern Generation ..........................75 SD Test Patterns...........................................................................75 ED/HD Test Patterns ..................................................................75 Appendix 5—SD Timing................................................................76 Appendix 6—HD Timing ..............................................................81 Appendix 7—Video Output Levels...............................................82 SD YPrPb Output Levels—SMPTE/EBU N10........................82 ED/HD YPrPb Output Levels ...................................................83 SD/ED/HD RGB Output Levels................................................84 SD Output Plots ..........................................................................85 Appendix 8—Video Standards ......................................................86 Outline Dimensions........................................................................88 Ordering Guide ...........................................................................88 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 3 of 88 ADV7340/ADV7341 DETAILED FEATURES High definition (HD) programmable features (720p/1080i/1035i) 4× oversampling (297 MHz) Internal test pattern generator Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS (720p/1080i) and CGMS Type B (720p/1080i) Undershoot limiter Dual data rate (DDR) input support EIA/CEA-861B compliance support Enhanced definition(ED) programmable features (525p/625p) 8× oversampling (216 MHz output) Internal test pattern generator Color and black bar, hatch, flat field/frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) CGMS (525p/625p) and CGMS Type B (525p) Dual data rate (DDR) input support EIA/CEA-861B compliance support Standard definition (SD) programmable features 16× oversampling (216 MHz) Internal test pattern generator Color and black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAF™ filter with programmable gain/attenuation PrPb SSAF™ Separate pedestal control on component and composite/S-Video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 Copy generation management system (CGMS) Wide screen signaling Closed captioning EIA/CEA-861B compliance support The ADV7340/ADV7341 each have a 30-bit pixel input port that can be configured in a variety of ways. SD video formats are supported over a SDR interface and ED/HD video formats are supported over SDR and DDR interfaces. Pixel data can be supplied in either the YCrCb or RGB color spaces. The parts also support embedded EAV/SAV timing codes, external video synchronization signals, and I2C and SPI communication protocols. In addition, simultaneous SD and ED/HD input and output are supported. 216 MHz (SD and ED) and 297 MHz (HD) oversampling ensures that external output filtering is not required, while full-drive DACs ensure that external output buffering is not required. Cable detection and DAC auto power-down features keep power consumption to a minimum. Table 1 lists the video standards directly supported by the ADV7340/ADV7341. Table 1. Standards Directly Supported by the ADV7340/ADV7341 1 Resolution 720 × 240 720 × 288 720 × 480 720 × 576 720 × 480 720 × 576 720 × 483 720 × 483 720 × 483 720 × 576 720 × 483 720 × 576 1920 × 1035 1920 × 1035 1280 × 720 1280 × 720 I/P 2 P P I I I I P P P P P P I I P P Frame Rate (Hz) 59.94 50 29.97 25 29.97 25 59.94 59.94 59.94 50 59.94 50 30 29.97 60, 50, 30, 25, 24 23.97, 59.94, 29.97 30, 25 29.97 30, 25, 24 23.98, 29.97 24 Clock Input (MHz) 27 27 27 27 24.54 29.5 27 27 27 27 27 27 74.25 74.1758 74.25 74.1758 Standard ITU-R BT.601/656 ITU-R BT.601/656 NTSC Square Pixel PAL Square Pixel SMPTE 293M BTA T-1004 ITU-R BT.1358 ITU-R BT.1358 ITU-R BT.1362 ITU-R BT.1362 SMPTE 240M SMPTE 240M SMPTE 296M SMPTE 296M GENERAL DESCRIPTION The ADV7340/ADV7341 are high speed, digital-to-analog video encoders in a 64-lead LQFP package. Six high speed, NSV, 3.3 V, 12-bit video DACs provide support for composite (CVBS), S-Video (Y/C), and component (YPrPb/RGB) analog outputs in either standard definition (SD), enhanced definition (ED), or high definition (HD) video formats. 1920 × 1080 1920 × 1080 1920 × 1080 1920 × 1080 1920 × 1080 1 2 I I P P P 74.25 74.1758 74.25 74.1758 74.25 SMPTE 274M SMPTE 274M SMPTE 274M SMPTE 274M ITU-R BT.709-5 Other standards are supported in the ED/HD nonstandard timing mode. I = interlaced, P = progressive. Rev. 0 | Page 4 of 88 ADV7340/ADV7341 SPECIFICATIONS POWER SUPPLY AND VOLTAGE SPECIFICATIONS All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 2. Parameter SUPPLY VOLTAGES VDD VDD_IO PVDD VAA POWER SUPPLY REJECTION RATIO Conditions Min 1.71 2.97 1.71 2.6 Typ 1.8 3.3 1.8 3.3 0.002 Max 1.89 3.63 1.89 3.465 Unit V V V V %/% VOLTAGE REFERENCE SPECIFICATIONS All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 3. Parameter Internal Reference Range, VREF External Reference Range, VREF External VREF Current 1 1 Conditions Min 1.186 1.15 Typ 1.248 1.235 ±10 Max 1.31 1.31 Unit V V μA External current required to overdrive internal VREF. INPUT CLOCK SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 4. Parameter fCLKIN_A fCLKIN_A fCLKIN_A fCLKIN_B fCLKIN_B CLKIN_A High Time, t9 CLKIN_A Low Time, t10 CLKIN_B High Time, t9 CLKIN_B Low Time, t10 CLKIN_A Peak-to-Peak Jitter Tolerance CLKIN_B Peak-to-Peak Jitter Tolerance 1 Conditions 1 SD/ED ED (at 54 MHz) HD ED HD Min Typ 27 54 74.25 27 74.25 Max 40 40 40 40 2 2 Unit MHz MHz MHz MHz MHz % of one clock cycle % of one clock cycle % of one clock cycle % of one clock cycle ±ns ±ns SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition. Rev. 0 | Page 5 of 88 ADV7340/ADV7341 ANALOG OUTPUT SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. VREF = 1.235 V (driven externally). All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 5. Parameter Full-Drive Output Current (Full-Scale) 1 Low Drive Output Current (Full-Scale) 2 DAC-to-DAC Matching Output Compliance, VOC Output Capacitance, COUT Analog Output Delay 3 DAC Analog Output Skew Conditions RSET = 510 Ω, RL = 37.5 Ω RSET = 4.12 kΩ, RL = 300 Ω DAC 1 to DAC 6 DAC 1, DAC 2, DAC 3 DAC 4, DAC 5, DAC 6 DAC 1, DAC 2, DAC 3 DAC 4, DAC 5, DAC 6 DAC 1, DAC 2, DAC 3 DAC 4, DAC 5, DAC 6 Min 33 4.1 0 10 6 8 6 2 1 Typ 34.6 4.3 1.0 Max 37 4.5 1.4 Unit mA mA % V pF pF ns ns ns ns 1 2 Applicable to full-drive capable DACs only, that is, DAC 1, DAC 2, DAC 3. Applicable to all DACs. 3 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition. DIGITAL INPUT/OUTPUT SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 6. Parameter Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIN Input Capacitance, CIN Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance Conditions Min 2.0 Typ Max 0.8 ±10 4 ISOURCE = 400 μA ISINK = 3.2 mA VIN = 0.4 V, 2.4 V 2.4 0.4 ±1.0 4 Unit V V μA pF V V μA pF VIN = VDD_IO Rev. 0 | Page 6 of 88 ADV7340/ADV7341 DIGITAL TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 7. Parameter VIDEO DATA AND VIDEO CONTROL PORT 2, 3 Data Setup Time, t11 4 Conditions 1 SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) Min 2.1 2.3 2.3 1.7 1.0 1.1 1.1 1.0 2.1 2.3 1.7 1.0 1.1 1.0 12 10 4.0 3.5 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Hold Time, t124 Control Setup Time, t114 Control Hold Time, t124 Digital Output Access Time, t134 Digital Output Hold Time, t144 PIPELINE DELAY 5 SD 1 CVBS/YC Outputs (2×) CVBS/YC Outputs (16×) Component Outputs (2×) Component Outputs (16×) E D1 Component Outputs (1×) Component Outputs (8×) H D1 Component Outputs (1×) Component Outputs (4×) 1 2 SD oversampling disabled SD oversampling enabled SD oversampling disabled SD oversampling enabled ED oversampling disabled ED oversampling enabled HD oversampling disabled HD oversampling enabled 68 67 78 84 41 46 40 44 clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. Video data: C[9:0], Y[9:0], and S[9:0]. 3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design. Rev. 0 | Page 7 of 88 ADV7340/ADV7341 MPU PORT TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 8. Parameter MPU PORT, I2C MODE 1 SCL Frequency SCL High Pulse Width, t1 SCL Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDA, SCL Rise Time, t6 SDA, SCL Fall Time, t7 Setup Time (Stop Condition), t8 MPU PORT, SPI MODE1 SCLK Frequency SPI_SS to SCLK Setup Time, t1 SCLK High Pulse Width, t2 SCLK Low Pulse Width, t3 Data Access Time after SCLK Falling Edge, t4 Data Setup Time prior to SCLK Rising Edge, t5 Data Hold Time after SCLK Rising Edge, t6 SPI_SS to SCLK Hold Time, t7 SPI_SS to MISO High Impedance, t8 1 Conditions See Figure 19 Min 0 0.6 1.3 0.6 0.6 100 Typ Max 400 Unit kHz μs μs μs μs ns ns ns μs MHz ns ns ns ns ns ns ns ns 300 300 0.6 See Figure 20 0 20 50 50 20 0 0 40 10 35 Guaranteed by characterization. POWER SPECIFICATIONS VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = 25°C. Table 9. Parameter NORMAL POWER MODE 1, 2 IDD 3 Conditions SD only (16× oversampling) ED only (8× oversampling) 4 HD only (4× oversampling)4 SD (16× oversampling) and ED (8× oversampling) SD (16× oversampling) and HD (4× oversampling) 3 DACs enabled (ED/HD only) 6 DACs enabled (SD only and simultaneous modes ) SD only, ED only or HD only modes Simultaneous modes Min Typ 90 65 91 95 122 1 124 140 5 10 5 0.3 0.2 0.1 Max Unit mA mA mA mA mA mA mA mA mA mA μA μA μA μA IDD_IO IAA IPLL SLEEP MODE IDD IAA IDD_IO IPLL 1 2 RSET1 = 510 Ω (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). RSET2 = 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode). 75% color bar test pattern applied to pixel data pins. 3 IDD is the continuous current required to drive the digital core. 4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes. Rev. 0 | Page 8 of 88 ADV7340/ADV7341 VIDEO PERFORMANCE SPECIFICATIONS VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = 25°C, VREF driven externally. Table 10. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity 1 +ve Differential Nonlinearity1 −ve STANDARD DEFINTION (SD) MODE Luminance Nonlinearity Differential Gain Differential Phase SNR SNR ENHANCED DEFINITION (ED) MODE Luma Bandwidth Chroma Bandwidth HIGH DEFINITION (HD) MODE Luma Bandwidth Chroma Bandwidth 1 Conditions Min Typ 12 0.75 1 0.25 0.8 0.43 0.35 0.35 0.3 0.4 63 79.5 12.5 5.8 30 13.75 Max Unit Bits LSBs LSBs LSBs LSBs LSBs LSBs ±% % Degrees dB dB MHz MHz MHz MHz RSET1 = 510 Ω, RL1 = 37.5 Ω RSET2 = 4.12 kΩ, RL2 = 300 Ω RSET1 = 510 Ω, RL1 = 37.5 Ω RSET2 = 4.12 kΩ, RL2 = 300 Ω RSET1 = 510 Ω, RL1 = 37.5 Ω RSET2 = 4.12 kΩ, RL2 = 300 Ω NTSC NTSC Luma ramp Flat field full bandwidth Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value. For −ve DNL, the actual step value lies below the ideal step value. Rev. 0 | Page 9 of 88 ADV7340/ADV7341 TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 13: • • • • t9 = Clock high time t10 = Clock low time t11 = Data setup time t12 = Data hold time CLKIN_A • • t13 = Control output access time t14 = Control output hold time In addition, refer to Table 31 for the ADV7340/ADV7341 input configuration. t9 CONTROL INPUTS S_HSYNC, S_VSYNC t10 t12 IN SLAVE MODE S9 TO S0/ Y9 TO Y0* Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 CONTROL OUTPUTS t13 IN MASTER/SLAVE MODE t14 *SELECTED BY SUBADDRESS 0x01, BIT 7. 06398-002 Figure 2. SD Only, 8-/10-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000) CLKIN_A t9 CONTROL INPUTS S_HSYNC, S_VSYNC S9 TO S0/ Y9 TO Y0* Y9 TO Y0/ C9 TO C0* t10 t12 IN SLAVE MODE Y0 Y1 Y2 Y3 Cb0 Cr0 Cb2 Cr2 t11 CONTROL OUTPUTS t13 IN MASTER/SLAVE MODE 06398-003 t14 *SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 3. SD Only, 16-/20-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000) Rev. 0 | Page 10 of 88 ADV7340/ADV7341 CLKIN_A t9 CONTROL INPUTS S_HSYNC, S_VSYNC t10 t12 Y9 TO Y2/ Y9 TO Y0 C9 TO C2/ C9 TO C0 G0 G1 G2 B0 B1 B2 t11 S9 TO S2/ S9 TO S0 CONTROL OUTPUTS 06398-004 R0 R1 R2 t14 t13 Figure 4. SD Only, 24-/30-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000) CLKIN_A t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y9 TO Y2/ Y9 TO Y0 C9 TO C2/ C9 TO C0 Y0 Cb0 t10 t12 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y4 Cb4 Y5 Cr4 t11 CONTROL OUTPUTS t13 06398-005 t14 Figure 5. ED/HD-SDR Only, 16-/20-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 001) CLKIN_A t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y9 TO Y2/ Y9 TO Y0 C9 TO C2/ C9 TO C0 Y0 t10 t12 Y1 Cb1 Y2 Cb2 Y3 Cb3 Y4 Cb4 Y5 Cb5 Cb0 t11 S9 TO S2/ S9 TO S0 CONTROL OUTPUTS 06398-006 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 t14 t13 Figure 6. ED/HD-SDR Only, 24-/30-Bit, 4:4:4 YCrCb Pixel Input Mode (Input Mode 001) Rev. 0 | Page 11 of 88 ADV7340/ADV7341 CLKIN_A t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y9 TO Y2/ Y9 TO Y0 C9 TO C2/ C9 TO C0 G0 B0 t10 t12 G1 B1 G2 B2 G3 B3 G4 B4 G5 B5 t11 S9 TO S2/ S9 TO S0 CONTROL OUTPUTS 06398-007 R0 R1 R2 R3 R4 R5 t14 t13 Figure 7. ED/HD-SDR Only, 24-/30-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001) CLKIN_A* t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y9 TO Y2/ Y9 TO Y0 Cb0 Y0 t10 Cr0 Y1 Cb2 Y2 Cr2 t11 CONTROL OUTPUTS t12 t11 t12 t13 t14 *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. 06398-008 Figure 8. ED/HD-DDR Only, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 010) CLKIN_A* t9 Y9 TO Y2/ Y9 TO Y0 3FF 00 t10 00 XY Cb0 Y0 Cr0 Y1 t11 CONTROL OUTPUTS t12 t11 t12 t13 *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 9. ED/HD-DDR Only, 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010) Rev. 0 | Page 12 of 88 06398-009 t14 ADV7340/ADV7341 CLKIN_B t9 CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y9 TO Y2/ Y9 TO Y0 C9 TO C2/ C9 TO C0 Y0 Cb0 t10 t12 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y4 Cb4 Y5 Cr4 Y6 Cb6 ED/HD INPUT t11 CLKIN_A t9 CONTROL INPUTS S_HSYNC, S_VSYNC S9 TO S2/ S9 TO S0 Cb0 t10 t12 SD INPUT 06398-010 Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 Figure 10. SD, ED/HD-SDR Input Mode, 16-/20-Bit, 4:2:2 ED/HD and 8-/10-Bit, SD Pixel Input Mode (Input Mode 011) CLKIN_B P_HSYNC, P_VSYNC, P_BLANK Y9 TO Y2/ Y9 TO Y0 Cb0 t9 t10 CONTROL INPUTS EH/HD INPUT Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 t12 t11 t12 CLKIN_A t9 CONTROL INPUTS S_HSYNC, S_VSYNC t10 t12 SD INPUT 06398-011 S9 TO S2/ S9 TO S0 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 Figure 11. SD, ED/HD-DDR Input Mode, 8-/10-Bit, 4:2:2 ED/HD and 8-/10-Bit, SD Pixel Input Mode (Input Mode 100) CLKIN_A CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y9 TO Y2/ Y9 TO Y0 t9 t10 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 t11 CONTROL OUTPUTS t12 t13 t14 06398-012 Figure 12. ED Only (at 54 MHz), 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 111) Rev. 0 | Page 13 of 88 ADV7340/ADV7341 CLKIN_A t9 Y9 TO Y2/ Y9 TO Y0 3FF t10 00 00 XY Cb0 Y0 Cr0 Y1 t11 CONTROL OUTPUTS t12 t13 t14 06398-013 Figure 13. ED Only (at 54 MHz), 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111) Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y9 TO Y2/ Y9 TO Y0 Y0 Y1 Y2 Y3 C9 TO C2/ C9 TO C0 Cb0 Cr0 Cb2 Cr2 b a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 14. ED-SDR, 16-/20-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Rev. 0 | Page 14 of 88 06398-014 ADV7340/ADV7341 Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y9 TO Y2/ Y9 TO Y0 Cb0 Y0 Cr0 Y1 b a = 32 CLKCYCLES FOR 525p a = 24 CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. 06398-015 Figure 15. ED-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y9 TO Y2/ Y9 TO Y0 Y0 Y1 Y2 Y3 C9 TO C2/ C9 TO C0 Cb0 Cr0 Cb2 Cr2 b a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 16. HD-SDR, 16-/20-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Rev. 0 | Page 15 of 88 06398-016 ADV7340/ADV7341 Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y9 TO Y2/ Y9 TO Y0 Cb0 Y0 Cr0 Y1 b a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 17. HD-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram S_HSYNC S_VSYNC S9 TO S0/ Y9 TO Y0* Cb Y Cr Y *SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 18. SD Input Timing Diagram (Timing Mode 1) Rev. 0 | Page 16 of 88 06398-018 PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES 06398-017 ADV7340/ADV7341 t3 SDA t5 t3 t6 SCL t1 t2 t7 t4 2 t8 Figure 19. MPU Port Timing Diagram (I C Mode) SPI_SS t1 SCLK t2 06398-019 t3 t5 t6 D3 D2 D1 D0 X X X X X X X X t7 MOSI X D7 D6 D5 D4 MISO X X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 Figure 20. MPU Port Timing Diagram (SPI Mode) Rev. 0 | Page 17 of 88 06398-020 t4 t8 ADV7340/ADV7341 ABSOLUTE MAXIMUM RATINGS Table 11. Parameter1 VAA to AGND VDD to DGND PVDD to PGND VDD_IO to GND_IO VAA to VDD VDD to PVDD VDD_IO to VDD AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to GND_IO Digital Input Voltage to GND_IO Analog Outputs to AGND Storage Temperature Range (TS) Junction Temperature (TJ) Lead Temperature (Soldering, 10 sec) 1 Rating −0.3 V to +3.9 V −0.3 V to +2.3 V −0.3 V to +2.3 V −0.3 V to +3.9 V −0.3 V to +2.2 V −0.3 V to +0.3 V −0.3 V to +2.2 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to VDD_IO + 0.3 V −0.3 V to VAA −65°C to +150°C 150°C 260°C The ADV7340/ADV7341 are high performance integrated circuits with an ESD rating of THRESHOLD MAIN SIGNAL PATH 06398-077 Y DATA INPUT – + SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL DNR OUT Figure 76. Output Signal from ED/HD Adaptive Filter (Mode B) DNR SHARPNESS MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN SD DIGITAL NOISE REDUCTION Subaddress 0xA3 to Subaddress 0xA5 Digital noise reduction (DNR) is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). There are two DNR modes available: DNR mode and DNR sharpness mode. In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal is subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise. Otherwise, if the level exceeds the threshold, now identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) is added to the original signal to boost high frequency components and sharpen the video image. In MPEG systems, it is common to process the video information in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels × 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset. The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing. NOISE SIGNAL PATH CORING GAIN DATA CORING GAIN BORDER INPUT FILTER BLOCK FILTER OUTPUT > THRESHOLD? FILTER OUTPUT < THRESHOLD MAIN SIGNAL PATH + DNR OUT 06398-078 Y DATA INPUT ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL + Figure 77. SD DNR Block Diagram Coring Gain Border—Subaddress 0xA3, Bits[3:0] These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal. Coring Gain Data—Subaddress 0xA3, Bits[7:4] These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal. Rev. 0 | Page 61 of 88 ADV7340/ADV7341 APPLY DATA CORING GAIN APPLY BORDER CORING GAIN DNR Mode Control—Subaddress 0xA5, Bit 4 This bit controls the DNR mode selected. Logic 0 selects DNR mode; Logic 1 selects DNR sharpness mode. OFFSET CAUSED BY VARIATIONS IN INPUT TIMING 06398-079 OXXXXXXOOXXXXXXO OXXXXXXOOXXXXXXO DNR27 TO DNR24 = 0x01 OXXXXXXOOXXXXXXO DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, because this data is assumed to be valid data and not noise. The overall effect is that the signal is boosted (similar to using the extended SSAF filter). Figure 78. SD DNR Offset Control DNR Threshold—Subaddress 0xA4, Bits[5:0] These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value. Border Area—Subaddress 0xA4, Bit 6 When this bit is set to Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz. 720 × 485 PIXELS (NTSC) 2-PIXEL BORDER DATA DNR Block Offset Control—Subaddress 0xA5, Bits[7:4] Four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. SD ACTIVE VIDEO EDGE CONTROL Subaddress 0x82, Bit 7 8 × 8 PIXEL BLOCK 8 × 8 PIXEL BLOCK The ADV7340/ADV7341 are able to control fast rising and falling signals at the start and end of active video in order to minimize ringing. When the active video edge control feature is enabled (Subaddress 0x82, Bit 7 = 1), the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. At the start of active video, the first three pixels are multiplied by 1/8, 1/2, and 7/8, respectively. Approaching the end of active video, the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively. All other active video pixels pass through unprocessed. Figure 79. SD DNR Border Area Block Size Control—Subaddress 0xA4, Bit 7 This bit is used to select the size of the data blocks to be processed. Setting the block size control function to Logic 1 defines a 16 pixel × 16 pixel data block, and Logic 0 defines an 8 pixel × 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz. DNR Input Select Control—Subaddress 0xA5, Bits[2:0] Three bits are assigned to select the filter, which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that is DNR processed. Figure 80 shows the filter responses selectable with this control. 1.0 FILTER D 0.8 MAGNITUDE FILTER C 0.6 0.4 FILTER B 0.2 FILTER A 06398-081 0 0 1 2 3 4 FREQUENCY (MHz) 5 6 Figure 80. SD DNR Input Select Rev. 0 | Page 62 of 88 06398-080 ADV7340/ADV7341 LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE 100 IRE 87.5 IRE 50 IRE 0 IRE 12.5 IRE 0 IRE LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED Figure 81. Example of Active Video Edge Functionality VOLTS IRE:FLT 100 0.5 50 0 0 –50 0 2 4 6 8 10 12 Figure 82. Example of Video Output with Subaddress 0x82, Bit 7 = 0 VOLTS IRE:FLT 100 0.5 50 0 0 –50 –2 0 2 4 6 8 10 12 Figure 83. Example of Video Output with Subaddress 0x82, Bit 7 = 1 Rev. 0 | Page 63 of 88 06398-084 F2 L135 06398-083 F2 L135 06398-082 ADV7340/ADV7341 EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For synchronization purposes, the ADV7340/ADV7341 are able to accept either time codes embedded in the input pixel data or external synchronization signals provided on the S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK pins (see Table 49). It is also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 50 to Table 52). Table 49. Timing Synchronization Signal Input Options Signal SD HSYNC In SD VSYNC In ED/HD HSYNC In ED/HD VSYNC In ED/HD BLANK In 1 Pin S_HSYNC S_VSYNC P_HSYNC P_VSYNC P_BLANK Condition SD Slave Timing Mode 1, 2, or 3 selected (Subaddress 0x8A[2:0]).1 SD Slave Timing Mode 1, 2, or 3 selected (Subaddress 0x8A[2:0]).1 ED/HD Timing Sync. Inputs enabled (Subaddress 0x30, Bit 2 = 0). ED/HD Timing Sync. Inputs enabled (Subaddress 0x30, Bit 2 = 0). SD and ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02[7:6] = 00). Table 50. Timing Synchronization Signal Output Options Signal SD HSYNC Out SD VSYNC Out ED/HD HSYNC Out ED/HD VSYNC Out 1 Pin S_HSYNC S_VSYNC S_HSYNC S_VSYNC Condition SD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 6 = 1).1 SD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 6 = 1).1 ED/HD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 7 = 1). ED/HD Timing Sync. Outputs enabled (Subaddress 0x02, Bit 7 = 1). ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02, Bit 7 = 0). Table 51. HSYNC Output Control1 ED/HD Input Sync Format (0x30, Bit 2) x x 0 1 x 1 ED/HD HSYNC Control (0x34, Bit 1) x x 0 0 1 ED/HD Sync Output Enable (0x02, Bit 7) 0 0 1 1 1 SD Sync Output Enable (0x02, Bit 6) 0 1 x x x Signal on S_HSYNC Pin Tristate. Pipelined SD HSYNC. Pipelined ED/HD HSYNC. Pipelined ED/HD HSYNC based on AV Code H bit. Pipelined ED/HD HSYNC based on horizontal counter. Duration – See Appendix 5— SD Timing. As per HSYNC timing. Same as line blanking interval. Same as embedded HSYNC. In all ED/HD standards where there is a HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video. Table 52. VSYNC Output Control 1 ED/HD Input Sync Format (0x30, Bit 2) x x 0 1 1 x x ED/HD VSYNC Control (0x34, Bit 2) X X 0 0 0 1 1 ED/HD Sync Output Enable (0x02, Bit 7) 0 0 1 1 1 1 1 SD Sync Output Enable (0x02, Bit 6) 0 1 x x x x x Video Standard x Interlaced x All HD interlaced standards All ED/HD progressive standards All ED/HD standards except 525p 525p Signal on S_VSYNC Pin Tristate. Pipelined SD VSYNC/Field. Pipelined ED/HD VSYNC or field signal. Pipelined field signal based on AV Code F bit. Pipelined VSYNC based on AV Code V bit. Pipelined ED/HD VSYNC based on vertical counter. Pipelined ED/HD VSYNC based on vertical counter. Duration – See Appendix 5— SD Timing. As per VSYNC or field signal timing. Field. Vertical blanking interval. Aligned with serration lines. Vertical blanking interval. 1 In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video. Rev. 0 | Page 64 of 88 ADV7340/ADV7341 LOW POWER MODE Subaddress 0x0D, Bits[2:0] For power sensitive applications, the ADV7340/ADV7341 support an Analog Devices, Inc. proprietary low power mode of operation on DAC 1, DAC 2, and DAC 3. To utilize this low power mode, these DACs must be operating in full-drive mode (RSET = 510 Ω, RL = 37.5 Ω). Low power mode is not available in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Low power mode can be independently enabled or disabled on DAC 1, DAC 2, and DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is disabled by default on each DAC. In low power mode, DAC current consumption is content dependent. On a typical video stream, it can be reduced by as much as 40%. For applications requiring the highest possible video performance, low power mode should be disabled. With this feature enabled, the cable detection circuitry monitors DAC 1 and/or DAC 2 once per frame. If they are unconnected, some or all of the DACs automatically power down. Which DAC or DACs are powered down depends on the selected output configuration. For CVBS/YC output configurations, if DAC 1 is unconnected, only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and DAC 3 power down. For YPrPb and RGB output configurations, if DAC 1 is unconnected, all three DACs power down. DAC 2 is not monitored for YPrPb and RGB output configurations. Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable is detected, the appropriate DAC or DACs remain powered up for the duration of the frame. If no cable is detected, the appropriate DAC or DACs power down until the next frame when the process is repeated. CABLE DETECTION Subaddress 0x10 The ADV7340/ADV7341 include an Analog Devices, Inc. proprietary cable detection feature. The cable detection feature is available on DAC 1 and DAC 2, while operating in full-drive mode (RSET1 = 510 Ω, RL1 = 37.5 Ω, assuming a connected cable). The feature is not available in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω). For a DAC to be monitored, the DAC must be powered up in Subaddress 0x00. The cable detection feature can be used with all SD, ED, and HD video standards. It is available for all output configurations, that is, CVBS, YC, YPrPb, and RGB output configurations. For CVBS/YC output configurations, both DAC 1 and DAC 2 are monitored, that is, the CVBS and YC luma outputs are monitored. For YPrPb and RGB output configurations, only DAC 1 is monitored, that is, the luma or green output is monitored. Once per frame, the ADV7340/ADV7341 monitor DAC 1 and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1, respectively. If a cable is detected on one of the DACs, the relevant bit is set to 0. If not, the bit is set to 1. PIXEL AND CONTROL PORT READBACK Subaddress 0x12 to Subaddress 0x16 The ADV7340/ADV7341 support the readback of most digital inputs via the I2C/SPI MPU port. This feature is useful for board-level connectivity testing with upstream devices. The pixel port (S[9:0], Y[9:0], and C[9:0]), the control port (S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC and P_BLANK), and the SFL/MISO pin are available for readback via the MPU port. The readback registers are located at Subaddress 0x12 to Subaddress 0x16. When using this feature, a clock signal should be applied to the CLKIN_A pin in order to register the levels applied to the input pins. RESET MECHANISM Subaddress 0x17, Bit 1 The ADV7340/ADV7341 have a software reset accessible via the I2C/SPI MPU port. A software reset is activated by writing a 1 to Subaddress 0x17, Bit 1. This resets all registers to their default values. This bit is self-clearing, that is, after a 1 has been written to the bit, the bit automatically returns to 0. When operating in SPI mode, a software reset does not cause the device to revert to I2C mode. For this to occur, the ADV7340/ADV7341 need to be powered down. The ADV7340/ADV7341 include a power-on reset (POR) circuit to ensure correct operation after power-up. DAC AUTO POWER-DOWN Subaddress 0x10, Bit 4 For power sensitive applications, a DAC auto power-down feature can be enabled using Subaddress 0x10, Bit 4. This feature is only available when the cable detection feature is enabled. Rev. 0 | Page 65 of 88 ADV7340/ADV7341 PRINTED CIRCUIT BOARD LAYOUT AND DESIGN DAC CONFIGURATIONS The ADV7340/ADV7341 contain six DACs. All six DACs can be configured to operate in low drive mode. Low drive mode is defined as 4.33 mA full-scale current into a 300 Ω load, RL. DAC 1, DAC 2, and DAC 3 can also be configured to operate in full-drive mode. Full-drive mode is defined as 34.7 mA fullscale current into a 37.5 Ω load, RL. Full-drive is the recommended mode of operation for DAC 1, DAC 2, and DAC 3. The ADV7340/ADV7341 contain two RSET pins. A resistor connected between the RSET1 pin and AGND is used to control the full-scale output current and, therefore, the DAC output voltage levels of DAC 1, DAC 2, and DAC 3. For low drive operation, RSET1 must have a value of 4.12 kΩ, and RL must have a value of 300 Ω. For full-drive operation, RSET1 must have a value of 510 Ω, and RL must have a value of 37.5 Ω. A resistor connected between the RSET2 pin and AGND is used to control the full-scale output current and, therefore, the DAC output voltage levels of DAC 4, DAC 5, and DAC 6. RSET2 must have a value of 4.12 kΩ, and RL must have a value of 300 Ω (that is, low drive operation only). The resistors connected to the RSET1 and RSET2 pins should have a 1% tolerance. The ADV7340/ADV7341 contain two compensation pins, COMP1 and COMP2. A 2.2 nF compensation capacitor should be connected from each of these pins to VAA. For applications requiring an output buffer and reconstruction filter, the ADA4430-1, ADA4411-3, and ADA4410-6 integrated video filter buffers should be considered. Table 53. ADV7340/ADV7341 Output Rates Input Mode (0x01, Bits[6:4]) SD Only ED Only HD Only PLL Control (0x00, Bit 1) Off On Off On Off On Output Rate (MHz) 27 (2x) 216 (16x) 27 (1x) 216 (8x) 74.25 (1x) 297 (4x) Table 54. Output Filter Requirements Cutoff Frequency (MHz) >6.5 >6.5 >12.5 >12.5 >30 >30 Attenuation –50 dB @ (MHz) 20.5 209.5 14.5 203.5 44.25 267 Application SD SD ED ED HD HD Oversampling 2× 16× 1× 8× 1× 4× 10µH DAC OUTPUT 600Ω 22pF 600 Ω 3 1 4 75Ω VOLTAGE REFERENCE The ADV7340/ADV7341 contain an on-chip voltage reference that can be used as a board-level voltage reference via the VREF pin. Alternatively, the ADV7340/ADV7341 can be used with an external voltage reference by connecting the reference source to the VREF pin. For optimal performance, an external voltage reference such as the AD1580 should be used with the ADV7340/ADV7341. If an external voltage reference is not used, a 0.1 μF capacitor should be connected from the VREF pin to VAA. BNC OUTPUT 560 Ω Figure 84. Example of Output Filter for SD, 16× Oversampling 4.7µH DAC OUTPUT 6.8pF 600Ω 6.8pF 600Ω 4 3 75Ω 1 BNC OUTPUT VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER An output buffer is necessary on any DAC that operates in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Analog Devices, Inc. produces a range of op amps suitable for this application, for example, the AD8061. For more information about line driver buffering circuits, see the relevant op amp data sheet. An optional reconstruction (anti-imaging) low-pass filter (LPF) may be required on the ADV7340/ADV7341 DAC outputs if the part is connected to a device that requires this filtering. The filter specifications vary with the application. The use of 16× (SD), 8× (ED), or 4× (HD) oversampling can remove the requirement for a reconstruction filter altogether. Rev. 0 | Page 66 of 88 DAC OUTPUT 3 560Ω Figure 85. Example of Output Filter for ED, 8× Oversampling 300Ω 4 1 75Ω 390nH 3 BNC OUTPUT 1 33pF 33pF 75Ω 4 500 Ω 500Ω Figure 86. Example of Output Filter for HD, 4× Oversampling 06398-087 06398-086 560Ω 06398-085 560 Ω ADV7340/ADV7341 0 –10 MAGNITUDE (dB) –20 –30 CIRCUIT FREQUENCY RESPONSE 0 24n –30 21n –60 18n –90 PHASE (Degrees) 15n –120 12n –150 GROUP DELAY (Seconds) –60 –70 –80 1M 9n –180 6n –210 3n –240 0 1G PRINTED CIRCUIT BOARD (PCB) LAYOUT The ADV7340/ADV7341 are highly integrated circuits containing both precision analog and high speed digital circuitry. They have been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system-level design so that optimal performance is achieved. The layout should be optimized for lowest noise on the ADV7340/ADV7341 power and ground planes by shielding the digital inputs and providing good power supply decoupling. It is recommended to use a 4-layer printed circuit board with ground and power planes separating the signal trace layer and the solder side layer. 06398-088 GAIN (dB) –40 –50 10M 100M FREQUENCY (Hz) Figure 87. Output Filter Plot for SD, 16× Oversampling Component Placement 0 –10 MAGNITUDE (dB) –20 –30 320 14n 240 160 80 8n –60 –70 –80 –90 1M 0 6n –80 4n –160 2n –240 0 1G 12n 10n –50 CIRCUIT FREQUENCY RESPONSE 480 18n 400 16n Component placement should be carefully considered to separate noisy circuits, such as clock signals and high speed digital circuitry from analog circuitry. The external loop filter components and components connected to the COMP, VREF, and RSET pins should be placed as close as possible to and on the same side of the PCB as the ADV7340/ADV7341. Adding vias to the PCB to get the components closer to the ADV7340/ADV7341 is not recommended. It is recommended that the ADV7340/ADV7341 be placed as close as possible to the output connector, with the DAC output traces as short as possible. 06398-089 GAIN (dB) –40 GROUP DELAY (Seconds) PHASE (Degrees) 10M 100M FREQUENCY (Hz) Figure 88. Output Filter Plot for ED, 8× Oversampling The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV7340/ADV7341. The termination resistors should overlay the PCB ground plane. External filter and buffer components connected to the DAC outputs should be placed as close as possible to the ADV7340/ADV7341 to minimize the possibility of noise pickup from neighboring circuitry, and to minimize the effect of trace capacitance on output bandwidth. This is particularly important when operating in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω). 0 CIRCUIT FREQUENCY RESPONSE PHASE (Degrees) MAGNITUDE (dB) 200 –10 GROUP DELAY (Seconds) GAIN (dB) 120 –20 40 PHASE (Degree) –30 –40 Power Supplies It is recommended that a separate regulated supply be provided for each power domain (VAA, VDD, VDD_IO, and PVDD). For optimal performance, linear regulators rather than switch mode regulators should be used. If switch mode regulators must be used, care must be taken with regard to the quality of the output voltage in terms of ripple and noise. This is particularly true for the VAA and PVDD power domains. Each power supply should be individually connected to the system power supply at a single point through a suitable filtering device, such as a ferrite bead. –40 –120 1 10 FREQUENCY (MHz) 100 Figure 89. Output Filter Plot for HD, 4× Oversampling Rev. 0 | Page 67 of 88 06398-090 –50 –200 ADV7340/ADV7341 Power Supply Decoupling It is recommended that each power supply pin be decoupled with 10 nF and 0.1 μF ceramic capacitors. The VAA, PVDD, VDD_IO, and both VDD pins should be individually decoupled to ground. The decoupling capacitors should be placed as close as possible to the ADV7340/ADV7341 with the capacitor leads kept as short as possible to minimize lead inductance. A 1 μF tantalum capacitor is recommended across the VAA supply in addition to the 10 nF and 0.1 μF ceramic capacitors. Due to the high clock rates used, avoid long clock traces to the ADV7340/ADV7341 to minimize noise pickup. Any pull-up termination resistors for the digital inputs should be connected to the VDD power supply. Any unused digital inputs should be tied to ground. Analog Signal Interconnect DAC output traces should be treated as transmission lines with appropriate measures taken to ensure optimal performance (for example, impedance matched traces). The DAC output traces should be kept as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV7340/ADV7341. To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the traces connected to the DAC output pins. Adding ground traces between the DAC output traces is also recommended. Power Supply Sequencing The ADV7340/ADV7341 are robust to all power supply sequencing combinations. Any particular sequence can be used. Digital Signal Interconnect The digital signal traces should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal traces should not overlay the VAA or PVDD power planes. Rev. 0 | Page 68 of 88 ADV7340/ADV7341 TYPICAL APPLICATION CIRCUIT VDD_IO FERRITE BEAD 33µF 10µF 0.1µF GND_IO 0.01µF GND_IO VDD_IO POWER SUPPLY DECOUPLING NOTES 1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP, RSET, VREF AND DAC OUTPUT PINS SHOULD BE LOCATED CLOSE TO AND ON THE SAME SIDE OF THE PCB AS THE ADV7340/ADV7341. 2. WHEN OPERATING IN I2C MODE, THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB/SPI_SS PIN: ALSB/SPI_SS = 0, I2C DEVICE ADDRESS = 0xD4 OR 0x54 ALSB/SPI_SS = 1, I2C DEVICE ADDRESS = 0xD6 OR 0x56 3. THE RESISTORS CONNECTED TO THE RSET PINS SHOULD HAVE A 1% TOLERANCE. PVDD (1.8V) GND_IO GND_IO FERRITE BEAD 33µF 10µF 0.1µF PGND 0.01µF PGND VAA PGND PGND FERRITE BEAD 33µF 10µF PVDD POWER SUPPLY DECOUPLING 0.1µF AGND 0.01µF AGND 1µF VDD (1.8V) AGND AGND FERRITE BEAD 33µF DGND 10µF DGND VAA POWER SUPPLY AGND DECOUPLING VDD POWER SUPPLY DECOUPLING FOR EACH POWER PIN 0.1µF DGND 0.01µF DGND VAA VAA 2.2nF 2.2nF VAA 1.1kΩ 1.235V 0.1µF OPTIONAL. IF THE INTERNAL VOLTAGE REFERENCE IS USED, A 0.1µF CAPACITOR SHOULD BE CONNECTED FROM VREF TO VAA. VDD_IO VDD VDD VAA PVDD COMP1 COMP2 VREF Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 AD1580 AGND ADV7340/ADV7341 RSET1 RSET2 4.12kΩ AGND DAC 1 DAC 2 DAC 3 OPTIONAL LPF 510Ω AGND OPTIONAL LPF OPTIONAL LPF DAC 1 DAC 2 DAC 3 DACs 1-3 FULL DRIVE OPTION PIXEL PORT INPUTS 75Ω AGND 75Ω AGND 75Ω AGND DACs 1-3 LOW DRIVE OPTION OPTIONAL LPF DAC 4 + – 300Ω 510Ω AGND 510Ω AGND OPTIONAL LPF DAC 5 + – 300Ω 510Ω AGND 510Ω AGND OPTIONAL LPF DAC 6 + – 300Ω DAC 2 + – 300Ω 510Ω +V –V DAC 1 + – 300Ω 510Ω +V –V AD8061 +V –V 75Ω DAC 4 RSET1 4.12kΩ AGND OPTIONAL LPF AD8061 75Ω DAC 1 S_HSYNC S_VSYNC CONTROL INPUTS/OUTPUTS P_HSYNC P_VSYNC P_BLANK CLKIN_A CLKIN_B SDA/SCLK SCL/MOSI SFL/MISO ALSB/SPI_SS AD8061 +V –V AGND 75Ω DAC 5 510Ω AGND OPTIONAL LPF CLOCK INPUTS AD8061 75Ω DAC 2 MPU PORT INPUTS/OUTPUTS EXTERNAL LOOP FILTERS PVDD 12nF AD8061 +V –V AGND 75Ω DAC 6 510Ω AGND EXT_LF2 150nF 170Ω EXT_LF2 AGND PGND DGND DGND 170Ω GND_IO 12nF 150nF 510Ω AGND 510Ω AGND DAC 3 OPTIONAL LPF + – AD8061 +V –V 75Ω DAC 3 LOOP FILTER COMPONENTS SHOULD BE LOCATED CLOSE TO THE EXT_LF PINS AND ON THE SAME SIDE OF THE PCB AS THE ADV7340/ADV7341. AGND PGND DGND DGND GND_IO 300Ω 510Ω AGND 510Ω AGND 06398-091 Figure 90. ADV7340/ADV7341 Typical Application Circuit Rev. 0 | Page 69 of 88 ADV7340/ADV7341 APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV7340/ADV7341 support copy generation management system (CGMS) conforming to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both. SD CGMS data can only be transmitted when the ADV7340/ ADV7341 are configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 91). When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p CGMS data is applied to Line 24 of the luminance vertical blanking interval. When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i CGMS data is applied to Line 19 and Line 582 of the luminance vertical blanking interval. The HD CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV7340/ADV7341 also support CGMS Type B packets in HD mode (720p and 1080i) in accordance with CEA-805-A. When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 720p CGMS data is applied to Line 23 of the luminance vertical blanking interval. When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 1080i CGMS data is applied to Line 18 and Line 581 of the luminance vertical blanking interval. The HD CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E. ED CGMS Subaddress 0x41 to Subaddress 0x43 Subaddress 0x5E to Subaddress 0x6E 525p The ADV7340/ADV7341 support copy generation management system (CGMS) in 525p mode in accordance with EIAJ CPR1204-1. When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p CGMS data is inserted on Line 41. The 525p CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV7340/ADV7341 also support CGMS Type B packets in 525p mode in accordance with CEA-805-A. When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 525p CGMS Type B data is inserted on Line 40. The 525p CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E. CGMS CRC FUNCTIONALITY If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS data bits, C19 to C14, which comprise the 6-bit CRC check sequence, are automatically calculated on the ADV7340/ADV7341. This calculation is based on the lower 14 bits (C13 to C0) of the data in the CGMS data registers and the result is output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If SD CGMS CRC or ED/HD CGMS CRC are disabled, all 20 bits (C19 to C0) are output directly from the CGMS registers (CRC must be calculated by the user manually). If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is enabled, the upper six CGMS Type B data bits (P122 to P127) that comprise the 6-bit CRC check sequence are automatically calculated on the ADV7340/ADV7341. This calculation is based on the lower 128 bits (H0 to H5 and P0 to P121) of the data in the CGMS Type B data registers. The result is output with the remaining 128 bits to form the complete 134 bits of the CGMS Type B data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5 and P0 to P127) are output directly from the CGMS Type B registers (CRC must be calculated by the user manually). 625p The ADV7340/ADV7341 support copy generation management system (CGMS) in 625p mode in accordance with IEC62375 (2004). When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p CGMS data is inserted on Line 43. The 625p CGMS data registers are at Subaddress 0x42 and Subaddress 0x43. HD CGMS Subaddress 0x41 to Subaddress 0x43 Subaddress 0x5E to Subaddress 0x6E The ADV7340/ADV7341 support copy generation management system (CGMS) in HD mode (720p and 1080i) in accordance with EIAJ CPR-1204-2. Rev. 0 | Page 70 of 88 ADV7340/ADV7341 +100 IRE REF +70 IRE CRC SEQUENCE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0 IRE –40 IRE 11.2µs 2.235µs ± 20ns Figure 91. Standard Definition CGMS Waveform CRC SEQUENCE +700mV REF 70% ± 10% BIT 1 BIT 2 BIT 20 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV –300mV 5.8µs ± 0.15µs 6T 21.2µs ± 0.22µs 22T 06398-093 06398-095 T = 1/(fH × 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T ± 30ns Figure 92. Enhanced Definition (525p) CGMS Waveform PEAK WHITE R = RUN-IN S = START CODE 500mV ± 25mV R S C0 LSB C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 MSB SYNC LEVEL 13.7µs 06398-094 5.5µs ± 0.125µs Figure 93. Enhanced Definition (625p) CGMS Waveform +700mV REF 70% ± 10% BIT 1 BIT 2 CRC SEQUENCE BIT 20 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV –300mV 4T 3.128µs ± 90ns T ± 30ns 17.2µs ± 160ns 22T T = 1/(fH × 1650/58) = 781.93ns fH = HORIZONTAL SCAN FREQUENCY 1H Figure 94. High Definition (720p) CGMS Waveform Rev. 0 | Page 71 of 88 06398-092 49.1µs ± 0.5µs ADV7340/ADV7341 +700mV REF 70% ± 10% BIT 1 BIT 2 CRC SEQUENCE BIT 20 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV –300mV 4T 4.15µs ± 60ns T ± 30ns 22.84µs ± 210ns 22T T = 1/(fH × 2200/77) = 1.038µs fH = HORIZONTAL SCAN FREQUENCY 1H Figure 95. High Definition (1080i) CGMS Waveform +700mV 70% ± 10% START BIT 1 BIT 2 CRC SEQUENCE BIT 134 H0 H1 H2 H3 H4 H5 P0 P1 P2 P3 P4 . . . P122 P123 P124 P125 P126 P127 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. 06398-097 Figure 96. Enhanced Definition (525p) CGMS Type B Waveform +700mV 70% ± 10% START BIT 1 BIT 2 CRC SEQUENCE BIT 134 H0 H1 H2 H3 H4 H5 P0 P1 P2 P3 P4 . . . P122 P123 P124 P125 P126 P127 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. 06398-098 Figure 97. High Definition (720p and 1080i) CGMS Type B Waveform Rev. 0 | Page 72 of 88 06398-096 ADV7340/ADV7341 APPENDIX 2—SD WIDE SCREEN SIGNALING Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV7340/ADV7341 support wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long. The function of each of these bits is shown in Table 55. Table 55. Function of WSS Bit Description Aspect Ratio, Format, Position 13 12 11 10 9 Bit Number 876 5 4 3 1 0 0 1 0 1 1 0 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Setting 4:3, full format, N/A 14:9, letterbox, center 14:9, letterbox, top 16:9, letterbox, center 16:9, letterbox, top >16:9, letterbox, center 14:9, full format, center 16:0, N/A, N/A Camera mode Film mode Normal PAL Motion Adaptive ColorPlus Not present Present No Yes No Subtitles in active image area Subtitles out of active image area Reserved No Yes No copyright asserted or unknown Copyright asserted Copying not restricted Copying restricted The WSS data is preceded by a run-in sequence and a start code (see Figure 98). If SD WSS (Subaddress 0x99, Bit 7) is set to Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 sec from the falling edge of HSYNC) is available for the insertion of video. It is possible to blank the WSS portion of Line 23 with Subaddress 0xA1, Bit 7. Mode Color Encoding Helper Signals Reserved Teletext Subtitles Open Subtitles 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 Surround Sound Copyright Copy Protection 500mV RUN-IN SEQUENCE START CODE W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 ACTIVE VIDEO 11.0µs 42.5µs 06398-099 38.4µs Figure 98. WSS Waveform Diagram Rev. 0 | Page 73 of 88 ADV7340/ADV7341 APPENDIX 3—SD CLOSED CAPTIONING Subaddress 0x91 to Subaddress 0x94 The ADV7340/ADV7341 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency- and phase-locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by the Logic 1 start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in the SD closed captioning registers (Subaddress 0x93 to Subaddress 0x94). The ADV7340/ADV7341 also support the extended closed captioning operation, which is active during even fields and encoded on Scan Line 284. The data for this operation is stored in the SD closed captioning registers (Subaddress 0x91 to Subaddress 0x92). The ADV7340/ADV7341 automatically generate all clock runin signals and timing that support closed captioning on Line 21 and Line 284. All pixels inputs are ignored on Line 21 and Line 284 if closed captioning is enabled. The FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA-608 describe the closed captioning information for Line 21 and Line 284. The ADV7340/ADV7341 use a single buffering method. This means that the closed captioning buffer is only 1-byte deep. Therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. The data must be loaded one line before it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn loads the new data (2 bytes) in every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes, on Line 21. Otherwise, a TV does not recognize them. If there is a message such as “Hello World” that has an odd number of characters, it is important to add a blank character at the end to make sure that the end-of-caption, 2-byte control code lands in the same field. 10.5 ± 0.25µs 12.91µs 7 CYCLES OF 0.5035MHz CLOCK RUN-IN TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A D0 TO D6 R T BYTE 0 P A R I T Y P A R I T Y 50 IRE D0 TO D6 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003µs 27.382µs BYTE 1 33.764µs Figure 99. SD Closed Captioning Waveform, NTSC Rev. 0 | Page 74 of 88 06398-100 ADV7340/ADV7341 APPENDIX 4—INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS The ADV7340/ADV7341 are able to generate SD color bar and black bar test patterns. The register settings in Table 56 are used to generate an SD NTSC 75% color bar test pattern. CVBS output is available on DAC 4, S-Video (Y/C) output is on DAC 5 and DAC 6, and YPrPb output is on DAC 1 to DAC 3. Upon power-up, the subcarrier frequency registers default to the appropriate values for NTSC. All other registers are set as normal/default. Table 56. SD NTSC Color Bar Test Pattern Register Writes Subaddress 0x00 0x82 0x84 Setting 0xFC 0xC9 0x40 Note that when programming the FSC registers, the user must write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full FSC value to be written is accepted only after the FSC3 write is complete. ED/HD TEST PATTERNS The ADV7340/ADV7341 are able to generate ED/HD color bar, black bar, and hatch test patterns. The register settings in Table 58 are used to generate an ED 525p hatch test pattern. YPrPb output is available on DAC 1 to DAC 3. All other registers are set as normal/default. Table 58. ED 525p Hatch Test Pattern Register Writes Subaddress 0x00 0x01 0x31 Setting 0x1C 0x10 0x05 To generate an SD NTSC black bar test pattern, the same settings shown in Table 56 should be used with an additional write of 0x24 to Subaddress 0x02. For PAL output of either test pattern, the same settings are used, except that Subaddress 0x80 is programmed to 0x11 and the subcarrier frequency registers are programmed as shown in Table 57. Table 57. PAL FSC Register Writes Subaddress 0x8C 0x8D 0x8E 0x8F Description FSC0 FSC1 FSC2 FSC3 Setting 0xCB 0x8A 0x09 0x2A To generate an ED 525p black bar test pattern, the same settings as shown in Table 58 should be used with an additional write of 0x24 to Subaddress 0x02. To generate an ED 525p flat field test pattern, the same settings shown in Table 58 should be used, except that 0x0D should be written to Subaddress 0x31. The Y, Cr, and Cb levels for the hatch and flat field test patterns can be controlled using Subaddress 0x36, Subaddress 0x37, and Subaddress 0x38, respectively. For ED/HD standards other than 525p, the same settings as shown in Table 58 (and subsequent comments) are used except that Subaddress 0x30, Bits[7:3] are updated as appropriate. Rev. 0 | Page 75 of 88 ADV7340/ADV7341 APPENDIX 5—SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0) The ADV7340/ADV7341are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. If the S_VSYNC and S_HSYNC pins are not used, they should be tied high during this mode. ANALOG VIDEO EAV CODE INPUT PIXELS C F0 0X818 1 Y Y r F0 0Y000 0 4 CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) 4 CLOCK END OF ACTIVE VIDEO LINE 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 CLOCK 280 CLOCK SAV CODE 8 1 8 1 F 0 0 X CY C YC Y CY C b r b 0000F00Yb r 4 CLOCK 4 CLOCK 1440 CLOCK 1440 CLOCK 06398-101 START OF ACTIVE VIDEO LINE Figure 100. SD Slave Mode 0 Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1) The ADV7340/ADV7341 generate H and F signals required for the SAV and EAV time codes in the CCIR656 standard. The H bit is output on S_HSYNC and the F bit is output on S_VSYNC. DISPLAY DISPLAY VERTICAL BLANK 522 H F 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 H F 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD Figure 101. SD Master Mode 0, NTSC Rev. 0 | Page 76 of 88 06398-102 ADV7340/ADV7341 DISPLAY VERTICAL BLANK DISPLAY 622 H 623 624 625 1 2 3 4 5 6 7 21 22 23 F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 309 H 310 311 312 313 314 315 316 317 318 319 320 334 335 336 F ODD FIELD EVEN FIELD Figure 102. SD Master Mode 0, PAL ANALOG VIDEO H F Figure 103. SD Master Mode 0, Data Transitions Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0) In this mode, the ADV7340/ADV7341 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7340/ADV7341 automatically blank all normally blank lines as per CCIR624. HSYNC and FIELD are input on the S_HSYNC and S_VSYNC pins, respectively. DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 06398-104 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC FIELD 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 06398-103 ODD FIELD EVEN FIELD Figure 104. SD Slave Mode 1, NTSC Rev. 0 | Page 77 of 88 06398-105 ADV7340/ADV7341 DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 309 HSYNC FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 105. SD Slave Mode 1, PAL Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1) In this mode, the ADV7340/ADV7341 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7340/ADV7341 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the S_HSYNC and S_VSYNC pins, respectively. HSYNC FIELD PIXEL DATA Cb Y Cr Y 06398-107 PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 Figure 106. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave) Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0) In this mode, the ADV7340/ADV7341 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7340/ADV7341 automatically blank all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the S_HSYNC and S_VSYNC pins, respectively. Rev. 0 | Page 78 of 88 06398-106 ADV7340/ADV7341 DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC VSYNC 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD DISPLAY ODD FIELD DISPLAY VERTICAL BLANK 260 HSYNC VSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD Figure 107. SD Slave Mode 2, NTSC DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC VSYNC 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD DISPLAY ODD FIELD DISPLAY VERTICAL BLANK 309 HSYNC VSYNC 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 108. SD Slave Mode 2, PAL Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1) In this mode, the ADV7340/ADV7341 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7340/ADV7341 automatically blank all normally blank lines as per CCIR-624. HSYNC and VSYNC are output on the S_HSYNC and S_VSYNC pins, respectively. HSYNC VSYNC PIXEL DATA PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 Cb Y Cr Y 06398-110 Figure 109. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave) Rev. 0 | Page 79 of 88 06398-109 06398-108 ADV7340/ADV7341 HSYNC VSYNC PAL = 864 × CLOCK/2 NTSC = 858 × CLOCK/2 PIXEL DATA PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 Cb Y Cr Y Cb 06398-111 Figure 110. SD Timing Mode 2 Odd-to-Even Field Transition (Master/Slave) Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode, the ADV7340/ADV7341 accept or generate horizontal sync and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7340/ADV7341 automatically blank all normally blank lines as per CCIR-624. HSYNC and VSYNC are output in master mode and input in slave mode on the S_VSYNC and S_VSYNC pins, respectively. DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD DISPLAY ODD FIELD DISPLAY VERTICAL BLANK 260 HSYNC FIELD 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD Figure 111. SD Timing Mode 3, NTSC DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD DISPLAY ODD FIELD DISPLAY VERTICAL BLANK 309 HSYNC FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 EVEN FIELD ODD FIELD Figure 112. SD Timing Mode 3, PAL Rev. 0 | Page 80 of 88 06398-113 06398-112 ADV7340/ADV7341 APPENDIX 6—HD TIMING DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL 1124 P_VSYNC 1125 1 2 3 4 5 6 7 8 20 21 22 560 P_HSYNC DISPLAY FIELD 2 VERTICAL BLANKING INTERVAL 561 P_VSYNC 562 563 564 565 566 567 568 569 570 583 584 585 1123 P_HSYNC Figure 113. 1080i HSYNC and VSYNC Input Timing Rev. 0 | Page 81 of 88 06398-114 ADV7340/ADV7341 APPENDIX 7—VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars MAGENTA MAGENTA YELLOW YELLOW GREEN GREEN BLACK BLACK BLACK BLACK 06398-120 WHITE WHITE CYAN BLUE CYAN 700mV 700mV 300mV 06398-115 300mV 06398-118 Figure 114. Y Levels—NTSC MAGENTA YELLOW GREEN BLACK WHITE WHITE Figure 117. Y Levels—PAL MAGENTA YELLOW GREEN CYAN CYAN BLUE RED 700mV 700mV BLUE RED BLUE RED RED 06398-116 Figure 115. Pr Levels—NTSC MAGENTA YELLOW GREEN BLACK WHITE WHITE Figure 118. Pr Levels—PAL MAGENTA YELLOW GREEN CYAN CYAN BLUE RED 700mV 700mV 06398-117 Figure 116. Pb Levels—NTSC Figure 119. Pb Levels—PAL Rev. 0 | Page 82 of 88 BLUE RED 06398-119 ADV7340/ADV7341 ED/HD YPrPb OUTPUT LEVELS INPUT CODE 940 EIA-770.2, STANDARD FOR Y INPUT CODE 940 EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE OUTPUT VOLTAGE 700mV 700mV 64 300mV 64 300mV EIA-770.2, STANDARD FOR Pr/Pb 960 EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE OUTPUT VOLTAGE 960 600mV 512 512 700mV 700mV 06398-121 06398-123 64 64 Figure 120. EIA-770.2 Standard Output Signals (525p/625p) INPUT CODE 940 EIA-770.1, STANDARD FOR Y OUTPUT VOLTAGE 782mV Figure 122. EIA-770.3 Standard Output Signals (1080i/720p) INPUT CODE 1023 Y–OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE 714mV 700mV 64 64 286mV 300mV EIA-770.1, STANDARD FOR Pr/Pb 960 OUTPUT VOLTAGE INPUT CODE 1023 Pr/Pb–OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE 512 700mV 700mV 06398-122 64 300mV 06398-124 64 Figure 121. EIA-770.1 Standard Output Signals (525p/625p) Figure 123. Output Levels for Full Input Selection Rev. 0 | Page 83 of 88 ADV7340/ADV7341 SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R 700mV/525mV R 700mV/525mV 300mV 300mV G 700mV/525mV G 700mV/525mV 300mV 300mV B 700mV/525mV 06398-125 B 700mV/525mV 06398-127 300mV 300mV Figure 124. SD/ED RGB Output Levels—RGB Sync Disabled Figure 126. HD RGB Output Levels—RGB Sync Disabled R R 700mV/525mV 600mV 700mV/525mV 300mV 300mV 0mV 0mV G G 700mV/525mV 600mV 700mV/525mV 300mV 300mV 0mV 0mV B B 700mV/525mV 600mV 700mV/525mV 300mV 300mV 06398-128 06398-126 0mV 0mV Figure 125. SD/ED RGB Output Levels—RGB Sync Enabled Figure 127. HD RGB Output Levels—RGB Sync Enabled Rev. 0 | Page 84 of 88 ADV7340/ADV7341 SD OUTPUT PLOTS VOLTS IRE:FLT VOLTS 0.6 100 0.4 0.5 50 0.2 0 0 0 –50 F1 L76 –0.2 L608 0 10 20 30 40 50 60 MICROSECONDS NOISE REDUCTION: 0.00dB APL = 39.1% PRECISION MODE OFF 625 LINE NTSC NO FILTERING SYNCHRONOUS SOUND-IN-SYNC OFF SLOW CLAMP TO 0.00 AT 6.72µs FRAMES SELECTED 1, 2, 3, 4 06398-129 Figure 128. NTSC Color Bars (75%) VOLTS IRE:FLT 0.6 Figure 131. PAL Color Bars (75%) VOLTS 0.5 0.4 50 0.2 0 0 0 0 –0.2 0 10 F2 L238 20 L575 0 10 20 30 40 50 60 70 06398-130 Figure 129. NTSC Luma VOLTS IRE:FLT 0.4 50 VOLTS 0.5 Figure 132. PAL Luma 0.2 0 0 0 –0.2 –50 –0.4 F1 L76 30 40 50 60 MICROSECONDS NOISE REDUCTION: 15.05dB PRECISION MODE OFF APL NEEDS SYNC SOURCE. SYNCHRONOUS SYNC = B 525 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00 AT 6.72µs 0 10 20 0 –0.5 L575 30 40 50 60 MICROSECONDS APL NEEDS SYNC SOURCE. NO BUNCH SIGNAL 625 LINE PAL NO FILTERING PRECISION MODE OFF SLOW CLAMP TO 0.00 AT 6.72µs SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1 10 20 06398-131 Figure 130. NTSC Chroma Rev. 0 | Page 85 of 88 Figure 133. PAL Chroma 06398-134 06398-133 30 40 50 60 MICROSECONDS NOISE REDUCTION: 15.05dB APL = 44.3% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = SOURCE SLOW CLAMP TO 0.00V AT 6.72µs μ FRAMES SELECTED 1, 2 MICROSECONDS APL NEEDS SYNC SOURCE. NO BUNCH SIGNAL 625 LINE PAL NO FILTERING PRECISION MODE OFF SLOW CLAMP TO 0.00 AT 6.72µs SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1 06398-132 0 10 20 30 40 50 60 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC =A SLOW CLAMP TO 0.00V AT 6.72µs μ FRAMES SELECTED 1, 2 ADV7340/ADV7341 APPENDIX 8—VIDEO STANDARDS 0HDATUM SMPTE 274M ANALOG WAVEFORM DIGITAL HORIZONTAL BLANKING *1 4T EAV CODE INPUT PIXELS F F 00F 00V H* 4 CLOCK SAMPLE NUMBER 2112 2116 2156 0 2199 44 188 272T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE 4T SAV CODE 1920T DIGITAL ACTIVE LINE CY r F 0 0F C C V F 0 0 H* b Y r 4 CLOCK 192 2111 FOR A FRAME RATE OF 30Hz: 40 SAMPLES FOR A FRAME RATE OF 25Hz: 480 SAMPLES Figure 134. EAV/SAV Input Data Timing Diagram (SMPTE 274M) SMPTE 293M ANALOG WAVEFORM EAV CODE INPUT PIXELS F F00V F 0 0 H* 4 CLOCK SAMPLE NUMBER 719 723 736 0HDATUM 799 DIGITAL HORIZONTAL BLANKING FVH* = FVH AND PARITY BITS SAV: LINE 43–525 = 200H SAV: LINE 1–42 = 2AC EAV: LINE 43–525 = 274H EAV: LINE 1–42 = 2D8 ANCILLARY DATA (OPTIONAL) SAV CODE F 0 0F V F 0 0 H* 4 CLOCK 853 857 0 719 DIGITAL ACTIVE LINE C C bYr C YrY Figure 135. EAV/SAV Input Data Timing Diagram (SMPTE293M) ACTIVE VIDEO VERTICAL BLANK ACTIVE VIDEO 522 523 524 525 1 2 5 6 7 8 9 12 13 14 15 16 42 43 44 Figure 136. SMPTE 293M (525p) Rev. 0 | Page 86 of 88 06398-137 06398-136 06398-135 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1 SAV/EAV: LINE 21–560; 584–1123: V = 0 ADV7340/ADV7341 ACTIVE VIDEO VERTICAL BLANK ACTIVE VIDEO 622 623 624 625 1 2 4 5 6 7 8 9 10 11 12 13 43 44 45 Figure 137. ITU-R BT.1358 (625p) DISPLAY VERTICAL BLANKING INTERVAL 06398-138 06398-140 06398-139 747 748 749 750 1 2 3 4 5 6 7 8 25 26 27 744 745 Figure 138. SMPTE 296M (720p) DISPLAY VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 1 2 3 4 5 6 7 8 20 21 22 DISPLAY 560 VERTICAL BLANKING INTERVAL FIELD 2 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 Figure 139. SMPTE 274M (1080i) Rev. 0 | Page 87 of 88 ADV7340/ADV7341 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 1 PIN 1 12.20 12.00 SQ 11.80 64 49 48 TOP VIEW (PINS DOWN) 10.20 10.00 SQ 9.80 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 16 17 32 33 0.08 COPLANARITY VIEW A COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 140. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model ADV7340BSTZ 2 ADV7341BSTZ 2 EVAL-ADV7340EBZ2 EVAL-ADV7341EBZ2 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Macrovision 1 Antitaping Yes No Yes No Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] ADV7340 Evaluation Platform ADV7341 Evaluation Platform 051706-A ROTATED 90° CCW VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 Package Option ST-64-2 ST-64-2 Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video. Z = Pb-free part. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06398-0-10/06(0) Rev. 0 | Page 88 of 88