Multiformat Video Encoder
Six, 11-Bit, 297 MHz DACs
ADV7342/ADV7343
Data Sheet
FEATURES
74.25 MHz 16-/24-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
Six 11-bit, 297 MHz video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD), 4:4:4 YCrCb (ED and HD), and
4:4:4 RGB (SD, ED, and HD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Simultaneous SD and ED/HD operation
EIA/CEA-861B compliance support
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
On-board voltage reference (optional external input)
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (FSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Undershoot limiter
Dual data rate (DDR) input support
Rev. E
Enhanced definition(ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7342 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7342 only)
Copy generation management system (CGMS)
Wide screen signaling
Closed captioning
Serial MPU interface with I2C compatibility
3.3 V analog operation, 1.8 V digital operation, and 1.8 V or
3.3 V I/O operation
Temperature range: −40°C to +85°C
Qualified for automotive applications
APPLICATIONS
DVD recorders and players
High definition Blu-ray DVD players
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ADV7342/ADV7343
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SD Subcarrier Frequency Lock ................................................. 53
Applications ....................................................................................... 1
SD VCR FF/RW Sync ................................................................ 54
Revision History ............................................................................... 4
Vertical Blanking Interval ......................................................... 54
General Description ......................................................................... 5
SD Subcarrier Frequency Control ............................................ 54
Functional Block Diagram .............................................................. 6
SD Noninterlaced Mode ............................................................ 54
Specifications..................................................................................... 7
SD Square Pixel Mode ............................................................... 55
Power Supply and Voltage Specifications .................................. 7
Filters............................................................................................ 56
Voltage Reference Specifications ................................................ 7
ED/HD Test Pattern Color Controls ....................................... 57
Input Clock Specifications .......................................................... 7
Color Space Conversion Matrix ............................................... 57
Analog Output Specifications ..................................................... 8
SD Luma and Color Scale Control ........................................... 59
Digital Input/Output Specifications—3.3 V ............................. 8
SD Hue Adjust Control.............................................................. 59
Digital Input/Output Specifications—1.8 V ............................. 8
SD Brightness Detect ................................................................. 59
Digital Timing Specifications—3.3 V ........................................ 9
SD Brightness Control ............................................................... 59
Digital Timing Specifications—1.8 V ...................................... 10
SD Input Standard Autodetection ............................................ 60
MPU Port Timing Specifications ............................................. 11
Double Buffering ........................................................................ 61
Power Specifications .................................................................. 11
Programmable DAC Gain Control .......................................... 61
Video Performance Specifications ........................................... 12
Gamma Correction .................................................................... 61
Timing Diagrams ............................................................................ 13
ED/HD Sharpness Filter and Adaptive Filter Controls ......... 63
Absolute Maximum Ratings .......................................................... 20
Thermal Resistance .................................................................... 20
ED/HD Sharpness Filter and Adaptive Filter Application
Examples ...................................................................................... 64
ESD Caution ................................................................................ 20
SD Digital Noise Reduction ...................................................... 65
Pin Configuration and Function Descriptions ........................... 21
SD Active Video Edge Control ................................................. 66
Typical Performance Characteristics ........................................... 23
External Horizontal and Vertical Synchronization Control ... 68
MPU Port Description ................................................................... 28
Low Power Mode ........................................................................ 69
I2C Operation .............................................................................. 28
Cable Detection .......................................................................... 69
Register Map Access ....................................................................... 30
DAC Autopower-Down ............................................................. 69
Register Programming ............................................................... 30
Sleep Mode .................................................................................. 70
Subaddress Register (SR7 to SR0) ............................................ 30
Pixel and Control Port Readback ............................................. 70
Input Configuration ....................................................................... 48
Reset Mechanism........................................................................ 70
Standard Definition Only .......................................................... 48
SD Teletext Insertion ................................................................. 70
Enhanced Definition/High Definition Only .......................... 49
Printed Circuit Board Layout and Design .................................. 72
Simultaneous Standard Definition and Enhanced
Definition/High Definition ....................................................... 49
Unused Pins ................................................................................ 72
Enhanced Definition Only (at 54 MHz) ................................. 50
Voltage Reference ....................................................................... 72
Output Configuration .................................................................... 51
Video Output Buffer and Optional Output Filter .................. 72
Design Features ............................................................................... 52
Printed Circuit Board (PCB) Layout ....................................... 73
Output Oversampling ................................................................ 52
Typical Application Circuit ....................................................... 75
HD Interlace External P_HSYNC and P_VSYNC
Considerations ............................................................................ 53
Copy Generation Management System ....................................... 76
ED/HD Timing Reset ................................................................ 53
ED CGMS .................................................................................... 76
DAC Configurations .................................................................. 72
SD CGMS .................................................................................... 76
Rev. E | Page 2 of 106
Data Sheet
ADV7342/ADV7343
HD CGMS ....................................................................................76
ED/HD YPrPb Output Levels ................................................... 89
CGMS CRC Functionality .........................................................76
SD/ED/HD RGB Output Levels................................................ 90
SD Wide Screen Signaling ..............................................................79
SD Output Plots .......................................................................... 91
SD Closed Captioning ....................................................................80
Video Standards .............................................................................. 92
Internal Test Pattern Generation ...................................................81
Configuration Scripts ..................................................................... 94
SD Test Patterns ...........................................................................81
Standard Definition .................................................................... 94
ED/HD Test Patterns ..................................................................81
Enhanced Definition .................................................................. 98
SD Timing ........................................................................................82
High Definition .........................................................................101
HD Timing .......................................................................................87
Outline Dimensions ......................................................................106
Video Output Levels .......................................................................88
Ordering Guide .........................................................................106
SD YPrPb Output Levels—SMPTE/EBU N10 ........................88
Automotive Products ................................................................106
Rev. E | Page 3 of 106
ADV7342/ADV7343
Data Sheet
REVISION HISTORY
7/15—Rev. D to Rev. E
Changes to Features Section............................................................ 1
Changes to Ordering Guide ........................................................ 106
Added Automotive Products Section......................................... 106
3/12—Rev. C to Rev. D
Changed ADV7340/ADV7341 to ADV7342/ADV7343........... 70
3/12—Rev. B to Rev. C
Reorganized Layout ............................................................ Universal
Change to Features Section ............................................................. 1
Moved Revision History Section .................................................... 4
Change to Table 1 ............................................................................. 5
Changes to Digital Input/Output Specifications—
1.8 V Section ..................................................................................... 8
Changes to Table 15 ........................................................................ 21
Changes to Table 21 ........................................................................ 33
Changes to Table 24 ........................................................................ 36
Changes to Table 29 ........................................................................ 41
Changes to Table 30 ........................................................................ 42
Changes to 24-Bit 4:4:4 RGB Mode Section ............................... 48
Deleted ED/HD Nonstandard Timing Mode Section, Figure 59,
and Table 42, Renumbered Sequentially ..................................... 50
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode Section, and
Figure 60 .......................................................................................... 51
Deleted Figure 61 ............................................................................ 52
Added External Sync Polarity Section ......................................... 52
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section .................................................................................... 53
Changes to ED/HD Test Patterns Section ................................... 81
9/11—Rev. A to Rev. B
Changes to MPU Port Description Section ................................ 27
3/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Deleted Detailed Features Section, Changes to Table 1............... 4
Changes to Figure 1 .......................................................................... 5
Changes to Table 6 ............................................................................ 7
Added Digital Input/Output Specifications—1.8 V Section and
Table 7 ................................................................................................ 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................ 8
Added Table 9.................................................................................... 9
Changes to MPU Port Timing Specifications Section,
Default Conditions ......................................................................... 10
Deleted Figure 20............................................................................ 18
Changes to Table 13 ....................................................................... 19
Changes to Table 15 ....................................................................... 20
Changes to MPU Port Description Section ................................ 27
Changes to I2C Operation Section ............................................... 27
Added Table 16 ............................................................................... 27
Added Figure 49 ............................................................................. 28
Changes to Table 17 ....................................................................... 29
Changes to Table 18 ....................................................................... 29
Changes to Table 21, 0x30 Bit Description ................................. 32
Changes to Table 29 ....................................................................... 39
Changes to Table 30 ....................................................................... 40
Changes to Table 31, 0xA0 Register Name ................................. 42
Changes to Table 32 ....................................................................... 43
Added Table 33 and Table 34 ........................................................ 44
Changes to Standard Definition Only Section ........................... 46
Added Figure 52 ............................................................................. 47
Changes to Figure 53...................................................................... 47
Changes to Figure 56, Figure 57, and Figure 58 ......................... 48
Renamed Features Section to Design Features Section ............. 50
Changes to ED/HD Nonstandard Timing Mode Section ......... 50
Changes to Figure 60...................................................................... 51
Added HD Interlace External P_HSYNC and P_VSYNC
Considerations Section .................................................................. 51
Changes to SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section .................................................. 51
Changes to Programming the FSC Section................................... 53
Changes to Subaddress 0x8C to Subaddress 0x8F Section ....... 53
Changes to Subaddress 0x82, Bit 4 Section ................................. 53
Added SD Manual CSC Matrix Adjust Feature Section ............ 56
Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 57
Changes to SD Brightness Detect Section ................................... 58
Changes to Figure 71...................................................................... 60
Added Sleep Mode Section ........................................................... 68
Changes to Pixel and Control Port Readback Section .............. 68
Added SD Teletext Insertion Section ........................................... 68
Added Unused Pins Section .......................................................... 70
Added Figure 86 and Figure 87 .................................................... 70
Changes to Power Supply Sequencing Section ........................... 72
Changes to Figure 94...................................................................... 75
Changes to SD Wide Screen Signaling Section .......................... 77
Changes to Internal Test Pattern Generation Section ............... 79
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section .................................. 80
Added Configuration Scripts Section .......................................... 92
10/06—Revision 0: Initial Version
Rev. E | Page 4 of 106
Data Sheet
ADV7342/ADV7343
GENERAL DESCRIPTION
The ADV7342/ADV7343 are high speed, digital-to-analog
video encoders in a 64-lead LQFP package. Six high speed,
3.3 V, 11-bit video DACs provide support for composite
(CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog
outputs in standard definition (SD), enhanced definition (ED),
or high definition (HD) video formats.
The ADV7342/ADV7343 have a 24-bit pixel input port that can
be configured in a variety of ways. SD video formats are supported over an SDR interface, and ED/HD video formats are
supported over SDR and DDR interfaces. Pixel data can be
supplied in either the YCrCb or RGB color spaces.
The parts also support embedded EAV/SAV timing codes,
external video synchronization signals, and I2C® communication
protocol.
In addition, simultaneous SD and ED/HD input and output are
supported. Full-drive DACs ensure that external output buffering
is not required, while 216 MHz (SD and ED) and 297 MHz
(HD) oversampling ensures that external output filtering is not
required.
Cable detection and DAC autopower-down features keep power
consumption to a minimum.
Table 1 lists the video standards directly supported by the
ADV7342/ADV7343.
Table 1. Standards Directly Supported by the ADV7342/
ADV7343
Active
Resolution
720 × 240
720 × 288
720 × 480
I/P1
P
P
I
Frame
Rate (Hz)
59.94
50
29.97
Clock Input
(MHz)
27
27
27
720 × 576
I
25
27
640 × 480
I
29.97
24.54
768 × 576
I
25
29.5
720 × 483
720 × 483
720 × 483
720 × 576
720 × 483
720 × 576
1920 × 1035
1920 × 1035
1280 × 720
P
P
P
P
P
P
I
I
P
27
27
27
27
27
27
74.25
74.1758
74.25
1280 × 720
P
74.1758
SMPTE 296M
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
I
I
P
P
P
59.94
59.94
59.94
50
59.94
50
30
29.97
60, 50, 30,
25, 24
23.97,
59.94, 29.97
30, 25
29.97
30, 25, 24
23.98, 29.97
24
ITU-R
BT.601/656
ITU-R
BT.601/656
NTSC Square
Pixel
PAL Square
Pixel
SMPTE 293M
BTA T-1004
ITU-R BT.1358
ITU-R BT.1358
ITU-R BT.1362
ITU-R BT.1362
SMPTE 240M
SMPTE 240M
SMPTE 296M
74.25
74.1758
74.25
74.1758
74.25
SMPTE 274M
SMPTE 274M
SMPTE 274M
SMPTE 274M
ITU-R BT.709-5
1
I = interlaced, P = progressive.
Rev. E | Page 5 of 106
Standard
ADV7342/ADV7343
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
ALSB
VIDEO
DATA
4:2:2 TO 4:4:4
SD
DEINTERLEAVE
R
G/B
8-/16-/24-BIT
ED/HD
SUBCARRIER FREQUENCY
LOCK (SFL)
MPU PORT
VIDEO
DATA
RGB
TO
YCrCb
MATRIX
RGB
ASYNC
BYPASS
POWER
MANAGEMENT
CONTROL
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
YCrCb
TO
RGB
SIN/COS DDS
BLOCK
16×
FILTER
16×
FILTER
RGB
YCbCr
SDR/DDR
ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
VAA
ADV7342/ADV7343
VBI DATA SERVICE
INSERTION
VDD_IO
8-/16-/24-BIT
SD
AGND
SFL
PROGRAMMABLE
HDTV FILTERS
HDTV
TEST
PATTERN
GENERATOR
YCbCr
TO
RGB MATRIX
4×
FILTER
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
VIDEO TIMING GENERATOR
P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC
Figure 1.
Rev. E | Page 6 of 106
16x/4x OVERSAMPLING
DAC PLL
CLKIN (2) PVDD
11-BIT
DAC 1
DAC 1
11-BIT
DAC 2
DAC 2
11-BIT
DAC 3
DAC 3
11-BIT
DAC 4
DAC 4
11-BIT
DAC 5
DAC 5
11-BIT
DAC 6
DAC 6
REFERENCE
AND CABLE
DETECT
PGND EXT_LF (2) VREF
COMP (2)
RSET (2)
06399-001
GND_IO
VDD (2)
MULTIPLEXER
DGND (2)
Data Sheet
ADV7342/ADV7343
SPECIFICATIONS
POWER SUPPLY AND VOLTAGE SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 2.
Parameter
SUPPLY VOLTAGES
VDD
VDD_IO
PVDD
VAA
POWER SUPPLY REJECTION RATIO
Min
Typ
Max
Unit
1.71
1.71
1.71
2.6
1.8
3.3
1.8
3.3
0.002
1.89
3.63
1.89
3.465
V
V
V
V
%/%
Min
1.186
1.15
Typ
1.248
1.235
±10
Max
1.31
1.31
Unit
V
V
µA
Max
Unit
MHz
MHz
MHz
MHz
MHz
% of one clock cycle
% of one clock cycle
% of one clock cycle
% of one clock cycle
±ns
±ns
VOLTAGE REFERENCE SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter
Internal Reference Range, VREF
External Reference Range, VREF
External VREF Current1
1
External current required to overdrive internal VREF.
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter
fCLKIN_A
fCLKIN_A
fCLKIN_A
fCLKIN_B
fCLKIN_B
CLKIN_A High Time, t9
CLKIN_A Low Time, t10
CLKIN_B High Time, t9
CLKIN_B Low Time, t10
CLKIN_A Peak-to-Peak Jitter Tolerance
CLKIN_B Peak-to-Peak Jitter Tolerance
1
Conditions1
SD/ED
ED (at 54 MHz)
HD
ED
HD
Min
Typ
27
54
74.25
27
74.25
40
40
40
40
2
2
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
Rev. E | Page 7 of 106
ADV7342/ADV7343
Data Sheet
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V VREF = 1.235 V (driven externally).
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Full-Drive Output Current (Full-Scale)
Low-Drive Output Current (Full-Scale)3
DAC-to-DAC Matching
Output Compliance, VOC
Output Capacitance, COUT
Analog Output Delay4
DAC Analog Output Skew
Conditions
RSET = 510 Ω, RL = 37.5 Ω
DAC 1, DAC 2, DAC 3 enabled1
RSET = 510 Ω, RL = 37.5 Ω
DAC 1 enabled only2
RSET = 4.12 kΩ, RL = 300 Ω
DAC 1 to DAC 6
Min
33
Typ
34.6
Max
37
Unit
mA
33
33.5
37
mA
4.1
4.3
1.0
4.5
mA
%
V
pF
pF
ns
ns
ns
ns
0
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
1.4
10
6
8
6
2
1
Applicable to full-drive capable DACs only, that is, DAC 1, DAC 2, DAC 3.
The recommended method of bringing this typical value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.
3
Applicable to all DACs.
4
Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
1
2
DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 6.
Parameter
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIN
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
Conditions
Min
2.0
Typ
Max
0.8
±10
VIN = VDD_IO
4
ISOURCE = 400 µA
ISINK = 3.2 mA
VIN = 0.4 V, 2.4 V
2.4
0.4
±1.0
4
Unit
V
V
µA
pF
V
V
µA
pF
DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V
When VDD_IO is set to 1.8 V, all the digital video inputs and control inputs, such as I2C, HS, and VS, should use 1.8 V levels.
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
Input High Voltage, VIH
Input Low Voltage, VIL
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Output Capacitance
Conditions
Min
0.7 VDD_IO
Typ
Max
0.3 VDD_IO
4
ISOURCE = 400 µA
ISINK = 3.2 mA
VDD_IO – 0.4
0.4
4
Rev. E | Page 8 of 106
Unit
V
V
pF
V
V
pF
Data Sheet
ADV7342/ADV7343
DIGITAL TIMING SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 8.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t114
Data Input Hold Time, t124
Control Input Setup Time, t114
Control Input Hold Time, t124
Control Output Access Time, t134
Control Output Hold Time, t144
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (4×)
Conditions1
Min
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
2.1
2.3
2.3
1.7
1.0
1.1
1.1
1.0
2.1
2.3
1.7
1.0
1.1
1.0
Typ
Max
12
10
4.0
3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
68
67
78
84
Clock cycles
Clock cycles
Clock cycles
Clock cycles
ED oversampling disabled
ED oversampling enabled
41
46
Clock cycles
Clock cycles
HD oversampling disabled
HD oversampling enabled
40
44
Clock cycles
Clock cycles
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
Video data: C[7:0], Y[7:0], and S[7:0].
3
Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
1
2
Rev. E | Page 9 of 106
ADV7342/ADV7343
Data Sheet
DIGITAL TIMING SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 9.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t114
Data Input Hold Time, t124
Control Input Setup Time, t114
Control Input Hold Time, t124
Control Output Access Time, t134
Control Output Hold Time, t144
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (4×)
Conditions1
Min
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
1.4
1.9
1.9
1.6
1.4
1.5
1.5
1.3
1.4
1.2
1.0
1.4
1.0
1.0
Typ
Max
13
12
4.0
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
68
67
78
84
Clock cycles
Clock cycles
Clock cycles
Clock cycles
ED oversampling disabled
ED oversampling enabled
41
46
Clock cycles
Clock cycles
HD oversampling disabled
HD oversampling enabled
40
44
Clock cycles
Clock cycles
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
Video data: C[7:0], Y[7:0], and S[7:0].
3
Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
1
2
Rev. E | Page 10 of 106
Data Sheet
ADV7342/ADV7343
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 10.
Parameter
MPU PORT, I2C MODE1
SCL Frequency
SCL High Pulse Width, t1
SCL Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDA, SCL Rise Time, t6
SDA, SCL Fall Time, t7
Setup Time (Stop Condition), t8
1
Conditions
See Figure 19
Min
Typ
0
0.6
1.3
0.6
0.6
100
Max
Unit
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
300
300
0.6
Guaranteed by characterization.
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 11.
Parameter
NORMAL POWER MODE1, 2
IDD3
IDD_IO
IAA5
IPLL
Conditions
Min
SD only (16× oversampling)
ED only (8× oversampling)4
HD only (4× oversampling)4
SD (16× oversampling) and ED (8× oversampling)
SD (16× oversampling) and HD (4× oversampling)
Three DACs enabled (ED/HD only)
Six DACs enabled (SD only and simultaneous modes )
SD only, ED only, or HD only modes
Simultaneous modes
SLEEP MODE
IDD
IAA
IDD_IO
IPLL
Typ
2
Rev. E | Page 11 of 106
Unit
90
65
91
95
122
1
124
140
5
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
0.3
0.2
0.1
µA
µA
µA
µA
RSET1 = 510 Ω (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). RSET2 = 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode).
75% color bar test pattern applied to pixel data pins.
3
IDD is the continuous current required to drive the digital core.
4
Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5
IAA is the total current required to supply all DACs.
1
Max
ADV7342/ADV7343
Data Sheet
VIDEO PERFORMANCE SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = 25°C, VREF driven externally.
Table 12.
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity1 +ve
Differential Nonlinearity1 −ve
STANDARD DEFINTION (SD) MODE
Luminance Nonlinearity
Differential Gain
Differential Phase
Signal-to-Noise Ratio (SNR)
Conditions
Typ
Max
Unit
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
11
0.4
0.5
0.15
0.5
0.25
0.2
Bits
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
NTSC
NTSC
Luma ramp
Flat field full bandwidth
0.5
0.5
0.6
58
75
±%
%
Degrees
dB
dB
12.5
5.8
MHz
MHz
30
13.75
MHz
MHz
ENHANCED DEFINITION (ED) MODE
Luma Bandwidth
Chroma Bandwidth
HIGH DEFINITION (HD) MODE
Luma Bandwidth
Chroma Bandwidth
1
Min
Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For −ve DNL, the actual step value lies below the ideal step value.
Rev. E | Page 12 of 106
Data Sheet
ADV7342/ADV7343
TIMING DIAGRAMS
The following abbreviations are used in Figure 2 to Figure 13:
t9 = clock high time
t10 = clock low time
t11 = data setup time
t12 = data hold time
t13 = control output access time
t14 = control output hold time
In addition, refer to Table 36 for the ADV7342/ADV7343 input
configuration.
CLKIN_A
CONTROL
INPUTS
t12
t10
t9
S_HSYNC,
S_VSYNC
S7 TO S0/
Y7 TO Y0*
IN SLAVE MODE
Y0
Cb0
Y1
Cr0
Y2
Cb2
t11
Cr2
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
06399-002
t14
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 2. SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
CLKIN_A
t9
CONTROL
INPUTS
t10
t12
S_HSYNC,
S_VSYNC
IN SLAVE MODE
S7 TO S0/
Y7 TO Y0*
Y0
Y1
Y2
Y3
Y7 TO Y0/
C7 TO C0*
Cb0
Cr0
Cb2
Cr2
t11
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
06399-003
t14
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 3. SD Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC
Y7 TO Y0
G0
G1
G2
C7 TO C0
B0
B1
B2
R1
R2
t11
S7 TO S0
R0
CONTROL
OUTPUTS
t14
t13
Figure 4. SD Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000)
Rev. E | Page 13 of 106
06399-004
•
•
•
•
•
•
ADV7342/ADV7343
Data Sheet
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7 TO C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
t13
06399-005
CONTROL
OUTPUTS
t14
Figure 5. ED/HD-SDR Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 001)
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7 TO C0
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cr2
Cr3
Cr4
Cr5
t11
S7 TO S0
Cr0
Cr1
CONTROL
OUTPUTS
06399-006
t14
t13
Figure 6. ED/HD-SDR Only, 24-Bit, 4:4:4 YCrCb Pixel Input Mode (Input Mode 001)
CLKIN_A
t9
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
G0
G1
G2
G3
G4
G5
C7 TO C0
B0
B1
B2
B3
B4
B5
R2
R3
R4
R5
t11
S7 TO S0
R0
R1
CONTROL
OUTPUTS
t14
t13
Figure 7. ED/HD-SDR Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001)
Rev. E | Page 14 of 106
06399-007
CONTROL
INPUTS
t12
t10
Data Sheet
ADV7342/ADV7343
CLKIN_A*
t10
t9
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
Y0
Cb0
t11
Cb2
Y1
Cr0
Y2
Cr2
t12
t12
t11
t13
CONTROL
OUTPUTS
06399-008
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED
USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 8. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 010)
CLKIN_A*
t9
Y7 TO Y0
3FF
t11
t10
00
00
XY
Y0
Cb0
Cr0
Y1
t12
t12
t11
t13
CONTROL
OUTPUTS
06399-009
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED
USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 9. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010)
CLKIN_B
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
C7 TO C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Cb6
Cb2
Y2
Cr2
ED/HD INPUT
t11
CLKIN_A
t9
t10
t12
S_HSYNC,
S_VSYNC
SD INPUT
S7 TO S0
Cb0
Y0
Cr0
Y1
t11
Figure 10. SD and ED/HD-SDR, 16-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 011)
Rev. E | Page 15 of 106
06399-010
CONTROL
INPUTS
ADV7342/ADV7343
Data Sheet
CLKIN_B
CONTROL
INPUTS
t9
P_HSYNC,
P_VSYNC,
P_BLANK
t10
EH/HD INPUT
Y0
Cb0
Y7 TO Y0
t11
Cr0
Y1
t12
Y2
Cb2
Cr2
t12
t11
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC
SD INPUT
Cb0
Cr0
Y0
Y1
Cb2
Cr2
Y2
06399-011
S7 TO S0
t11
Figure 11. SD and ED/HD-DDR, 8-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 100)
CLKIN_A
CONTROL
INPUTS
t9
P_HSYNC,
P_VSYNC,
P_BLANK
t10
Cr0
Y0
Cb0
Y7 TO Y0
Y1
t12
t11
Cb2
Cr2
Y2
t13
t14
06399-012
CONTROL
OUTPUTS
Figure 12. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 111)
CLKIN_A
t9
Y7 TO Y0
t11
3FF
t12
t10
00
00
XY
Cb0
Y0
Cr0
Y1
t13
06399-013
t14
CONTROL
OUTPUTS
Figure 13. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111)
Rev. E | Page 16 of 106
Data Sheet
ADV7342/ADV7343
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
C7 TO C0
Cb0
Cr0
Cb2
Cr2
b
a AND b AS PER RELEVANT STANDARD.
06399-014
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 14. ED-SDR, 16-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Cb0
Y7 TO Y0
Y0
Cr0
Y1
b
a = 32 CLOCK CYCLES FOR 525p
a = 24 CLOCK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLOCK CYCLES FOR 525p
b(MIN) = 264 CLOCK CYCLES FOR 625p
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 15. ED-DDR, 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. E | Page 17 of 106
06399-015
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
ADV7342/ADV7343
Data Sheet
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
C7 TO C0
Cb0
Cr0
Cb2
Cr2
b
a AND b AS PER RELEVANT STANDARD.
06399-016
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 16. HD-SDR, 16-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Cb0
Y7 TO Y0
Y0
Cr0
Y1
b
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 17. HD-DDR, 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. E | Page 18 of 106
06399-017
a AND b AS PER RELEVANT STANDARD.
Data Sheet
ADV7342/ADV7343
S_HSYNC
S_VSYNC
Cb
Cr
Y
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 18. SD Input Timing Diagram (Timing Mode 1)
t3
t5
t3
SDA
t1
t2
t7
t4
t8
2C Mode)
Figure 19. MPU Port Timing Diagram (I
Rev. E | Page 19 of 106
06399-019
t6
SCL
Y
06399-018
Y7 TO Y0*
ADV7342/ADV7343
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 13.
Parameter1
VAA to AGND
VDD to DGND
PVDD to PGND
VDD_IO to GND_IO
AGND to DGND
AGND to PGND
AGND to GND_IO
DGND to PGND
DGND to GND_IO
PGND to GND_IO
Digital Input Voltage to GND_IO
Analog Outputs to AGND
Maximum CLKIN Input Frequency
Storage Temperature Range (TS)
Junction Temperature (TJ)
Lead Temperature (Soldering, 10 sec)
1
Rating
−0.3 V to +3.9 V
−0.3 V to +2.3 V
−0.3 V to +2.3 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to VDD_IO + 0.3 V
−0.3 V to VAA
80 MHz
−65°C to +150°C
150°C
260°C
Analog output short circuit to any power supply or common can be of an
indefinite duration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The ADV7342/ADV7343 are high performance integrated
circuits with an ESD rating of THRESHOLD
–
SUBTRACT
SIGNAL IN
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
+
DNR OUT
06399-077
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
Figure 73. Output Signal from ED/HD Adaptive Filter (Mode B)
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
SD DIGITAL NOISE REDUCTION
GAIN
Subaddress 0xA3 to Subaddress 0xA5
In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (coring gain border, coring gain data) of this noise
signal is subtracted from the original signal. In DNR sharpness
mode, if the absolute value of the filter output is less than the
programmed threshold, it is assumed to be noise. Otherwise, if
the level exceeds the threshold, now identified as a valid signal,
a fraction of the signal (coring gain border, coring gain data) is
added to the original signal to boost high frequency components
and sharpen the video image.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems or 16 pixels ×
16 pixels for MPEG1 systems (block size control). DNR can be
applied to the resulting block transition areas that are known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(border area).
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
NOISE
SIGNAL PATH
INPUT FILTER
BLOCK
Y DATA
INPUT
ADD SIGNAL
ABOVE
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
FILTER
OUTPUT
> THRESHOLD?
FILTER OUTPUT
< THRESHOLD
+
+
DNR OUT
MAIN SIGNAL PATH
06399-078
Digital noise reduction (DNR) is applied to the Y data only.
A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute
value of the filter output is compared to a programmable
threshold value (DNR threshold control). There are two DNR
modes available: DNR mode and DNR sharpness mode.
CORING GAIN DATA
CORING GAIN BORDER
Figure 74. SD DNR Block Diagram
Coring Gain Border—Subaddress 0xA3, Bits[3:0]
These four bits are assigned to the gain factor applied to border
areas. In DNR mode, the range of gain values is 0 to 1 in
increments of 1/8. This factor is applied to the DNR filter
output that lies below the set threshold range. The result is then
subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
Coring Gain Data—Subaddress 0xA3, Bits[7:4]
These four bits are assigned to the gain factor applied to the luma
data inside the MPEG pixel block. In DNR mode, the range of
gain values is 0 to 1 in increments of 1/8. This factor is applied
to the DNR filter output that lies below the set threshold range.
The result is then subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
Rev. E | Page 65 of 106
ADV7342/ADV7343
APPLY DATA
CORING GAIN
Data Sheet
DNR Input Select Control—Subaddress 0xA5, Bits[2:0]
APPLY BORDER
CORING GAIN
Three bits are assigned to select the filter, which is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that is DNR processed. Figure 77
shows the filter responses selectable with this control.
OXXXXXXOOXXXXXXO
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
06399-079
OXXXXXXOOXXXXXXO
OXXXXXXOOXXXXXXO
DNR27 TO DNR24 = 0x01
Figure 75. SD DNR Offset Control
DNR Threshold—Subaddress 0xA4, Bits[5:0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area—Subaddress 0xA4, Bit 6
When this bit is set to Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to Logic 0, the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
720 × 485 PIXELS
(NTSC)
TWO-PIXEL
BORDER DATA
DNR Mode Control—Subaddress 0xA5, Bit 3
This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal because this data is assumed to be valid data and
not noise. The overall effect is that the signal is boosted (similar
to using the extended SSAF filter).
DNR Block Offset Control—Subaddress 0xA5, Bits[7:4]
8 × 8 PIXEL BLOCK
06399-080
8 × 8 PIXEL BLOCK
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
Figure 76. SD DNR Border Area
SD ACTIVE VIDEO EDGE CONTROL
Block Size Control—Subaddress 0xA4, Bit 7
Subaddress 0x82, Bit 7
This bit is used to select the size of the data blocks to be
processed. Setting the block size control function to Logic 1
defines a 16 pixel × 16 pixel data block, and Logic 0 defines
an 8 pixel × 8 pixel data block, where one pixel refers to two
clock cycles at 27 MHz.
The ADV7342/ADV7343 are able to control fast rising and
falling signals at the start and end of active video in order to
minimize ringing.
When the active video edge control feature is enabled
(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last
three pixels of the active video on the luma channel are scaled
so that maximum transitions on these pixels are not possible.
1.0
FILTER D
At the start of active video, the first three pixels are multiplied by
1/8, 1/2, and 7/8, respectively. Approaching the end of active video,
the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively.
All other active video pixels pass through unprocessed.
FILTER C
0.6
0.4
FILTER B
0.2
FILTER A
0
0
1
2
3
4
FREQUENCY (MHz)
5
6
06399-081
MAGNITUDE
0.8
Figure 77. SD DNR Input Select
Rev. E | Page 66 of 106
Data Sheet
ADV7342/ADV7343
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
100 IRE
100 IRE
87.5 IRE
50 IRE
0 IRE
06399-082
12.5 IRE
0 IRE
Figure 78. Example of Active Video Edge Functionality
VOLTS
IRE:FLT
100
0.5
50
0
F2
L135
–50
0
2
4
6
8
10
12
06399-083
0
Figure 79. Example of Video Output with Subaddress 0x82, Bit 7 = 0
VOLTS
IRE:FLT
100
0.5
50
0
F2
L135
–50
–2
0
2
4
6
8
10
Figure 80. Example of Video Output with Subaddress 0x82, Bit 7 = 1
Rev. E | Page 67 of 106
12
06399-084
0
ADV7342/ADV7343
Data Sheet
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input
pixel data or external synchronization signals provided on the S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK pins (see
Table 54). It is also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 55 to Table 57).
Table 54. Timing Synchronization Signal Input Options
Signal
SD HSYNC In
SD VSYNC/FIELD In
ED/HD HSYNC In
ED/HD VSYNC/FIELD In
ED/HD BLANK In
1
Pin
S_HSYNC
S_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
Condition
SD slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0])1
SD slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0])1
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 55. Timing Synchronization Signal Output Options
Signal
SD HSYNC Out
SD VSYNC/FIELD Out
ED/HD HSYNC Out
ED/HD VSYNC/FIELD Out
1
Pin
S_HSYNC
S_VSYNC
S_HSYNC
S_VSYNC
Condition
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)1
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)1
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
Table 56. S_HSYNC Output Control1, 2
ED/HD Input Sync
Format
(Subaddress
0x30, Bit 2)
X
X
0
1
ED/HD HSYNC
Control
(Subaddress
0x34, Bit 1)
X
X
0
0
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
0
0
1
1
SD Sync
Output Enable
(Subaddress
0x02, Bit 6)
0
1
X
X
X
1
1
X
1
2
Signal on S_HSYNC Pin
Tristate
Pipelined SD HSYNC
Pipelined ED/HD HSYNC
Pipelined ED/HD HSYNC based on
AV Code H bit
Pipelined ED/HD HSYNC based on
horizontal counter
Duration
N/A
See the SD Timing section.
As per HSYNC timing.
Same as line blanking
interval.
Same as embedded
HSYNC.
In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
X = don’t care.
Rev. E | Page 68 of 106
Data Sheet
ADV7342/ADV7343
Table 57. S_VSYNC Output Control1, 2
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
X
X
ED/HD VSYNC
Control
(Subaddress
0x34, Bit 2)
X
X
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
0
0
SD Sync Output
Enable
(Subaddress 0x02,
Bit 6)
0
1
Video Standard
X
Interlaced
0
0
1
x
X
1
0
1
X
1
0
1
X
X
1
1
X
X
1
1
X
All HD interlaced
standards
All ED/HD
progressive
standards
All ED/HD
standards
except 525p
525p
1
2
Signal on S_VSYNC Pin
Tristate
Pipelined SD VSYNC/field
Pipelined ED/HD VSYNC
or field signal
Pipelined field signal
based on AV Code F bit
Pipelined VSYNC based
on AV Code V bit
Pipelined ED/HD VSYNC
based on the
vertical counter
Pipelined ED/HD VSYNC
based on the vertical
counter
Duration
N/A
See the SD Timing
section
As per VSYNC or
field signal timing
Field
Vertical blanking
interval
Aligned with
serration lines
Vertical blanking
interval
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
X = don’t care.
DAC 1 is monitored; that is, the luma or green output is
monitored.
LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power-sensitive applications, the ADV7342/ADV7343
support an Analog Devices proprietary low power mode of
operation on DAC 1, DAC 2, and DAC 3. To use this low power
mode, these DACs must be operating in full-drive mode (RSET1
= 510 Ω, RL = 37.5 Ω). Low power mode is not available in lowdrive mode (RSET = 4.12 kΩ, RL = 300 Ω). Low power mode can
be independently enabled or disabled on DAC 1, DAC 2, and
DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is
disabled by default on each DAC.
In low power mode, DAC current consumption is content
dependent. On a typical video stream, it can be reduced by as
much as 40%. For applications requiring the highest possible video
performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10
The ADV7342/ADV7343 include an Analog Devices proprietary cable detection feature. The cable detection feature is
available on DAC 1 and DAC 2, while operating in full-drive
mode (RSET1 = 510 Ω, RL1 = 37.5 Ω, assuming a connected
cable). The feature is not available in low-drive mode (RSET1 =
4.12 kΩ, RL = 300 Ω). For a DAC to be monitored, the DAC
must be powered up in Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, YC, YPrPb, and RGB output configurations.
Once per frame, the ADV7342/ADV7343 monitor DAC 1
and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,
respectively. If a cable is detected on one of the DACs, the
relevant bit is set to 0. If not, the bit is set to 1.
DAC AUTOPOWER-DOWN
Subaddress 0x10, Bit 4
For power-sensitive applications, a DAC autopower-down
feature can be enabled using Subaddress 0x10, Bit 4. This feature
is available only when the cable detection feature is enabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame. If they are unconnected,
some or all of the DACs automatically power down. Which
DAC or DACs are powered down depends on the selected
output configuration.
For CVBS/YC output configurations, if DAC 1 is unconnected,
only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and
DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is
unconnected, all three DACs power down. DAC 2 is not
monitored for YPrPb and RGB output configurations.
Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is
detected, the appropriate DAC or DACs remain powered up for
the duration of the frame. If no cable is detected, the appropriate
DAC or DACs power down until the next frame, when the process
is repeated.
For CVBS/YC output configurations, both DAC 1 and DAC 2
are monitored; that is, the CVBS and YC luma outputs are
monitored. For YPrPb and RGB output configurations, only
Rev. E | Page 69 of 106
ADV7342/ADV7343
Data Sheet
SLEEP MODE
The ADV7342/ADV7343 include a power-on reset (POR)
circuit to ensure correct operation after power-up.
Subaddress 0x00, Bit 0
SD TELETEXT INSERTION
In sleep mode, most of the digital I/O pins of the ADV7342/
ADV7343 are disabled. For inputs, this means that the external
data is ignored, and internally the logic normally driven by a
given input is just tied low or high. This includes CLKINx.
Subaddress 0xC9 to Subaddress 0xCE
The ADV7342/ADV7343 support the insertion of teletext data,
using a 2-pin interface, when operating in PAL mode. Teletext
insertion is enabled using Subaddress 0xC9, Bit 0.
For digital output pins, this means that the pin goes into tristate
(high impedance) mode.
In accordance with the PAL WST teletext standard, teletext data
should be inserted into the ADV7342/ADV7343 at a rate of
6.9375 Mbps. The teletext data can be inserted on the
S_VSYNC, P_VSYNC, or C0 pin. The pin on which the teletext
data is inserted is selected using Subaddress 0xC9, Bits [3:2].
There are some exceptions to allow the user to continue to
communicate with the part via I2C: the ALSB, SDA, and SCL
pins are kept alive.
PIXEL AND CONTROL PORT READBACK
When teletext insertion is enabled, a teletext request signal is
output from the ADV7342/ADV7343 to indicate when teletext
data should be inserted. The teletext request signal is output on
the SFL pin. The position (relative to the teletext data) and
width of the request signal are configurable using Subaddress
0xCA. The request signal can operate in either a line or a bit
mode. The request signal mode is controlled using Subaddress
0xC9, Bit 1.
Subaddress 0x12 to Subaddress 0x14, Subaddress 0x16
The ADV7342/ADV7343 support the readback of most digital
inputs via the I2C MPU port. This feature is useful for board
level connectivity testing with upstream devices.
The pixel port (S[7:0], Y[7:0], and C[7:0]), the control port
(S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK),
and the SFL pin are available for readback via the MPU port.
The readback registers are located at Subaddress 0x12 to
Subaddress 0x14 and Subaddress 0x16.
To account for the noninteger relationship between the teletext
insertion rate (6.9375 Mbps) and the pixel clock (27 MHz), a
teletext insertion protocol is implemented in the ADV7342/
ADV7343. At a rate of 6.9375 Mbps, the time taken for the
insertion of 37 teletext bits equates to 144 pixel clock cycles (at
27 MHz). For every 37 teletext bits inserted into the ADV7342/
ADV7343, the 10th, 19th, 28th, and 37th bits are carried for three
pixel clock cycles, and the remainder are carried for four pixel
clock cycles (totaling 144 pixel clock cycles). The teletext
insertion protocol repeats every 37 teletext bits or 144 pixel
clock cycles until all 360 teletext bits are inserted.
When using this feature, apply a clock signal to the CLKIN_A
pin to register the levels applied to the input pins.
RESET MECHANISM
Subaddress 0x17, Bit 1
The ADV7342/ADV7343 have a software reset accessible via
the I2C MPU port. A software reset is activated by writing
a 1 to Subaddress 0x17, Bit 1. This resets all registers to their
default values. This bit is self-clearing; that is, after a 1 has been
written to the bit, the bit automatically returns to 0.
45 BYTES (360 BITS) – PAL
RUN-IN CLOCK
Figure 81. Teletext VBI Line
Rev. E | Page 70 of 106
06399-143
ADDRESS AND DATA
TELETEXT VBI LINE
Data Sheet
ADV7342/ADV7343
tSYNTTXOUT
CVBS/Y
tPD
tPD
HSYNC
10.2µs
TTXDATA
TTXDEL
TTXREQ
PROGRAMMABLE PULSE EDGES
tSYNTTXOUT = 10.2µs.
tPD = PIPELINE DELAY THROUGH ADV7342/ADC7343.
TTXDEL = TTXREQ TO TTXDATA (PROGRAMMABLE RANGE = 4 BITS [0 TO 15 PIXEL CLOCK CYCLES]).
Figure 82. Teletext Functionality Diagram
Rev. E | Page 71 of 106
06399-144
TTXST
ADV7342/ADV7343
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT AND DESIGN
UNUSED PINS
If the S_HSYNC, S_VSYNC, P_HSYNC, and P_VSYNC pins are
not used, they should be tied to VDD_IO through a pull-up resistor
(10 kΩ or 4.7 kΩ). Any other unused digital inputs should be tied
to ground. Unused digital output pins should be left floating. DAC
outputs can be either left floating or connected to GND. Disabling
these outputs is recommended.
DAC CONFIGURATIONS
The ADV7342/ADV7343 contain six DACs. All six DACs can
be configured to operate in low-drive mode. Low-drive mode is
defined as 4.33 mA full-scale current into a 300 Ω load, RL.
An optional reconstruction (anti-imaging) low-pass filter (LPF)
may be required on the ADV7342/ADV7343 DAC outputs if
the ADV7342/ADV7343 are connected to a device that requires
this filtering.
The filter specifications vary with the application. The use of
16× (SD), 8× (ED), or 4× (HD) oversampling can remove the
requirement for a reconstruction filter altogether.
For applications requiring an output buffer and reconstruction
filter, the ADA4430-1, ADA4411-3, and ADA4410-6 integrated
video filter buffers should be considered.
Table 58. ADV7342/ADV7343 Output Rates
DAC 1, DAC 2, and DAC 3 can also be configured to operate in
full-drive mode. Full-drive mode is defined as 34.7 mA fullscale current into a 37.5 Ω load, RL. Full-drive is the recommended
mode of operation for DAC 1, DAC 2, and DAC 3.
Input Mode
(Subaddress 0x01,
Bits[6:4])
SD Only
The ADV7342/ADV7343 contain two RSET pins. A resistor
connected between the RSET1 pin and AGND is used to control
the full-scale output current and, therefore, the DAC output
voltage levels of DAC 1, DAC 2, and DAC 3. For low-drive
operation, RSET1 must have a value of 4.12 kΩ, and RL must have a
value of 300 Ω. For full-drive operation, RSET1 must have a value
of 510 Ω, and RL must have a value of 37.5 Ω.
ED Only
A resistor connected between the RSET2 pin and AGND is used
to control the full-scale output current and, therefore, the DAC
output voltage levels of DAC 4, DAC 5, and DAC 6. RSET2 must
have a value of 4.12 kΩ, and RL must have a value of 300 Ω (that
is, low-drive operation only).
HD Only
PLL Control
(Subaddress
0x00, Bit 1)
Off
On
Off
On
Off
On
Output Rate (MHz)
27
(2x)
216
(16x)
27
(1x)
216
(8x)
74.25
(1x)
297
(4x)
Table 59. Output Filter Requirements
The resistors connected to the RSET1 and RSET2 pins should have a
1% tolerance.
Application
SD
SD
ED
ED
HD
HD
The ADV7342/ADV7343 contain two compensation pins,
COMP1 and COMP2. A 2.2 nF compensation capacitor should
be connected from each of these pins to VAA.
DAC
OUTPUT
Cutoff
Frequency
(MHz)
>6.5
>6.5
>12.5
>12.5
>30
>30
Oversampling
2×
16×
1×
8×
1×
4×
Attenuation
–50 dB at
(MHz)
20.5
209.5
14.5
203.5
44.25
267
10µH
3
600Ω
VOLTAGE REFERENCE
22pF
75Ω
600Ω
1
BNC
OUTPUT
4
06399-085
560Ω
560Ω
Figure 83. Example of Output Filter for SD, 16× Oversampling
4.7µH
DAC
OUTPUT
VIDEO OUTPUT BUFFER AND OPTIONAL
OUTPUT FILTER
3
6.8pF
600Ω
6.8pF
600Ω
1
Rev. E | Page 72 of 106
BNC
OUTPUT
4
560Ω
An output buffer is necessary on any DAC that operates in lowdrive mode (RSETx = 4.12 kΩ, RL = 300 Ω). Analog Devices
produces a range of op amps suitable for this application, for
example, the AD8061. For more information about line driver
buffering circuits, see the relevant op amp data sheet.
75Ω
560Ω
Figure 84. Example of Output Filter for ED, 8× Oversampling
06399-086
The ADV7342/ADV7343 contain an on-chip voltage reference
that can be used as a board-level voltage reference via the VREF
pin. Alternatively, the ADV7342/ADV7343 can be used with an
external voltage reference by connecting the reference source to
the VREF pin. For optimal performance, use an external voltage
reference such as the AD1580 with the ADV7342/ADV7343. If an
external voltage reference is not used, a 0.1 µF capacitor should
be connected from the VREF pin to VAA.
Data Sheet
ADV7342/ADV7343
DAC
OUTPUT
CIRCUIT FREQUENCY RESPONSE
0
300Ω
1
75Ω
390nH
33pF
4
33pF
75Ω
200
MAGNITUDE (dB)
BNC
OUTPUT
3
PHASE
(Degrees)
–10
120
1
GROUP DELAY (Seconds)
06399-087
500Ω
500Ω
Figure 85. Example of Output Filter for HD, 4× Oversampling
CIRCUIT FREQUENCY RESPONSE
0
24n
–30
–40
–40
–120
–60
1
–90
–30
PHASE (Degrees)
–50
GROUP DELAY (Seconds)
–60
12n
–150
PRINTED CIRCUIT BOARD (PCB) LAYOUT
9n
–180
The ADV7342/ADV7343 are highly integrated circuits
containing both precision analog and high speed digital
circuitry. They are designed to minimize interference effects on
the integrity of the analog circuitry by the high speed digital
circuitry. It is imperative that these same design and layout
techniques be applied to the system-level design so that optimal
performance is achieved.
3n
–240
0
1G
10M
100M
FREQUENCY (Hz)
06399-088
–80
1M
Figure 86. Output Filter Plot for SD, 16× Oversampling
CIRCUIT FREQUENCY RESPONSE
0
The layout should be optimized for lowest noise on the
ADV7342/ADV7343 power and ground planes by shielding the
digital inputs and providing good power supply decoupling.
480
18n
400
–10
MAGNITUDE (dB)
It is recommended to use a 4-layer printed circuit board with
ground and power planes separating the signal trace layer and
the solder side layer.
16n
320
–20
14n
240
–30
PHASE
(Degrees)
GROUP DELAY (Seconds)
12n
Component Placement
10n
Component placement should be carefully considered to
separate noisy circuits, such as clock signals and high speed
digital circuitry, from analog circuitry.
160
80
–50
8n
–60
0
–70
–80
–80
–160
6n
10M
100M
2n
–240
0
1G
FREQUENCY (Hz)
Figure 87. Output Filter Plot for ED, 8× Oversampling
06399-089
4n
–90
1M
100
Figure 88. Output Filter Plot for HD, 4× Oversampling
6n
–210
–70
10
FREQUENCY (MHz)
15n
–120
–40
–200
–50
18n
06399-090
21n
MAGNITUDE (dB)
GAIN (dB)
40
–30
–20
GAIN (dB)
–20
0
–10
–40
GAIN (dB)
4
PHASE (Degrees)
3
The external loop filter components and components connected
to the COMP, VREF, and RSETx pins should be placed as close as
possible to and on the same side of the PCB as the ADV7342/
ADV7343. Adding vias to the PCB to get the components closer
to the ADV7342/ADV7343 is not recommended.
It is recommended that the ADV7342/ADV7343 be placed as
close as possible to the output connector, with the DAC output
traces as short as possible.
The termination resistors on the DAC output traces should be
placed as close as possible to and on the same side of the PCB as
the ADV7342/ADV7343. The termination resistors should
overlay the PCB ground plane.
Rev. E | Page 73 of 106
ADV7342/ADV7343
Data Sheet
External filter and buffer components connected to the DAC
outputs should be placed as close as possible to the ADV7342/
ADV7343 to minimize the possibility of noise pickup from
neighboring circuitry and to minimize the effect of trace
capacitance on output bandwidth. This is particularly important
when operating in low-drive mode (RSETx = 4.12 kΩ, RL = 300 Ω).
Power Supplies
It is recommended that a separate regulated supply be provided
for each power domain (VAA, VDD, VDD_IO, and PVDD). For
optimal performance, linear regulators rather than switch mode
regulators should be used. If switch mode regulators must be
used, care must be taken with regard to the quality of the output
voltage in terms of ripple and noise. This is particularly true for
the VAA and PVDD power domains. Each power supply should be
individually connected to the system power supply at a single
point through a suitable filtering device, such as a ferrite bead.
Power Supply Decoupling
It is recommended that each power supply pin be decoupled
with 10 nF and 0.1 µF ceramic capacitors. The VAA, PVDD,
VDD_IO, and both VDD pins should be individually decoupled to
ground. The decoupling capacitors should be placed as close as
possible to the ADV7342/ADV7343 with the capacitor leads
kept as short as possible to minimize lead inductance.
A 1 µF tantalum capacitor is recommended across the VAA
supply in addition to the 10 nF and 0.1 µF ceramic capacitors.
be established a minimum of 250 µs prior to the VDD power
supply being established. The VAA and PVDD power supplies can
be established at any time and in any order. Tying ALSB to
VDD_IO completely removes this PSS requirement.
Digital Signal Interconnect
The digital signal traces should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal traces should not overlay the VAA or PVDD power plane.
Due to the high clock rates used, avoid long clock traces to the
ADV7342/ADV7343 to minimize noise pickup.
Any pull-up termination resistors for the digital inputs should
be connected to the VDD_IO power supply.
Any unused digital inputs should be tied to ground.
Analog Signal Interconnect
DAC output traces should be treated as transmission lines with
appropriate measures taken to ensure optimal performance (for
example, impedance matched traces). The DAC output traces
should be kept as short as possible. The termination resistors on
the DAC output traces should be placed as close as possible to,
and on the same side of the PCB as, the ADV7342/ADV7343.
To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the
traces connected to the DAC output pins. Adding ground traces
between the DAC output traces is also recommended.
Power Supply Sequencing
If the ALSB pin is tied low, a power supply sequence is required
for proper operation of the part. The VDD_IO power supply must
Rev. E | Page 74 of 106
Data Sheet
ADV7342/ADV7343
TYPICAL APPLICATION CIRCUIT
FERRITE BEAD
33µF
10µF
GND_IO
GND_IO
FERRITE BEAD
PVDD
(1.8V)
33µF
10µF
PGND
PGND
FERRITE BEAD
VAA
33µF
33µF
DGND
0.01µF
GND_IO
GND_IO
0.1µF
0.01µF
PGND
10µF
AGND
10µF
0.1µF
DGND
PGND
PIXEL PORT INPUTS
AGND
VDD POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
DGND
CLOCK INPUTS
I2C PORT
150nF
VDD_IO
VAA
PVDD
VDD
VDD
VAA
1.235V
VREF
S0
S1
S2
S3
S4
S5
S6
S7
AD1580
0.1µF
RSET1
ADV7342/ADV7343
RSET2
AGND
4.12kΩ
510Ω
AGND
AGND
OPTIONAL LPF
DAC 1
DAC 1
OPTIONAL LPF
DAC 2
DAC 3
OPTIONAL LPF
ALSB
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
75Ω
75Ω
75Ω
AGND
AGND
AGND
TIE EITHER LOW
OR HIGH
(SEE NOTE 2)
DAC1 TO DAC3 LOW DRIVE OPTION
ADA4411-3
75Ω
DAC 4
RSET1
DAC 4
4.12kΩ
AGND
LPF
ADA4411-3
300Ω
P_HSYNC
P_VSYNC
P_BLANK
DAC 1
LPF
ADA4411-3
75Ω
DAC 5
300Ω
DAC 5
AGND
LPF
CLKIN_A
CLKIN_B
75Ω
DAC 1
AGND
ADA4411-3
300Ω
SDA
SCL
300Ω
75Ω
DAC 6
DAC 6
AGND
LPF
ADA4411-3
300Ω
170Ω
75Ω
DAC 3
AGND PGND DGND DGND
GND_IO
DAC 2
LPF
ADA4411-3
EXT_LF2
75Ω
DAC 2
AGND
170Ω
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PINS AND ON THE SAME
SIDE OF THE PCB AS THE
ADV7342/ADV7343.
DAC1 TO DAC3 FULL DRIVE OPTION
DAC 2
DAC 3
EXT_LF1
12nF
OPTIONAL. IF THE INTERNAL VOLTAGE
REFERENCE IS USED, A 0.1µF CAPACITOR
SHOULD BE CONNECTED FROM VREF TO VAA.
1.1kΩ
EXTERNAL LOOP FILTERS
PVDD
12nF
150nF
3. THE RESISTORS CONNECTED TO THE RSET PINS SHOULD
HAVE A 1% TOLERANCE.
COMP2
S_HSYNC
S_VSYNC
CONTROL
INPUTS/OUTPUTS
2.2nF
I2C DEVICE ADDRESS = 0xD4 OR 0x54
I2C DEVICE ADDRESS = 0xD6 OR 0x56
ADI RECOMMENDS TO TIE ALSB TO VDD_IO. PLEASE
REFER TO POWER SUPPLY SEQUENCING SECTION FOR
MORE INFORMATION ON THIS.
VAA
2.2nF
COMP1
C0
C1
C2
C3
C4
C5
C6
C7
UNUSED
CONNECT TO DGND
ALSB = 0,
ALSB = 1,
VAA POWER
SUPPLY
AGND DECOUPLING
VAA
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
2. THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE
ALSB PIN:
1µF
0.01µF
DGND
NOTES
1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS
CONNECTED TO THE COMP, RSET , VREF AND DAC OUTPUT
PINS SHOULD BE LOCATED CLOSE TO AND ON THE SAME
SIDE OF THE PCB AS THE ADV7342/ADV7343.
VDD_IO POWER
SUPPLY
DECOUPLING
PVDD POWER
SUPPLY
DECOUPLING
0.01µF
0.1µF
AGND
AGND
FERRITE BEAD
VDD
(1.8V)
0.1µF
DAC 3
LPF
AGND
300Ω
AGND PGND DGND DGND
AGND
GND_IO
Figure 89. ADV7342/ADV7343 Typical Application Circuit
Rev. E | Page 75 of 106
06399-091
VDD_IO
ADV7342/ADV7343
Data Sheet
COPY GENERATION MANAGEMENT SYSTEM
SD CGMS
Subaddress 0x99 to Subaddress 0x9B
The ADV7342/ADV7343 support a copy generation
management system (CGMS) conforming to the EIAJ CPR1204 and ARIB TR-B15 standards. CGMS data is transmitted
on Line 20 of odd fields and Line 283 of even fields. Subaddress
0x99, Bits[6:5] control whether CGMS data is output on odd or
even fields or both.
SD CGMS data can be transmitted only when the ADV7342/
ADV7343 are configured in NTSC mode. The CGMS data is 20
bits long. The CGMS data is preceded by a reference pulse of
the same amplitude and duration as a CGMS bit (see Figure 90).
ED CGMS
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i
CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.
The HD CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43.
The ADV7342/ADV7343 also support CGMS Type B packets in
HD mode (720p and 1080i) in accordance with CEA-805-A.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
720p CGMS data is applied to Line 23 of the luminance vertical
blanking interval.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
1080i CGMS data is applied to Line 18 and Line 581 of the
luminance vertical blanking interval.
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
525p Mode
The HD CGMS Type B data registers are at Subaddress 0x5E to
Subaddress 0x6E.
The ADV7342/ADV7343 support a copy generation management system (CGMS) in 525p mode in accordance with EIAJ
CPR-1204-1.
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS
CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS
data bits, C19 to C14, which comprise the 6-bit CRC check
sequence, are automatically calculated on the
ADV7342/ADV7343. This calculation is based on the lower 14
bits (C13 to C0) of the data in the CGMS data registers, and the
result is output with the remaining 14 bits to form the complete
20 bits of the CGMS data. The calculation of the CRC sequence
is based on the polynomial x6 + x + 1 with a preset value of
111111.
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p
CGMS data is inserted on Line 41 and the 525p CGMS data
registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV7342/ADV7343 also support CGMS
Type B packets in 525p mode in accordance with CEA-805-A.
When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
525p CGMS Type B data is inserted on Line 40. The 525p CGMS
Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
625p Mode
The ADV7342/ADV7343 support a copy generation management
system (CGMS) in 625p mode in accordance with IEC62375
(2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p
CGMS data is inserted on Line 43. The 625p CGMS data
registers are at Subaddress 0x42 and Subaddress 0x43.
HD CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
The ADV7342/ADV7343 support a copy generation management
system (CGMS) in HD mode (720p and 1080i) in accordance
with EIAJ CPR-1204-2.
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
CGMS CRC FUNCTIONALITY
If SD CGMS CRC or ED/HD CGMS CRC are disabled, all
20 bits (C19 to C0) are output directly from the CGMS registers
(CRC must be calculated by the user manually).
If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is
enabled, the upper six CGMS Type B data bits (P122 to P127)
that comprise the 6-bit CRC check sequence are automatically
calculated on the ADV7342/ADV7343. This calculation is
based on the lower 128 bits (H0 to H5 and P0 to P121) of the
data in the CGMS Type B data registers. The result is output
with the remaining 128 bits to form the complete 134 bits of the
CGMS Type B data. The calculation of the CRC sequence is
based on the polynomial x6 + x + 1 with a preset value of
111111.
If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5
and P0 to P127) are output directly from the CGMS Type B
registers (CRC must be calculated by the user manually).
Rev. E | Page 76 of 106
Data Sheet
ADV7342/ADV7343
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
–40 IRE
06399-092
49.1µs ± 0.5µs
11.2µs
2.235µs ± 20ns
Figure 90. Standard Definition CGMS Waveform
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2
BIT 20
70% ± 10%
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
T = 1/(fH × 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T ± 30ns
06399-093
21.2µs ± 0.22µs
22T
5.8µs ± 0.15µs
6T
Figure 91. Enhanced Definition (525p) CGMS Waveform
R = RUN-IN
S = START CODE
PEAK WHITE
R
500mV ± 25mV
S
C0
LSB
C1
C2
C3
C4
SYNC LEVEL
C5
C6
C7
C8
C9
C10
C11 C12
C13
MSB
06399-094
13.7µs
5.5µs ± 0.125µs
Figure 92. Enhanced Definition (625p) CGMS Waveform
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2
BIT 20
70% ± 10%
C0
0mV
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
T ± 30ns
4T
3.128µs ± 90ns
17.2µs ± 160ns
22T
T = 1/(fH × 1650/58) = 781.93ns
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 93. High Definition (720p) CGMS Waveform
Rev. E | Page 77 of 106
06399-095
–300mV
C1
ADV7342/ADV7343
Data Sheet
CRC SEQUENCE
+700mV
REF
BIT 20
BIT 1 BIT 2
70% ± 10%
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
T ± 30ns
22.84µs ± 210ns
22T
T = 1/(fH × 2200/77) = 1.038µs
fH = HORIZONTAL SCAN FREQUENCY
1H
4T
4.15µs ± 60ns
06399-096
–300mV
Figure 94. High Definition (1080i) CGMS Waveform
CRC SEQUENCE
+700mV
START
70% ± 10%
BIT 1 BIT 2
H0
H1
BIT 134
H2
H3
H4
H5
P0
P1
P2
P3
P4
.
.
.
P122 P123 P124 P125 P126 P127
0mV
06399-097
–300mV
NOTES
1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
Figure 95. Enhanced Definition (525p) CGMS Type B Waveform
CRC SEQUENCE
+700mV
START
70% ± 10%
BIT 1 BIT 2
H0
H1
BIT 134
H2
H3
H4
H5
P0
P1
P2
P3
P4
.
.
.
P122 P123 P124 P125 P126 P127
0mV
NOTES
1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
Figure 96. High Definition (720p and 1080i) CGMS Type B Waveform
Rev. E | Page 78 of 106
06399-098
–300mV
Data Sheet
ADV7342/ADV7343
SD WIDE SCREEN SIGNALING
Figure 97). The latter portion of Line 23 (after 42.5 µs from the
falling edge of HSYNC) is available for the insertion of video.
WSS data transmission on Line 23 can be enabled using
Subaddress 0x99, Bit 7. It is possible to blank the WSS portion
of Line 23 with Subaddress 0xA1, Bit 7.
Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B
The ADV7342/ADV7343 support wide screen signaling (WSS)
conforming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the
device is configured in PAL mode. The WSS data is 14 bits long.
The function of each of these bits is shown in Table 60. The
WSS data is preceded by a run-in sequence and a start code (see
Table 60. Function of WSS
Bit Description
Aspect Ratio, Format, Position
13
12
11
10
9
Bit Number
8 7 6 5
4
Mode
3
1
0
0
1
0
1
1
0
2
0
0
0
0
1
1
1
1
W8
W9
0
1
Color Encoding
0
1
Helper Signals
0
1
Reserved
Teletext Subtitles
0
0
1
Open Subtitles
0
0
1
1
Surround Sound
0
1
0
1
0
1
Copyright
0
1
Copy Protection
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Setting
4:3, full format, N/A
14:9, letterbox, center
14:9, letterbox, top
16:9, letterbox, center
16:9, letterbox, top
>16:9, letterbox, center
14:9, full format, center
16:0, N/A, N/A
Camera mode
Film mode
Normal PAL
Motion Adaptive ColorPlus
Not present
Present
N/A
No
Yes
No
Subtitles in active image area
Subtitles out of active image area
Reserved
No
Yes
No copyright asserted or unknown
Copyright asserted
Copying not restricted
Copying restricted
500mV
RUN-IN
SEQUENCE
START
CODE
W0
W1
W2
W3
W4
W5
W6
W7
W10 W11 W12 W13
ACTIVE
VIDEO
11.0µs
06399-099
38.4µs
42.5µs
Figure 97. WSS Waveform Diagram
Rev. E | Page 79 of 106
ADV7342/ADV7343
Data Sheet
SD CLOSED CAPTIONING
and Line 284. All pixels inputs are ignored on Line 21 and on
Line 284 if closed captioning is enabled.
Subaddress 0x91 to Subaddress 0x94
The ADV7342/ADV7343 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and
Line 284 of the even fields.
The FCC Code of Federal Regulations (CFR) 47 Section 15.119
and EIA-608 describe the closed captioning information for
Line 21 and Line 284.
Closed captioning consists of a seven-cycle sinusoidal burst that
is frequency- and phase-locked to the caption data. After the
clock run-in signal, the blanking level is held for two data bits
and is followed by the Logic 1 start bit. Sixteen bits of data
follow the start bit. These consist of two 8-bit bytes, seven data
bits, and one odd parity bit. The data for these bytes is stored in
the SD closed captioning registers (Subaddress 0x93 to
Subaddress 0x94).
The ADV7342/ADV7343 also support the extended closed
captioning operation, which is active during even fields and
encoded on scan Line 284. The data for this operation is stored
in the SD closed captioning registers (Subaddress 0x91 to
Subaddress 0x92).
The ADV7342/ADV7343 automatically generate all clock runin signals and timing that support closed captioning on Line 21
10.5 ± 0.25µs
The ADV7342/ADV7343 use a single buffering method. This
means that the closed captioning buffer is only 1-byte deep.
Therefore, there is no frame delay in outputting the closed
captioning data, unlike other 2-byte deep buffering systems.
The data must be loaded one line before it is output on Line 21
and Line 284. A typical implementation of this method is to use
VSYNC to interrupt a microprocessor, which in turn loads the
new data (two bytes) in every field. If no new data is required
for transmission, 0s must be inserted in both data registers; this
is called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21. Otherwise, a TV does not
recognize them. If there is a message such as “Hello World”
that has an odd number of characters, it is important to add a
blank character at the end to make sure that the end-of-caption,
2-byte control code lands in the same field.
12.91µs
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
S
T
A D0 TO D6
R
T
50 IRE
D0 TO D6
BYTE 0
P
A
R
I
T
Y
BYTE 1
40 IRE
10.003µs
27.382µs
33.764µs
Figure 98. SD Closed Captioning Waveform, NTSC
Rev. E | Page 80 of 106
06399-100
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
Data Sheet
ADV7342/ADV7343
INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
ED/HD TEST PATTERNS
The ADV7342/ADV7343 are able to internally generate SD
color bar and black bar test patterns. For this function, a
27 MHz clock signal must be applied to the CLKIN_A pin.
The ADV7342/ADV7343 are able to internally generate ED/HD
black bar and hatch test patterns. For ED test patterns, a 27 MHz
clock signal must be applied to the CLKIN_A pin. For HD test
patterns, a 74.25 MHz clock signal must be applied to the
CLKIN_A pin.
The register settings in Table 61 are used to generate an SD
NTSC 75% color bar test pattern. CVBS output is available on
DAC 4, S-Video (Y-C) output is on DAC 5 and DAC 6, and
YPrPb output is on DAC 1 to DAC 3. On power-up, the
subcarrier frequency registers default to the appropriate values
for NTSC. All other registers are set as normal/default.
Table 61. SD NTSC Color Bar Test Pattern Register Writes
Subaddress
0x00
0x82
0x84
Setting
0xFC
0xC9
0x40
To generate an SD NTSC black bar test pattern, the settings
shown in Table 61 should be used with an additional write of
0x24 to Subaddress 0x02.
For PAL output of either test pattern, the same settings are used,
except that Subaddress 0x80 is programmed to 0x11, and the
subcarrier frequency registers are programmed as shown in
Table 62.
Table 62. PAL FSC Register Writes
Subaddress
0x8C
0x8D
0x8E
0x8F
Description
FSC0
FSC1
FSC2
FSC3
The register settings in Table 63 are used to generate an ED
525p hatch test pattern. YPrPb output is available on DAC 1 to
DAC 3. All other registers are set as normal/default.
Table 63. ED 525p Hatch Test Pattern Register Writes
Subaddress
0x00
0x01
0x31
Setting
0x1C
0x10
0x05
To generate an ED 525p black bar test pattern, the settings
shown in Table 63 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the settings
shown in Table 63 should be used, except that 0x0D should be
written to Subaddress 0x31.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
For ED/HD standards other than 525p, the settings shown in
Table 63 (and subsequent comments) are used, except that
Subaddress 0x30, Bits[7:3] are updated as appropriate.
Setting
0xCB
0x8A
0x09
0x2A
Note that, when programming the FSC registers, the user must
write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full
FSC value to be written is accepted only after the FSC3 write is
complete.
Rev. E | Page 81 of 106
ADV7342/ADV7343
Data Sheet
SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV7342/ADV7343 are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the
pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. If the S_VSYNC and S_HSYNC pins are not used, they should be tied to
VDD_IO during this mode.
ANALOG
VIDEO
EAV CODE
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
0 F F A A A
0 F F B B B
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
4 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
1440 CLOCK
1440 CLOCK
280 CLOCK
06399-101
INPUT PIXELS
SAV CODE
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 99. SD Slave Mode 0
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV7342/ADV7343 generate H and F signals required for the SAV and EAV time codes in the CCIR656 standard. The H bit is
output on S_HSYNC and the F bit is output on S_VSYNC.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
F
ODD FIELD
06399-102
H
EVEN FIELD
Figure 100. SD Master Mode 0, NTSC
Rev. E | Page 82 of 106
Data Sheet
ADV7342/ADV7343
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
4
3
2
6
5
21
7
22
23
H
ODD FIELD
EVEN FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
314
313
315
316
318
317
319
335
334
320
336
ODD FIELD
F
06399-103
H
EVEN FIELD
Figure 101. SD Master Mode 0, PAL
ANALOG
VIDEO
06399-104
H
F
Figure 102. SD Master Mode 0, Data Transitions
Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)
In this mode, the ADV7342/ADV7343 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field
input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as required by
the CCIR-624 standard. HSYNC and FIELD are input on the S_HSYNC and S_VSYNC pins, respectively.
DISPLAY
DISPLAY
522
523
VERTICAL BLANK
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
HSYNC
FIELD
EVEN FIELD ODD FIELD
DISPLAY
260
261
DISPLAY
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
FIELD
ODD FIELD
06399-105
HSYNC
EVEN FIELD
Figure 103. SD Slave Mode 1, NTSC
Rev. E | Page 83 of 106
ADV7342/ADV7343
Data Sheet
DISPLAY
DISPLAY
622
623
VERTICAL BLANK
624
625
1
2
4
3
5
6
7
21
22
23
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
FIELD
06399-106
HSYNC
EVEN FIELD
Figure 104. SD Slave Mode 1, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as
required by the CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and
FIELD are output on the S_HSYNC and S_VSYNC pins, respectively.
HSYNC
FIELD
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Cr
Y
06399-107
PIXEL
DATA
Figure 105. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV7342/ADV7343 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV7342/ADV7343 automatically blank all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are input
on the S_HSYNC and S_VSYNC pins, respectively.
Rev. E | Page 84 of 106
Data Sheet
ADV7342/ADV7343
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
4
3
2
5
7
6
8
10
9
20
11
21
22
HSYNC
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
VSYNC
06399-108
HSYNC
EVEN FIELD
ODD FIELD
Figure 106. SD Slave Mode 2, NTSC
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
23
22
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
309
310
DISPLAY
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
VSYNC
06399-109
HSYNC
EVEN FIELD
Figure 107. SD Slave Mode 2, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV7342/ADV7343 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV7342/ADV7343 automatically blank all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are output
on the S_HSYNC and S_VSYNC pins, respectively.
HSYNC
VSYNC
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 108. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
Rev. E | Page 85 of 106
Y
Cr
Y
06399-110
PIXEL
DATA
ADV7342/ADV7343
Data Sheet
HSYNC
VSYNC
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Cb
06399-111
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 109. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7342/ADV7343 accept or generate horizontal sync and odd/even field signals. When HSYNC is high, a transition
of the field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as
required by the CCIR-624 standard. HSYNC and VSYNC are output in master mode and input in slave mode on the S_VSYNC and
S_VSYNC pins, respectively.
DISPLAY
DISPLAY
522
523
VERTICAL BLANK
524
525
1
2
4
3
5
6
8
7
9
10
20
11
21
22
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260
DISPLAY
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
285
284
FIELD
ODD FIELD
06399-112
HSYNC
EVEN FIELD
Figure 110. SD Timing Mode 3, NTSC
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
FIELD
EVEN FIELD
06399-113
HSYNC
ODD FIELD
Figure 111. SD Timing Mode 3, PAL
Rev. E | Page 86 of 106
Data Sheet
ADV7342/ADV7343
HD TIMING
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
6
5
7
8
20
21
560
22
P_VSYNC
P_HSYNC
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
06399-114
P_VSYNC
P_HSYNC
Figure 112. 1080i HSYNC and VSYNC Input Timing
Rev. E | Page 87 of 106
ADV7342/ADV7343
Data Sheet
VIDEO OUTPUT LEVELS
SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10
BLACK
BLUE
MAGENTA
RED
CYAN
GREEN
WHITE
700mV
YELLOW
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Pattern: 100% Color Bars
700mV
300mV
06399-118
06399-115
300mV
Figure 113. Y Levels—NTSC
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 116. Y Levels—PAL
700mV
06399-119
06399-116
700mV
Figure 114. Pr Levels—NTSC
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 117. Pr Levels—PAL
700mV
06399-120
06399-117
700mV
Figure 115. Pb Levels—NTSC
Figure 118. Pb Levels—PAL
Rev. E | Page 88 of 106
Data Sheet
ADV7342/ADV7343
ED/HD YPrPb OUTPUT LEVELS
INPUT CODE
EIA-770.2, STANDARD FOR Y
INPUT CODE
OUTPUT VOLTAGE
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE
940
940
700mV
700mV
64
64
300mV
300mV
EIA-770.3, STANDARD FOR Pr/Pb
EIA-770.2, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
OUTPUT VOLTAGE
960
960
600mV
512
700mV
64
06399-123
700mV
06399-121
512
64
Figure 121. EIA-770.3 Standard Output Signals (1080i/720p)
Figure 119. EIA-770.2 Standard Output Signals (525p/625p)
INPUT CODE
INPUT CODE
EIA-770.1, STANDARD FOR Y
OUTPUT VOLTAGE
782mV
Y–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
940
700mV
714mV
64
300mV
64
286mV
INPUT CODE
EIA-770.1, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
Pr/Pb–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
960
700mV
512
700mV
64
Figure 120. EIA-770.1 Standard Output Signals (525p/625p)
Rev. E | Page 89 of 106
300mV
Figure 122. Output Levels for Full Input Selection
06399-124
06399-122
64
ADV7342/ADV7343
Data Sheet
SD/ED/HD RGB OUTPUT LEVELS
Pattern: 100%/75% Color Bars
R
R
700mV/525mV
700mV/525mV
300mV
300mV
G
G
700mV/525mV
700mV/525mV
300mV
300mV
B
B
06399-125
300mV
300mV
06399-127
700mV/525mV
700mV/525mV
Figure 125. HD RGB Output Levels—RGB Sync Disabled
Figure 123. SD/ED RGB Output Levels—RGB Sync Disabled
R
R
700mV/525mV
600mV
700mV/525mV
300mV
300mV
0mV
0mV
G
G
700mV/525mV
600mV
700mV/525mV
300mV
300mV
0mV
0mV
B
B
700mV/525mV
600mV
700mV/525mV
06399-126
0mV
Figure 124. SD/ED RGB Output Levels—RGB Sync Enabled
Rev. E | Page 90 of 106
06399-128
300mV
300mV
0mV
Figure 126. HD RGB Output Levels—RGB Sync Enabled
Data Sheet
ADV7342/ADV7343
SD OUTPUT PLOTS
VOLTS
VOLTS IRE:FLT
0.6
100
0.4
0.5
50
0.2
0
0
0
–0.2
F1
L76
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
APL = 44.5%
SYNCHRONOUS SYNC = A
525 LINE NTSC
µs
FRAMES SELECTED 1, 2
SLOW CLAMP TO 0.00V AT 6.72
0
20
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 0.00dB
PRECISION MODE OFF
APL = 39.1%
SYNCHRONOUS SOUND-IN-SYNC OFF
625 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72µs
FRAMES SELECTED 1, 2, 3, 4
20
10
Figure 127. NTSC Color Bars (75%)
06399-132
10
L608
0
06399-129
–50
Figure 130. PAL Color Bars (75%)
VOLTS
VOLTS IRE:FLT
0.6
0.5
0.4
50
0.2
0
00
F2
L238
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.3%
PRECISION MODE OFF
525 LINE NTSC NO FILTERING
SYNCHRONOUS SYNC = SOURCE
SLOW CLAMP TO 0.00V AT 6.72s
µ
FRAMES SELECTED 1, 2
0
10
L575
20
0
10
20
30
40
50
60
70
MICROSECONDS
APL NEEDS SYNC SOURCE.
NO BUNCH SIGNAL
PRECISION MODE OFF
625 LINE PAL NO FILTERING
SYNCHRONOUS SOUND-IN-SYNC OFF
SLOW CLAMP TO 0.00 AT 6.72µs
FRAMES SELECTED 1
Figure 128. NTSC Luma
06399-133
–0.2
06399-130
0
Figure 131. PAL Luma
VOLTS IRE:FLT
0.4
50
VOLTS
0.5
0.2
0
0
0
–0.2
–50
–0.4
–0.5
F1
L76
L575
20
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 15.05dB
PRECISION MODE OFF
APL NEEDS SYNC SOURCE.
SYNCHRONOUS SYNC = B
525 LINE NTSC NO FILTERING
FRAMES SELECTED 1, 2
SLOW CLAMP TO 0.00 AT 6.72µs
0
30
40
50
60
MICROSECONDS
APL NEEDS SYNC SOURCE.
NO BUNCH SIGNAL
625 LINE PAL NO FILTERING
PRECISION MODE OFF
SLOW CLAMP TO 0.00 AT 6.72µs
SYNCHRONOUS SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 129. NTSC Chroma
10
20
Figure 132. PAL Chroma
Rev. E | Page 91 of 106
06399-134
10
06399-131
0
ADV7342/ADV7343
Data Sheet
VIDEO STANDARDS
0HDATUM
SMPTE 274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING
*1
272T
4T
ANCILLARY DATA
(OPTIONAL) OR BLANKING CODE
EAV CODE
1920T
DIGITAL
ACTIVE LINE
F 0 0 F C
V b Y C
r
F 0 0 H*
0 0 F
0 0 V
H*
F
F
INPUT PIXELS
4T
SAV CODE
4 CLOCK
SAMPLE NUMBER
4 CLOCK
0
2199
2116 2156
2112
C Y
r
44
188
192
2111
06399-135
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
FOR A FRAME RATE OF 30Hz: 40 SAMPLES
FOR A FRAME RATE OF 25Hz: 480 SAMPLES
Figure 133. EAV/SAV Input Data Timing Diagram (SMPTE 274M)
SMPTE 293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
EAV CODE
INPUT PIXELS
F
F 0 0 V
F 0 0 H*
F 0 0 F
V
F 0 0 H*
4 CLOCK
4 CLOCK
719
SAMPLE NUMBER
723 736
0HDATUM
799
DIGITAL
ACTIVE LINE
SAV CODE
853
C
C
b Y r
C
Y r Y
857 0
719
DIGITAL HORIZONTAL BLANKING
06399-136
FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8
Figure 134. EAV/SAV Input Data Timing Diagram (SMPTE 293M)
522
523
524
ACTIVE
VIDEO
VERTICAL BLANK
525
1
2
5
6
7
8
9
12
13
Figure 135. SMPTE 293M (525p)
Rev. E | Page 92 of 106
14
15
16
42
43
44
06399-137
ACTIVE
VIDEO
Data Sheet
ADV7342/ADV7343
622
624
623
ACTIVE
VIDEO
VERTICAL BLANK
625
1
2
5
4
6
7
8
9
10
12
11
13
43
45
44
06399-138
ACTIVE
VIDEO
Figure 136. ITU-R BT.1358 (625p)
DISPLAY
747
748
749
4
3
2
1
750
7
6
5
8
25
26
744
27
745
06399-139
VERTICAL BLANKING INTERVAL
Figure 137. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
560
22
DISPLAY
VERTICAL BLANKING INTERVAL
561
562
563
564
565
566
567
568
569
Figure 138. SMPTE 274M (1080i)
Rev. E | Page 93 of 106
570
583
584
585
1123
06399-140
FIELD 2
ADV7342/ADV7343
Data Sheet
CONFIGURATION SCRIPTS
The scripts listed in the following pages can be used to configure
the ADV7342/ADV7343 for basic operation. Certain features
are enabled by default. If required for a specific application,
additional features can be enabled.
Table 64 lists the scripts available for the SD modes of operation.
Similarly, Table 85 and Table 111 list the scripts available for ED
and HD modes of operation, respectively. For all scripts, only
the necessary register writes are included. All other registers are
assumed to have their default values.
STANDARD DEFINITION
Table 64. SD Configuration Scripts
Input Format
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
Input Data Width1
8-bit SDR
8-bit SDR
8-bit SDR
8-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
Synchronization Format
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
Output Color Space
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
Table Number
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
NTSC Sq. Pixel
NTSC Sq. Pixel
8-bit SDR
16-bit SDR
EAV/SAV
HSYNC/VSYNC
YCrCb
RGB
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
Table 73
Table 74
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
8-bit SDR
8-bit SDR
8-bit SDR
8-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
PAL Sq. Pixel
PAL Sq. Pixel
8-bit SDR
16-bit SDR
EAV/SAV
HSYNC/VSYNC
YCrCb
RGB
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
Table 83
Table 84
1
SDR = single data rate.
Rev. E | Page 94 of 106
Data Sheet
ADV7342/ADV7343
Table 65. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb and
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0xFC
0x00
0x10
0x82
0xC9
Table 69. 16-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0xFC
0x00
0x10
0x82
0xC9
0x88
0x8A
0x08
0x0C
Table 66. 8-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0xFC
0x00
0x10
0x82
0xC9
0x8A
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 67. 8-Bit 525i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0xFC
0x00
0x10
0x80
0x10
0x82
0xC9
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Table 70. 16-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0xFC
0x00
0x10
0x80
0x10
0x82
0xC9
0x88
0x8A
0x08
0x0C
Setting
0x02
0xFC
0x00
0x10
0x80
0x10
0x82
0xC9
0x8A
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
16-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 71. 24-Bit 525i RGB In, YPrPb and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0xFC
0x00
0x10
0x82
0xC9
0x87
0x88
0x8A
0x80
0x10
0x0C
Table 68. 8-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
16-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Rev. E | Page 95 of 106
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
RGB input enabled.
24-bit RGB input enabled
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
ADV7342/ADV7343
Data Sheet
Table 72. 24-Bit 525i RGB In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0xFC
0x00
0x10
0x80
0x10
0x82
0xC9
0x87
0x88
0x8A
0x80
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
RGB input enabled.
24-bit RGB input enabled
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 73. 8-Bit NTSC Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
0x82
0xDB
0x8C
0x8D
0x8E
0x8F
0x55
0x55
0x55
0x25
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled. Square pixel mode enabled.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in NTSC square pixel mode (24.5454
MHz input clock).
Table 74. 16-Bit NTSC Square Pixel RGB In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
0x82
0xDB
0x87
0x88
0x8A
0x80
0x10
0x0C
0x8C
0x8D
0x8E
0x8F
0x55
0x55
0x55
0x25
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal
enabled. Square pixel mode enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values for
CVBS and/or S-Video (Y-C) output in
NTSC square pixel mode (24.5454 MHz
input clock).
Table 75. 8-Bit 625i YCrCb In (EAV/SAV), YPrPb and
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0xFC
0x00
0x11
0x82
0xC1
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
Table 76. 8-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0xFC
0x00
0x11
0x82
0xC1
0x8A
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 77. 8-Bit 625i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0xFC
0x00
0x10
0x80
0x11
0x82
0xC1
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
Table 78. 8-Bit 625i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0xFC
0x00
0x10
0x80
0x11
0x82
0xC1
0x8A
0x0C
Rev. E | Page 96 of 106
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Data Sheet
ADV7342/ADV7343
Table 79. 16-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out
Table 82. 24-Bit 625i RGB In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0xFC
0x00
0x11
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0xFC
0x00
0x10
0x82
0xC1
0x80
0x11
0x88
0x8A
0x08
0x0C
0x82
0xC1
0x87
0x88
0x8A
0x80
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
16-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 80. 16-Bit 625i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0xFC
0x00
0x10
0x80
0x11
0x82
0xC1
0x88
0x8A
0x08
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
16-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 81. 24-Bit 625i RGB In, YPrPb and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0xFC
0x00
0x11
0x82
0xC1
0x87
0x88
0x8A
0x80
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
RGB input enabled.
24-Bit RGB input enabled
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
RGB input enabled.
24-bit RGB input enabled
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 83. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x82
0xD3
0x8C
0x8D
0x8E
0x8F
0x0C
0x8C
0x79
0x26
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
Table 84. 16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x82
0xD3
0x87
0x88
0x8A
0x80
0x10
0x0C
0x8C
0x8D
0x8E
0x8F
0x0C
0x8C
0x79
0x26
Rev. E | Page 97 of 106
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
ADV7342/ADV7343
Data Sheet
ENHANCED DEFINITION
Table 85. ED Configuration Scripts
Input Format
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
Input Data Width1
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
Synchronization Format
EAV/SAV
HSYNC/VSYNC
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
Output Color Space
YPrPb
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
RGB
Table Number
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table 97
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
8-bit DDR
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
RGB
Table 98
Table 99
Table 100
Table 101
Table 102
Table 103
Table 104
Table 105
Table 106
Table 107
Table 108
Table 109
Table 110
1
SDR = single data rate; DDR = dual data rate.
Table 86. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Table 88. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x04
0x02
0x10
0x31
0x01
0x30
0x04
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 87. 8-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x00
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p at 59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 89. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x04
0x31
0x01
Rev. E | Page 98 of 106
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Data Sheet
ADV7342/ADV7343
Table 95. 24-Bit 525p YCrCb In (EAV/SAV), RGB Out
Table 90. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x00
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 91. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x04
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 92. 16-Bit 525p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x00
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x04
0x31
0x33
0x01
0x28
Table 96. 24-Bit 525p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x00
0x31
0x33
0x01
0x28
Setting
0x02
0x1C
0x10
0x10
Table 93. 24-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
0x30
0x00
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x04
0x31
0x33
0x35
0x01
0x28
0x02
0x31
0x33
0x01
0x28
Table 94. 24-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x00
0x31
0x33
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Table 97. 24-Bit 525p RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
RGB input enabled.
Table 98. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x1C
0x31
0x01
Rev. E | Page 99 of 106
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
ADV7342/ADV7343
Data Sheet
Table 99. 8-Bit 625p YCrCb In, YPrPb Out
Table 104. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x18
0x30
0x1C
0x31
0x01
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
Table 100. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x1C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x18
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
Table 102. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x1C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 103. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x18
0x31
0x01
Table 105. 16-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x18
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 106. 24-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Table 101. 8-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x1C
0x31
0x33
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Table 107. 24-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x18
0x31
0x33
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Table 108. 24-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x1C
0x31
0x33
0x01
0x28
Rev. E | Page 100 of 106
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Data Sheet
ADV7342/ADV7343
Table 109. 24-Bit 625p YCrCb In, RGB Out
Table 110. 24-Bit 625p RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x18
0x30
0x18
0x31
0x33
0x01
0x28
0x31
0x33
0x35
0x01
0x28
0x02
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
RGB input enabled.
HIGH DEFINITION
Table 111. HD Configuration Scripts
Input Format
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
Input Data Width1
8-bit DDR
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
Synchronization Format
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
Output Color Space
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
RGB
Table Number
Table 112
Table 113
Table 114
Table 115
Table 116
Table 117
Table 118
Table 119
Table 120
Table 121
Table 122
Table 123
Table 124
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
8-bit DDR
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
RGB
Table 125
Table 126
Table 127
Table 128
Table 129
Table 130
Table 131
Table 132
Table 133
Table 134
Table 135
Table 136
Table 137
1
SDR = single data rate; DDR = dual data rate.
Rev. E | Page 101 of 106
ADV7342/ADV7343
Data Sheet
Table 112. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Table 116. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x2C
0x30
0x2C
0x31
0x01
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 117. 16-Bit 720p YCrCb In, YPrPb Out
Table 113. 8-Bit 720p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x28
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output
levels.
Pixel data valid. 4× oversampling.
Table 114. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x2C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 115. 8-Bit 720p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x28
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output
levels.
Pixel data valid. 4× oversampling.
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x28
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 118. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x2C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 119. 16-Bit 720p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x28
0x31
0x01
Rev. E | Page 102 of 106
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Data Sheet
ADV7342/ADV7343
Table 120. 24-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Table 124. 24-Bit 720p RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x2C
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x31
0x33
0x01
0x28
0x30
0x28
0x31
0x33
0x35
0x01
0x28
0x02
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
Table 121. 24-Bit 720p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x28
0x31
0x33
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
Table 122. 24-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x2C
0x31
0x33
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
Table 123. 24-Bit 720p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x28
0x31
0x33
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
RGB input enabled.
Table 125. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x6C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 126. 8-Bit 1080i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x68
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
1080i at 30 Hz/29.97 Hz. HSYNC/
VSYNC synchronization. EIA-770.3
output levels.
Pixel data valid. 4× oversampling.
Table 127. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x6C
0x31
0x01
Rev. E | Page 103 of 106
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. HSYNC/
VSYNC synchronization. EIA-770.3
output levels.
Pixel data valid. 4× oversampling.
ADV7342/ADV7343
Data Sheet
Table 128. 8-Bit 1080i YCrCb In, RGB Out
Table 132. 16-Bit 1080i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x02
0x10
0x30
0x68
0x30
0x68
0x31
0x01
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 133. 24-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Table 129. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x6C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x6C
0x31
0x33
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
Table 130. 16-Bit 1080i YCrCb In, YPrPb Out
Table 134. 24-Bit 1080i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x68
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x68
0x31
0x01
0x31
0x33
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
Table 131. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x6C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 135. 24-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x6C
0x31
0x33
0x01
0x28
Rev. E | Page 104 of 106
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
Data Sheet
ADV7342/ADV7343
Table 136. 24-Bit 1080i YCrCb In, RGB Out
Table 137. 24-Bit 1080i RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x68
0x30
0x68
0x31
0x33
0x01
0x28
0x31
0x33
0x35
0x01
0x28
0x02
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
Rev. E | Page 105 of 106
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data.
RGB input enabled.
ADV7342/ADV7343
Data Sheet
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
16
33
32
17
0.08
COPLANARITY
VIEW A
VIEW A
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
1.45
1.40
1.35
Figure 139. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADV7342BSTZ
ADV7343BSTZ
ADV7343WBSTZ
ADV7343WBSTZ-RL
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Macrovision3
Antitaping
Yes
No
No
No
Package Description
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Package Option
ST-64-2
ST-64-2
ST-64-2
ST-64-2
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
3
Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video.
1
2
AUTOMOTIVE PRODUCTS
The ADV7343W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06399-0-7/15(E)
Rev. E | Page 106 of 106