Low Power, Chip Scale 10-Bit SD/HD Video Encoder ADV7390/ADV7391/ADV7392/ADV7393
FEATURES
3 high quality, 10-bit video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 RGB (SD) Multiformat video output support Composite (CVBS) and S-Video (Y/C) Component YPrPb (SD, ED, and HD) Component RGB (SD, ED, and HD) Lead frame chip scale package (LFCSP) options 32-lead, 5 mm × 5 mm LFCSP 40-lead, 6 mm × 6 mm LFCSP Advanced power management Patented content-dependent low power DAC operation Automatic cable detection and DAC power-down Individual DAC on/off control Sleep mode with minimal power consumption 74.25 MHz 8-/10-/16-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p), and 240M (1035i) EIA/CEA-861B compliance support NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
SCL/ SDA/ ALSB/ MOSI SCLK SPI_SS
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Programmable features Luma and chroma filter responses Vertical blanking interval (VBI) Subcarrier frequency (FSC) and phase Luma delay Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern generation Serial MPU interface with dual I2C® and SPI® compatibility 2.7 V or 3.3 V analog operation 1.8 V digital operation 3.3 V I/O operation Temperature range: −40°C to +85°C
APPLICATIONS
Mobile handsets Digital still cameras Portable media and DVD players Portable game consoles Digital camcorders Set-top box (STB) Automotive infotainment (ADV7393 only)
FUNCTIONAL BLOCK DIAGRAM
DGND (2) VDD (2) SFL/ MISO AGND VAA
GND_IO VDD_IO
VBI DATA SERVICE INSERTION
MPU PORT
ADV739x
SUBCARRIER FREQUENCY LOCK (SFL) YUV TO YCrCb/ RGB SIN/COS DDS BLOCK 16× FILTER 10-BIT DAC 1 10-BIT DAC 2 DAC 1
4:2:2 TO 4:4:4 P15 TO P0/ P7 TO P0 INPUT DEINTERLEAVE
ADD BURST
PROGRAMMABLE CHROMINANCE FILTER
MULTIPLEXER
RGB/YCrCb TO YUV MATRIX
ADD SYNC
PROGRAMMABLE LUMINANCE FILTER
DAC 2
16× FILTER
10-BIT DAC 3
DAC 3
ASYNC BYPASS YCrCb HDTV TEST PATTERN GENERATOR POWER MANAGEMENT CONTROL PROGRAMMABLE ED/HD FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL YCbCr TO RGB MATRIX
4× FILTER
VIDEO TIMING GENERATOR
16x/4x OVERSAMPLING PLL
REFERENCE AND CABLE DETECT
RSET
06234-001
RESET
HSYNC
VSYNC
CLKIN
PVDD
PGND EXT_LF
COMP
Figure 1.
Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights. Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098, and other intellectual property rights. Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADV7390/ADV7391/ADV7392/ADV7393 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Detailed Features .............................................................................. 4 General Description ......................................................................... 4 Specifications..................................................................................... 5 Power Supply Specifications........................................................ 5 Input Clock Specifications .......................................................... 5 Analog Output Specifications..................................................... 5 Digital Input/Output Specifications........................................... 6 MPU Port Timing Specifications ............................................... 6 Digital Timing Specifications ..................................................... 7 Video Performance Specifications ............................................. 8 Power Specifications .................................................................... 8 Timing Diagrams.............................................................................. 9 Absolute Maximum Ratings.......................................................... 15 Thermal Resistance .................................................................... 15 ESD Caution................................................................................ 15 Pin Configurations and Function Descriptions ......................... 16 Typical Performance Characteristics ........................................... 18 MPU Port Description................................................................... 23 I2C Operation.............................................................................. 23 SPI Operation.............................................................................. 24 Register Map.................................................................................... 25 Register Programming............................................................... 25 Subaddress Register (SR7 to SR0) ............................................ 25 ADV7390/ADV7391 Input Configuration ................................. 41 Standard Definition.................................................................... 41 Enhanced Definition/High Definition .................................... 41 Enhanced Definition (At 54 MHz) .......................................... 41 ADV7392/ADV7393 Input Configuration ................................. 42 Standard Definition.................................................................... 42 Enhanced Definition/High Definition .................................... 43 Enhanced Definition (At 54 MHz) .......................................... 43 Output Configuration .................................................................... 44 Features ............................................................................................ 45 Output Oversampling ................................................................ 45 ED/HD Nonstandard Timing Mode........................................ 45 ED/HD Timing Reset ................................................................ 46 SD Subcarrier Frequency Lock, Subcarrier Reset, and Timing Reset ............................................................................................. 46 SD VCR FF/RW Sync ................................................................ 47 Vertical Blanking Interval ......................................................... 47 SD Subcarrier Frequency Registers.......................................... 47 SD NonInterlaced Mode............................................................ 48 SD Square Pixel Mode ............................................................... 48 Filters............................................................................................ 49 ED/HD Test Pattern Color Controls ....................................... 50 Color Space Conversion Matrix ............................................... 50 SD Luma and Color Control..................................................... 51 SD Hue Adjust Control.............................................................. 52 SD Brightness Detect ................................................................. 52 SD Brightness Control............................................................... 52 SD Input Standard Auto Detection.......................................... 52 Double Buffering ........................................................................ 53 Programmable DAC Gain Control .......................................... 53 Gamma Correction .................................................................... 53 ED/HD Sharpness Filter and Adaptive Filter Controls......... 55 ED/HD Sharpness Filter and Adaptive Filter Application Examples...................................................................................... 56 SD Digital Noise Reduction...................................................... 57 SD Active Video Edge Control ................................................. 59 External Horizontal and Vertical Synchronization Control ........................................................... 60 Low Power Mode........................................................................ 61 Cable Detection .......................................................................... 61 DAC Auto Power-Down............................................................ 61 Pixel and Control Port Readback............................................. 61 Reset Mechanisms ...................................................................... 61 Printed Circuit Board Layout and Design .................................. 62 DAC Configurations.................................................................. 62 Video Output Buffer and Optional Output Filter.................. 62 Printed Circuit Board (PCB) Layout ....................................... 63 Typical Application Circuit....................................................... 65 Appendix 1–Copy Generation Management System ................ 66 SD CGMS .................................................................................... 66 ED CGMS.................................................................................... 66 HD CGMS................................................................................... 66 CGMS CRC Functionality ........................................................ 66 Appendix 2–SD Wide Screen Signaling ...................................... 69
Rev. 0 | Page 2 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Appendix 3–SD Closed Captioning..............................................70 Appendix 4–Internal Test Pattern Generation ............................71 SD Test Patterns...........................................................................71 ED/HD Test Patterns ..................................................................71 Appendix 5–SD Timing..................................................................72 Appendix 6–HD Timing ................................................................77 Appendix 7–Video Output Levels.................................................78 SD YPrPb Output Levels—SMPTE/EBU N10 ........................78 ED/HD YPrPb Output Levels ...................................................79 SD/ED/HD RGB Output Levels................................................80 SD Output Plots ..........................................................................81 Appendix 8–Video Standards........................................................82 Appendix 9–Configuration Scripts...............................................84 Standard Definition ....................................................................84 Enhanced Definition ..................................................................90 High Definition ...........................................................................92 Outline Dimensions........................................................................95 Ordering Guide ...........................................................................96
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 3 of 96
ADV7390/ADV7391/ADV7392/ADV7393
DETAILED FEATURES
High definition (HD) programmable features (720p/1080i/1035i) 4× oversampling (297 MHz) Internal test pattern generator Color and black bar, hatch, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS (720p/1080i) and CGMS Type B (720p/1080i) Dual data rate (DDR) input support EIA/CEA-861B compliance support Enhanced definition (ED) programmable features (525p/625p) 8× oversampling (216 MHz output) Internal test pattern generator Color and black bar, hatch, flat field/frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) CGMS (525p/625p) and CGMS Type B (525p) Dual data rate (DDR) input support EIA/CEA-861B compliance support Standard definition (SD) programmable features 16× oversampling (216 MHz) Internal test pattern generator Color and black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAF™ filter with programmable gain/attenuation PrPb SSAF™ Separate pedestal control on component and composite/S-Video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 Copy generation management system (CGMS) Wide screen signaling (WSS) Closed captioning EIA/CEA-861B compliance support
(YPrPb/RGB) analog outputs in either standard-definition (SD) or high-definition (HD) video formats. Optimized for low power operation, occupying a minimal footprint and requiring few external components, these encoders are ideally suited to portable and power sensitive applications requiring TV-Out functionality. Cable detection and DAC auto power-down features ensure that power consumption is kept to a minimum. The ADV7390/ADV7391 have an 8-bit video input port that supports SD video formats over a SDR interface and HD video formats over a DDR interface. The ADV7392/ADV7393 have a 16-bit video input port that can be configured in a variety of ways. SD RGB input is supported. All members of the family support embedded EAV/SAV timing codes, external video synchronization signals and the I2C and SPI communication protocols. Table 1 lists the video standards directly supported by the ADV739x family. Table 1. Standards Directly Supported by the ADV739x 1
Resolution 720 × 240 720 × 288 720 × 480 720 × 576 720 × 480 720 × 576 720 × 483 720 × 483 720 × 483 720 × 576 720 × 483 720 × 576 1920 × 1035 1920 × 1035 1280 × 720 1280 × 720 1920 × 1080 1920 × 1080 1920 × 1080 1920 × 1080 1920 × 1080
1 2
I/P 2 P P I I I I P P P P P P I I P P I I P P P
Frame Rate (Hz) 59.94 50 29.97 25 29.97 25 59.94 59.94 59.94 50 59.94 50 30 29.97 60, 50, 30, 25, 24 23.97, 59.94, 29.97 30, 25 29.97 30, 25, 24 23.98, 29.97 24
Clock Input (MHz) 27 27 27 27 24.54 29.5 27 27 27 27 27 27 74.25 74.1758 74.25 74.1758 74.25 74.1758 74.25 74.1758 74.25
Standard
ITU-R BT.601/656 ITU-R BT.601/656 NTSC Square Pixel PAL Square Pixel SMPTE 293M BTA T-1004 ITU-R BT.1358 ITU-R BT.1358 ITU-R BT.1362 ITU-R BT.1362 SMPTE 240M SMPTE 240M SMPTE 296M SMPTE 296M SMPTE 274M SMPTE 274M SMPTE 274M SMPTE 274M ITU-R BT.7095
GENERAL DESCRIPTION
The ADV7390/ADV7391/ADV7392/ADV7393 are a family of high speed, digital-to-analog video encoders on single monolithic chips. Three 2.7 V/3.3 V 10-bit video DACs provide support for composite (CVBS), S-Video (YC), or component
Other standards are supported in the ED/HD nonstandard timing mode. I = interlaced, P = progressive.
Rev. 0 | Page 4 of 96
ADV7390/ADV7391/ADV7392/ADV7393 SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 2.
Parameter SUPPLY VOLTAGES VDD VDD_IO PVDD VAA POWER SUPPLY REJECTION RATIO Conditions Min 1.71 2.97 1.71 2.6 Typ 1.8 3.3 1.8 3.3 0.002 Max 1.89 3.63 1.89 3.465 Unit V V V V %/%
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 3.
Parameter fCLKIN Conditions 1 SD/ED ED (at 54 MHz) HD Min Typ 27 54 74.25 Max Unit MHz MHz MHz % of one clock cycle % of one clock cycle ±ns
CLKIN High Time, t9 CLKIN Low Time, t10 CLKIN Peak-to-Peak Jitter Tolerance
1
40 40 2
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 4.
Parameter Full-Drive Output Current Low Drive Output Current DAC-to-DAC Matching Output Compliance, VOC Output Capacitance, COUT Analog Output Delay 1 DAC Analog Output Skew
1
Conditions RSET = 510 Ω, RL = 37.5 Ω RSET = 4.12 kΩ, RL = 300 Ω DAC 1, DAC 2, DAC 3
Min 33
Typ 34.6 4.3 2.0 10 6 1
Max 37
0
1.4
DAC 1, DAC 2, DAC 3
Unit mA mA % V pF ns ns
Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
Rev. 0 | Page 5 of 96
ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL INPUT/OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 5.
Parameter Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIN Input Capacitance, CIN Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance Conditions Min 2.0 Typ Max 0.8 ±10 4 ISOURCE = 400 μA ISINK = 3.2 mA VIN = 0.4 V, 2.4 V 2.4 0.4 ±1 4 Unit V V μA pF V V μA pF
VIN = VDD_IO
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 6.
Parameter MPU PORT, I2C MODE 1 SCL Frequency SCL High Pulse Width, t1 SCL Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDA, SCL Rise Time, t6 SDA, SCL Fall Time, t7 Setup Time (Stop Condition), t8 MPU PORT, SPI MODE1 SCLK Frequency SPI_SS to SCLK Setup Time, t1 SCLK High Pulse Width, t2 SCLK Low Pulse Width, t3 Data Access Time after SCLK Falling Edge, t4 Data Setup Time prior to SCLK Rising Edge, t5 Data Hold Time after SCLK Rising Edge, t6 SPI_SS to SCLK Hold Time, t7 SPI_SS to MISO High Impedance, t8
1
Conditions See Figure 15
Min 0 0.6 1.3 0.6 0.6 100
Typ
Max 400
Unit kHz μs μs μs μs ns ns ns μs MHz ns ns ns ns ns ns ns ns
300 300 0.6 See Figure 16 0 20 50 50 20 0 0 40 10
35
Guaranteed by characterization.
Rev. 0 | Page 6 of 96
ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 7.
Parameter VIDEO DATA AND VIDEO CONTROL PORT 2, 3 Data Input Setup Time, t11 4 Conditions 1 SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) Min 2.1 2.3 2.3 1.7 1.0 1.1 1.1 1.0 2.1 2.3 1.7 1.0 1.1 1.0 12 10 4.0 3.5 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Input Hold Time, t124
Control Input Setup Time, t114
Control Input Hold Time, t124
Control Output Access Time, t134 Control Output Hold Time, t144 PIPELINE DELAY 5 SD 1 CVBS/YC Outputs (2×) CVBS/YC Outputs (8×) CVBS/YC Outputs (16×) Component Outputs (2×) Component Outputs (8×) Component Outputs (16×) E D1 Component Outputs (1×) Component Outputs (4×) Component Outputs (8×) H D1 Component Outputs (1×) Component Outputs (2×) Component Outputs (4×) RESET CONTROL RESET Low Time
1 2
SD oversampling disabled SD oversampling disabled SD oversampling enabled SD oversampling disabled SD oversampling disabled SD oversampling enabled ED oversampling disabled ED oversampling disabled ED oversampling enabled HD oversampling disabled HD oversampling disabled HD oversampling enabled 100
68 79 67 78 69 84 41 49 46 40 42 44
clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles ns
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. Video Data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391. 3 Video Control: HSYNC and VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design.
Rev. 0 | Page 7 of 96
ADV7390/ADV7391/ADV7392/ADV7393
VIDEO PERFORMANCE SPECIFICATIONS
Table 8.
Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity (INL) 1 Differential Nonlinearity (DNL)1, 2 STANDARD DEFINTION (SD) MODE Luminance Nonlinearity Differential Gain Differential Phase Signal-to-Noise Ratio (SNR) 3 ENHANCED DEFINITION (ED) MODE Luma Bandwidth Chroma Bandwidth HIGH DEFINITION (HD) MODE Luma Bandwidth Chroma Bandwidth
1 2
Conditions
Min
Typ 10 0.5 0.5 0.5 0.5 0.6 58 75 12.5 5.8 30.0 13.75
Max
Unit Bits LSBs LSBs ±% % Degrees dB dB MHz MHz MHz MHz
RSET = 510 Ω, RL = 37.5 Ω RSET = 510 Ω, RL = 37.5 Ω
NTSC NTSC Luma ramp Flat field full bandwidth
Measured on DAC 1, DAC 2, and DAC 3. Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value. For −ve DNL, the actual step value lies below the ideal step value. 3 Measured on the ADV7392/ADV7393 operating in 10-bit input mode.
POWER SPECIFICATIONS
Table 9.
Parameter NORMAL POWER MODE 1, 2 IDD 3 Conditions SD (16× oversampling enabled), CVBS SD (16× oversampling enabled), YPrPb ED (8× oversampling enabled) 4 HD (4× oversampling enabled)4 1 DAC enabled All DACs enabled Min Typ 33 68 59 81 1 50 122 4 5 0.3 0.2 0.1 Max Unit mA mA mA mA mA mA mA mA μA μA μA μA
IDD_IO IAA 5 IPLL SLEEP MODE IDD IAA IDD_IO IPLL
1 2 3
RSET = 510 Ω (all DACs operating in full-drive mode). 75% color bar test pattern applied to pixel data pins. IDD is the continuous current required to drive the digital core. 4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes. 5 IAA is the total current required to supply all DACs.
Rev. 0 | Page 8 of 96
ADV7390/ADV7391/ADV7392/ADV7393 TIMING DIAGRAMS
The following abbreviations are used in Figure 2 to Figure 9. • • • • • • t9 = Clock high time t10 = Clock low time t11 = Data setup time t12 = Data hold time t13 = Control output access time t14 = Control output hold time In addition, refer to Table 30 for the ADV7390/ADV7391 input configuration and Table 31 for the ADV7392/ADV7393 input configuration.
CLKIN
t9
CONTROL INPUTS HSYNC VSYNC
t10
t12
IN SLAVE MODE
PIXEL PORT
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
t11
CONTROL OUTPUTS
t13
IN MASTER/SLAVE MODE
t14
Figure 2. SD Input, 8-/10-Bit 4:2:2 YCrCb (Input Mode 000)
CLKIN
t9
CONTROL INPUTS HSYNC VSYNC
t10
t12
IN SLAVE MODE
PIXEL PORT
Y0
Y1
Y2
Y3
PIXEL PORT
Cb0
Cr0
Cb2
Cr2
t11
CONTROL OUTPUTS
t13
IN MASTER/SLAVE MODE
06234-002
t14
Figure 3. SD Input, 16-Bit 4:2:2 YCrCb (Input Mode 000)
Rev. 0 | Page 9 of 96
06234-003
ADV7390/ADV7391/ADV7392/ADV7393
CLKIN
t9
CONTROL INPUTS HSYNC VSYNC
t10
t12
IN SLAVE MODE
PIXEL PORT
Y0
Y1
Y2
Y3
PIXEL PORT
Cb0
Cr0
Cb2
Cr2
t11
CONTROL OUTPUTS
t13
IN MASTER/SLAVE MODE
t14
Figure 4. SD Input, 16-Bit 4:4:4 RGB (Input Mode 000)
CLKIN
t9
CONTROL INPUTS HSYNC VSYNC
t10
t12
PIXEL PORT
G0
G1
G2
PIXEL PORT
B0
B1
B2
t11
PIXEL PORT R0 R1 R2
CONTROL OUTPUTS
06234-004
t14 t13
Figure 5. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb (Input Mode 001)
CLKIN*
t9
CONTROL INPUTS HSYNC VSYNC
t10
PIXEL PORT
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
t11
t12 t11
t12 t13
CONTROL OUTPUTS
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 6. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 010
Rev. 0 | Page 10 of 96
06234-006
06234-003
ADV7390/ADV7391/ADV7392/ADV7393
CLKIN*
t9
t10
PIXEL PORT
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
t11
t12 t11
t12 t13
CONTROL OUTPUTS
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 7. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010
CLKIN
t9
CONTROL INPUTS HSYNC VSYNC Cb0
t10
PIXEL PORT
Y0
Cr0
Y1
Cb2
Y2
Cr2
t11
CONTROL OUTPUTS
t12
t13 t14
06234-008
Figure 8. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 111
CLKIN
t9
t10
PIXEL PORT
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
t11
CONTROL OUTPUTS
t12
t13 t14
06234-009
Figure 9. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111
Rev. 0 | Page 11 of 96
06234-007
ADV7390/ADV7391/ADV7392/ADV7393
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Y0
Y1
Y2
Y3
PIXEL PORT*
Cb0
Cr0
Cb2
Cr2
a a = AS PER RELEVANT STANDARD.
06234-010
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 10. ED-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Cb0
Y0
Cr0
Y1
a
a(MIN) = 244 CLOCK CYCLES FOR 525p. a(MIN) = 264 CLOCK CYCLES FOR 625p.
06234-011
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 11. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. 0 | Page 12 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Y0
Y1
Y2
Y3
PIXEL PORT
Cb0
Cr0
Cb2
Cr2
a
a = AS PER RELEVANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 12. HD-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Cb0
Y0
Cr0
Y1
a a = AS PER RELEVANT STANDARD.
06234-013
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 13. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. 0 | Page 13 of 96
06234-012
ADV7390/ADV7391/ADV7392/ADV7393
HSYNC
VSYNC
PIXEL PORT
Cb
Y
Cr
Y
PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES
Figure 14. SD Input Timing Diagram (Timing Mode 1)
t3
SDA
t5
t3
t6
SCL
t1 t2 t7 t4
2
t8
Figure 15. MPU Port Timing Diagram (I C Mode)
SPI_SS SPI_SS
t1
SCLK
t2
t3
06234-015
06234-014
t7
t5
MOSI
X D7 D6 D5 D4
t6
D3 D2 D1 D0 X X X X X X X X
06234-016
t4
MISO
X X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0
t8
Figure 16. MPU Port Timing Diagram (SPI Mode)
Rev. 0 | Page 14 of 96
ADV7390/ADV7391/ADV7392/ADV7393 ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter1 VAA to AGND VDD to DGND PVDD to PGND VDD_IO to GND_IO VAA to VDD VDD to PVDD VDD_IO to VDD AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to GND_IO Digital Input Voltage to GND_IO Analog Outputs to AGND Storage Temperature Range (tS) Junction Temperature (tJ) Lead Temperature (Soldering, 10 sec)
1
THERMAL RESISTANCE
Rating −0.3 V to +3.9 V −0.3 V to +2.3 V −0.3 V to +2.3 V −0.3 V to +3.9 V −0.3 V to +2.2 V −0.3 V to +0.3 V −0.3 V to +2.2 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to VDD_IO + 0.3 V −0.3 V to VAA −60°C to +100°C 150°C 260°C
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 11. Thermal Resistance1
Package Type 32-Lead LFCP 40-Lead LFCSP
1 2
θJA2 27 26
θJC 32 32
Unit °C/W °C/W
Values are based on a JEDEC 4 layer test board. With the exposed metal paddle on the underside of the LFCSP soldered to the PCB ground.
The ADV739x is a Pb-free product. The lead finish is 100% pure Sn electroplate. The device is RoHS compliant, suitable for Pbfree applications up to 255°C (±5°C) IR reflow (JEDEC STD-20). The ADV739x is backward-compatible with conventional SnPb soldering processes. The electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220°C to 235°C.
ESD CAUTION
Analog output short circuit to any power supply or common can be of an indefinite duration.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 15 of 96
ADV7390/ADV7391/ADV7392/ADV7393 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND_IO P1 P0 DGND VDD HSYNC VSYNC SFL/MISO 32 31 30 29 28 27 26 25
VDD_IO P2 P3 P4 VDD DGND P5 P6
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
ADV7390/ ADV7391
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
RSET COMP DAC 1 DAC 2 DAC 3 VAA AGND PVDD
VDD_IO 1 P4 2 P5 3 P6 4 P7 5 VDD 6 DGND 7 P8 8 P9 9 P10 10
40 39 38 37 36 35 34 33 32 31
GND_IO P3 P2 P1 DGND VDD P0 HSYNC VSYNC SFL/MISO
PIN 1 INDICATOR
ADV7392/ ADV7393
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
RSET COMP DAC 1 DAC 2 DAC 3 VAA AGND PVDD EXT_LF PGND
9 10 11 12 13 14 15 16
P7 ALSB/SPI_SS SDA/SCLK SCL/MOSI CLKIN RESET PGND EXT_LF
P11 ALSB/SPI_SS SDA/SCLK SCL/MOSI P12 P13 P14 P15 CLKIN RESET
06234-017
11 12 13 14 15 16 17 18 19 20
Figure 17. ADV7390/ADV7391 Pin Configuration
Figure 18. ADV7392/ADV7393 Pin Configuration
Table 12. Pin Function Descriptions
Pin Number ADV7390/91 ADV7392/93 9 to 7, 4 to 2, 31, 30 18 to 15, 11 to 8, 5 to 2, 39 to 37, 34 13 19 27 33 Mnemonic P7 to P0 P15 to P0 CLKIN HSYNC Input/ Output I I I I/O Description 8-Bit Pixel Port (P7 to P0). P0 is the LSB. Refer to Table 30 for input modes (ADV7390/ADV7391). 16-Bit Pixel Port (P15 to P0). P0 is the LSB. Refer to Table 31 for input modes (ADV7392/ADV7393). Pixel Clock Input for HD (74.25 MHz), ED 1 (27 MHz or 54 MHz), or SD (27 MHz). Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD horizontal synchronization signal. See the External Horizontal and Vertical Synchronization Control section. Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control section. Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output (MISO). The SFL input is used to drive the color subcarrier DDS system, timing reset, or subcarrier reset. Controls the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from RSET to AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be connected from RSET to AGND. Compensation Pin. Connect a 2.2 nF capacitor from COMP to VAA. DAC Outputs. Full-drive and low-drive capable DACs. Multifunctional Pin: I2C Clock Input/SPI Data Input. Multifunctional Pin: I2C Data Input/Output. Also, SPI clock input. Multifunctional Pin: ALSB sets up the LSB 2 of the MPU I2C address/SPI slave select (SPI_SS). Resets the on-chip timing generator and sets the ADV739x into its default mode. Analog Power Supply (3.3 V). Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering. Input/Output Digital Power Supply (3.3 V). PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering.
26
32
VSYNC
I/O
25
31
SFL/MISO
I/O
24
30
RSET
I
23 22, 21, 20 12 11 10 14 19 5, 28
29 28, 27, 26 14 13 12 20 25 6, 35
COMP DAC 1, DAC 2, DAC 3 SCL/MOSI SDA/SCLK ALSB/SPI_SS RESET VAA VDD
O O I I/O I I P P
1 17
1 23
VDD_IO PVDD
P P
Rev. 0 | Page 16 of 96
06234-018
ADV7390/ADV7391/ADV7392/ADV7393
Pin Number ADV7390/91 ADV7392/93 16 22 15 21 18 24 6, 29 7, 36 32 40
1 2
Mnemonic EXT_LF PGND AGND DGND GND_IO
Input/ Output I G G G G
Description External Loop Filter for the Internal PLL. PLL Ground Pin. Analog Ground Pin. Digital Ground Pin. Input/Output Supply Ground Pin.
ED = enhanced definition = 525p and 625p. LSB = least significant bit. In the ADV7390, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the ADV7391, setting the LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.
Rev. 0 | Page 17 of 96
ADV7390/ADV7391/ADV7392/ADV7393 TYPICAL PERFORMANCE CHARACTERISTICS
ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 0.5 –10 –20
GAIN (dB)
1.0
Y RESPONSE IN ED 8× OVERSAMPLING MODE
0 –0.5
GAIN (dB)
06234-019
–30 –40 –50 –60 –70 –80
–1.0 –1.5 –2.0 –2.5
06234-022
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
–3.0
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 19. ED 8× Oversampling, PrPb Filter (Linear) Response
ED Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20
GAIN (dB)
Figure 22. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)
HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
10 0 –10 –20 –30
GAIN (dB)
06234-020
–30 –40 –50 –60 –70 –80
–40 –50 –60 –70 –80 –90
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
0
18.5
37.0
55.5 74.0 92.5 FREQUENCY (MHz)
111.0
129.5
148.0
Figure 20. ED 8× Oversampling, PrPb Filter (SSAF) Response
Y RESPONSE IN ED 8× OVERSAMPLING MODE 0 –10 –20
GAIN (dB)
Figure 23. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:2:2 Input)
HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE 0 –10 –20 –30
GAIN (dB)
–30 –40 –50 –60 –70
06234-021
–40 –50 –60 –70 –80 –90 –100
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
10 20 30 40 50 60 70 80 90 100 110 120 130 140 FREQUENCY (MHz)
Figure 21. ED 8× Oversampling, Y Filter Response
Figure 24. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:4:4 Input)
Rev. 0 | Page 18 of 96
06234-024
–80
06234-023
–100
ADV7390/ADV7391/ADV7392/ADV7393
10 0 –10 –20 –30
GAIN (dB)
MAGNITUDE (dB)
Y RESPONSE IN HD 4× OVERSAMPLING MODE
0 –10 –20 –30 –40 –50 –60 –70
–40 –50 –60 –70 –80 –90
06234-025
0
18.5
37.0
55.5 74.0 92.5 FREQUENCY (MHz)
111.0
129.5
148.0
0
2
4 6 8 FREQUENCY (MHz)
10
12
Figure 25. HD 4× Oversampling, Y Filter Response
3.0 1.5 0 Y PASS BAND IN HD 4x OVERSAMPLING MODE
Figure 28. SD PAL, Luma Low-Pass Filter Response
0 –10 –20 –30 –40 –50 –60
GAIN (dB)
–3.0 –4.5 –6.0 –7.5 –9.0
–10.5
06234-026
MAGNITUDE (dB)
–1.5
0
2
FREQUENCY (MHz)
4 6 8 FREQUENCY (MHz)
10
12
Figure 26. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)
Figure 29. SD NTSC, Luma Notch Filter Response
0 –10 –20 –30 –40 –50 –60 –70
0 –10 –20 –30 –40 –50 –60 –70
MAGNITUDE (dB)
MAGNITUDE (dB)
06234-027
0
2
4 6 8 FREQUENCY (MHz)
10
12
0
2
4 6 8 FREQUENCY (MHz)
10
12
Figure 27. SD NTSC, Luma Low-Pass Filter Response
Figure 30. SD PAL, Luma Notch Filter Response
Rev. 0 | Page 19 of 96
06234-030
06234-029
–12.0 27.750 30.063 32.375 34.688 37.000 39.312 41.625 43.937 46.250
–70
06234-028
–100
ADV7390/ADV7391/ADV7392/ADV7393
Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20 4 5
GAIN (dB)
–30 –40 –50 –60
MAGNITUDE (dB)
3
2
1
0 –70
06234-031
06234-034
06234-036
–80
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
–1
0
1
2
3 4 FREQUENCY (MHz)
5
6
7
Figure 31. SD 16× Oversampling, Y Filter Response
1 0 –10 –20 –30 –40 –50 –60 –70 –4 0
Figure 34. SD Luma SSAF Filter, Programmable Gain
MAGNITUDE (dB)
MAGNITUDE (dB)
–1
–2
–3
06234-032
0
2
4 6 8 FREQUENCY (MHz)
10
12
0
1
2
3 4 FREQUENCY (MHz)
5
6
7
Figure 32. SD Luma SSAF Filter Response up to 12 MHz
Figure 35. SD Luma SSAF Filter, Programmable Attenuation
4 2 0
0 –10 –20 –30 –40 –50
MAGNITUDE (dB)
–2 –4 –6 –8 –10
06234-033
MAGNITUDE (dB)
–60 –70
–12
0
1
2
3 4 FREQUENCY (MHz)
5
6
7
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 33. SD Luma SSAF Filter, Programmable Responses
Figure 36. SD Luma CIF Low-Pass Filter Response
Rev. 0 | Page 20 of 96
06234-035
–5
ADV7390/ADV7391/ADV7392/ADV7393
0 –10 –20 –30 –40 –50 –60 –70
0 –10 –20 –30 –40 –50 –60 –70
MAGNITUDE (dB)
MAGNITUDE (dB)
0
2
4
06234-037
6 8 FREQUENCY (MHz)
10
12
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 37. SD Luma QCIF Low-Pass Filter Response
Figure 40. SD Chroma 1.3 MHz Low-Pass Filter Response
0 –10 –20 –30 –40 –50 –60 –70
0 –10 –20 –30 –40 –50 –60
06234-041
06234-042
MAGNITUDE (dB)
MAGNITUDE (dB)
0
2
4
6 8 FREQUENCY (MHz)
10
12
06234-038
–70
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 38. SD Chroma 3.0 MHz Low-Pass Filter Response
Figure 41. SD Chroma 1.0 MHz Low-Pass Filter Response
0 –10 –20 –30 –40 –50 –60 –70
0 –10 –20 –30 –40 –50 –60
06234-039
MAGNITUDE (dB)
MAGNITUDE (dB)
0
2
4
6 8 FREQUENCY (MHz)
10
12
–70
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 39. SD Chroma 2.0 MHz Low-Pass Filter Response
Figure 42. SD Chroma 0.65 MHz Low-Pass Filter Response
Rev. 0 | Page 21 of 96
06234-040
ADV7390/ADV7391/ADV7392/ADV7393
0 –10 –20 –30 –40 –50 –60 –70 0 –10 –20 –30 –40 –50 –60 –70
MAGNITUDE (dB)
MAGNITUDE (dB)
06234-043
0
2
4
6 8 FREQUENCY (MHz)
10
12
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 43. SD Chroma CIF Low-Pass Filter Response
Figure 44. SD Chroma QCIF Low-Pass Filter Response
Rev. 0 | Page 22 of 96
06234-044
ADV7390/ADV7391/ADV7392/ADV7393 MPU PORT DESCRIPTION
Devices such as a microprocessor can communicate with the ADV739x through one of the following protocols: • • 2-wire serial (I2C-compatible) bus 4-wire serial (SPI-compatible) bus The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is when the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADV739x acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period, the user should only issue a start condition, a stop condition, or a stop condition followed by a start condition. If an invalid subaddress is issued by the user, the ADV739x does not issue an acknowledge and does return to the idle condition. If the user utilizes the auto-increment method of addressing the encoder and exceeds the highest subaddress, the following actions are taken: • In read mode, the highest subaddress register contents are output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition occurs when the SDA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV739x, and the part returns to the idle condition.
After power-up or reset, the MPU port is configured for I2C operation. SPI operation can be invoked at any time by following the procedure outlined in the SPI Operation section.
I2C OPERATION
The ADV739x supports a 2-wire serial (I C-compatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV739x. Each slave device is recognized by a unique address. The ADV739x has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 45 and Figure 46. The LSB either sets a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. A1 is controlled by setting the ALSB/SPI_SS pin of the ADV739x to Logic 0 or Logic 1.
1 1 0 1 0 1 A1 X
2
ADDRESS CONTROL SET UP BY ALSB/SPI_SS READ/WRITE CONTROL 0 1 WRITE READ
06234-045
Figure 45. ADV7390/ADV7392 Slave Address = 0xD4 or 0xD6
0 1 0 1 0 1 A1 X
ADDRESS CONTROL SET UP BY ALSB/SPI_SS READ/WRITE CONTROL 0 1 WRITE READ
06234-046
•
Figure 46. ADV7391/ADV7393 Slave Address = 0x54 or 0x56
To control the various devices on the bus, use the following protocol. The master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit).
Figure 47 shows an example of data transfer for a write sequence and the start and stop conditions. Figure 48 shows bus write and read sequences.
Rev. 0 | Page 23 of 96
ADV7390/ADV7391/ADV7392/ADV7393
SDA
S 9 1–7 8 START ADDR R/W ACK
9 1–7 8 SUBADDRESS ACK
1–7 DATA
8
9 ACK
P STOP
Figure 47. I2C Data Transfer
WRITE SEQUENCE
S
SLAVE ADDR
A(S) LSB = 0
SUBADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
READ SEQUENCE
S
SLAVE ADDR
A(S)
SUBADDR
A(S) S SLAVE ADDR
A(S)
DATA
A(M)
06234-047
SCL
DATA
A(M) P
06234-048
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER
Figure 48. I2C Read and Write Sequence
SPI OPERATION
The ADV739x supports a 4-wire serial (SPI-compatible) bus connecting multiple peripherals. Two inputs, master out slave in (MOSI) and serial clock (SCLK), and one output, master in slave out (MISO), carry information between a master SPI peripheral on the bus and the ADV739x. Each slave device on the bus has a slave select pin that is connected to the master SPI peripheral by a unique slave select line. As such, slave device addressing is not required. To invoke SPI operation, a master SPI peripheral (for example, a microprocessor) should issue three low pulses on the ADV739x ALSB/SPI_SS pin. When the encoder detects the third rising edge on the ALSB/SPI_SS pin, it automatically switches to SPI communication mode. The ADV739x remains in SPI communication mode until a hardware reset or power-down occurs. To control the ADV739x, use the following protocol for both read and write transactions. First, the master initiates a data transfer by driving and holding the ADV739x ALSB/SPI_SS pin low. On the first SCLK rising edge after ALSB/SPI_SS has been driven low, the write command, defined as 0xD4, is written to the ADV739x over the MOSI line. The second byte written to the MOSI line is interpreted as the starting subaddress. Data on the MOSI line is written MSB first and clocked on the rising edge of SCLK. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. The user can also access any unique subaddress register on a one-by-one basis. In a write data transfer, 8-bit data bytes are written to the ADV739x, MSB first, on the MOSI line immediately after the starting subaddress. The data bytes are clocked into the ADV739x on the rising edge of SCLK. When all data bytes have been written, the master completes the transfer by driving and holding the ADV739x ALSB/SPI_SS pin high. In a read data transfer, after the subaddress has been clocked in on the MOSI line, the ALSB/SPI_SS pin is driven and held high for at least one clock cycle. Then, the ALSB/SPI_SS pin is driven and held low again. On the first SCLK rising edge after ALSB/SPI_SS has been driven low, the read command, defined as 0xD5, is written, MSB first, to the ADV739x over the MOSI line. Subsequently, 8-bit data bytes are read from the ADV739x, MSB first, on the MISO line. The data bytes are clocked out of the part on the falling edge of SCLK. When all data bytes have been read, the master completes the transfer by driving and holding the ADV739x ALSB/SPI_SS pin high.
Rev. 0 | Page 24 of 96
ADV7390/ADV7391/ADV7392/ADV7393 REGISTER MAP
A microprocessor can read from or write to all registers of the ADV739x via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines the register accessed by the next read or write operation. All communication through the MPU port starts with an access to the subaddress register. A read/write operation is then performed from/to the target address, incrementing to the next address until the transaction is complete.
REGISTER PROGRAMMING
Table 13 to Table 27 describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the MPU port is accessed and a read/write operation is selected, the subaddress is set up. The subaddress register determines which register performs the next operation.
Table 13. Register 0x00
SR7 to SR0 0x00 Register Power Mode Register Bit Description Sleep Mode. With this control enabled, the current consumption is reduced to μA level. All DACs and the internal PLL circuit are disabled. Registers can be read from and written to in sleep mode. PLL and Oversampling Control. This control allows the internal PLL circuit to be powered down and the oversampling to be switched off. DAC 3: Power on/off. DAC 2: Power on/off. DAC 1: Power on/off. Reserved. 0 0 0 0 1 0 1 0 1 7 6 Bit Number 5432 1 0 0 1 0 1 Register Setting Sleep mode off. Sleep mode on. PLL on. PLL off. DAC 3 off. DAC 3 on. DAC 2 off. DAC 2 on. DAC 1 off. DAC 1 on. Reset Value 0x12
Rev. 0 | Page 25 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 14. Register 0x01 to Register 0x09
SR7 to SR0 0x01 Register Mode Select Register Bit Description Reserved. DDR Clock Edge Alignment. Note: Only used for ED 1 and HD DDR modes. 7 6 Bit Number 5432 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 x x x x 0x05 0x06 0x07 0x08 0x09
1 2
1 0 1 0 1
0 0
Register Setting Chroma clocked in on rising clock edge and luma clocked in on falling clock edge. Reserved. Reserved. Luma clocked in on rising clock edge and chroma clocked in on falling clock edge. SD input. ED/HD-SDR input 2 ED/HD-DDR input. Reserved. Reserved. Reserved. Reserved. ED (at 54 MHz) input.
Reset Value 0x00
Reserved. Input Mode. Note: See Reg. 0x30, Bits[7:3] for ED/HD format selection.
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0
0x02
Mode Register 0
Reserved. Reserved. Test Pattern Black Bar. 3 Manual RGB Matrix Adjust. Sync on RGB. RGB/YPrPb Output Select. SD Sync Output Enable. ED/HD Sync Output Enable.
Zero must be written to these bits. Disabled. Enabled. Disable manual RGB matrix adjust. Enable manual RGB matrix adjust. No sync. Sync on all RGB outputs. RGB component outputs. YPrPb component outputs. No sync output. Output SD syncs on HSYNC and VSYNC pins. No sync output. Output ED/HD syncs on HSYNC and VSYNC pins. LSBs for GY. LSBs for RV. LSBs for BU. LSBs for GV. LSBs for GU. Bits[9:2] for GY. Bits[9:2] for GU. Bits[9:2] for GV. Bits[9:2] for BU. Bits[9:2] for RV.
0x20
0x03 0x04
ED/HD CSC Matrix 0 ED/HD CSC Matrix 1 x x x x x x x x x x x x x x x x x x
x x
0x03 0xF0
x
ED/HD CSC Matrix 2 ED/HD CSC Matrix 3 ED/HD CSC Matrix 4 ED/HD CSC Matrix 5 ED/HD CSC Matrix 6
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
0x4E 0x0E 0x24 0x92 0x7C
ED = enhanced definition = 525p and 625p. Available on the ADV7392/ADV7393 (40-pin devices) only. 3 Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
Rev. 0 | Page 26 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 15. Register 0x0B to Register 0x17
SR7 to SR0 0x0B Register DAC 1, DAC 2, DAC 3 Output Level Bit Description Positive Gain to DAC Output Voltage. 7 0 0 0 … 0 0 1 1 1 … 1 6 0 0 0 … 0 1 1 1 0 … 1 5 0 0 0 … 1 0 0 0 0 … 1 Bit Number 4 3 0 0 0 0 0 0 …… 1 1 0 0 0 0 0 0 0 0 …… 1 1 2 0 0 0 … 1 0 0 0 0 … 1 1 0 0 1 … 1 0 0 0 1 … 1 0 0 1 0 … 1 0 0 1 0 … 1 0 1 Register Setting 0% +0.018% +0.036% … +7.382% +7.5% −7.5% −7.382% −7.364% … −0.018% DAC 1 low power disabled DAC 1 low power enabled DAC 2 low power disabled DAC 2 low power enabled DAC 3 low power disabled DAC 3 low power enabled SD = 16×, ED = 8× SD = 8×, ED = 4× Cable detected on DAC 1 DAC 1 unconnected Cable detected on DAC 2 DAC 2 unconnected DAC auto power-down disable DAC auto power-down enable x x x x Read only 0xXX Reset Value 0x00
Negative Gain to DAC Output Voltage.
0x0D
DAC Power Mode
DAC 1 Low Power Mode. DAC 2 Low Power Mode. DAC 3 Low Power Mode. SD/ED Oversample Rate Select. Reserved. DAC 1 Cable Detect. Read Only. DAC 2 Cable Detect. Read Only. Reserved. Unconnected DAC auto power-down. 0 0 0 0 0 1 0 1 0 1
0x00
0x10
Cable Detection
0 1 0 1 0 0 1 0
0x00
0x13
Pixel Port Readback A 1 Pixel Port Readback B1 Control Port Readback1
Reserved. P[7:0] Readback (ADV7390/ADV7391). P[15:8] Readback (ADV7392/ADV7393). P[7:0] Readback (ADV7392/ADV7393). Reserved. VSYNC Readback. HSYNC Readback. SFL/MISO Readback. Reserved. Reserved. Software Reset.
0 x
0 x
0 x
x
0x14 0x16
x
x
x
x
x
x x
x x
x x
Read only Read only
0xXX 0xXX
x x x x x 0 0 1 0 0 0 0 0 0 Writing a 1 resets the device; this is a selfclearing bit 0x00
0x17
Software Reset
Reserved.
1
For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.
Rev. 0 | Page 27 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 16. Register 0x30
SR7 to SR0 0x30 Register ED/HD Mode Register 1 Bit Description ED/HD Output Standard. 7 6 Bit Number 5432 1 0 0 1 1 ED/HD Input Synchronization Format. 0 1 ED/HD Input Mode. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 Register Setting EIA-770.2 output EIA-770.3 output EIA-770.1 output Output levels for full input range Reserved External HSYNC, VSYNC and field inputs 1 Embedded EAV/SAV codes SMPTE 293M, ITU-BT.1358 Nonstandard timing mode BTA-1004, ITU-BT.1362 ITU-BT.1358 ITU-BT.1362 SMPTE 296M-1, SMPTE 274M-2 SMPTE 296M-3 SMPTE 296M-4, SMPTE 274M-5 SMPTE 296M-6 SMPTE 296M-7, SMPTE 296M-8 SMPTE 240M Reserved Reserved SMPTE 274M-4, SMPTE 274M-5 SMPTE 274M-6 SMPTE 274M-7, SMPTE 274M-8 SMPTE 274M-9 SMPTE 274M-10, SMPTE 274M-11 ITU-R BT.709-5 Reserved Note ED HD Reset Value 0x00
525p @ 59.94 Hz 525p @ 59.94 Hz 625p @ 50 Hz 625p @ 50 Hz 720p @ 60 Hz/59.94 Hz 720p @ 50 Hz 720p @ 30 Hz/29.97 Hz 720p @ 25 Hz 720p @ 24 Hz/23.98 Hz 1035i @ 60 Hz/59.94 Hz
0010 10011 to 11111
1080i @ 30 Hz/29.97 Hz 1080i @ 25 Hz 1080p @ 30 Hz/29.97 Hz 1080p @ 25 Hz 1080p @ 24 Hz/23.98 Hz 1080Psf @ 24 Hz
1
Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6.
Rev. 0 | Page 28 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 17. Register 0x31 to Register 0x33
SR7 to SR0 0x31 Register ED/HD Mode Register 2 Bit Description ED/HD Pixel Data Valid. HD Oversample Rate Select. ED/HD Test Pattern Enable. ED/HD Test Pattern Hatch/Field. ED/HD Vertical Blanking Interval (VBI) Open. ED/HD Undershoot Limiter. 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 7 6 Bit Number 5432 1 0 0 1 Register Setting Pixel data valid off Pixel data valid on 4× 2× HD test pattern off HD test pattern on Hatch Field/frame Disabled Enabled Disabled −11 IRE −6 IRE −1.5 IRE Disabled Enabled 0 clock cycles 1 clock cycle 2 clock cycles 3 clock cycles 4 clock cycles 0 clock cycles 1 clock cycle 2 clock cycles 3 clock cycles 4 clock cycles Disabled Enabled Disabled Enabled Cb after falling edge of HSYNC Cr after falling edge of HSYNC 0 must be written to this bit 8-bit input 10-bit input 1 Disabled Enabled 0 must be written to this bit Disabled Enabled 1 must be written to this bit Disable Enabled Reset Value 0x00
0 1
ED/HD Sharpness Filter. 0x32 ED/HD Mode Register 3 ED/HD Y Delay with Respect to Falling Edge of HSYNC.
0x00
ED/HD Color Delay with Respect to Falling Edge of HSYNC.
ED/HD CGMS Enable. ED/HD CGMS CRC Enable. 0x33 ED/HD Mode Register 4 ED/HD Cr/Cb Sequence. Reserved. ED/HD Input Format. Sinc Compensation Filter on DAC 1, DAC 2, DAC 3. Reserved. ED/HD Chroma SSAF Filter. Reserved. ED/HD Double Buffering.
0x68
1
Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. 0 | Page 29 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 18. Register 0x34 to Register 0x38
SR7 to SR0 0x34 Register ED/HD Mode Register 5 Bit Description ED/HD Timing Reset. ED/HD HSYNC Control. 1 ED/HD VSYNC Control.1 Reserved. ED Macrovision Enable. 2 Reserved. ED/HD VSYNC Input/Field Input. ED/HD Horizontal/Vertical Counter Mode. 3 0x35 ED/HD Mode Register 6 Reserved. Reserved. ED/HD Sync on PrPb. ED/HD Color DAC Swap. ED/HD Gamma Correction Curve Select. ED/HD Gamma Correction Enable. ED/HD Adaptive Filter Mode. ED/HD Adaptive Filter Enable. 0x36 0x37 0x38
1 2
7
6
Bit Number 5432
1
0 0 1
Register Setting Internal ED/HD timing counters enabled Resets the internal ED/HD timing counters
HSYNC output control (refer to Table 50) VSYNC output control (refer to Table 51)
Reset Value 0x48
0 1 0 1 1 0 1 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 x x x
ED Macrovision disabled ED Macrovision enabled 0 must be written to this bit 0 = Field input 1 = VSYNC input Update field/line counter Field/line counter free running 0x00 Disabled Enabled DAC 2 = Pb, DAC 3 = Pr DAC 2 = Pr, DAC 3 = Pb Gamma Correction Curve A Gamma Correction Curve B Disabled Enabled Mode A Mode B Disabled Enabled Y level value Cr level value Cb level value
ED/HD Y Level 4 ED/HD Cr Level4 ED/HD Cb Level4
ED/HD Test Pattern Y Level. ED/HD Test Pattern Cr Level. ED/HD Test Pattern Cb Level.
x x x
x x x
x x x
x x x
x x x
x x x
x x x
0xA0 0x80 0x80
Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1. Applies to the ADV7390 and ADV7392 only. 3 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. 4 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
Rev. 0 | Page 30 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 19. Register 0x39 to Register 0x43
SR7 to SR0 0x39 Register ED/HD Mode Register 7 Bit Description Reserved. ED/HD EIA/CEA-861B Synchronization Compliance. Reserved. ED/HD Sharpness Filter Gain Value A. 7 6 5 0 1 0 0 0 0 … 0 1 … 1 0 0 … 0 1 … 1 0 C15 C7 0 0 … 1 0 … 1 0 C14 C6 0 0 … 1 0 … 1 0 C13 C5 0 1 … 1 0 … 1 0 C12 C4 0 0 … 1 0 … 1 0 0 … 1 0 … 1 0 1 … 1 0 … 1 Gain A = 0 Gain A = +1 … Gain A = +7 Gain A = −8 … Gain A = −1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = −8 … Gain B = −1 CGMS C19 to C16 CGMS C15 to C8 CGMS C7 to C0 0x00 Bit Number 4 3 2 0 0 0 1 0 0 0 Register Setting Disabled Enabled Reset Value 0x00
0x40
ED/HD Sharpness Filter Gain
ED/HD Sharpness Filter Gain Value B.
0x41 0x42 0x43
ED/HD CGMS Data 0 ED/HD CGMS Data 1 ED/HD CGMS Data 2
ED/HD CGMS Data Bits. ED/HD CGMS Data Bits. ED/HD CGMS Data Bits.
C19 C11 C3
C18 C10 C2
C17 C9 C1
C16 C8 C0
0x00 0x00 0x00
Table 20. Register 0x44 to Register 0x57
SR7 to SR0 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 Register ED/HD Gamma A0 ED/HD Gamma A1 ED/HD Gamma A2 ED/HD Gamma A3 ED/HD Gamma A4 ED/HD Gamma A5 ED/HD Gamma A6 ED/HD Gamma A7 ED/HD Gamma A8 ED/HD Gamma A9 ED/HD Gamma B0 ED/HD Gamma B1 ED/HD Gamma B2 ED/HD Gamma B3 ED/HD Gamma B4 ED/HD Gamma B5 ED/HD Gamma B6 ED/HD Gamma B7 ED/HD Gamma B8 ED/HD Gamma B9 Bit Description ED/HD Gamma Curve A (Point 24). ED/HD Gamma Curve A (Point 32). ED/HD Gamma Curve A (Point 48). ED/HD Gamma Curve A (Point 64). ED/HD Gamma Curve A (Point 80). ED/HD Gamma Curve A (Point 96). ED/HD Gamma Curve A (Point 128). ED/HD Gamma Curve A (Point 160). ED/HD Gamma Curve A (Point 192). ED/HD Gamma Curve A (Point 224). ED/HD Gamma Curve B (Point 24). ED/HD Gamma Curve B (Point 32). ED/HD Gamma Curve B (Point 48). ED/HD Gamma Curve B (Point 64). ED/HD Gamma Curve B (Point 80). ED/HD Gamma Curve B (Point 96). ED/HD Gamma Curve B (Point 128). ED/HD Gamma Curve B (Point 160). ED/HD Gamma Curve B (Point 192). ED/HD Gamma Curve B (Point 224). 7 x x x x x x x x x x x x x x x x x x x x 6 x x x x x x x x x x x x x x x x x x x x 5 x x x x x x x x x x x x x x x x x x x x Bit Number 4 3 2 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x x x x Register Setting A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Rev. 0 | Page 31 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 21. Register 0x58 to Register 0x5D
SR7 to SR0 0x58 Register ED/HD Adaptive Filter Gain 1 Bit Description ED/HD Adaptive Filter Gain 1, Value A. 7 6 5 Bit Number 4 3 0 0 … 0 1 … 1 0 1 … 1 0 … 1 0 0 … 0 1 … 1 0 1 … 1 0 … 1 0 0 … 0 1 … 1 0 1 … 1 0 … 1 x x x x x x 2 0 0 … 1 0 … 1 1 0 0 … 1 0 … 1 0 0 1 … 1 0 … 1 Register Setting Gain A = 0 Gain A = +1 … Gain A = +7 Gain A = −8 … Gain A = −1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = −8 … Gain B = −1 Gain A = 0 Gain A = +1 … Gain A = +7 Gain A = −8 … Gain A = −1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = −8 … Gain B = −1 Gain A = 0 Gain A = +1 … Gain A = +7 Gain A = −8 … Gain A = −1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = −8 … Gain B = −1 Threshold A Threshold B Threshold C Reset Value 0x00
ED/HD Adaptive Filter Gain 1, Value B.
0 0 … 0 1 … 1
0 0 … 1 0 … 1
0 0 … 1 0 … 1
0x59
ED/HD Adaptive Filter Gain 2
ED/HD Adaptive Filter Gain 2, Value A.
0 0 … 1 0 … 1
0 0 … 1 0 … 1
0 1 … 1 0 … 1
0x00
ED/HD Adaptive Filter Gain 2, Value B.
0 0 … 0 1 … 1
0 0 … 1 0 … 1
0 0 … 1 0 … 1
0x5A
ED/HD Adaptive Filter Gain 3
ED/HD Adaptive Filter Gain 3, Value A.
0 0 … 1 0 … 1
0 0 … 1 0 … 1
0 1 … 1 0 … 1
0x00
ED/HD Adaptive Filter Gain 3, Value B.
0x5B 0x5C 0x5D
ED/HD Adaptive Filter Threshold A ED/HD Adaptive Filter Threshold B ED/HD Adaptive Filter Threshold C
ED/HD Adaptive Filter Threshold A. ED/HD Adaptive Filter Threshold B. ED/HD Adaptive Filter Threshold C.
0 0 … 0 1 … 1 x x x
0 0 … 1 0 … 1 x x x
0 0 … 1 0 … 1 x x x
x x x
x x x
x x x
0x00 0x00 0x00
Rev. 0 | Page 32 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 22. Register 0x5E to Register 0x6E
SR7 to SR0 0x5E Register ED/HD CGMS Type B Register 0 Bit Description ED/HD CGMS Type B Enable. ED/HD CGMS Type B CRC Enable. ED/HD CGMS Type B Header Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. ED/HD CGMS Type B Data Bits. H5 P7 P15 P23 P31 P39 P47 P55 P63 P71 P79 P87 P95 P103 P111 P119 P127 H4 P6 P14 P22 P30 P38 P46 P54 P62 P70 P78 P86 P94 P102 P110 P118 P126 H3 P5 P13 P21 P29 P37 P45 P53 P61 P69 P77 P85 P93 P101 P109 P117 P125 H2 P4 P12 P20 P28 P36 P44 P52 P60 P68 P76 P84 P92 P100 P108 P116 P124 H1 P3 P11 P19 P27 P35 P43 P51 P59 P67 P75 P83 P91 P99 P107 P115 P123 H0 P2 P10 P18 P26 P34 P42 P50 P58 P66 P74 P82 P90 P98 P106 P114 P122 P1 P9 P17 P25 P33 P41 P49 P57 P65 P73 P81 P89 P97 P105 P113 P121 P0 P8 P16 P24 P32 P40 P48 P56 P64 P72 P80 P88 P96 P104 P112 P120 7 6 5 Bit Number 4 3 2 1 0 0 1 Register Setting Disabled Enabled Disabled Enabled H5 to H0 P7 to P0 P15 to P8 P23 to P16 P31 to P24 P39 to P32 P47 to P40 P55 to P48 P63 to P56 P71 to P64 P79 to P72 P87 to P80 P95 to P88 P103 to P96 P111 to P104 P119 to P112 P127 to P120 Reset Value 0x00
0 1
0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E
ED/HD CGMS Type B Register 1 ED/HD CGMS Type B Register 2 ED/HD CGMS Type B Register 3 ED/HD CGMS Type B Register 4 ED/HD CGMS Type B Register 5 ED/HD CGMS Type B Register 6 ED/HD CGMS Type B Register 7 ED/HD CGMS Type B Register 8 ED/HD CGMS Type B Register 9 ED/HD CGMS Type B Register 10 ED/HD CGMS Type B Register 11 ED/HD CGMS Type B Register 12 ED/HD CGMS Type B Register 13 ED/HD CGMS Type B Register 14 ED/HD CGMS Type B Register 15 ED/HD CGMS Type B Register 16
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Rev. 0 | Page 33 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 23. Register 0x80 to Register 0x83
SR7 to SR0 0x80 Register SD Mode Register 1 Bit Description SD Standard. 7 6 Bit Number 5432 1 0 0 1 1 0 0 1 0 1 Register Setting NTSC PAL B, PAL D, PAL G, PAL H, PAL I PAL M PAL N LPF NTSC LPF PAL Notch NTSC Notch PAL Luma SSAF Luma CIF Luma QCIF Reserved 1.3 MHz 0.65 MHz 1.0 MHz 2.0 MHz Reserved Chroma CIF Chroma QCIF 3.0 MHz Disabled Enabled Refer to Table 32 in the Output Configuration section Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled No pedestal on YPrPb 7.5 IRE pedestal on YPrPb Y = 700 mV/300 mV Y = 714 mV/286 mV 700 mV p-p (PAL), 1000 mV p-p (NTSC) 700 mV p-p 1000 mV p-p 648 mV p-p Disabled Enabled Closed captioning disabled Closed captioning on odd field only Closed captioning on even field only Closed captioning on both fields Reserved Reset Value 0x10
SD Luma Filter.
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
SD Chroma Filter.
0x82
SD Mode Register 2
SD PrPb SSAF Filter. SD DAC Output 1. Reserved. SD Pedestal. SD Square Pixel Mode. SD VCR FF/RW Sync. SD Pixel Data Valid. SD Active Video Edge Control. 0 1 0 1 0 1 0 1 0 0 1 0 1
0 1
0x0B
0x83
SD Mode Register 3
SD Pedestal YPrPb Output. SD Output Levels Y. SD Output Levels PrPb. 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1
0 1
0x04
SD Vertical Blanking Interval (VBI) Open. SD Closed Captioning Field Control.
Reserved.
Rev. 0 | Page 34 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 24. Register 0x84 to Register 0x87
SR7 to SR0 0x84 Register SD Mode Register 4 Bit Description SD VSYNC-3H. 7 6 Bit Number 5432 1 0 0 1 Register Setting Disabled VSYNC= 2.5 lines (PAL), VSYNC= 3 lines (NTSC) Disabled Subcarrier reset mode enabled Timing reset mode enabled SFL mode enabled 720 pixels 710 (NTSC), 702 (PAL) Chroma enabled Chroma disabled Enabled Disabled Disabled Enabled DAC 2 = luma, DAC 3 = chroma DAC 2 = chroma, DAC 3 = luma 5.17 μs 5.31 μs 5.59 μs (must be set for Macrovision compliance) Reserved Disabled Enabled Update field/line counter Field/line counter free running Normal Color reversal enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 0 must be written to this bit SD YCrCb input SD RGB input Reset Value 0x00
SD SFL/SCR/TR Mode Select.
0 0 1 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1
SD Active Video Length. SD Chroma. SD Burst. SD Color Bars. SD Luma/Chroma Swap. 0x86 SD Mode Register 5 NTSC Color Subcarrier Adjust (Delay from the falling edge of output HSYNC pulse to start of color burst).
0 0 1 1
0 1 0 1
0x02
Reserved. SD EIA/CEA-861B Synchronization Compliance. Reserved. SD Horizontal/Vertical Counter Mode. 1 SD RGB Color Swap. 2 0x87 SD Mode Register 6 SD PrPb Scale. SD Y Scale. SD Hue Adjust. SD Brightness. SD Luma SSAF Gain. SD Input Standard Auto Detection. Reserved. SD RGB Input Enable.2 0 0 1 0 1 0 1 0 1 0 0 1 0
0 0 1
0 1 0 1 0 1 0 1
0x00
1
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. 2 Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. 0 | Page 35 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 25. Register 0x88 to Register 0x89
SR7 to SR0 0x88 Register SD Mode Register 7 Bit Description Reserved. SD Noninterlaced Mode. SD Double Buffering. SD Input Format. 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 7 6 Bit Number 5432 1 0 1 0 1 0 0 Register Setting Disabled Enabled Disabled Enabled 8-bit input 16-bit input 1 10-bit input1 Reserved Disabled Enabled Disabled Enabled Gamma Correction Curve A Gamma Correction Curve B Disabled −11 IRE −6 IRE −1.5 IRE 0 must be written to this bit Disabled Enabled Disabled 4 clock cycles 8 clock cycles Reserved 0 must be written to these bits Reset Value 0x00
SD Digital Noise Reduction. SD Gamma Correction Enable. SD Gamma Correction Curve Select. 0x89 SD Mode Register 8 SD Undershoot Limiter.
0x00
Reserved. SD Black Burst Output on DAC Luma. SD Chroma Delay.
Reserved.
1
Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. 0 | Page 36 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 26. Register 0x8A to Register 0x98
SR7 to SR0 0x8A Register SD Timing Register 0 Bit Description SD Slave/Master Mode. SD Timing Mode. 7 6 5 Bit Number 4 3 2 1 0 0 1 Register Setting Slave mode Master mode Mode 0 Mode 1 Mode 2 Mode 3 No delay 2 clock cycles 4 clock cycles 6 clock cycles −40 IRE −7.5 IRE A low-high-low transition resets the internal SD timing counters ta = 1 clock cycle ta = 4 clock cycles ta = 16 clock cycles ta = 128 clock cycles tb = 0 clock cycles tb = 4 clock cycles tb = 8 clock cycles tb = 18 clock cycles tc = tb tc = tb + 32 μs 1 clock cycle 4 clock cycles 16 clock cycles 128 clock cycles 0 clock cycles 1 clock cycle 2 clock cycles 3 clock cycles Subcarrier Frequency Bits[7:0] Subcarrier Frequency Bits[15:8] Subcarrier Frequency Bits[23:16] Subcarrier Frequency Bits[31:24] Subcarrier Phase Bits[9:2] Extended Data Bits[7:0] Extended Data Bits[15:8]. Data Bits[7:0] Data Bits[15:8] Setting any of these bits to 1 disables pedestal on the line number indicated by the bit settings Reset Value 0x08
0 0 1 1 1 0 0 1 1 0 1 x 0 1 0 1
0 1 0 1
Reserved. SD Luma Delay.
SD Minimum Luma Value. SD Timing Reset.
0x8B
SD Timing Register 1 Note: Applicable in master modes only, that is, Subaddress 0x8A, Bit 0 = 1.
SD HSYNC Width.
0 0 1 1 0 0 1 1 x x 0 0 1 1 0 0 1 1 x x x x x x x x x 17 25 17 25 0 1 0 1 x x x x x x x x x 16 24 16 24 0 1 0 1 0 1 0 1 0 1
0 1 0 1
0x00
SD HSYNC to VSYNC Delay.
SD HSYNC to VSYNC Rising Edge Delay (Mode 1 Only). VSYNC Width (Mode 2 Only).
HSYNC to Pixel Data Adjust.
0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98
1
SD FSC Register 0 1 SD FSC Register 11 SD FSC Register 21 SD FSC Register 31 SD FSC Phase SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Pedestal Register 0 SD Pedestal Register 1 SD Pedestal Register 2 SD Pedestal Register 3
Subcarrier Frequency Bits[7:0] Subcarrier Frequency Bits[15:8] Subcarrier Frequency Bits[23:16] Subcarrier Frequency Bits[31:24] Subcarrier Phase Bits[9:2] Extended Data on Even Fields. Extended Data on Even Fields. Data on Odd Fields. Data on Odd Fields. Pedestal on Odd Fields. Pedestal on Odd Fields. Pedestal on Even Fields. Pedestal on Even Fields.
x x x x x x x x x 15 23 15 23
x x x x x x x x x 14 22 14 22
x x x x x x x x x 13 21 13 21
x x x x x x x x x 12 20 12 20
x x x x x x x x x 11 19 11 19
x x x x x x x x x 10 18 10 18
0x1F 0x7C 0xF0 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
SD subcarrier frequency registers default to NTSC subcarrier frequency values. Rev. 0 | Page 37 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 27. Register 0x99 to Register 0xA5
SR7 to SR0 0x99 Register SD CGMS/WSS 0 Bit Description SD CGMS Data. SD CGMS CRC. SD CGMS on Odd Fields. SD CGMS on Even Fields. SD WSS. 0x9A SD CGMS/WSS 1 SD CGMS/WSS Data. SD CGMS Data. SD CGMS/WSS Data. LSBs for SD Y Scale Value. LSBs for SD Cb Scale Value. LSBs for SD Cr Scale Value. LSBs for SD FSC Phase. SD Y Scale Value. SD Cb Scale Value. SD Cr Scale Value. SD Hue Adjust Value. SD Brightness Value. SD Blank WSS Data. SD Luma SSAF Gain/Attenuation. Note: Only applicable if Subaddress 0x87, Bit 4 = 1. x x x x 0 1 x x x x x x 0 1 7 6 5 Bit Number 4 3 2 x x 0 1 1 x 0 x Register Setting CGMS Data Bits[C19:C16] Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled CGMS Data Bits[C13:C8] or WSS Data Bits[W13:W8] CGMS Data Bits[C15:C14] CGMS Data Bits[C7:C0] or WSS Data Bits[W7:W0] SD Y Scale Bits[1:0] SD Cb Scale Bits[1:0] SD Cr Scale Bits[1:0] Subcarrier Phase Bits[1:0] SD Y Scale Bits[7:2] SD Cb Scale Bits[7:2] SD Cr Scale Bits[7:2] SD Hue Adjust Bits[7:0] SD Brightness Bits[6:0] Disabled Enabled −4 dB … 0 dB … +4 dB No gain +1/16 [−1/8] +2/16 [−2/8] +3/16 [−3/8] +4/16 [−4/8] +5/16 [−5/8] +6/16 [−6/8] +7/16 [−7/8] +8/16 [−1] No gain +1/16 [−1/8] +2/16 [−2/8] +3/16 [−3/8] +4/16 [−4/8] +5/16 [−5/8] +6/16 [−6/8] +7/16 [−7/8] +8/16 [−1] Reset Value 0x00
0 1
0x00
0x9B 0x9C
SD CGMS/WSS 2 SD Scale LSB Register
x
x
x
x
x x
x x
0x00 0x00
x x x x x x x 0 1 0 … 0 … 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 x x x x x x x x x x x x x x x x x x x x x x
x
0x9D 0x9E 0x9F 0xA0 0xA1
SD Y Scale Register SD Cb Scale Register SD Cr Scale Register SD Hue Register SD Brightness/WSS
x x x x x
x x x x x
x x x x x
0x00 0x00 0x00 0x00 0x00
0xA2
SD Luma SSAF
0 … 1 … 1 0 0 0 0 1 1 1 1 0
0 … 1 … 0 0 0 1 1 0 0 1 1 0
0 … 0 … 0 0 1 0 1 0 1 0 1 0
0x00
0xA3
SD DNR 0
Reserved. Coring Gain Border. Note: In DNR mode, the values in brackets apply.
0x00
Coring Gain Data. Note: In DNR mode, the values in brackets apply.
Rev. 0 | Page 38 of 96
ADV7390/ADV7391/ADV7392/ADV7393
SR7 to SR0 0xA4 Register SD DNR 1 Bit Description DNR Threshold. 7 6 5 0 0 … 1 1 Bit Number 4 3 0 0 0 0 …… 1 1 1 1 2 0 0 … 1 1 1 0 0 … 1 1 0 0 1 … 0 1 Register Setting 0 1 … 62 63 2 pixels 4 pixels 8 pixels 16 pixels Filter A Filter B Filter C Filter D DNR mode DNR sharpness mode 0 pixel offset 1 pixel offset … 14 pixel offset 15 pixel offset Reset Value 0x00
Border Area. Block Size. 0xA5 SD DNR 2 DNR Input Select. 0 1
0 1
0 0 0 1 0 1 0 1 … 0 1
0 1 1 0
1 0 1 0
0x00
DNR Mode. DNR Block Offset. 0 0 … 1 1 0 0 … 1 1 0 0 … 1 1
Table 28. Register 0xA6 to Register 0xBB
SR7 to SR0 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB Register SD Gamma A0 SD Gamma A1 SD Gamma A2 SD Gamma A3 SD Gamma A4 SD Gamma A5 SD Gamma A6 SD Gamma A7 SD Gamma A8 SD Gamma A9 SD Gamma B0 SD Gamma B1 SD Gamma B2 SD Gamma B3 SD Gamma B4 SD Gamma B5 SD Gamma B6 SD Gamma B7 SD Gamma B8 SD Gamma B9 SD Brightness Detect Field Count Register Bit Description SD Gamma Curve A (Point 24). SD Gamma Curve A (Point 32). SD Gamma Curve A (Point 48). SD Gamma Curve A (Point 64). SD Gamma Curve A (Point 80). SD Gamma Curve A (Point 96). SD Gamma Curve A (Point 128). SD Gamma Curve A (Point 160). SD Gamma Curve A (Point 192). SD Gamma Curve A (Point 224). SD Gamma Curve B (Point 24). SD Gamma Curve B (Point 32). SD Gamma Curve B (Point 48). SD Gamma Curve B (Point 64). SD Gamma Curve B (Point 80). SD Gamma Curve B (Point 96). SD Gamma Curve B (Point 128). SD Gamma Curve B (Point 160). SD Gamma Curve B (Point 192). SD Gamma Curve B (Point 224). SD Brightness Value. Field Count. Reserved. Revision Code. 7 x x x x x x x x x x x x x x x x x x x x x 6 x x x x x x x x x x x x X x x x x x x x x 5 x x x x x x x x x x x x x x x x x x x x x 0 0 0 Bit Number 4 3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 2 x x x x x x x x x x x x x x x x x x x x x x 1 x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x x x x x x Register Setting A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Read only Read only Reserved Read only Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xXX 0x0X
Rev. 0 | Page 39 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 29. Register 0xE0 to Register 0xF1
SR7 to SR0 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1
1
Register 1 Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision
Bit Description MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bits. MV Control Bit.
7 x x x x x x x x x x x x x x x x x 0
6 x x x x x x x x x x x x x x x x x 0
5 x x x x x x x x x x x x x x x x x 0
Bit Number 4 3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0
2 x x x x x x x x x x x x x x x x x 0
1 x x x x x x x x x x x x x x x x x 0
0 x x x x x x x x x x x x x x x x x x
Register Setting
Bits[7:1] must be 0
Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Macrovision registers are only available on the ADV7390 and the ADV7392.
Rev. 0 | Page 40 of 96
ADV7390/ADV7391/ADV7392/ADV7393 ADV7390/ADV7391 INPUT CONFIGURATION
The ADV7390/ADV7391 supports a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7390/ADV7391 defaults to standard definition (SD) mode upon power-up. Table 30 provides an overview of all possible input configurations. Each input mode is described in detail in this section. Table 30. ADV7390/ADV7391 Input Configuration
Input Mode 000 SD 010 ED/HD-DDR 111 ED (at 54 MHz) P7 P6 P5 P4 P2 YCrCb YCrCb YCrCb P2 P1 P0
The CrCb pixel data is also input on Pin P7 to Pin P0 upon the opposite edge of CLKIN. P0 is the LSB. Whether the Y data is clocked in upon the rising or falling edge of CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 50 and Figure 51).
CLKIN
P[7:0]
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
06234-050
NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
Figure 50. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in an interleaved 4:2:2 format over an 8-bit bus rate of 27 MHz. A 27 MHz clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported. The ITU-R BT.601/656 input standard is supported. The interleaved pixel data is input on Pin P7 to Pin P0, with P0 being the LSB.
ADV7390/ ADV7391
2 MPEG2 DECODER 27MHz VSYNC, HSYNC CLKIN
CLKIN P[7:0] 3FF 00 00 XY Y0 Cb0 Y1 Cr0
06234-051
06234-052
NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
Figure 51. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
MPEG2 DECODER YCrCb
ADV7390/ ADV7391
CLKIN
YCrCb INTERLACED TO PROGRESSIVE 2
8
P[7:0]
VSYNC, HSYNC
Figure 52. ED/HD-DDR Example Application
YCrCb 8
06234-049
P[7:0]
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format over an 8-bit bus rate of 54 MHz. A 54 MHz clock signal must be provided on the CLKIN pin. Embedded EAV/SAV timing codes are supported. External synchronization signals are not supported in this mode. The interleaved pixel data is input on Pin P7 to Pin P0, with P0 being the LSB.
CLKIN
06234-053
Figure 49. SD Example Application
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 010
ED or HD YCrCb data can be input in an interleaved 4:2:2 format over an 8-bit DDR bus. The clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported.
8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P7 to Pin P0 upon either the rising or falling edge of CLKIN. P0 is the LSB.
P[7:0]
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
Figure 53. ED (At 54 MHz) Input Sequence (EAV/SAV)
Rev. 0 | Page 41 of 96
ADV7390/ADV7391/ADV7392/ADV7393 ADV7392/ADV7393 INPUT CONFIGURATION
The ADV7392/ADV7393 supports a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7392/ADV7393 defaults to standard definition (SD) mode upon power-up. Table 31 provides an overview of all possible input configurations. Each input mode is described in detail in this section.
16-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0 Subaddress 0x88, Bits[4:3] = 01
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P15 to Pin P8, with P8 being the LSB. The CrCb pixel data is input on Pin P7 to Pin P0, with P0 being the LSB. The pixel data is updated at half the rate of the clock, that is, at a rate of 13.5 MHz (see Figure 3).
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in 4:2:2 format over an 8-, 10-, or 16bit bus. SD RGB data can be input in 4:4:4 format over a 16-bit bus. A 27 MHz clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported in 8-bit and 10-bit modes.
16-Bit 4:4:4 RGB Mode Subaddress 0x87, Bit 7 = 1
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on Pin P4 to Pin P0, the green pixel data is input on Pin P10 to Pin P5, and the blue pixel data is input on Pin P15 to Pin P11. P0, P5, and P11 are the respective bus LSBs. The pixel data is updated at half the rate of the clock, that is, at a rate of 13.5 MHz (see Figure 4).
ADV7392/ ADV7393
2 MPEG2 DECODER 27MHz VSYNC, HSYNC CLKIN
8-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0 Subaddress 0x88, Bits[4:3] = 00
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is input on Pin P15 to Pin P8, with P8 being the LSB. The ITU-R BT.601/656 input standard is supported.
YCrCb
8/10
In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is input on Pin P15 to Pin P6, with P6 being the LSB. The ITU-R BT.601/656 input standard is supported. Table 31. ADV7392/ADV7393 Input Configuration
Input Mode 1 000 SD 2 8-Bit 10-Bit 16-Bit 3 16-Bit3 ED/HD-SDR (16-Bit) ED/HD-DDR 4 8-Bit 10-Bit ED (At 54 MHz) 8-Bit 10-Bit
1 2 3
P[15:8]/P[15:6]
Figure 54. SD Example Application
P15
P14
P13
P12
P11
P10 P9 P8 P7 P6 P5 SD RGB Input Enable (0x87[7]) = 0
P4
P3
P2
06234-054
10-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0 Subaddress 0x88, Bits[4:3] = 10
P1
P0
YCrCb YCrCb Y B Y ED/HD Input Format (0x33[2]) = 0 YCrCb ED/HD Input Format (0x33[2]) = 1 YCrCb ED/HD Input Format (0x33[2]) = 0 YCrCb ED/HD Input Format (0x33[2]) = 1 YCrCb SD RGB Input Enable (0x87[7]) = 1 G CrCb CrCb R
001 010
111
The input mode is determined by Subaddress 0x01, Bits[6:4]. In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3]. External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported. 4 ED = enhanced definition = 525p and 625p.
Rev. 0 | Page 42 of 96
ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an 8-/10-bit DDR bus or a 16-bit SDR bus. The clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported.
MPEG2 DECODER
YCrCb
ADV7392/ ADV7393
CLKIN
CrCb 8 INTERLACED TO PROGRESSIVE Y 8 2
P[7:0] P[15:8]
06234-057
VSYNC HSYNC
16-Bit 4:2:2 YCrCb Mode (SDR)
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P15 to Pin P8, with P8 being the LSB. The CrCb pixel data is input on Pin P7 to Pin P0, with P0 being the LSB.
Figure 57. ED/HD-SDR Example Application
MPEG2 DECODER YCrCb
ADV7392/ ADV7393
CLKIN
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P15 to Pin P8/P6 upon either the rising or falling edge of CLKIN. P8/P6 is the LSB. The CrCb pixel data is also input on Pin P15 to Pin P8/P6 upon the opposite edge of CLKIN. P8/P6 is the LSB. 10-bit mode is enabled using Subaddress 0x33, Bit 2. Whether the Y data is clocked in upon the rising or falling edge of CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 55 and Figure 56).
CLKIN P[15:8]/ P]15:6]
YCrCb 8/10 INTERLACED TO PROGRESSIVE
06234-058
P[15:8]/P[15:6]
2
VSYNC HSYNC
Figure 58. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on an 8-/10-bit bus at a rate of 54 MHz. A 54 MHz clock signal must be provided on the CLKIN pin. Embedded EAV/SAV timing codes are supported. External synchronization signals are not supported in this mode.
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
06234-055
NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE. 2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
The interleaved pixel data is input on Pin P15 to Pin P8/P6, with P8/P6 being the LSB. 10-bit mode is enabled using Subaddress 0x33, Bit 2.
CLKIN
Figure 55. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
CLKIN
P[15:8]/P[15:6] 3FF 00 00 XY Cb0 Y0 Cr0 Y1
06234-059
P[15:8]/ P[15:P6]
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
NOTES 1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
06234-056
NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE. 2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
Figure 59. ED (At 54 MHz) Input Sequence (EAV/SAV)
Figure 56. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
MPEG2 DECODER YCrCb 54MHz
ADV7392/ ADV7393
CLKIN
YCrCb 8/10 INTERLACED TO PROGRESSIVE 2
P[15:8]/P[15:6]
06234-060
VSYNC, HSYNC
Figure 60. ED (At 54 MHz) Example Application
Rev. 0 | Page 43 of 96
ADV7390/ADV7391/ADV7392/ADV7393 OUTPUT CONFIGURATION
The ADV739x supports a number of different output configurations. Table 32 to Table 34 lists all possible output configurations. Table 32. SD Output Configurations
RGB/YPrPb Output Select 1 (0x02, Bit 5) 0 1 1 1
1
SD DAC Output 1 (0x82, Bit 1) 0 0 1 1
SD Luma/Chroma Swap (0x84, Bit 7) 0 0 0 1
DAC 1 G Y CVBS CVBS
DAC 2 B Pb Luma Chroma
DAC 3 R Pr Chroma Luma
If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.
Table 33. ED/HD Output Configurations
RGB/YPrPb Output Select (0x02, Bit 5) 0 0 1 1 ED/HD Color DAC Swap (0x35, Bit 3) 0 1 0 1 DAC 1 G G Y Y DAC 2 B R Pb Pr DAC 3 R B Pr Pb
Table 34. ED (at 54 MHz) Output Configurations
RGB/YPrPb Output Select (0x02, Bit 5) 0 0 1 1 ED/HD Color DAC Swap (0x35, Bit 3) 0 1 0 1 DAC 1 G G Y Y DAC 2 B R Pb Pr DAC 3 R B Pr Pb
Rev. 0 | Page 44 of 96
ADV7390/ADV7391/ADV7392/ADV7393 FEATURES
OUTPUT OVERSAMPLING
The ADV739x include an on-chip phase-locked loop (PLL) that allows for oversampling of SD, ED, and HD video data. By default, the PLL is disabled. The PLL can be enabled using Subaddress 0x00, Bit 1 = 0. Table 35 shows the various oversampling rates supported in the ADV739x. various output levels that can be generated. Table 36 lists the transitions required to generate the various output levels. Embedded EAV/SAV timing codes are not supported in ED/HD nonstandard timing mode. The user must ensure that appropriate pixel data is applied to the encoder where the blanking level is expected at the output. Macrovision (ADV7390/ADV7392 only) and output oversampling are not available in ED/HD nonstandard timing mode. The PLL must be disabled (Subaddress 0x00, Bit 1 = 1) in ED/HD nonstandard timing mode.
ANALOG OUTPUT a b c
06234-061
ED/HD NONSTANDARD TIMING MODE
Subaddress 0x30, Bits[7:3] = 00001
For any ED/HD input data that does not conform to the standards listed in the ED/HD input mode table (Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard timing mode can be used to interface to the ADV739x. ED/HD nonstandard timing mode can be enabled by setting Subaddress 0x30, Bits[7:3] to 00001. A clock signal must be provided on the CLKIN pin. HSYNC and VSYNC must be toggled by the user to generate the appropriate horizontal and vertical synchronization pulses on the analog output from the encoder. Figure 61 illustrates the Table 35. Output Oversampling Modes and Rates
Input Mode (0x01, Bits[6:4]) 000 SD 000 SD 000 SD 001/010 ED 001/010 ED 001/010 ED 001/010 HD 001/010 HD 001/010 HD 111 ED (at 54 MHz) 111 ED (at 54 MHz) 111 ED (at 54 MHz) PLL and Oversampling Control (0x00, Bit 1) 1 0 0 1 0 0 1 0 0 1 0 0
b ACTIVE VIDEO
b BLANKING LEVEL
a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL. b = BLANKING LEVEL/ACTIVE VIDEO LEVEL. c = SYNCHRONIZATION PULSE LEVEL.
Figure 61. ED/HD Nonstandard Timing Mode Output Levels
SD/ED Oversample Rate Select (0x0D, Bit 3) x 1 0 x 1 0 x x x x 1 0
HD Oversample Rate Select (0x31, Bit 1) x x x x x x x 1 0 x x x
Oversampling Mode and Rate SD (2×) SD (8×) SD (16×) ED (1×) ED (4×) ED (8×) HD (1×) HD (2×) HD (4×) ED (@ 54 MHz) (1×) ED (@ 54 MHz) (4×) ED (@ 54 MHz) (8×)
Table 36. ED/HD Nonstandard Timing Mode Synchronization Signal Generation
Output Level Transition 1 b→c c→a a→b c→b
1 2
HSYNC 1→0 0 0→1 0→1
VSYNC 1 → 0 or 0 2 0→1 1 0
a = Tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. See Figure 61. If VSYNC = 1, it should transition to 0. If VSYNC = 0, it should remain at 0. If tri-level synchronization pulse generation is not required, VSYNC should always be 0.
Rev. 0 | Page 45 of 96
ADV7390/ADV7391/ADV7392/ADV7393
ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by setting the ED/HD timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this state, the horizontal and vertical counters remain reset. When this bit is set back to 0, the internal counters resume counting. This timing reset applies to the ED/HD timing counters only. • In subcarrier reset (SCR) mode (Subaddress 0x84, Bits[2:1] = 01), a low-to-high transition on the SFL/MISO pin resets the subcarrier phase to 0 on the field following the subcarrier phase reset. This reset signal must be held high for a minimum of one clock cycle. Because the field counter is not reset, it is recommended to apply the reset signal in Field 7 (PAL) or Field 3 (NTSC). The reset of the phase then occurs on the next field, that is, Field 1, which is lined up correctly with the internal counters. The field count register at Subaddress 0xBB can be used to identify the number of the active field. • In subcarrier frequency lock (SFL) mode (Subaddress 0x84, Bits[2:1] = 11), the ADV739x can be used to lock to an external video source. The SFL mode allows the ADV739x to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device such as an ADV7403 video decoder that outputs a digital data stream in the SFL format, the part automatically changes to the compensated subcarrier frequency on a line-by-line basis (see Figure 64). This digital data stream is 67 bits wide and the subcarrier is contained in Bit 0 to Bit 21. Each bit is two clock cycles long.
FSC PHASE = FIELD 4 OR 8
SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER RESET, AND TIMING RESET
Subaddress 0x84, Bits[2:1]
Together with the SFL/MISO pin and SD Mode Register 4 (Subaddress 0x84, Bits[2:1]), the ADV739x can be used in timing reset mode, subcarrier phase reset mode, or SFL mode. • In timing reset (TR) mode (Subaddress 0x84, Bits[2:1] = 10), a timing reset is achieved in a low-to-high transition on the SFL/MISO pin. In this state, the horizontal and vertical counters remain reset. Upon releasing this pin (set to low), the internal counters resume counting, starting with Field 1, and the subcarrier phase is reset. The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal may not be recognized. This timing reset applies to the SD timing counters only.
DISPLAY START OF FIELD 4 OR 8
307
310
313
320
NO TIMING RESET APPLIED DISPLAY START OF FIELD 1 FSC PHASE = FIELD 1
307
1
2
3
4
5
6
7
21
TIMING RESET PULSE TIMING RESET APPLIED
Figure 62. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 10)
DISPLAY
START OF FIELD 4 OR 8
FSC PHASE = FIELD 4 OR 8
307 NO FSC RESET APPLIED
310
313
320
DISPLAY
START OF FIELD 4 OR 8
FSC PHASE = FIELD 1
307
310
313
320
FSC RESET APPLIED
Figure 63. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)
Rev. 0 | Page 46 of 96
06234-063
FSC RESET PULSE
06234-062
ADV7390/ADV7391/ADV7392/ADV7393
ADV739x
CLKIN DAC 1
LCC1 COMPOSITE VIDEO1
SFL
P10
SFL/MISO
DAC 2 DAC 3
ADV7403 P19 TO
VIDEO DECODER PIXEL PORT5 4 BITS RESERVED
H/L TRANSITION COUNT START 128 RTC
14 BITS SUBCARRIER LOW PHASE 13 0
SEQUENCE BIT3
RESET BIT4 RESERVED
21
FSC PLL INCREMENT2
0
TIME SLOT 01
14
19 VALID SAMPLE INVALID SAMPLE 8/LINE LOCKED CLOCK
6768 5 BITS RESERVED
1FOR EXAMPLE, VCR OR CABLE. 2F SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. 3SEQUENCE BIT
4RESET ADV739x DDS. 5REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 “INPUT CONFIGURATION” TABLES FOR PIXEL DATA PIN ASSIGNMENTS.
Figure 64. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, that is, in fast forward or rewind modes. In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields is reached. In rewind mode, this sync signal usually occurs after the total number of lines/fields is reached. Conventionally, this means that the output video has corrupted field signals because one signal is generated by the incoming video and another is generated when the internal line/field counters reach the end of a field. When the VCR FF/RW sync control is enabled (Subaddress 0x82, Bit 5), the line/field counters are updated according to the incoming VSYNC signal and when the analog output matches the incoming VSYNC signal. This control is available in all slave-timing modes except Slave Mode 0.
VBI data can be present on Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL. In SD Timing Mode 0 (slave option), if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten. It is possible to use VBI in this timing mode as well. If CGMS is enabled and VBI is disabled, the CGMS data is nevertheless available at the output.
SD SUBCARRIER FREQUENCY REGISTERS
Subaddress 0x8C to Subaddress 0x8F
Four 8-bit registers are used to set up the subcarrier frequency. The value of these registers is calculated using the following equation:
Subcarrier Frequency Register = Number of subcarrier periods in one video line Number of 27 MHz clock cycles in one video line × 2 32
where the sum is rounded to the nearest integer. For example, in NTSC mode:
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV739x is able to accept input data that contains vertical blanking interval (VBI) data (such as CGMS, WSS, VITS) in SD, ED, and HD modes. If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress 0x83, Bit 4 for SD), VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave timing modes. For the SMPTE 293M (525p) standard, VBI data can be inserted on Line 13 to Line 42 of each frame, or on Line 6 to Lind 43 for the ITU-R BT.1358 (625p) standard.
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227.5 ⎞ 32 Subcarrier Register Value = ⎛ ⎟ × 2 = 569408543 ⎜ ⎝ 1716 ⎠
where: Subcarrier Register Value = 569408543d = 0×21F07C1F SD FSC Register 0: 0x1F SD FSC Register 1: 0x7C SD FSC Register 2: 0xF0 SD FSC Register 3: 0x21
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PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE
ADV7390/ADV7391/ADV7392/ADV7393
Programming the FSC
The subcarrier frequency register value is divided into four FSC registers as shown in the previous example. The four subcarrier frequency registers must be updated sequentially, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3. The subcarrier frequency updates only after the last subcarrier frequency register byte has been received by the ADV739x. A 27 MHz clock signal must be provided on the CLKIN pin. Embedded EAV/SAV timing codes or external horizontal and vertical synchronization signals provided on the HSYNC and VSYNC pins can be used to synchronize the input pixel data. All input configurations, output configurations, and features available in NTSC and PAL modes are available in SD noninterlaced mode. For 240p/59.94 Hz input, the ADV739x should be configured for NTSC operation and Subaddress 0x88, Bit 1 should be set to 1. For 288p/50 Hz input, the ADV739x should be configured for PAL operation and Subaddress 0x88, Bit 1 should be set to 1.
Typical FSC Values
Table 37 outlines the values that should be written to the subcarrier frequency registers for NTSC and PAL B/D/G/H/I. Table 37. Typical FSC Values
Subaddress 0x8C 0x8D 0x8E 0x8F Description FSC0 FSC1 FSC2 FSC3 NTSC 0x1F 0x7C 0xF0 0x21 PAL B/D/G/H/I 0xCB 0x8A 0x09 0x2A
SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
The ADV739x can be used to operate in square pixel mode (Subaddress 0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. In square pixel mode, the timing diagrams shown in Figure 65 and Figure 66 apply.
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
The ADV739x supports a SD noninterlaced mode. Using this mode, progressive inputs at twice the frame rate of NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input into the ADV739x. The SD noninterlaced mode can be enabled using Subaddress 0x88, Bit 1.
ANALOG VIDEO
EAV CODE INPUT PIXELS Y F0 0X818 1 C Y F0 0Y000 0 r 4 CLOCK 4 CLOCK END OF ACTIVE VIDEO LINE 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 272 CLOCK 344 CLOCK
SAV CODE C C 8 1 8 1 F 0 0X CY C YC Y rYb b 0000F00Yb r 4 CLOCK 4 CLOCK START OF ACTIVE VIDEO LINE
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NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz)
1280 CLOCK 1536 CLOCK
Figure 65. Square Pixel Mode EAV/SAV Embedded Timing
HSYNC
FIELD
PIXEL DATA
Cb
Y
Cr
Y
PAL = 308 CLOCK CYCLES NTSC = 236 CLOCK CYCLES
Figure 66. Square Pixel Mode Active Pixel Timing
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ADV7390/ADV7391/ADV7392/ADV7393
FILTERS
Table 38 shows an overview of the programmable filters available on the ADV739x. Table 38. Selectable Filters
Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1.3 MHz SD Chroma 2.0 MHz SD Chroma 3.0 MHz SD Chroma CIF SD Chroma QCIF SD PrPb SSAF ED/HD Sinc Compensation Filter ED/HD Chroma SSAF Subaddress 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x82 0x33 0x33
GAIN (dB)
EXTENDED (SSAF) PrPb FILTER MODE 0
–10
–20
–30
–40
–50
0
1
2
3 4 FREQUENCY (MHz)
5
6
Figure 67. PrPb SSAF Filter
If this filter is disabled, one of the chroma filters shown in Table 39 can be selected and used for the CVBS or luma/ chroma signal. Table 39. Internal Filter Specifications
Filter Luma LPF NTSC Luma LPF PAL Luma Notch NTSC Luma Notch PAL Luma SSAF Luma CIF Luma QCIF Chroma 0.65 MHz Chroma 1.0 MHz Chroma 1.3 MHz Chroma 2.0 MHz Chroma 3.0 MHz Chroma CIF Chroma QCIF
1
SD Internal Filter Response Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0
The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. The PrPb filter supports several different frequency responses, including six low-pass responses, a CIF response, and a QCIF response, as shown in Figure 36 and Figure 37. If SD Luma SSAF gain is enabled (Subaddress 0x87, Bit 4), there are 13 response options in the range −4 dB to +4 dB. The desired response can be programmed using Subaddress 0xA2. The variation of frequency responses are shown in Figure 33 to Figure 35. In addition to the chroma filters listed in Table 38, the ADV739x contains an SSAF filter specifically designed for the color difference component outputs, Pr and Pb. This filter has a cutoff frequency of ~2.7 MHz and a gain of –40 dB at 3.8 MHz (see Figure 67). This filter can be controlled with Subaddress 0x82, Bit 0.
Pass-Band Ripple (dB)1 0.16 0.1 0.09 0.1 0.04 0.127 Monotonic Monotonic Monotonic 0.09 0.048 Monotonic Monotonic Monotonic
3 dB Bandwidth (MHz)2 4.24 4.81 2.3/4.9/6.6 3.1/5.6/6.4 6.45 3.02 1.5 0.65 1 1.395 2.2 3.2 0.65 0.5
Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the −3 dB points. 2 3 dB bandwidth refers to the −3 dB cutoff frequency.
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–60
ADV7390/ADV7391/ADV7392/ADV7393
ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3
The ADV739x includes a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled by default. It can be disabled using Subaddress 0x33, Bit 3. The benefit of the filter is illustrated in Figure 68 and Figure 69.
0.5 0.4 0.3 0.2
GAIN (dB)
Table 40 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA770.2/EIA770.3 (Subaddress 0x30, Bits[1:0] = 00). Table 40. Sample Color Values for EIA770.2/EIA770.3 ED/HD Output Standard Selection
Sample Color White Black Red Green Blue Yellow Cyan Magenta Y Value 235 (0xEB) 16 (0x10) 81 (0x51) 145 (0x91) 41 (0x29) 210 (0xD2) 170 (0xAA) 106 (0x6A) Cr Value 128 (0x80) 128 (0x80) 240 (0xF0) 34 (0x22) 110 (0x6E) 146 (0x92) 16 (0x10) 222 (0xDE) Cb Value 128 (0x80) 128 (0x80) 90 (0x5A) 54 (0x36) 240 (0xF0) 16 (0x10) 166 (0xA6) 202 (0xCA)
0.1 0 –0.1 –0.2 –0.3 –0.4 0 5 10 15 20 FREQUENCY (MHz) 25 30
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COLOR SPACE CONVERSION MATRIX
Subaddress 0x03 to Subaddress 0x09
The internal color space conversion (CSC) matrix automatically performs all color space conversions based on the input mode programmed in the mode select register (Subaddress 0x01, Bits[6:4]). Table 41 and Table 42 show the options available in this matrix. An SD color space conversion from RGB-in to YPrPb-out is possible on the ADV7392/ADV7393. An ED/HD color space conversion from RGB-in to YPrPb-out is not possible. Table 41. SD Color Space Conversion Options
Input YCrCb YCrCb RGB2 RGB2
1
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–0.5
Figure 68. ED/HD Sinc Compensation Filter Enabled
0.5 0.4 0.3 0.2
GAIN (dB)
0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 5 10 15 20 FREQUENCY (MHz) 25 30
Output1 YPrPb RGB YPrPb RGB
YPrPb/RGB Out (Reg. 0x02, Bit 5) 1 0 1 0
RGB In/YCrCb In (Reg. 0x87, Bit 7) 0 0 1 1
2
CVBS/YC outputs are available for all CSC combinations. Available on the ADV7392/ADV7393 (40-pin devices) only.
Figure 69. ED/HD Sinc Compensation Filter Disabled
Table 42. ED/HD Color Space Conversion Options
Input YCrCb YCrCb Output YPrPb RGB YPrPb/RGB Out (Reg. 0x02, Bit 5) 1 0
ED/HD TEST PATTERN COLOR CONTROLS
Subaddress 0x36 to Subaddress 0x38
Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38 are used to program the output color of the internal ED/HD test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it be the lines of the cross hatch pattern or the uniform field test pattern. They are not functional as color controls for external pixel data input. The values for the luma (Y) and color difference (Cr and Cb) signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard.
ED/HD Manual CSC Matrix Adjust Feature
The ED/HD manual CSC matrix adjust feature provides custom coefficient manipulation for color space conversions and is used in ED and HD modes only. The ED/HD manual CSC matrix adjust feature can be enabled using Subaddress 0x02, Bit 3. Normally, there is no need to enable this feature because the CSC matrix automatically performs the color space conversion based on the input mode chosen (ED or HD) and the output color space selected (see Table 42). For this reason, the ED/HD manual CSC matrix adjust feature is disabled by default.
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ADV7390/ADV7391/ADV7392/ADV7393
If RGB output is selected, the ED/HD CSC matrix scalar uses the following equations: R = GY × Y + RV × Pr G = GY × Y − (GU × Pb) − (GV × Pr) B = GY × Y + BU × Pb Note that subtractions are implemented in hardware. If YPrPb output is selected, the following equations are used: Y = GY × Y P r = RV × Pr Pb = BU × Pb where: GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0]. GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6]. GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4]. BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2]. RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0]. Upon power-up, the CSC matrix is programmed with the default values shown in Table 43. Table 43. ED/HD Manual CSC Matrix Default Values
Subaddress 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Default 0x03 0xF0 0x4E 0x0E 0x24 0x92 0x7C
For example, SMPTE 293M uses the following conversion: R = Y + 1.402Pr G = Y − 0.714Pr − 0.344Pb B = Y + 1.773Pb The programmable CSC matrix is used for external ED/HD pixel data and is not functional when internal test patterns are enabled.
Programming the CSC Matrix
If custom manipulation of the ED/HD CSC matrix coefficients is required for a YCrCb-to-RGB color space conversion, follow the following procedure: 1. 2. 3. 4. Enable the ED/HD manual CSC matrix adjust feature (Subaddress 0x02, Bit 3). Set the output to RGB (Subaddress 0x02, Bit 5). Disable sync on PrPb (Subaddress 0x35, Bit 2). Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).
The GY value controls the green signal output level, the BU value controls the blue signal output level, and the RV value controls the red signal output level.
SD LUMA AND COLOR CONTROL
Subaddress 0x9C to Subaddress 0x9F
SD Y Scale, SD Cb Scale, and SD Cr Scale are three 10-bit control registers that scale the SD Y, Cb, and Cr output levels. Each of these registers represent the value required to scale the Cb or Cr level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 times its initial level. The value of these 10 bits is calculated using the following equation: Y, Cb, or Cr Scale Value = Scale Factor × 512 For example, if Scale Factor = 1.3 Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6 Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer) Y, Cb, or Cr Scale Value = 1010 0110 10b Subaddress 0x9C, SD Scale LSB Register = 0x2A Subaddress 0x9D, SD Y Scale Register = 0xA6 Subaddress 0x9E, SD Cb Scale Register = 0xA6 Subaddress 0x9F, SD Cr Scale Register = 0xA6 Note that this feature affects all interlaced output signals, that is, CVBS, Y-C, YPrPb, and RGB.
When the ED/HD manual CSC matrix adjust feature is enabled, the default coefficient values in Subaddress 0x03 to Subaddress 0x09 are correct for the HD color space only. The color components are converted according to the following 1080i and 720p standards (SMPTE 274M, SMPTE 296M): R = Y + 1.575Pr G = Y − 0.468Pr − 0.187Pb B = Y + 1.855Pb The conversion coefficients should be multiplied by 315 before being written to the ED/HD CSC matrix registers. This is reflected in the default values for GY = 0x13B, GU = 0x03B, GV = 0x093, BU = 0x248, and RV = 0x1F0. If the ED/HD manual CSC matrix adjust feature is enabled and another input standard (such as ED) is used, the scale values for GY, GU, GV, BU, and RV must be adjusted according to this input standard color space. The user should consider that the color component conversion might use different scale values.
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ADV7390/ADV7391/ADV7392/ADV7393
SD HUE ADJUST CONTROL
Subaddress 0xA0
When enabled, the SD hue adjust control register (Subaddress 0xA0) is used to adjust the hue on the SD composite and chroma outputs. This feature can be enabled using Subaddress 0x87, Bit 2. Subaddress 0xA0 contains the bits required to vary the hue of the video data, that is, the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV739x provides a range of ±22.5° in increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits, respectively, of the attainable adjustment in NTSC mode. Values 0xFF and 0x01 represent the upper and lower limits, respectively, of the attainable adjustment in PAL mode. The hue adjust value is calculated using the following equation: Hue Adjust (°) = 0.17578125° (HCRd − 128) where = HCRd hue adjust control register (decimal) For example, to adjust the hue by +4°, write 0x97 to the hue adjust control register:
4 ⎛ ⎞ + 128 ≈ 151d = 0 x 97 ⎜ ⎟ ⎝ 0.17578125 ⎠
For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal (see Figure 70) and for PAL, the setup can vary from −7.5 IRE to +15 IRE. The SD brightness control register is an 8-bit register. The seven LSBs of this 8-bit register are used to control the brightness level, which can be a positive or negative value. For example, To add +20 IRE brightness level to an NTSC signal with pedestal, write 0x28 to Subaddress 0xA1. 0 × (SD Brightness Value) = 0 × (IRE Value × 2.015631) = 0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28 To add –7 IRE brightness level to a PAL signal, write 0x72 to Subaddress 0xA1. 0 × (SD Brightness Value) = 0 × (IRE Value × 2.075631) = 0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b 0001110b into two’s complement = 1110010b = 0x72 Table 44. Sample Brightness Control Values1
Setup Level (NTSC) with Pedestal 22.5 IRE 15 IRE 7.5 IRE 0 IRE
1
where the sum is rounded to the nearest integer. To adjust the hue by −4°, write 0x69 to the hue adjust control register:
−4 ⎛ ⎜ ⎝ 0.17578125 ⎞ + 128 ≈ 105d = 0 x 69 ⎟ ⎠
Setup Level (NTSC) Without Pedestal 15 IRE 7.5 IRE 0 IRE −7.5 IRE
Setup Level (PAL) 15 IRE 7.5 IRE 0 IRE −7.5 IRE
Brightness Control Value 0x1E 0x0F 0x00 0x71
Values in the range of 0x3F to 0x44 can result in an invalid output signal.
where the sum is rounded to the nearest integer.
SD INPUT STANDARD AUTO DETECTION
Subaddress 0x87, Bit 5
The ADV739x include an SD input standard auto detect feature that can be enabled by setting Subaddress 0x87, Bit 5 to Bit 1. When enabled, the ADV739x can automatically identify an NTSC or PAL B/D/G/H/I input stream. The ADV739x automatically updates the subcarrier frequency registers with the appropriate value for the identified standard. The ADV739x is also configured to correctly encode the identified standard. The SD standard bits (Subaddress 0x80, Bits[1:0]) and the subcarrier frequency registers are not updated to reflect the identified standard. All registers retain their default or userdefined values.
SD BRIGHTNESS DETECT
Subaddress 0xBA
The ADV739x allows monitoring of the brightness level of the incoming video data. The SD brightness detect register (Subaddress 0xBA) is a read-only register.
SD BRIGHTNESS CONTROL
Subaddress 0xA1, Bits[6:0]
When this feature is enabled, the SD brightness/WSS control register (Subaddress 0xA1) is used to control brightness by adding a programmable setup level onto the scaled Y data. This feature can be enabled using Subaddress 0x87, Bit 3.
NTSC WITHOUT PEDESTAL 100 IRE
+7.5 IRE
0 IRE NO SETUP VALUE ADDED POSITIVE SETUP VALUE ADDED NEGATIVE SETUP VALUE ADDED
–7.5 IRE
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Figure 70. Examples of Brightness Control Values
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ADV7390/ADV7391/ADV7392/ADV7393
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD, Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not be made during active video, but take effect prior to the start of the active video on the next field. Using Subaddress 0x33, Bit 7, double buffering can be activated on the following ED/HD registers: ED/HD Gamma A and Gamma B curves, and ED/HD CGMS registers. Using Subaddress 0x88, Bit 2, double buffering can be activated on the following SD registers: SD Gamma A and Gamma B curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD closed captioning, and SD Macrovision Bits[5:0] (Subaddress 0xE0, Bits[5:0]). In Case B of Figure 71, the video output signal is reduced. The absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. The overall gain of the signal is reduced from the reference signal. The range of this feature is specified for ±7.5% of the nominal output from the DACs. For example, if the output current of the DAC is 4.33 mA, the DAC gain control feature can change this output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%). The reset value of the control registers is 0x00, that is, nominal DAC current is output. Table 45 is an example of how the output current of the DACs varies for a nominal 4.33 mA output current. Table 45. DAC Gain Control
Subaddress 0x0B 0100 0000 (0x40) 0011 1111 (0x3F) 0011 1110 (0x3E) ... ... 0000 0010 (0x02) 0000 0001 (0x01) 0000 0000 (0x00) 1111 1111 (0xFF) 1111 1110 (0xFE) ... ... 1100 0010 (0xC2) 1100 0001 (0xC1) 1100 0000 (0xC0) DAC Current (mA) 4.658 4.653 4.648 ... ... 4.43 4.38 4.33 4.25 4.23 ... ... 4.018 4.013 4.008 % Gain 7.5000% 7.3820% 7.3640% ... ... 0.0360% 0.0180% 0.0000% −0.0180% −0.0360% ... ... −7.3640% −7.3820% −7.5000% Note
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down from its absolute level. This is illustrated in Figure 71. DAC 1 to DAC 3 are controlled by Register 0x0B.
CASE A GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0B 700mV
Reset value, nominal
300mV CASE B 700mV NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0B
GAMMA CORRECTION
Subaddress 0x44 to Subaddress 0x57 for ED/HD, Subaddress 0xA6 to Subaddress 0xB9 for SD
Generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and output brightness level (as perceived on a CRT). It can also be applied wherever nonlinear processing is used.
300mV
06234-071
Gamma correction uses the function SignalOUT = (SignalIN)γ where γ = gamma correction factor. Gamma correction is available for SD and ED/HD video. For both variations, there are 20, 8-bit registers. They are used to program Gamma Correction Curve A and Curve B. ED/HD gamma correction is enabled using Subaddress 0x35, Bit 5. ED/HD Gamma Correction Curve A is programmed at Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma Correction Curve B is programmed at Subaddress 0x4E to Subaddress 0x57.
Figure 71. Programmable DAC Gain—Positive and Negative Gain
In Case A of Figure 71, the video output signal is gained. The absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. The overall gain of the signal is increased from the reference signal.
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ADV7390/ADV7391/ADV7392/ADV7393
SD gamma correction is enabled using Subaddress 0x88, Bit 6. SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9. Gamma correction is performed on the luma data only. The user can choose one of two correction curves, Curve A or Curve B. Only one of these curves can be used at a time. For ED/HD gamma correction, curve selection is controlled using Subaddress 0x35, Bit 4. For SD gamma correction, curve selection is controlled using Subaddress 0x88, Bit 7. The shape of the gamma correction curve is controlled by defining the curve response at 10 different locations along the curve. By altering the response at these locations, the shape of the gamma correction curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the 10 programmable locations are at points 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed. From curve locations 16 to 240, the values at the programmable locations and, therefore, the response of the gamma correction curve, should be calculated to produce the following result: xDESIRED = (xINPUT)γ where: xDESIRED = desired gamma corrected output xINPUT = linear input signal γ = gamma correction factor To program the gamma correction registers, calculate the 10 programmable curve values using the following formula: ⎛ n − 16 ⎞ γ ⎞ ⎟ γn = ⎜⎛ ⎜ ⎜ 240 − 16 ⎟ × (240 − 16) ⎟ + 16 ⎠ ⎝⎝ ⎠ where: γn = value to be written into the gamma correction register for point n on the gamma correction curve n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224 γ = gamma correction factor For example, setting γ = 0.5 for all programmable curve data points results in the following yn values: y24 = [(8/224)0.5 × 224] + 16 = 58 y32 = [(16/224)0.5 × 224] + 16 = 76 y48 = [(32/224)0.5 × 224] + 16 = 101 y64 = [(48/224)0.5 × 224] + 16 = 120 y80 = [(64/224)0.5 × 224] + 16 = 136 y96 = [(80/224)0.5 × 224] + 16 = 150 y128 = [(112/224)0.5 × 224] + 16 = 174 y160 = [(144/224)0.5 × 224] + 16 = 195 y192 = [(176/224)0.5 × 224] + 16 = 214 y224 = [(208/224)0.5 × 224] + 16 = 232 where the sum of each equation is rounded to the nearest integer. The gamma curves in Figure 72 and Figure 73 are examples only; any user-defined curve in the range from 16 to 240 is acceptable.
300
GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
300
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
GAMMA CORRECTED AMPLITUDE
250
200
GAMMA CORRECTED AMPLITUDE
SIGNAL OUTPUT
250 0.3 0.5 150
0.5
200
150
100 SIGNAL INPUT
100
SI
I AL GN
UT NP
1.5
50
1.8
50
0
50
100
150 LOCATION
200
250
Figure 72. Signal Input (Ramp) and Signal Output for Gamma 0.5
Figure 73. Signal Input (Ramp) and Selectable Output Curves
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0
50
100
150 LOCATION
200
250
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0
0
ADV7390/ADV7391/ADV7392/ADV7393
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS
Subaddress 0x40, Subaddress 0x58 to Subaddress 0x5D
There are three filter modes available on the ADV739x: sharpness filter mode and two adaptive filter modes. The derivative of the incoming signal is compared to the three programmable threshold values: ED/HD Adaptive Filter Threshold A, Threshold B, and Threshold C (Subaddress 0x5B, Subaddress 0x5C, and Subaddress 0x5D). The recommended threshold range is 16 to 235, although any value in the range of 0 to 255 can be used. The edges can then be attenuated with the settings in the ED/HD Adaptive Filter Gain 1, Gain 2, and Gain 3 registers (Subaddress 0x58, Subaddress 0x59 and Subaddress 0x5A), and the ED/HD sharpness filter gain register (Subaddress 0x40). There are two adaptive filter modes available. The mode is selected using the ED/HD adaptive filter mode control (Subaddress 0x35, Bit 6): • Mode A is used when the ED/HD adaptive filter mode control is set to 0. In this case, Filter B (LPF) is used in the adaptive filter block. In addition, only the programmed values for Gain B in the ED/HD sharpness filter gain register and ED/HD Adaptive Filter Gain 1, Gain 2, and Gain 3 registers are applied when needed. The Gain A values are fixed and cannot be changed. Mode B is used when ED/HD adaptive filter mode control is set to 1. In this mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the ED/HD sharpness filter gain register and ED/HD Adaptive Filter Gain 1, Gain 2, and Gain 3 registers become active when needed.
ED/HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges shown in Figure 74, the ED/HD sharpness filter must be enabled (Subaddress 0x31, Bit 7 = 1) and the ED/HD adaptive filter must be disabled (Subaddress 0x35, Bit 7 = 0). To select one of the 256 individual responses, the corresponding gain values, ranging from −8 to +7 for each filter, must be programmed into the ED/HD sharpness filter gain register at Subaddress 0x40.
ED/HD Adaptive Filter Mode
In ED/HD adaptive filter mode, the following registers are used: • • • • • • • ED/HD Adaptive Filter Threshold A ED/HD Adaptive Filter Threshold B ED/HD Adaptive Filter Threshold C ED/HD Adaptive Filter Gain 1 ED/HD Adaptive Filter Gain 2 ED/HD Adaptive Filter Gain 3 ED/HD sharpness filter gain register
•
To activate the adaptive filter control, the ED/HD sharpness filter and the ED/HD adaptive filter must be enabled (Subaddress 0x31, Bit 7 = 1, and Subaddress 0x35, Bit 7 = 1, respectively).
1.4 1.3 1.2
1.4 1.3 1.2
MAGNITUDE RESPONSE (Linear Scale)
1.5
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK 1.5
1.6 1.5 1.4 1.3 1.2 1.1 1.0
MAGNITUDE
INPUT SIGNAL: STEP
1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka)
MAGNITUDE
1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER B RESPONSE (Gain Kb)
0
2
FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 74. ED/HD Sharpness and Adaptive Filter Control Block
Rev. 0 | Page 55 of 96
06234-074
6 8 10 4 FREQUENCY (MHz)
12
ADV7390/ADV7391/ADV7392/ADV7393
d
1
a
R2
b
R4 R1
e
c
1 R2
f
CH1 500mV REF A
500mV 4.00µs
1
M 4.00µs 9.99978ms
CH1 ALL FIELDS
CH1 500mV REF A
500mV 4.00µs
1
M 4.00µs 9.99978ms
CH1 ALL FIELDS
Figure 75. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES
Sharpness Filter Application
The ED/HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings in Table 46 were used to achieve the results shown in Figure 75. Input data was generated by an external signal source. Table 46. ED/HD Sharpness Control
Subaddress 0x00 0x01 0x02 0x30 0x31 0x40 0x40 0x40 0x40 0x40 0x40
1
Adaptive Filter Control Application
The register settings in Table 47 are used to obtain the results shown in Figure 77, that is, to remove the ringing on the input Y signal, as shown in Figure 76. Input data is generated by an external signal source. Table 47. Register Settings for Figure 77
Subaddress 0x00 0x01 0x02 0x30 0x31 0x35 0x40 0x58 0x59 0x5A 0x5B 0x5C 0x5D Register Setting 0xFC 0x38 0x20 0x00 0x81 0x80 0x00 0xAC 0x9A 0x88 0x28 0x3F 0x64
Register Setting 0xFC 0x10 0x20 0x00 0x81 0x00 0x08 0x04 0x40 0x80 0x22
Reference1
a b c d e f
See Figure 75.
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ADV7390/ADV7391/ADV7392/ADV7393
In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal is subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise as before. However, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) is added to the original signal to boost high frequency components and sharpen the video image.
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Figure 76. Input Signal to ED/HD Adaptive Filter
In MPEG systems, it is common to process the video information in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels × 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset. The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing.
DNR MODE
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DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN
Figure 77. Output Signal from ED/HD Adaptive Filter (Mode A)
When changing the adaptive filter mode to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 78 can be obtained.
Y DATA INPUT
NOISE SIGNAL PATH
CORING GAIN DATA CORING GAIN BORDER
INPUT FILTER BLOCK FILTER OUTPUT < THRESHOLD? FILTER OUTPUT > THRESHOLD MAIN SIGNAL PATH – + SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL DNR OUT
DNR SHARPNESS MODE
DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN
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Figure 78. Output Signal from ED/HD Adaptive Filter (Mode B)
NOISE SIGNAL PATH
CORING GAIN DATA CORING GAIN BORDER
INPUT FILTER BLOCK
SD DIGITAL NOISE REDUCTION
Subaddress 0xA3 to Subaddress 0xA5
Digital noise reduction (DNR) is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). There are two DNR modes available: DNR mode and DNR sharpness mode.
Rev. 0 | Page 57 of 96
Y DATA INPUT
FILTER OUTPUT > THRESHOLD? FILTER OUTPUT < THRESHOLD MAIN SIGNAL PATH +
ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL DNR OUT
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+
Figure 79. SD DNR Block Diagram
ADV7390/ADV7391/ADV7392/ADV7393
Coring Gain Border—Subaddress 0xA3, Bits[3:0]
These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal.
Block Size—Subaddress 0xA4, Bit 7
This bit is used to select the size of the data blocks to be processed. Setting the block size control function to Logic 1 defines a 16 pixel × 16 pixel data block, and Logic 0 defines an 8 pixel × 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz.
DNR Input Select—Subaddress 0xA5, Bits[2:0]
These three bits are assigned to select the filter that is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal processed by DNR. Figure 82 shows the filter responses selectable with this control.
1.0 FILTER D 0.8
Coring Gain Data—Subaddress 0xA3, Bits[7:4]
These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal.
APPLY DATA CORING GAIN APPLY BORDER CORING GAIN
MAGNITUDE
FILTER C 0.6
0.4
FILTER B
0.2 FILTER A
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OXXXXXXOOXXXXXXO OFFSET CAUSED BY VARIATIONS IN INPUT TIMING
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0
0
1
2
3 4 FREQUENCY (MHz)
5
6
OXXXXXXOOXXXXXXO
Figure 82. SD DNR Input Select
DNR27 TO DNR24 = 0x01 O X X X X X X O O X X X X X X O
DNR Mode—Subaddress 0xA5, Bit 4
This bit controls the DNR mode selected. Logic 0 selects DNR mode; Logic 1 selects DNR sharpness mode. DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal because this data is assumed to be valid data and not noise. The overall effect is that the signal is boosted (similar to using the extended SSAF filter).
Figure 80. SD DNR Offset Control
DNR Threshold—Subaddress 0xA4, Bits[5:0]
These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value.
Border Area—Subaddress 0xA4, Bit 6
When this bit is set to Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.
720 × 485 PIXELS (NTSC) 2-PIXEL BORDER DATA
Block Offset Control—Subaddress 0xA5, Bits[7:4]
Four bits are assigned to this control that allows a shift in the data block of 15 pixels maximum. The coring gain positions are fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.
8 × 8 PIXEL BLOCK 8 × 8 PIXEL BLOCK
Figure 81. SD DNR Border Area
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ADV7390/ADV7391/ADV7392/ADV7393
SD ACTIVE VIDEO EDGE CONTROL
Subaddress 0x82, Bit 7
The ADV739x is able to control fast rising and falling signals at the start and end of active video to minimize ringing. When the active video edge control feature is enabled (Subaddress 0x82, Bit 7 = 1), the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible.
LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE 100 IRE 87.5 IRE 50 IRE 0 IRE 12.5 IRE 0 IRE
At the start of active video, the first three pixels are multiplied by ⅛, ½, and ⅞, respectively. Approaching the end of active video, the last three pixels are multiplied by ⅞, ½, and ⅛, respectively. All other active video pixels pass through unprocessed.
LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED
Figure 83. Example of Active Video Edge Functionality
VOLTS
IRE:FLT 100
0.5 50
0
0
–50 0 2 4 6
8
10
12
Figure 84. Example of Video Output with Subaddress 0x82, Bit 7 = 0
VOLTS
IRE:FLT 100
0.5 50
0
0
–50 –2 0 2 4
6
8
10
12
Figure 85. Example of Video Output with Subaddress 0x82, Bit 7 = 1
Rev. 0 | Page 59 of 96
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F2 L135
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F2 L135
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ADV7390/ADV7391/ADV7392/ADV7393
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the HSYNC and VSYNC pins (see Table 48). It is also possible to output synchronization signals on the HSYNC and VSYNC pins (see Table 49 to Table 51). Table 48. Timing Synchronization Signal Input Options
Signal SD HSYNC In SD VSYNC/FIELD In ED/HD HSYNC In ED/HD VSYNC/FIELD In
1
Pin HSYNC VSYNC HSYNC VSYNC
Condition SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).1 SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).1 ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0). ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 49. Timing Synchronization Signal Output Options
Signal SD HSYNC Out SD VSYNC/FIELD Out ED/HD HSYNC Out ED/HD VSYNC/FIELD Out
1 2
Pin HSYNC VSYNC HSYNC VSYNC
Condition SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).1 SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).1 ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).2 ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).2
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0). ED/HD timing synchronization inputs must also be disabled, that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).
Table 50. HSYNC Output Control1
ED/HD Input Sync Format (0x30, Bit 2) x x 0 1 x
1
ED/HD HSYNC Control (0x34, Bit 1) x x 0 0 1
ED/HD Sync Output Enable (0x02, Bit 7) 0 0 1 1 1
SD Sync Output Enable (0x02, Bit 6) 0 1 x x x
Signal on HSYNC Pin Tristate. Pipelined SD HSYNC. Pipelined ED/HD HSYNC. Pipelined ED/HD HSYNC based on AV Code H bit. Pipelined ED/HD HSYNC based on horizontal counter.
Duration – See Error! Reference source not found.. As per HSYNC timing. Same as line blanking interval. Same as embedded HSYNC.
In all ED/HD standards where there is a HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
Table 51. VSYNC Output Control 1
ED/HD Input Sync Format (0x30, Bit 2) x x ED/HD VSYNC Control (0x34, Bit 2) x x ED/HD Sync Output Enable (0x02, Bit 7) 0 0 SD Sync Output Enable (0x02, Bit 6) 0 1
Video Standard x Interlaced
Signal on VSYNC Pin Tristate. Pipelined SD VSYNC/Field.
0 1 1 x x
0 0 0 1 1
1 1 1 1 1
x x x x x
x All HD interlaced standards All ED/HD progressive standards All ED/HD standards except 525p 525p
Pipelined ED/HD VSYNC or field signal. Pipelined Field signal based on AV Code F bit. Pipelined VSYNC based on AV Code V bit. Pipelined ED/HD VSYNC based on vertical counter. Pipelined ED/HD VSYNC based on vertical counter.
Duration – See Error! Reference source not found.. As per VSYNC or Field signal timing. Field. Vertical blanking interval. Aligned with serration lines. Vertical blanking interval.
1
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
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ADV7390/ADV7391/ADV7392/ADV7393
LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power sensitive applications, the ADV739x supports an Analog Devices, Inc. proprietary low power mode of operation. To utilize this low power mode, the DACs must be operating in full-drive mode (RSET = 510 Ω, RL = 37.5 Ω). Low power mode is not available in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Low power mode can be independently enabled or disabled on each DAC using Subaddress 0x0D, Bits[2:0]. Low power mode is disabled by default on all DACs. In low power mode, DAC current consumption is content dependent, and on a typical video stream, it can be reduced by as much as 40%. For applications requiring the highest possible video performance, low power mode should be disabled. For CVBS/YC output configurations, if DAC 1 is unconnected, only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and DAC 3 power down. For YPrPb and RGB output configurations, if DAC 1 is unconnected, all three DACs are powered down. DAC 2 is not monitored for YPrPb and RGB output configurations. Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable is detected, the appropriate DAC or DACs remain powered up for the duration of the frame. If no cable is detected, the appropriate DAC or DACs power down until the next frame, when the process is repeated.
PIXEL AND CONTROL PORT READBACK
Subaddress 0x13, Subaddress 0x14, Subaddress 0x16
The ADV739x supports the readback of most digital inputs via the I2C/SPI MPU port. This feature is useful for board-level connectivity testing with upstream devices. The pixel port (P[15:0] or P[7:0]), HSYNC, VSYNC, and SFL/MISO are available for readback via the MPU port. The readback registers are located at Subaddress 0x13, Subaddress 0x14, and Subaddress 0x16. When using this feature, a clock signal should be applied to the CLKIN pin to register the levels applied to the input pins. The SD input mode (Subaddress 0x01, Bits[6:4] = 000) must be selected when using this feature.
CABLE DETECTION
Subaddress 0x10, Bits[1:0]
The ADV739x includes an Analog Devices, Inc. proprietary cable detection feature. The cable detection feature is available on DAC 1 and DAC 2 when operating in full-drive mode (RSET = 510 Ω, RL = 37.5 Ω, assuming a connected cable). The feature is not available in lowdrive mode (RSET = 4.12 kΩ, RL = 300 Ω). For a DAC to be monitored, the DAC must be powered up in Subaddress 0x00. The cable detection feature can be used with all SD, ED, and HD video standards. It is available for all output configurations, that is, CVBS, YC, YPrPb, and RGB output configurations. For CVBS/YC output configurations, both DAC 1 and DAC 2 are monitored, that is, the CVBS and YC luma outputs are monitored. For YPrPb and RGB output configurations, only DAC 1 is monitored, that is, the luma or green output is monitored. Once per frame, the ADV739x monitors DAC 1 and/or DAC 2, updating Subaddress 0x10, Bit 0 and/or Bit 1, respectively. If a cable is detected on one of the DACs, the relevant bit is set to 0. If not, the bit is set to 1.
RESET MECHANISMS
Subaddress 0x17, Bit 1
A hardware reset is activated with a high-to-low transition on the RESET pin in accordance with the timing specifications. This resets all registers to their default values. After a hardware reset, the MPU port is configured for I2C operation. For correct device operation, a hardware reset is necessary after power-up. The ADV739x also has a software reset accessible via the I2C/SPI MPU port. A software reset is activated by writing a 1 to Subaddress 0x17, Bit 1. This resets all registers to their default values. This bit is self-clearing, that is, after a 1 has been written to the bit, the bit automatically returns to 0. When operating in SPI mode, a software reset does not cause the device to revert to I2C mode. For this to occur, a hardware reset via the RESET pin or a power-down needs to occur. A hardware reset is necessary after power-up for correct device operation. If no hardware reset functionality is required by the application, the RESET pin can be connected to a RC network to provide the hardware reset necessary after power-up. After power-up, the time constant of the RC network holds the RESET pin low for long enough to cause a reset to take place. All subsequent resets can be done via software.
DAC AUTO POWER-DOWN
Subaddress 0x10, Bit 4
For power sensitive applications, a DAC auto power-down feature can be enabled using Subaddress 0x10, Bit 4. This feature is only available when the cable detection feature is enabled. With this feature enabled, the cable detection circuitry monitors DAC 1 and/or DAC 2 once per frame, and if they are unconnected, automatically powers down some or all of the DACs. Which DAC or DACs are powered down depends on the selected output configuration.
Rev. 0 | Page 61 of 96
ADV7390/ADV7391/ADV7392/ADV7393 PRINTED CIRCUIT BOARD LAYOUT AND DESIGN
DAC CONFIGURATIONS
The ADV739x contains three DACs. All three DACs can be configured to operate in full-drive mode. Full-drive mode is defined as 34.7 mA full-scale current into a 37.5 Ω load, RL. Full-drive is the recommended mode of operation for the DACs. Alternatively, all three DACs can be configured to operate in low drive mode. Low drive mode is defined as 4.33 mA full-scale current into a 300 Ω load, RL. The ADV739x contains a RSET pin. A resistor connected between the RSET pin and AGND is used to control the full-scale output current and, therefore, the output voltage levels of DAC 1, DAC 2, and DAC 3. For full-drive operation, RSET must have a value of 510 Ω and RL must have a value of 37.5 Ω. For low drive operation, RSET must have a value of 4.12 kΩ, and RL must have a value of 300 Ω. The resistor connected to the RSET pin should have a 1% tolerance. The ADV739x contains a compensation pin, COMP. A 2.2 nF compensation capacitor should be connected from the COMP pin to VAA. Table 52. ADV739x Output Rates
Input Mode (0x01, Bits[6:4]) SD Oversampling Off On On Off On On Off On On Output Rate (MHz) 27 (2×) 108 (8×) 216 (16×) 27 (1×) 108 (4×) 216 (8×) 74.25 (1×) 148.5 (2×) 297 (4×)
ED
HD
Table 53. Output Filter Requirements
Cutoff Frequency (MHz) > 6.5 > 6.5 > 6.5 > 12.5 > 12.5 > 12.5 > 30 > 30 > 30
3
Application SD
ED
VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER
An output buffer is necessary on any DAC that operates in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Analog Devices Inc. produces a range of op amps suitable for this application, for example, the AD8061. For more information about line driver buffering circuits, see the relevant op amp data sheet. An optional reconstruction (anti-imaging) low-pass filter (LPF) may be required on the ADV739x DAC outputs. The filter specifications vary with the application. The use of 16× (SD), 8× (ED), or 4× (HD) oversampling can remove the requirement for a reconstruction filter altogether. For applications requiring an output buffer and reconstruction filter, the ADA4430-1 and ADA4411-3 integrated video filter buffers should be considered.
HD
Oversampling 2× 8× 16× 1× 4× 8× 1× 2× 4×
10µH
Attenuation –50 dB @ (MHz) 20.5 101.5 209.5 14.5 95.5 203.5 44.25 118.5 267
DAC OUTPUT 600Ω 22pF 600 Ω
1 4
75Ω
BNC OUTPUT
560 Ω
Figure 86. Example of Output Filter for SD, 16× Oversampling
4.7µH
3
DAC OUTPUT 600Ω
6.8pF 6.8pF
600Ω
4
75Ω
1
BNC OUTPUT
560Ω
Figure 87. Example of Output Filter for ED, 8× Oversampling
DAC OUTPUT
3
300Ω
4
1
75Ω
390nH
3
BNC OUTPUT
1
33pF
33pF
75Ω
4
500 Ω
500Ω
Figure 88. Example of Output Filter for HD, 4× Oversampling
Rev. 0 | Page 62 of 96
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06234-087
560Ω
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560 Ω
ADV7390/ADV7391/ADV7392/ADV7393
0 –10 MAGNITUDE (dB) –20 –30
GAIN (dB)
CIRCUIT FREQUENCY RESPONSE
0 24n –30 21n –60 18n –90
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADV739x is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system-level design so that optimal performance is achieved. The layout should be optimized for lowest noise on the ADV739x power and ground planes by shielding the digital inputs and providing good power supply decoupling.
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PHASE (Degrees)
–40 –50 GROUP DELAY (Seconds) –60 –70 –80 1M
15n –120 12n –150 9n –180 6n –210 3n –240 0 1G
10M 100M FREQUENCY (Hz)
It is recommended to use a 4-layer printed circuit board with ground and power planes separating the signal trace layer and the solder side layer.
Figure 89. Output Filter Plot for SD, 16× Oversampling
Component Placement
Component placement should be carefully considered to separate noisy circuits, such as clock signals and high speed digital circuitry from analog circuitry. The external loop filter components and components connected to the COMP and RSET pins should be placed as close as possible to and on the same side of the PCB as the ADV739x. Adding vias to the PCB to get the components closer to the ADV739x is not recommended. It is recommended that the ADV739x be placed as close as possible to the output connector, with the DAC output traces as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV739x. The termination resistors should overlay the PCB ground plane. External filter and buffer components connected to the DAC outputs should be placed as close as possible to the ADV739x to minimize the possibility of noise pickup from neighboring circuitry, and to minimize the effect of trace capacitance on output bandwidth. This is particularly important when operating in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω).
PHASE (Degrees)
0 –10
CIRCUIT FREQUENCY RESPONSE
480 18n 400
MAGNITUDE (dB) –20 –30 320
16n 14n
GAIN (dB)
–40 –50 –60 –70 –80
GROUP DELAY (Seconds)
PHASE (Degrees)
240 160 80 8n 0 6n –80 4n –160 2n –240 0 1G 12n 10n
10M
100M
FREQUENCY (Hz)
Figure 90. Output Filter Plot for ED, 8× Oversampling
0
CIRCUIT FREQUENCY RESPONSE PHASE (Degrees) MAGNITUDE (dB)
200
–10 GROUP DELAY (Seconds)
120
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–90 1M
GAIN (dB)
–20
40
Power Supplies
It is recommended that a separate regulated supply be provided for each power domain (VAA, VDD, VDD_IO, and PVDD). For optimal performance, linear regulators rather than switch mode regulators should be used. If switch mode regulators must be used, care must be taken with regard to the quality of the output voltage in terms of ripple and noise. This is particularly true for the VAA and PVDD power domains. Each power supply should be individually connected to the system power supply at a single point through a suitable filtering device, such as a ferrite bead.
–30
–40
–40
–120
1
10 FREQUENCY (MHz)
100
Figure 91. Output Filter Plot for HD, 4× Oversampling
Rev. 0 | Page 63 of 96
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–50
–200
ADV7390/ADV7391/ADV7392/ADV7393
Power Supply Decoupling
It is recommended that each power supply pin be decoupled with 10 nF and 0.1 μF ceramic capacitors. The VAA, PVDD, VDD_IO, and both VDD pins should be individually decoupled to ground. The decoupling capacitors should be placed as close as possible to the ADV739x with the capacitor leads kept as short as possible to minimize lead inductance. A 1 μF tantalum capacitor is recommended across the VAA supply in addition to the 10 nF and 0.1 μF ceramic capacitors. Due to the high clock rates used, avoid long clock traces to the ADV739x to minimize noise pickup. Any pull-up termination resistors for the digital inputs should be connected to the VDD power supply. Any unused digital inputs should be tied to ground.
Analog Signal Interconnect
DAC output traces should be treated as transmission lines with appropriate measures taken to ensure optimal performance (for example, impedance matched traces). The DAC output traces should be kept as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV739x. To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the traces connected to the DAC output pins. Adding ground traces between the DAC output traces is also recommended.
Power Supply Sequencing
The ADV739x is robust to all power supply sequencing combinations. Any particular sequence can be used.
Digital Signal Interconnect
The digital signal traces should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal traces should not overlay the VAA or PVDD power planes.
Rev. 0 | Page 64 of 96
ADV7390/ADV7391/ADV7392/ADV7393
TYPICAL APPLICATION CIRCUIT
FERRITE BEAD VDD_IO 33µF 10µF 0.1µF GND_IO 0.1µF PGND 0.1µF AGND 0.1µF DGND 0.01µF GND_IO 0.01µF PGND 0.01µF AGND 0.01µF DGND 1µF VDD_IO POWER SUPPLY DECOUPLING PVDD POWER SUPPLY DECOUPLING VAA POWER SUPPLY AGND DECOUPLING NOTES 1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP, RSET AND DAC OUTPUT PINS SHOULD BE LOCATED CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS THE ADV739x. 2. WHEN OPERATING IN I2C MODE, THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB/SPI_SS PIN: ALSB/SPI_SS = 0, I2C DEVICE ADDRESS = 0xD4 OR 0x54 ALSB/SPI_SS = 1, I2C DEVICE ADDRESS = 0xD6 OR 0x56 3. THE RESISTOR CONNECTED TO THE RSET PIN SHOULD HAVE A 1% TOLERANCE. 4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULLDRIVE (RSET = 510Ω, RL = 37.5Ω).
GND_IO GND_IO FERRITE BEAD PVDD 33µF 10µF
PGND PGND FERRITE BEAD VAA 33µF 10µF
AGND AGND FERRITE BEAD VDD 33µF DGND 10µF DGND
VDD POWER SUPPLY DECOUPLING FOR EACH POWER PIN
VAA
VAA
VDD_IO
PVDD
VDD VDD
2.2nF COMP RSET
P0 P1 P2 P3 P4 P5 P6 P7
ADV739x
510Ω AGND DACs 1 TO 3 FULL DRIVE OPTION (RECOMMENDED) DAC 1
OPTIONAL LPF
PIXEL PORT INPUTS
P8 P9 P10 P11 P12 P13 P14 P15
DACs 1 TO 3 LOW DRIVE OPTION DAC 1 DAC 2 DAC 3 RSET 4.12kΩ AGND ADA4411-3 DAC 1 LPF 300Ω 75Ω DAC 1
ADV7392/ ADV7393 ONLY
DAC 2 DAC 3 75Ω AGND 75Ω
OPTIONAL LPF
75Ω
OPTIONAL LPF
AGND
AGND
CONTROL INPUTS/OUTPUTS
HSYNC VSYNC
CLOCK INPUT
CLKIN AGND SDA/SCLK SCL/MOSI SFL/MISO ALSB/SPI_SS ADA4411-3 DAC 2 LPF 300Ω RESET 75Ω DAC 2
MPU PORT INPUTS/OUTPUTS
EXTERNAL LOOP FILTER PVDD 12nF EXT_LF 150nF 170Ω DAC 3
AGND ADA4411-3 75Ω LPF 300Ω AGND
06234-092
DAC 3
LOOP FILTER COMPONENTS SHOULD BE LOCATED AGND PGND DGND DGND GND_IO CLOSE TO THE EXT_LF PIN AND ON THE SAME SIDE OF THE PCB AS THE ADV739x. AGND PGND DGND DGND GND_IO
Figure 92. ADV739x Typical Application Circuit
Rev. 0 | Page 65 of 96
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 1–COPY GENERATION MANAGEMENT SYSTEM
SD CGMS
Subaddress 0x99 to Subaddress 0x9B
The ADV739x supports copy generation management system (CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both. SD CGMS data can only be transmitted when the ADV739x is configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 93). When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i CGMS data is applied to Line 19 and Line 582 of the luminance vertical blanking interval. The HD CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV739x also supports CGMS Type B packets in HD mode (720p and 1080i) in accordance with CEA-805-A. When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 720p CGMS data is applied to Line 23 of the luminance vertical blanking interval. When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 1080i CGMS data is applied to Line 18 and Line 581 of the luminance vertical blanking interval. The HD CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
ED CGMS
Subaddress 0x41 to Subaddress 0x43 Subaddress 0x5E to Subaddress 0x6E 525p
The ADV739x supports copy generation management system (CGMS) in 525p mode in accordance with EIAJ CPR-1204-1. When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p CGMS data is inserted on Line 41. The 525p CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV739x also supports CGMS Type B packets in 525p mode in accordance with CEA-805-A. When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 525p CGMS Type B data is inserted on Line 40. The 525p CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
CGMS CRC FUNCTIONALITY
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS data bits (C19 to C14) that comprise the 6-bit CRC check sequence are automatically calculated on the ADV739x. This calculation is based on the lower 14 bits (C13 to C0) of the data in the CGMS data registers, and the result is output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If SD CGMS CRC or ED/HD CGMS CRC is disabled, all 20 bits (C19 to C0) are output directly from the CGMS registers (CRC must be calculated by the user manually). If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is enabled, the upper six CGMS Type B data bits (P122 to P127) that comprise the 6-bit CRC check sequence are automatically calculated on the ADV739x. This calculation is based on the lower 128 bits (H0 to H5 and P0 to P121) of the data in the CGMS Type B data registers. The result is output with the remaining 128 bits to form the complete 134 bits of the CGMS Type B data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5 and P0 to P127) are output directly from the CGMS Type B registers (CRC must be calculated by the user manually).
625p
The ADV739x supports copy generation management system (CGMS) in 625p mode in accordance with IEC 62375 (2004). When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p CGMS data is inserted on Line 43. The 625p CGMS data registers are at Subaddress 0x42 and Subaddress 0x43.
HD CGMS
Subaddress 0x41 to Subaddress 0x43 Subaddress 0x5E to Subaddress 0x6E
The ADV739x supports copy generation management system (CGMS) in HD mode (720p and 1080i) in accordance with EIAJ CPR-1204-2. When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p CGMS data is applied to Line 24 of the luminance vertical blanking interval.
Rev. 0 | Page 66 of 96
ADV7390/ADV7391/ADV7392/ADV7393
+100 IRE REF +70 IRE CRC SEQUENCE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE –40 IRE 11.2µs
2.235µs ± 20ns
Figure 93. Standard Definition CGMS Waveform
CRC SEQUENCE +700mV REF 70% ± 10% BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV –300mV 5.8µs ± 0.15µs 6T 21.2µs ± 0.22µs 22T
06234-094
06234-095
T = 1/(fH × 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T ± 30ns
Figure 94. Enhanced Definition (525p) CGMS Waveform
PEAK WHITE
R = RUN-IN S = START CODE
500mV ± 25mV
R
S
C0 C1 LSB
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 MSB
SYNC LEVEL
13.7µs
5.5µs ± 0.125µs
Figure 95. Enhanced Definition (625p) CGMS Waveform
+700mV REF 70% ± 10%
CRC SEQUENCE BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV –300mV 4T 3.128µs ± 90ns
T ± 30ns 17.2µs ± 160ns 22T T = 1/(fH × 1650/58) = 781.93ns fH = HORIZONTAL SCAN FREQUENCY 1H
06234-093
49.1µs ± 0.5µs
Figure 96. High Definition (720p) CGMS Waveform
Rev. 0 | Page 67 of 96
06234-096
ADV7390/ADV7391/ADV7392/ADV7393
+700mV REF 70% ± 10% CRC SEQUENCE BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV –300mV 4T 4.15µs ± 60ns
T ± 30ns 22.84µs ± 210ns 22T T = 1/(fH × 2200/77) = 1.038µs fH = HORIZONTAL SCAN FREQUENCY 1H
Figure 97. High Definition (1080i) CGMS Waveform
+700mV START 70% ± 10% BIT 1 BIT 2
CRC SEQUENCE BIT 134
P122
P123
P124
P125
P126
H0
H1
H2
H3
H4
H5
P2
P3
P0
0mV
06234-098
–300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
Figure 98. Enhanced Definition (525p) CGMS Type B Waveform
P1
P4
.
.
.
+700mV 70% ±10% START BIT 1 BIT 2
CRC SEQUENCE BIT 134
P122
P123
P124
P125
P126
H0
H1
H2
H3
H4
H5
P0
P1
P2
P3
0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
06234-099
Figure 99. High Definition (720p and 1080i) CGMS Type B Waveform
Rev. 0 | Page 68 of 96
P4
.
.
.
P127
P127
06234-097
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 2–SD WIDE SCREEN SIGNALING
Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B
The ADV739x supports wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the device is configured in PAL mode. The WSS data is 14 bits long. The function of each of these bits is shown in Table 54. The WSS data is preceded by a run-in sequence and a start code Table 54. Function of WSS Bits
Bit Description Aspect Ratio, Format, Position 13 12 11 10 9 Bit Number 8765 4 3 1 0 0 1 0 1 1 0 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Setting 4:3, full format, N/A 14:9, letterbox, center 14:9, letterbox, top 16:9, letterbox, center 16:9, letterbox, top >16:9, letterbox, center 14:9, full format, center 16:0, N/A, N/A Camera mode Film mode Normal PAL Motion Adaptive ColorPlus Not present Present No Yes No Subtitles in active image area Subtitles out of active image area Reserved No Yes No copyright asserted or unknown Copyright asserted Copying not restricted Copying restricted
(see Figure 100). The latter portion of Line 23 (after 42.5 μs from the falling edge of HSYNC) is available for the insertion of video. WSS data transmission on Line 23 can be enabled using Subaddress 0x99, Bit 7. It is possible to blank the WSS portion of Line 23 with Subaddress 0xA1, Bit 7.
Mode Color Encoding Helper Signals Reserved Teletext Subtitles Open Subtitles 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1
0 1
Surround Sound Copyright Copy Protection
500mV RUN-IN SEQUENCE START CODE W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 ACTIVE VIDEO
11.0µs 42.5µs
06234-100
38.4µs
Figure 100. WSS Waveform Diagram
Rev. 0 | Page 69 of 96
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 3–SD CLOSED CAPTIONING
Subaddress 0x91 to Subaddress 0x94
The ADV739x supports closed captioning conforming to the standard television synchronizing waveform for color transmission. When enabled, closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. Closed captioning can be enabled using Subaddress 0x83, Bits[6:5]. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase-locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic 1 start bit. Sixteen bits of data follow the start bit. The data consists of two 8-bit bytes (seven data bits, and one odd parity bit per byte). The data for these bytes is stored in SD closed captioning registers (Subaddress 0x93 to Subaddress 0x94). The ADV739x also supports the extended closed captioning operation, which is active during even fields and encoded on Line 284. The data for this operation is stored in SD closed captioning registers (Subaddress 0x91 to Subaddress 0x92). The ADV739x automatically generates all clock run-in signals and timing that support closed captioning on Line 21 and Line 284. All pixels inputs are ignored on Line 21 and Line 284 if closed captioning is enabled. The FCC Code of Federal Regulations (CFR) Title 47 Section 15.119 and EIA-608 describe the closed captioning information for Line 21 and Line 284. The ADV739x uses a single buffering method. This means that the closed captioning buffer is only 1-byte deep. Therefore, there is no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data must be loaded one line before it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn loads the new data (2 bytes) in every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes, on Line 21. Otherwise, a TV does not recognize them. If there is a message such as “Hello World” that has an odd number of characters, it is important to add a blank character at the end to make sure that the end-of-caption, 2-byte control code lands in the same field.
10.5 ± 0.25µs
12.91µs 7 CYCLES OF 0.5035MHz CLOCK RUN-IN TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A D0 TO D6 R T BYTE 0 P A R I T Y P A R I T Y
50 IRE
D0 TO D6
40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003µs 27.382µs
BYTE 1
33.764µs
Figure 101. SD Closed Captioning Waveform, NTSC
Rev. 0 | Page 70 of 96
06234-101
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 4–INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
The ADV739x is able to generate SD color bar and black bar test patterns. The register settings in Table 55 are used to generate an SD NTSC 75% color bar test pattern. All other registers are set as normal/ default. Component YPrPb output is available on DAC 1 to DAC 3. Upon power-up, the subcarrier frequency registers default to the appropriate values for NTSC. Table 55. SD NTSC Color Bar Test Pattern Register Writes
Subaddress 0x00 0x82 0x84 Setting 0x1C 0xC9 0x40
ED/HD TEST PATTERNS
The ADV739x is able to generate ED/HD color bar, black bar, and hatch test patterns. The register settings in Table 57 are used to generate an ED 525p hatch test pattern. All other registers are set as normal/ default. Component YPrPb output is available on DAC 1 to DAC 3. For component RGB output rather than YPrPb output, 0 should be written to Subaddress 0x02, Bit 5. Table 57. ED 525p Hatch Test Pattern Register Writes
Subaddress 0x00 0x01 0x31 Setting 0x1C 0x10 0x05
For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9 should be written to Subaddress 0x82. For component RGB output rather than YPrPb output, 0 should be written to Subaddress 0x02, Bit 5. To generate an SD NTSC black bar test pattern, the same settings shown in Table 55 should be used with an additional write of 0x24 to Subaddress 0x02. For PAL output of either test pattern, the same settings are used, except that Subaddress 0x80 is programmed to 0x11 and the subcarrier frequency (FSC) registers are programmed as shown in Table 56. Table 56. PAL FSC Register Writes
Subaddress 0x8C 0x8D 0x8E 0x8F Description FSC0 FSC1 FSC2 FSC3 Setting 0xCB 0x8A 0x09 0x2A
To generate an ED 525p black bar test pattern, the same settings as shown in Table 57 should be used with an additional write of 0x24 to Subaddress 0x02. To generate an ED 525p flat field test pattern, the same settings shown in Table 57 should be used, except that 0x0D should be written to Subaddress 0x31. The Y, Cr, and Cb levels for the hatch and flat field test patterns can be controlled using Subaddress 0x36, Subaddress 0x37, and Subaddress 0x38, respectively. For ED/HD standards other than 525p, the same settings as shown in Table 57 (and subsequent comments) are used except that Subaddress 0x30, Bits[7:3] are updated as appropriate.
Note that when programming the FSC registers, the user must write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full FSC value to be written is only accepted after the FSC3 write is complete.
Rev. 0 | Page 71 of 96
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 5–SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. If the VSYNC and HSYNC pins are not used, they should be tied high when using this mode.
ANALOG VIDEO
EAV CODE INPUT PIXELS C F0 0X818 1 Y Y r F0 0Y000 0 4 CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) 4 CLOCK END OF ACTIVE VIDEO LINE 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 CLOCK 280 CLOCK
SAV CODE 8 1 8 1 F 0 0 X CY C YC Y CY C b r b 0000F00Yb r 4 CLOCK 4 CLOCK
1440 CLOCK 1440 CLOCK
06234-102
START OF ACTIVE VIDEO LINE
Figure 102. SD Timing Mode 0, Slave Option
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV739x generates H and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is output on HSYNC and the F bit is output on VSYNC.
DISPLAY VERTICAL BLANK DISPLAY
522 H F
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
260 H F
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 103. SD Timing Mode 0, Master Option, NTSC
Rev. 0 | Page 72 of 96
06234-103
ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY VERTICAL BLANK DISPLAY
622 H
623
624
625
1
2
3
4
5
6
7
21
22
23
F
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
309 H
310
311
312
313
314
315
316
317
318
319
320
334
335
336
F
ODD FIELD
EVEN FIELD
Figure 104. SD Timing Mode 0, Master Option, PAL
ANALOG VIDEO
H
F
Figure 105. SD Timing Mode 0, Master Option, Data Transitions
Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)
In this mode, the ADV739x accepts horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as per CCIR-624. HSYNC and FIELD are input on the HSYNC and VSYNC pins, respectively.
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
06234-105
21
22
EVEN FIELD ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
260 HSYNC FIELD
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
06234-104
ODD FIELD
EVEN FIELD
Figure 106. SD Timing Mode 1,Slave Option, NTSC
Rev. 0 | Page 73 of 96
06234-106
ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY VERTICAL BLANK DISPLAY
622 HSYNC FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
309 HSYNC FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 107. SD Timing Mode 1, Slave Option, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the HSYNC and VSYNC pins, respectively.
HSYNC
FIELD
PIXEL DATA
Cb
Y
Cr
Y
06234-108
PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2
Figure 108. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV739x accepts horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV739x automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the HSYNC and VSYNC pins, respectively.
Rev. 0 | Page 74 of 96
06234-107
ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC VSYNC
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD DISPLAY
ODD FIELD DISPLAY
VERTICAL BLANK
260 HSYNC VSYNC
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 109. SD Timing Mode 2, Slave Option, NTSC
DISPLAY
VERTICAL BLANK
DISPLAY
622 HSYNC VSYNC
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD DISPLAY
ODD FIELD DISPLAY
VERTICAL BLANK
309 HSYNC VSYNC
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 110. SD Timing Mode 2, Slave Option, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV739x can generate horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV739x automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are output on the HSYNC and VSYNC pins, respectively.
HSYNC
VSYNC
PIXEL DATA PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2
Cb
Y
Cr
Y
06234-111
Figure 111. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
Rev. 0 | Page 75 of 96
06234-110
06234-109
ADV7390/ADV7391/ADV7392/ADV7393
HSYNC
VSYNC PAL = 864 × CLOCK/2 NTSC = 858 × CLOCK/2
PIXEL DATA PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2
Cb
Y
Cr
Y
Cb
06234-112
Figure 112. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV739x accepts or generates horizontal synchronization and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are output in master mode and input in slave mode on the HSYNC and VSYNC pins, respectively.
DISPLAY DISPLAY
VERTICAL BLANK
522 HSYNC FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD DISPLAY
ODD FIELD DISPLAY
VERTICAL BLANK
260 HSYNC FIELD
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 113. SD Timing Mode 3, NTSC
DISPLAY
VERTICAL BLANK
DISPLAY
622 HSYNC FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD DISPLAY
ODD FIELD DISPLAY
VERTICAL BLANK
309 HSYNC FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
EVEN FIELD
ODD FIELD
Figure 114. SD Timing Mode 3, PAL
Rev. 0 | Page 76 of 96
06234-114
06234-113
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 6–HD TIMING
DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL
1124
VSYNC
1125
1
2
3
4
5
6
7
8
20
21
22
560
HSYNC
DISPLAY
FIELD 2
VERTICAL BLANKING INTERVAL
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
VSYNC
06234-115
HSYNC
Figure 115. 1080i HSYNC and VSYNC Input Timing
Rev. 0 | Page 77 of 96
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 7–VIDEO OUTPUT LEVELS
SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10
Pattern: 100% Color Bars
MAGENTA YELLOW MAGENTA YELLOW GREEN GREEN BLACK WHITE CYAN BLUE RED BLACK WHITE CYAN BLUE RED
700mV
700mV
300mV
06234-116
300mV
06234-119
Figure 116. Y Levels—NTSC
Figure 119. Y Levels—PAL
MAGENTA
YELLOW
MAGENTA
YELLOW
GREEN
GREEN
BLACK
WHITE
CYAN
BLUE
RED
700mV
700mV
BLACK BLACK
06234-121 06234-120
WHITE
CYAN
06234-117
Figure 117. Pr Levels—NTSC
Figure 120. Pr Levels—PAL
MAGENTA
YELLOW
GREEN
BLACK
MAGENTA
YELLOW
GREEN
WHITE
CYAN
WHITE
CYAN
BLUE
RED
700mV
700mV
06234-118
Figure 118. Pb Levels—NTSC
Figure 121. Pb Levels—PAL
Rev. 0 | Page 78 of 96
BLUE
RED
BLUE
RED
ADV7390/ADV7391/ADV7392/ADV7393
ED/HD YPrPb OUTPUT LEVELS
INPUT CODE 940 EIA-770.2, STANDARD FOR Y
INPUT CODE 940 EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE
OUTPUT VOLTAGE
700mV
700mV
64
64 300mV
300mV
EIA-770.3, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
EIA-770.2, STANDARD FOR Pr/Pb 960
OUTPUT VOLTAGE
960
600mV 512
512
700mV
700mV
06234-124
64
06234-122
64
Figure 122. EIA-770.2 Standard Output Signals (525p/625p)
Figure 124. EIA-770.3 Standard Output Signals (1080i/720p)
INPUT CODE 940
EIA-770.1, STANDARD FOR Y
OUTPUT VOLTAGE 782mV
INPUT CODE 1023
Y–OUTPUT LEVELS FOR FULL INPUT SELECTION
OUTPUT VOLTAGE
700mV
714mV
64
64 286mV
300mV
EIA-770.1, STANDARD FOR Pr/Pb 960
INPUT CODE
OUTPUT VOLTAGE
Pr/Pb–OUTPUT LEVELS FOR FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
700mV
512 700mV
06234-123
64 300mV
06234-125
64
Figure 123. EIA-770.1 Standard Output Signals (525p/625p)
Figure 125. Output Levels for Full Input Selection
Rev. 0 | Page 79 of 96
ADV7390/ADV7391/ADV7392/ADV7393
SD/ED/HD RGB OUTPUT LEVELS
Pattern: 100%/75% Color Bars
R 700mV/525mV R 700mV/525mV
300mV
300mV
G 700mV/525mV
G 700mV/525mV
300mV
300mV
B 700mV/525mV
06234-126
B 700mV/525mV
06234-128
300mV
300mV
Figure 126. SD/ED RGB Output Levels—RGB Sync Disabled
Figure 128. HD RGB Output Levels—RGB Sync Disabled
R
R 700mV/525mV
600mV
700mV/525mV
300mV
300mV
0mV
0mV
G
G 700mV/525mV
600mV
700mV/525mV
300mV
300mV
0mV
0mV
B
B 700mV/525mV
600mV
700mV/525mV
300mV
300mV
06234-129
06234-127
0mV
0mV
Figure 127. SD/ED RGB Output Levels—RGB Sync Enabled
Figure 129. HD RGB Output Levels—RGB Sync Enabled
Rev. 0 | Page 80 of 96
ADV7390/ADV7391/ADV7392/ADV7393
SD OUTPUT PLOTS
VOLTS IRE:FLT
VOLTS 0.6
100
0.4
0.5 50
0.2
0
0
0
–0.2
–50 0 10
F1 L76 20
L608 0 10 20 30 40 50 60 MICROSECONDS NOISE REDUCTION: 0.00dB APL = 39.1% PRECISION MODE OFF 625 LINE NTSC NO FILTERING SYNCHRONOUS SOUND-IN-SYNC OFF SLOW CLAMP TO 0.00 AT 6.72µs FRAMES SELECTED 1, 2, 3, 4
06234-130
Figure 130. NTSC Color Bars (75%)
Figure 133. PAL Color Bars (75%)
VOLTS IRE:FLT 0.6
VOLTS
0.5
0.4
50
0.2
0
0
0 0
–0.2 0 10
F2 L238 20
0 10
L575 20 30 40 50 60 70
06234-131
Figure 131. NTSC Luma
Figure 134. PAL Luma
VOLTS IRE:FLT 0.4 50
VOLTS 0.5
0.2
0
0
0
–0.2 –50 –0.4 F1 L76 30 40 50 60 MICROSECONDS NOISE REDUCTION: 15.05dB PRECISION MODE OFF APL NEEDS SYNC SOURCE. SYNCHRONOUS SYNC = B 525 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00 AT 6.72µs 0 10 20
–0.5 L575 0 10 20 30 40 50 60 MICROSECONDS APL NEEDS SYNC SOURCE. NO BUNCH SIGNAL 625 LINE PAL NO FILTERING PRECISION MODE OFF SLOW CLAMP TO 0.00 AT 6.72µs SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1
06234-132
Figure 132. NTSC Chroma
Rev. 0 | Page 81 of 96
Figure 135. PAL Chroma
06234-135
06234-134
30 40 50 60 MICROSECONDS NOISE REDUCTION: 15.05dB APL = 44.3% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = SOURCE SLOW CLAMP TO 0.00V AT 6.72µs μ FRAMES SELECTED 1, 2
MICROSECONDS APL NEEDS SYNC SOURCE. NO BUNCH SIGNAL 625 LINE PAL NO FILTERING PRECISION MODE OFF SLOW CLAMP TO 0.00 AT 6.72µs SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1
06234-133
30 40 50 60 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72µs μ FRAMES SELECTED 1, 2
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 8–VIDEO STANDARDS
0HDATUM SMPTE 274M ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING *1 4T EAV CODE INPUT PIXELS F F 00F 00V H* 4 CLOCK SAMPLE NUMBER 2112 2116 2156 0 2199 44 188 272T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE 4T SAV CODE 1920T DIGITAL ACTIVE LINE CY r
F 0 0F C C V F 0 0 H* b Y r 4 CLOCK 192
2111
FOR A FRAME RATE OF 30Hz: 40 SAMPLES FOR A FRAME RATE OF 25Hz: 480 SAMPLES
Figure 136. EAV/SAV Input Data Timing Diagram (SMPTE 274M)
SMPTE 293M
ANALOG WAVEFORM EAV CODE INPUT PIXELS F F00V F 0 0 H* 4 CLOCK SAMPLE NUMBER 719 723 736 0HDATUM 799 DIGITAL HORIZONTAL BLANKING FVH* = FVH AND PARITY BITS SAV: LINE 43–525 = 200H SAV: LINE 1–42 = 2AC EAV: LINE 43–525 = 274H EAV: LINE 1–42 = 2D8 ANCILLARY DATA (OPTIONAL) SAV CODE F 0 0F V F 0 0 H* 4 CLOCK 853 857 0 719 DIGITAL ACTIVE LINE C C bYr C YrY
Figure 137. EAV/SAV Input Data Timing Diagram (SMPTE 293M)
ACTIVE VIDEO
VERTICAL BLANK
ACTIVE VIDEO
522
523
524
525
1
2
5
6
7
8
9
12
13
14
15
16
42
43
44
Figure 138. SMPTE 293M (525p)
Rev. 0 | Page 82 of 96
06234-138
06234-137
06234-136
FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1 SAV/EAV: LINE 21–560; 584–1123: V = 0
ADV7390/ADV7391/ADV7392/ADV7393
ACTIVE VIDEO VERTICAL BLANK ACTIVE VIDEO
622
623
624
625
1
2
4
5
6
7
8
9
10
11
12
13
43
44
45
Figure 139. ITU-R BT.1358 (625p)
DISPLAY VERTICAL BLANKING INTERVAL
06234-139
747
748
749
750
1
2
3
4
5
6
7
8
25
26
27
744
745
Figure 140. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
22 DISPLAY
560
VERTICAL BLANKING INTERVAL
FIELD 2
06234-141
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
Figure 141. SMPTE 274M (1080i)
Rev. 0 | Page 83 of 96
06234-140
ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 9–CONFIGURATION SCRIPTS
The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by default. If required for a specific application, further features can be enabled. Table 58 lists the scripts available for SD modes of operation. Similarly, Table 89 and Table 106 list the scripts available for ED and HD modes of operation, respectively.
STANDARD DEFINITION
Table 58. SD Configuration Scripts
Input Format 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 525i (NTSC) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) 625i (PAL) Input Data Width 8-Bit SDR 8-Bit SDR 8-Bit SDR 8-Bit SDR 8-Bit SDR 10-Bit SDR 10-Bit SDR 10-Bit SDR 10-Bit SDR 10-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 8-Bit SDR 8-Bit SDR 8-Bit SDR 8-Bit SDR 8-Bit SDR 10-Bit SDR 10-Bit SDR 10-Bit SDR 10-Bit SDR 10-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR Synchronization Format EAV/SAV EAV/SAV HSYNC/VSYNC EAV/SAV HSYNC/VSYNC EAV/SAV HSYNC/VSYNC HSYNC/VSYNC EAV/SAV HSYNC/VSYNC HSYNC/VSYNC HSYNC/VSYNC HSYNC/VSYNC HSYNC/VSYNC HSYNC/VSYNC EAV/SAV EAV/SAV HSYNC/VSYNC EAV/SAV HSYNC/VSYNC EAV/SAV HSYNC/VSYNC HSYNC/VSYNC EAV/SAV HSYNC/VSYNC HSYNC/VSYNC HSYNC/VSYNC HSYNC/VSYNC HSYNC/VSYNC HSYNC/VSYNC Input Color Space YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb RGB RGB RGB YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb RGB RGB RGB Output Color Space YPrPb CVBS/Y-C (S-Video) YPrPb RGB RGB YPrPb YPrPb CVBS/ Y-C (S-Video) RGB RGB YPrPb RGB YPrPb CVBS/ Y-C (S-Video) RGB YPrPb CVBS/Y-C (S-Video) YPrPb RGB RGB YPrPb YPrPb CVBS/Y-C (S-Video) RGB RGB YPrPb RGB YPrPb CVBS/Y-C (S-Video) RGB Table Number Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88
Table 59. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled.
Table 60. 8-Bit 525i YCrCb In (EAV/SAV), CVBS/Y-C Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xCB Description Software reset All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. CVBS/S-Video out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled.
Rev. 0 | Page 84 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 61. 8-Bit 525i YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
Table 64. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 10-bit input enabled.
0x8A
0x0C
0x88
0x10
Table 62. 8-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled.
Table 65. 10-Bit 525i YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 10-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
0x88 0x8A
0x10 0x0C
Table 63. 8-Bit 525i YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
Table 66. 10-Bit 525i YCrCb In, CVBS/Y-C Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xCB Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. CVBS/S-Video out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 10-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
0x8A
0x0C
0x88 0x8A
0x10 0x0C
Rev. 0 | Page 85 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 10-bit input enabled.
Table 70. 16-Bit 525i YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x10 0xC9 Description Software reset All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
0x88
0x10
0x88 0x8A
0x08 0x0C
Table 68. 10-Bit 525i YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 10-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
Table 71. 16-Bit 525i RGB In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. RGB input enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
0x88 0x8A
0x10 0x0C
0x87 0x88 0x8A
0x80 0x08 0x0C
Table 69. 16-Bit 525i YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. pedestal enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
Table 72. 16-Bit 525i RGB In, CVBS/Y-C Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0xCB Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. CVBS/S-Video out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. RGB input enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
0x88 0x8A
0x08 0x0C
0x87 0x88 0x8A
0x80 0x08 0x0C
Rev. 0 | Page 86 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 73. 16-Bit 525i RGB In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x10 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. RGB input enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization.
Table 76. 8-Bit 625i YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x8A 0x8C 0x8D 0x8E 0x8F
0x0C 0xCB 0x8A 0x09 0x2A
0x87 0x88 0x8A
0x80 0x08 0x0C
Table 74. 8-Bit 625i YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
Table 77. 8-Bit 625i YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x8C 0x8D 0x8E 0x8F
0xCB 0x8A 0x09 0x2A
0x8C 0x8D 0x8E 0x8F
0xCB 0x8A 0x09 0x2A
Table 75. 8-Bit 625i YCrCb In (EAV/SAV), CVBS/Y-C Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC3 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. CVBS/S-Video out. SSAF PrPb filter enabled. Active video edge control enabled. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
Table 78. 8-Bit 625i YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x8C 0x8D 0x8E 0x8F
0xCB 0x8A 0x09 0x2A
0x8A 0x8C 0x8D 0x8E 0x8F
Rev. 0 | Page 87 of 96
0x0C 0xCB 0x8A 0x09 0x2A
ADV7390/ADV7391/ADV7392/ADV7393
Table 79. 10-Bit 625i YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. 10-bit input enabled.
Table 82. 10-Bit 625i YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. 10-bit input enabled. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x88
0x10
Table 80. 10-Bit 625i YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. 10-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x88 0x8C 0x8D 0x8E 0x8F
0x10 0xCB 0x8A 0x09 0x2A
Table 83. 10-Bit 625i YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. 10-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x88 0x8A 0x8C 0x8D 0x8E 0x8F
0x10 0x0C 0xCB 0x8A 0x09 0x2A
0x88 0x8A 0x8C 0x8D 0x8E 0x8F
0x10 0x0C 0xCB 0x8A 0x09 0x2A
Table 81. 10-Bit 625i YCrCb In, CVBS/Y-C Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC3 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel Data Valid. CVBS/S-Video Out. SSAF PrPb Filter Enabled. Active Video Edge Control Enabled. 10-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
Table 84. 16-Bit 625i YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x88 0x8A 0x8C 0x8D 0x8E 0x8F
0x10 0x0C 0xCB 0x8A 0x09 0x2A
0x88 0x8A 0x8C 0x8D 0x8E 0x8F
0x08 0x0C 0xCB 0x8A 0x09 0x2A
Rev. 0 | Page 88 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 85. 16-Bit 625i YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
Table 87. 16-Bit 625i RGB In, CVBS/Y-C Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC3 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. CVBS/S-Video out. SSAF PrPb filter enabled. Active video edge control enabled. RGB input enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x88 0x8A 0x8C 0x8D 0x8E 0x8F
0x08 0x0C 0xCB 0x8A 0x09 0x2A
0x87 0x88 0x8A 0x8C 0x8D 0x8E 0x8F
0x80 0x08 0x0C 0xCB 0x8A 0x09 0x2A
Table 88. 16-Bit 625i RGB In, RGB Out Table 86. 16-Bit 625i RGB In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x80 0x82 Setting 0x02 0x1C 0x00 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. RGB input enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value. Subaddress 0x17 0x00 0x01 0x02 0x80 0x82 Setting 0x02 0x1C 0x00 0x10 0x11 0xC1 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. RGB input enabled. 16-bit input enabled. Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. PAL FSC value. PAL FSC value. PAL FSC value. PAL FSC value.
0x87 0x88 0x8A 0x8C 0x8D 0x8E 0x8F
0x80 0x08 0x0C 0xCB 0x8A 0x09 0x2A
0x87 0x88 0x8A 0x8C 0x8D 0x8E 0x8F
0x80 0x08 0x0C 0xCB 0x8A 0x09 0x2A
Rev. 0 | Page 89 of 96
ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION
Table 89. ED Configuration Scripts
Input Format 525p 525p 525p 525p 525p 525p 525p 525p 625p 625p 625p 625p 625p 625p 625p 625p Input Data Width 8-Bit DDR 8-Bit DDR 10-Bit DDR 10-Bit DDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 8-Bit DDR 8-Bit DDR 10-Bit DDR 10-Bit DDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR Synchronization Format EAV/SAV EAV/SAV EAV/SAV EAV/SAV EAV/SAV HSYNC/VSYNC EAV/SAV HSYNC/VSYNC EAV/SAV EAV/SAV EAV/SAV EAV/SAV EAV/SAV HSYNC/VSYNC EAV/SAV HSYNC/VSYNC Input Color Space YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb Output Color Space YPrPb RGB YPrPb RGB YPrPb YPrPb RGB RGB YPrPb RGB YPrPb RGB YPrPb YPrPb RGB RGB Table Number Table 98 Table 100 Table 99 Table 101 Table 90 Table 91 Table 92 Table 93 Table 102 Table 104 Table 103 Table 105 Table 94 Table 95 Table 96 Table 97
Table 90. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x10 0x04 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. 525p @ 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid.
Table 93. 16-Bit 525p YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x10 0x10 0x00 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. RGB output enabled. RGB output sync enabled. 525p @ 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. Pixel data valid.
Table 91. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x10 0x00 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. 525p @ 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. Pixel data valid.
Table 94. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x10 0x1C 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. 625p @ 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid.
Table 92. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x10 0x10 0x04 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. RGB output enabled. RGB output sync enabled. 525p @ 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid.
Table 95. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x10 0x18 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. 625p @ 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. Pixel data valid.
Rev. 0 | Page 90 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x10 0x10 0x1C 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. RGB output enabled. RGB output sync enabled. 625p @ 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid.
Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x20 0x10 0x04 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 525p @ 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid.
Table 97. 16-Bit 625p YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x10 0x10 0x18 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. RGB output enabled. RGB output sync enabled. 625p @ 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. Pixel data valid.
Table 101. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 0x33 Setting 0x02 0x1C 0x20 0x10 0x04 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 525p @ 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid. 10-bit input enabled.
Table 98. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x20 0x04 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 525p @ 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid.
Table 102. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 Setting 0x02 0x1C 0x20 0x1C 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 625p @ 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid.
Table 99. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 0x33 Setting 0x02 0x1C 0x20 0x04 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 525p @ 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid. 10-bit input enabled.
0x31
Table 103. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 0x33 Setting 0x02 0x1C 0x20 0x1C 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 625p @ 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid. 10-bit input enabled.
Rev. 0 | Page 91 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 104. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x20 0x10 0x1C 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 625p @ 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid.
Table 105. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 0x33 Setting 0x02 0x1C 0x20 0x10 0x1C 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 625p @ 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels. Pixel data valid. 10-bit input enabled.
HIGH DEFINITION
Table 106. HD Configuration Scripts
Input Format 720p 720p 720p 720p 720p 720p 720p 720p 1080i 1080i 1080i 1080i 1080i 1080i 1080i 1080i Input Data Width 8-Bit DDR 8-Bit DDR 10-Bit DDR 10-Bit DDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 8-Bit DDR 8-Bit DDR 10-Bit DDR 10-Bit DDR 16-Bit SDR 16-Bit SDR 16-Bit SDR 16-Bit SDR Synchronization Format EAV/SAV EAV/SAV EAV/SAV EAV/SAV EAV/SAV HSYNC/VSYNC EAV/SAV HSYNC/VSYNC EAV/SAV EAV/SAV EAV/SAV EAV/SAV EAV/SAV HSYNC/VSYNC EAV/SAV HSYNC/VSYNC Input Color Space YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb Output Color Space YPrPb RGB YPrPb RGB YPrPb YPrPb RGB RGB YPrPb RGB YPrPb RGB YPrPb YPrPb RGB RGB Table Number Table 115 Table 117 Table 116 Table 118 Table 107 Table 108 Table 109 Table 110 Table 119 Table 121 Table 120 Table 122 Table 111 Table 112 Table 113 Table 114
Rev. 0 | Page 92 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 107. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x10 0x2C 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. 720p @ 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 112. 16-Bit 1080i YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x10 0x18 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. 1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 108. 16-Bit 720p YCrCb In, YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x10 0x28 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. 720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 113. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x10 0x10 0x6C 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. RGB output enabled. RGB output sync enabled. 1080i @ 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 109. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x10 0x10 0x2C 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. RGB output enabled. RGB output sync enabled. 720p @ 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 114. 16-Bit 1080i YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x10 0x10 0x18 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. RGB output enabled. RGB output sync enabled. 1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 110. 16-Bit 720p YCrCb In, RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x10 0x10 0x28 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. RGB output enabled. RGB output sync enabled. 720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 115. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x20 0x2C 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 720p @ 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 111. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x10 0x6C 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. 1080i @ 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 116. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 0x33 Setting 0x02 0x1C 0x20 0x2C 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 720p @ 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling. 10-bit input enabled.
Rev. 0 | Page 93 of 96
ADV7390/ADV7391/ADV7392/ADV7393
Table 117. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x20 0x10 0x2C 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 720p @ 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 120. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 0x33 Setting 0x02 0x1C 0x20 0x6C 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 1080i @ 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling. 10-bit input enabled.
Table 118. 10-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 0x33 Setting 0x02 0x1C 0x20 0x10 0x2C 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 720p @ 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling. 10-bit input enabled.
Table 121. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 Setting 0x02 0x1C 0x20 0x10 0x6C 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 1080i @ 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
Table 122. 10-Bit 1080i YCrCb In (EAV/SAV), RGB Out Table 119. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress 0x17 0x00 0x01 0x30 0x31 Setting 0x02 0x1C 0x20 0x6C 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 1080i @ 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling. Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 0x33 Setting 0x02 0x1C 0x20 0x10 0x6C 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 1080i @ 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling. 10-bit input enabled.
Rev. 0 | Page 94 of 96
ADV7390/ADV7391/ADV7392/ADV7393 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30
12° MAX
9
0.25 MIN 3.50 REF
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
EXPOSED PADDLE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION, NOISE IMMUNITY AND MECHANICAL STRENGTH BENEFITS.
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 142. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
6.00 BSC SQ
0.60 MAX 0.60 MAX
31 30 40 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BCS SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10
21 20
0.25 MIN 4.50 REF
12° MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
EXPOSED PADDLE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION, NOISE IMMUNITY AND MECHANICAL STRENGTH BENEFITS.
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 143. 40-Lead Frame Chip Scale Package [LFCSP] (CP-40) Dimensions shown in millimeters
Rev. 0 | Page 95 of 96
ADV7390/ADV7391/ADV7392/ADV7393
ORDERING GUIDE
Model ADV7390BCPZ 2 ADV7390BCPZ-REEL2 ADV7391BCPZ2 ADV7391BCPZ-REEL2 ADV7392BCPZ2 ADV7392BCPZ-REEL2 ADV7393BCPZ2 ADV7393BCPZ-REEL2 EVAL-ADV739xFEZ2, 3 EVAL-ADV7390EBZ2 EVAL-ADV7391EBZ2 EVAL-ADV7392EBZ2 EVAL-ADV7393EBZ2
1 2 3
Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C
Macrovision 1 Anti-Taping Yes Yes No No Yes Yes No No N/A Yes No Yes No
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ADV739x Evaluation Platform Front-End Board. ADV7390 Evaluation Board ADV7391 Evaluation Board ADV7392 Evaluation Board ADV7393 Evaluation Board
Package Option CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-40 CP-40 CP-40 CP-40
Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video. Z = Pb-free. To be used in conjunction with any one of the ADV793x evaluation boards; this front-end board contains an Analog Devices decoder and Xilinx Spartan-3 FPGA.
Purchase of licensed I2 C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06234-0-10/06(0)
Rev. 0 | Page 96 of 96
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