Data Sheet
12-Bit, 170 MHz, Video and Graphics
Digitizer with Quad HDMI Receiver
ADV7604
FEATURES
Three 12-bit ADCs
ADC sampling rates up to 170 MHz
12-channel analog input mux
525i/625i component analog input
525p/625p component progressive scan support
720p/1080i/1080p/1250i component HDTV support
Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA)
VBI data slicer (including teletext)
Simultaneous HDMI and analog video sync processing
Ultralow jitter digital PLL
4:1 multiplexed HDMI receiver
HDMI 1.3a support
36-/30-/24-bit deep color support
Flexible audio interface (DSD, DST,
Dolby® TrueHD, DTS®-HD master audio, and DTS-HD
high resolution audio)
225 MHz HDMI receiver
Repeater support
High-bandwidth digital content protection (HDCP 1.3)
Programmable/adaptive equalizer for cable lengths up to
30 meters
Internal EDID RAM
EDID with HDMI cable power support
CEC support
General
S/PDIF (IEC90658-compatible) digital audio output
Highly flexible output interface
12-bit 4:4:4/8-bit 4:2:2 DDR pixel output interface
Dual STDI function support standard identification
2 any-to-any 3 × 3 color space conversion matrices
2 programmable interrupt request output pins
Advanced sync processing for robust sync extraction of
poor video sources
AV.Link support
APPLICATIONS
GENERAL DESCRIPTION
The ADV7604 is a high quality, single chip, multiformat video
decoder, graphics digitizer with an integrated 4:1 multiplexed
High-Definition Multimedia Interface (HDMI®) receiver.
The ADV7604 contains one main component processor (CP)
that processes YPrPb and RGB component formats, including
RGB graphics. The CP also processes the video signals from the
HDMI receiver. The ADV7604 can operate in quad HDMI and
analog input mode, thus providing simultaneous HDMI and
analog video sync processing. This allows for fast switching
between HDMI and the ADCs.
The ADV7604 supports the decoding of a component RGB/
YPrPb video signal into a digital YCrCb or RGB pixel output
stream. The support for component video includes 525i, 625i,
525p, 625p, 720p, 1080i, 1080p, and 1250i standards as well as
many other HD and SMPTE standards.
Graphics digitization is also supported by the ADV7604. The
ADV7604 is capable of digitizing RGB graphics signals from
VGA to UXGA rates and converting them into a digital RGB
or YCrCb pixel output stream.
The ADV7604 incorporates a quad input HDMI-compatible
receiver that supports all HDTV formats up to 1080p and display
resolutions up to UXGA (1600 × 1200 at 60 Hz). The reception
of encrypted video is possible with the inclusion of HDCP. The
HDMI receiver also includes programmable/adaptive equalization that ensures robust operation of the interface with cable
lengths up to 30 meters. The HDMI receiver has advanced
audio functionality, such as a mute controller that prevents
audible extraneous noise in the audio output.
Fabricated in an advanced CMOS process, the ADV7604 is
provided in a space-saving, 260-ball 15 mm × 15 mm BGA
surface-mount, RoHS-compliant package and is specified
over the −40°C to +70°C temperature range.
Advanced TV
PDP HDTVs
LCD TVs (HDTV ready)
LCD/DLP® rear projection HDTVs
CRT HDTVs
LCoS™ HDTVs
Rev. D
AVR video receivers
LCD/DLP front projectors
HDTV STBs with PVR
CRT HDTVs
DVD recorders with progressive scan input support
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADV7604
Data Sheet
TABLE OF CONTENTS
Features........................................................................................... 1
ESD Caution............................................................................... 9
Applications ................................................................................... 1
Pin Configuration and Function Descriptions.......................... 10
General Description ...................................................................... 1
Functional Overview................................................................... 17
Revision History ............................................................................ 2
Analog Front End .................................................................... 17
Functional Block Diagram............................................................ 3
HDMI Receiver........................................................................ 17
Specifications ................................................................................. 4
Component Processor (CP).................................................... 17
Analog, Digital, HDMI, and AC Specifications ...................... 4
CP Pixel Data Output Modes.................................................. 17
Video Specifications .................................................................. 5
RGB Graphics Processing ....................................................... 18
Data and I C Timing Characteristics ....................................... 5
Enhanced Standard Definition Processor.............................. 18
Power Specifications.................................................................. 8
I2C Interface ............................................................................. 18
Timing Diagrams....................................................................... 6
Other Features.......................................................................... 18
Absolute Maximum Ratings ......................................................... 9
Outline Dimensions .................................................................... 19
Package Thermal Performance ................................................. 9
Ordering Guide........................................................................ 19
2
REVISION HISTORY
9/13—Revision D: Initial Version
Rev. D | Page 2 of 20
Data Sheet
ADV7604
FUNCTIONAL BLOCK DIAGRAM
CLAMPIN
Y_MUX_OUT
12CHANNEL
INPUT
MATRIX
CLAMP
ADC0
CLAMP
ADC1
CLAMP
ADC2
RAW_SYNC
12
RAW_VSYNC
12
BACK
END
CSC
12
12
EMBEDDED
SYNC
SYNC1
SYNC2
SYNC3
SYNC4
CONTROL
AND
DATA
CONTROL
INTERFACE
I2C
TRILEVEL
SLICER
COMPONENT
PROCESSOR
AND
ENHANCED
STANDARD
DEFINITION
PROCESSOR
VIDEO DATA
PROCESSOR
CONTROL
P12 TO P23
P24 TO P35
LLC
INT1
SYNC_OUT/INT2
HS
VS_FIELD
DE
AVLINK
PACKET /
INFOFRAME
MEMORY
CEC
CONTROLLER
RXA_C±
RXB_C±
RXC_C±
RXD_C±
MUX
RXA_0±
RXA_1±
RXA_2±
EQUALIZER
SAMPLER
RXB_0±
RXB_1±
RXB_2±
EQUALIZER
SAMPLER
PLL
RXC_0±
RXC_1±
RXC_2±
EQUALIZER
SAMPLER
RXD_0±
RXD_1±
RXD_2±
EQUALIZER
SAMPLER
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
RXA_5V
RXB_5V
RXC_5V
RXD_5V
EP_MISO
EP_MOSI
EP_CS
EP_SCK
SHARED_EDID
PWRDN
12
P0 TO P11
HDMI
PROCESSOR
I2S0/DSD0B/HBR0
I2S1/DSD1A/HBR1
I2S2/DSD1B/HBR2
I2S3/DSD2A/HBR3
AUDIO
PACKET
PROCESSOR
HDCP
ENGINE
LRCLK/DSD2B/DST_FF
SCLK/DST_CLK
HDCP
EEPROM
MCLKOUT
SPDIF/DSD0/DST
EDID
REPEATER
CONTROLLER
ADV7604
Figure 1.
Rev. D | Page 3 of 20
07971-001
AVLINK
SCL
SDA
CEC
DATA
PREPROCESSOR
AND
COLOR
A
SPACE
B
CONVERTER
C
HS/CS, VS
BLC
SYNC PROCESSING
AND
CLOCK GENERATION
HS_IN1
VS_IN1
TRI7/HS_IN2
TRI8/VS_IN2
TRI1
TRI2
TRI3
TRI4
TRI5
TRI6
12
OUTPUT FORMATTER
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
ADV7604
Data Sheet
SPECIFICATIONS
AVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, CVDD = 1.8 V ± 5%,
TMIN to TMAX = −40°C to +70°C.
ANALOG, DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter
ANALOG
Clamp Circuitry
External Clamp Capacitor
Input Impedance
ADC Midscale (CML)
ADC Full-Scale Level
ADC Zero-Scale Level
ADC Dynamic Range
Clamp Level (When Locked)
DIGITAL INPUTS
Input High Voltage (VIH )
Input Low Voltage (VIL)
Input Current (IIN )
Input Capacitance (CIN )
DIGITAL INPUTS (5 V TOLERANT) 1
Input High Voltage (VIH )
Input Low Voltage (VIL)
Input Current (IIN )
Test Conditions/Comments
Typ
Max
100
10
0.89
CML + 0.550
CML − 0.550
1.1
CML − 0.130
CML
CML
CML − 0.130
Clamps switched off
Component input (Y signal)
Component input (Pr signal)
Component input (Pb signal)
PC RGB input (R, G, B)
RESET pin
Other digital inputs
−60
−10
0.8
+60
+10
10
V
V
µA
µA
pF
0.8
+60
+82
V
V
µA
µA
2.6
SHARED_EDID pin
Other 5 V digital inputs
−150
−82
2.4
0.4
10
20
0.3
TMDS Input Clock Range
Input Clock Jitter Tolerance
Unit
nF
MΩ
V
V
V
V
V
V
V
V
2
DIGITAL OUTPUTS
Output High Voltage (VOH )
Output Low Voltage (VOL)
High Impedance Leakage Current (ILEAK)
Output Capacitance (COUT)
HDMI
TMDS Differential Pin Capacitance
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew for TMDS
Clock Rates up to 222.75 MHz
Intrapair (+ to −) Differential Input Skew for TMDS
Clock Rates Above 222.75 MHz
Channel-to-Channel Differential Input Skew
1
Min
V
V
µA
pF
pF
0.4 TBIT
ps
0.15 TBIT
+ 112
ps
25
0.5
0.2 tPIXEL +
1.78
225
0.25 TBIT
ns
MHz
TBIT
The following pins are 5 V tolerant: HS_IN1, HS_IN2, VS_IN1, VS_IN2, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA,
RXA_5V, RXB_5V, RXC_5V, RXD_5V, SHARED_EDID, PWRDN , EP_MISO.
Rev. D | Page 4 of 20
Data Sheet
ADV7604
VIDEO SPECIFICATIONS
Table 2.
Parameter
NOISE SPECIFICATIONS
SNR Unweighted
Symbol
Analog Front-End Crosstalk
VIDEO STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
N
INL
Differential Nonlinearity
DNL
Test Conditions/Comments
Measure at 27 MHz LLC
Luma ramp
Luma flat field
Min
Typ
Max
Unit
60
60
60
12
−3.0
−3.0
−4.0
−3.5
−0.7
−0.7
−0.7
−0.7
−0.7
−0.6
27 MHz (at a 12-bit level)
54 MHz (at a 12-bit level)
74.25 MHz (at a 12-bit level)
108 MHz (at an 11-bit level)
170 MHz (at a 9-bit level)
27 MHz (at a 12-bit level)
54 MHz (at a 12-bit level)
75 MHz (at a 12-bit level)
108 MHz (at an 11-bit level)
170 MHz (at a 9-bit level)
dB
dB
dB
to +8.0
to +8.0
to +7.0
to +8.0
to +1.5
to +0.8
to +0.8
to +0.8
to +0.8
to +0.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
DATA AND I2C TIMING CHARACTERISTICS
Table 3.
Parameter
VIDEO SYSTEM CLOCK AND XTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC Frequency Range
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
±100
110
170
MHz
ppm
kHz
MHz
24.576/28.6363
10
12.82
5
External Clock Source 1
Input High Voltage
VIH
Input Low Voltage
VIL
External crystal must operate at 1.8 V
Ball H15 (XTALP) driven with external
clock source
Ball H15 (XTALP) driven with external
clock source
1.2
V
0.4
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
t9 :t10
45:55
I2 C PORTS (FAST MODE)
xCL Frequency 2
xCL Minimum Pulse Width High2
xCL Minimum Pulse Width Low2
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time2
xCL and xDA Rise Time2
xCL and xDA Fall Time2
Setup Time (Stop Condition)
t1
t2
t3
t4
t5
t6
t7
t8
600
1.3
600
600
100
5
ms
55:4
5
% duty
cycle
400
kHz
ns
µs
ns
ns
ns
ns
ns
µs
300
300
0.6
Rev. D | Page 5 of 20
V
ADV7604
Data Sheet
Parameter
I2C PORTS
Normal Mode
xCL Frequency2
xCL Minimum Pulse Width High2
xCL Minimum Pulse Width
Low2
Hold Time (Start Condition)2
Setup Time (Start Condition)2
xDA Setup Time2
xCL and xDA Rise Time2
xCL and xDA Fall Time2
Setup Time (Stop Condition)
DATA AND CONTROL OUTPUTS3
Data Output Transition Time SDR
(CP)
Data Output Transition Time SDR
(CP)
VIDEO I2S PORT
Master Mode
SCLK Mark Space Ratio
Symbol
Test Conditions/Comments
Min
t1
t2
4.0
4.7
t3
t4
t5
t6
t7
t8
4.0
4.7
250
Typ
Max
Unit
100
kHz
μs
μs
1000
300
4.0
μs
μs
ns
ns
ns
μs
t11
End of valid data to negative clock edge
0.55
ns
t12
Negative clock edge to start of valid data
1.0
ns
t13:t14
LRCLK Data Transition Time
t15
LRCLK Data Transition Time
t16
I2Sx Data Transition Time4
t17
I2Sx Data Transition Time4
t18
45:55
End of valid data to negative SCLK
edge
Negative SCLK edge to start of valid
data
End of valid data to negative SCLK
edge
Negative SCLK edge to start of valid
data
1
The XTAL_CTRL bit in AFE Map 0x4C[7:6] = 10b. This configures the XTAL pins for external oscillator operation. A 1.8 V oscillator must be used.
The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S.
3
LLC DLL disabled.
4
The suffix x refers to 0, 1, 2, and 3.
2
TIMING DIAGRAMS
t3
t5
t3
xDA
t6
t1
t2
t7
t4
NOTES
1. x REFERS TO S, DDCA_S, DDCB_S, DDCC_S, DDCD_S.
Figure 2. I2C Timing
Rev. D | Page 6 of 20
t8
07971-002
xCL
55:4
5
10
% duty
cycle
ns
10
ns
5
ns
5
ns
Data Sheet
ADV7604
t9
t10
LLC
t11
07971-003
t12
P0 TO P35, VS,
HS, DE
Figure 3. Pixel Port and Control SDR Output Timing
t13
SCL
t14
t15
LRCLK
t16
t17
MSB
MSB – 1
t18
I2Sx
I2S MODE
I2Sx
RIGHT-JUSTIFIED
MODE
t17
MSB
MSB – 1
t18
t17
MSB
LSB
t18
NOTES
1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3.
Figure 4. I2S Timing
Rev. D | Page 7 of 20
07971-004
I2Sx
LEFT-JUSTIFIED
MODE
ADV7604
Data Sheet
POWER SPECIFICATIONS
Table 4.
Parameter
POWER SUPPLIES
Analog Supply (AVDD)
Digital Core Power Supply (DVDD)
Digital I/O Power Supply (DVDDIO)
PLL Power Supply (PVDD)
Terminator Power Supply (TVDD)
Comparator Power Supply (CVDD)
CURRENT CONSUMPTION 1, 2, 3, 4
Analog Power Supply (IAVDD)
Comparator Power Supply (ICVDD)
Digital Core Power Supply (IDVDD)
Digital I/O Power Supply (IDVDDIO)
PLL Power Supply (IPVDD)
Termination Power Supply (ITVDD)
Min
Typ
Max
Unit
1.71
1.71
3.14
1.71
3.14
1.71
1.8
1.8
3.3
1.8
3.3
1.8
1.89
1.89
3.46
1.89
3.46
1.89
V
V
V
V
V
V
200.0
0.1
199.9
258.3
0.1
255.4
mA
mA
mA
0.0
3.6
102.9
102.8
0.0
5.6
121.9
120.2
mA
mA
mA
mA
3.7
143.7
212.4
239.7
4.0
204.2
290.2
303.7
mA
mA
mA
mA
2.3
54.2
29.7
101.8
2.5
131.2
167.0
165.8
mA
mA
mA
mA
1.3
64.1
74.7
75.1
1.4
75.6
87.5
88.2
mA
mA
mA
mA
0.2
2.5
185.3
185.3
0.22
4.8
204.5
204.5
mA
mA
mA
mA
1.1
1.2
mA
Test Conditions/Comments
Analog only: RGB sampling at 162 MHz (UXGA)
HDMI only: 1080p 12-bit Deep Color with 4-channel PCM
Simultaneous mode: 1080p 12-bit Deep Color with 4-channel
PCM and RGB sampling at 1080p
Power-Down Mode 0
Analog only: RGB sampling at 162 MHz (UXGA)
HDMI only: 1080p 12-bit Deep Color with 4-channel PCM
Simultaneous mode: 1080p 12-bit Deep Color with 4-channel
PCM and RGB sampling at 1080p
Power-Down Mode 0
Analog only: RGB sampling at 162 MHz (UXGA)
HDMI only: 1080p 12-bit Deep Color with 4-channel PCM
Simultaneous mode: 1080p 12-bit Deep Color with 4-channel
PCM and RGB sampling at 1080p
Power-Down Mode 0
Analog only: RGB sampling at 162 MHz (UXGA)
HDMI only: 1080p 12-bit Deep Color with 4-channel PCM
Simultaneous mode: 1080p 12-bit Deep Color with 4-channel
PCM and RGB sampling at 1080p
Power-Down Mode 0
Analog only: RGB sampling at 162 MHz (UXGA)
HDMI only: 1080p 12-bit Deep Color with 4-channel PCM
Simultaneous mode: 1080p 12-bit Deep Color with 4-channel
PCM and RGB sampling at 1080p
Power-Down Mode 0
Analog only: RGB sampling at 162 MHz (UXGA)
HDMI only: 1080p 12-bit Deep Color with 4-channel PCM
Simultaneous mode: 1080p 12-bit Deep Color with 4-channel
PCM and RGB sampling at 1080p
Power-Down Mode 0
All maximum current values are guaranteed by characterization to assist in power supply design.
Typical current consumption values are recorded with nominal voltage supply levels and a SMPTEBAR pattern.
3 Maximum current consumption values are recorded with maximum rated voltage supply levels and a MOIRE X pattern.
4 Termination power supply includes TVDD current consumed off chip.
1
2
Rev. D | Page 8 of 20
Data Sheet
ADV7604
ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL PERFORMANCE
Table 5.
Parameter
AVDD to GND
DVDD to GND
PVDD to GND
DVDDIO to GND
CVDD to GND
TVDD to GND
Digital Inputs Voltage to GND
5 V Tolerant Digital Inputs to GND1
Digital Output Voltage to GND
Analog Inputs to GND
XTAL Pins
Maximum Junction Temperature (TJ MAX)
Storage Temperature
Infrared Reflow Soldering (20 sec)
1
Rating
2.2 V
2.2 V
2.2 V
4.0 V
2.2 V
4.0 V
GND − 0.3 V to
DVDDIO + 0.3 V
5.3 V
GND − 0.3 V to
DVDDIO + 0.3 V
GND − 0.3 V to
AVDD + 0.3 V
−0.3 V to PVDD
to 0.3 V
125°C
150°C
260°C
The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1, HS_IN2,
VS_IN1, VS_IN2, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL,
DDCC_SDA, DDCD_SCL, DDCD_SDA, RXA_5V, RXB_5V, RXC_5V, RXD_5V,
SHARED_EDID, PWRDN , EP_MISO.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
To reduce power consumption when using the ADV7604, the
user is advised to turn off unused sections of the part.
Due to printed circuit board metal variation and, thus, variation
in PCB heat conductivity, the value of θJA may differ for various
PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this eliminates the variance associated with the θJA value.
The maximum junction temperature (TJ MAX ) of 125°C must not
be exceeded. The following equation calculates the junction
temperature using the measured package surface temperature
and applies only when no heat sink is used on DUT:
TJ = TS + (ΨJT × WTOTAL)
where:
TS = the package surface temperature (°C).
ΨJT = 0.3°C/W for a 260-ball CSP_BGA.
WTOTAL = ((PVDD × IPVDD) + (0.05 × TVDD × ITVDD) + (CVDD ×
ICVDD) + (AVDD × IAVDD) + (DVDD × IDVDD) + (DVDDIO ×
IDVDDIO)).
Note that for WTOTAL, 5% of TVDD power is dissipated on the
part itself.
ESD CAUTION
Rev. D | Page 9 of 20
ADV7604
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
DGND
RXD_2–
RXD_1–
RXD_0–
RXD_C–
DGND
RXC_2–
RXC_1–
RXC_0–
RXC_C–
TVDD
RXB_2–
RXB_1–
RXB_0–
RXB_C–
TVDD
TVDD
DGND
A
B
RXD_5V
RXD_2+
RXD_1+
RXD_0+
RXD_C+
TVDD
RXC_2+
RXC_1+
RXC_0+
RXC_C+
TVDD
RXB_2+
RXB_1+
RXB_0+
RXB_C+
TVDD
RXA_2+
RXA_2–
B
C
PWRDN
TVDD
TVDD
CVDD
DGND
TVDD
TVDD
DGND
DGND
DGND
TVDD
TVDD
DGND
DGND
DGND
DGND
RXA_1+
RXA_1–
C
D
RXC_5V
RXB_5V
RXA_5V
DDCD_
SDA
DDCD_
SCL
DDCC_
SDA
DDCC_
SCL
CVDD
DGND
RTERM
CVDD
DDCB_
SDA
DDCB_
SCL
DDCA_
SCL
DDCA_
SDA
TVDD
RXA_0+
RXA_0–
D
E
DE
CEC
NC
NC
DGND
DGND
RXA_C+
RXA_C–
E
F
HS
VS_
FIELD
DGND
CVDD
TVDD
DGND
F
G
P1
P0
EP_CS
EP_SCK
DGND
DGND
DGND
DGND
PVDD
PVDD
NC
NC
TEST1
TEST2
G
H
P3
P2
RAW_
VSYNC
RAW_
SYNC
DGND
DGND
DGND
DGND
AGND
AGND
XTALP
AVDD
REFN
REFP
H
DVDD
DGND
DGND
DGND
AGND
AGND
XTALN
AVDD
AGND
AGND
J
AVDD
AVDD
AIN11
AIN12
K
SYNC4
AIN10
L
EP_MISO EP_MOSI
J
DGND
DGND
MCLK
OUT
SPDIF/
DSD0A/
DST
K
P4
P5
LRCLK/
DSD2B/
DST_FF
SCLK/
DST_CLK
DVDD
DVDD
DGND
DGND
AGND
AVDD
L
P6
P7
I2S3/
DSD2A/
HBR3
I2S2/
DSD1B/
HBR2
DVDD
DVDD
DGND
DGND
AGND
AVDD
M
P8
DGND
DGND
DGND
DVDD
DVDD
DGND
DGND
AGND
AVDD
N
P9
DVDDIO
DVDDIO
TRI8/VS_ TRI7/HS_
IN2
IN2
TRI5
TRI6
AGND
AGND
M
DVDDIO
TRI3
TRI4
AIN8
AIN9
N
I2S1/
DSD1A/
HBR1
AVDD
AVDD
SYNC3
AIN7
P
P
P10
P11
I2S0/
DSD0B/
HBR0
R
P12
P13
DGND
DGND
SCL
DVDDIO
INT1
CLAMPIN
DVDDIO
DGND
FB_OUT
SHARED_
EDID
HS_IN1
AGND
Y_MUX_
OUT
TRI2
AGND
AGND
R
T
P14
P15
DGND
DGND
P25
DVDDIO
SDA
SYNC_
OUT/INT2
DVDDIO
DGND
RESET
AVLINK
VS_IN1
AGND
TRI1
SYNC2
AIN5
AIN6
T
U
P16
P17
P19
P21
P23
DGND
P26
DCLKIN
P28
DGND
P31
P33
P35
AGND
SYNC1
AVDD
AVDD
AIN4
U
V
DGND
P18
P20
P22
P24
DGND
P27
LLC
P29
DGND
P30
P32
P34
AGND
AIN1
AIN2
AIN3
AGND
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
Mnemonic
DGND
RXD_2−
RXD_1−
RXD_0−
RXD_C−
DGND
RXC_2−
RXC_1−
RXC_0−
RXC_C−
TVDD
RXB_2−
RXB_1−
RXB_0−
RXB_C−
Type
Ground
HDMI input
HDMI input
HDMI input
HDMI input
Ground
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
HDMI input
HDMI input
Description
Ground.
Digital Input Channel 2 Complement of Port D in the HDMI Interface.
Digital Input Channel 1 Complement of Port D in the HDMI Interface.
Digital Input Channel 0 Complement of Port D in the HDMI Interface.
Digital Input Clock Complement of Port D in the HDMI Interface.
Ground.
Digital Input Channel 2 Complement of Port C in the HDMI Interface.
Digital Input Channel 1 Complement of Port C in the HDMI Interface.
Digital Input Channel 0 Complement of Port C in the HDMI Interface.
Digital Input Clock Complement of Port C in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 2 Complement of Port B in the HDMI Interface.
Digital Input Channel 1 Complement of Port D in the HDMI Interface.
Digital Input Channel 0 Complement of Port B in the HDMI Interface.
Digital Input Clock Complement of Port B in the HDMI Interface.
Rev. D | Page 10 of 20
07971-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
ADV7604
Pin No.
A16
A17
A18
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
Mnemonic
TVDD
TVDD
DGND
RXD_5V
RXD_2+
RXD_1+
RXD_0+
RXD_C+
TVDD
RXC_2+
RXC_1+
RXC_0+
RXC_C+
TVDD
RXB_2+
RXB_1+
RXB_0+
RXB_C+
TVDD
RXA_2+
RXA_2−
PWRDN
Type
Power
Power
Ground
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
Input
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
TVDD
TVDD
CVDD
DGND
TVDD
TVDD
DGND
DGND
DGND
TVDD
TVDD
DGND
DGND
DGND
DGND
RXA_1+
RXA_1−
RXC_5V
RXB_5V
RXA_5V
DDCD_SDA
DDCD_SCL
DDCC_SDA
DDCC_SCL
CVDD
DGND
RTERM
Power
Power
Power
Ground
Power
Power
Ground
Ground
Ground
Power
Power
Ground
Ground
Ground
Ground
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
Power
Ground
Miscellaneous
analog
Description
Terminator Supply Voltage (3.3 V ).
Terminator Supply Voltage (3.3 V ).
Ground.
5 V Detect Pin for Port D in the HDMI Interface.
Digital Input Channel 2 True of Port D in the HDMI Interface.
Digital Input Channel 1 True of Port D in the HDMI Interface.
Digital Input Channel 0 True of Port D in the HDMI Interface.
Digital Input Clock True of Port D in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 2 True of Port C in the HDMI Interface.
Digital Input Channel 1 True of Port C in the HDMI Interface.
Digital Input Channel 0 True of Port C in the HDMI Interface.
Digital Input Clock True of Port C in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 2 True of Port B in the HDMI Interface.
Digital Input Channel 1 True of Port B in the HDMI Interface.
Digital Input Channel 0 True of Port B in the HDMI Interface.
Digital Input Clock True of Port B in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
Active Low System Power Detect. If low, EDID can be powered from 5 V signal of
HDMI port when connected to active equipment.
Terminator Supply Voltage (3.3 V ).
Terminator Supply Voltage (3.3 V ).
Comparator Supply Voltage (1.8 V ).
Ground.
Terminator Supply Voltage (3.3 V ).
Terminator Supply Voltage (3.3 V ).
Ground.
Ground.
Ground.
Terminator Supply Voltage (3.3 V ).
Terminator Supply Voltage (3.3 V ).
Ground.
Ground.
Ground.
Ground.
Digital Input Channel 1 Complement of Port A in the HDMI interface.
Digital Input Channel 1 Complement of Port A in the HDMI interface.
5 V Detect Pin for Port C in the HDMI Interface.
5 V Detect Pin for Port B in the HDMI Interface.
5 V Detect Pin for Port A in the HDMI Interface.
HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.
Comparator Supply Voltage (1.8 V ).
Ground.
Terminal Resistance. This pin sets internal termination resistance. Use a 500 Ω
resistor between this pin and GND.
Rev. D | Page 11 of 20
ADV7604
Data Sheet
Pin No.
D11
D12
D13
D14
D15
D16
D17
D18
E1
E2
E3
E4
E15
E16
E17
E18
F1
F2
Mnemonic
CVDD
DDCB_SDA
DDCB_SCL
DDCA_SCL
DDCA_SDA
TVDD
RXA_0+
RXA_0−
DE
CEC
NC
NC
DGND
DGND
RXA_C+
RXA_C−
HS
VS_FIELD
Type
Power
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
Digital video output
Digital I/O
No connect
No connect
Ground
Ground
HDMI input
HDMI input
Digital video output
Digital video output
F3
F4
F15
F16
F17
F18
G1
G2
G3
G4
G7
G8
G9
G10
G11
G12
G15
G16
G17
G18
H1
H2
H3
H4
H7
H8
H9
H10
H11
H12
EP_MISO
EP_MOSI
DGND
CVDD
TVDD
DGND
P1
P0
EP_CS
EP_SCK
DGND
DGND
DGND
DGND
PVDD
PVDD
NC
NC
TEST1
TEST2
P3
P2
RAW_VSYNC
RAW_SYNC
DGND
DGND
DGND
DGND
AGND
AGND
Digital input
Digital output
Ground
Power
Power
Ground
Digital video output
Digital video output
Digital output
Digital output
Ground
Ground
Ground
Ground
Power
Power
No connect
No connect
Test
Test
Digital video output
Digital video output
Analog output
Analog output
Ground
Ground
Ground
Ground
Ground
Ground
Description
Comparator Supply Voltage (1.8 V ).
HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
Terminator Supply Voltage (3.3 V ).
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
Data Enable. DE is a signal that indicates active pixel data.
Consumer Electronic Control Channel.
Do Not Connect.
Do Not Connect.
Ground.
Ground.
Digital Input Clock Complement of Port A in the HDMI Interface.
Digital Input Clock Complement of Port A in the HDMI Interface.
Horizontal Synchronization Output Signal in the CP and HDMI Processor.
Vertical Synchronization Output Signal in the CP and HDMI Processor. FIELD is a
field synchronization output signal in all interlaced video modes. VS or FIELD
can be configured for this pin.
SPI Master In/Slave Out for External EDID Interface.
SPI Master Out/Slave In for External EDID Interface.
Ground.
Comparator Supply Voltage (1.8 V ).
Terminator Supply Voltage (3.3 V ).
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
SPI Chip Select for External EDID Interface.
SPI Clock for External EDID Interface.
Ground.
Ground.
Ground.
Ground.
PLL Supply Voltage (1.8 V ).
PLL Supply Voltage (1.8 V ).
Do Not Connect.
Do Not Connect.
Do Not Connect.
Do Not Connect.
Video Pixel Output Port.
Video Pixel Output Port.
This pin outputs the raw-sliced, embedded CSYNC or raw digital HS/CS.
This pin outputs the raw-sliced, embedded CSYNC or raw digital HS/CS.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Rev. D | Page 12 of 20
Data Sheet
ADV7604
Description
Input pin for the 28.63636 MHz crystal or can be overdriven by an external 1.8 V
28.63636 MHz clock oscillator source to clock the ADV7604. The following
crystal frequencies are also supported: 24.576 MHz and 27.00 MHz.
Analog Supply Voltage (1.8 V ).
Internal Voltage Reference Output.
Internal Voltage Reference Output.
Ground.
Ground.
Audio Master Clock Output.
Multipurpose Pin. S/PDIF Digital Audio Output.
First DSD Data Channel.
DST Stream.
Digital Supply Voltage (1.8 V ).
Ground.
Ground.
Ground.
Ground.
Ground.
This pin should be connected to the 28.63636 MHz crystal or left as a no
connect if an external 1.8 V 28.63636 MHz clock oscillator source is used to clock
the ADV7604. In crystal mode, the crystal must be a fundamental crystal. The
following crystal frequencies are also supported: 24.576 MHz and 27.00 MHz.
Analog Supply Voltage (1.8 V ).
Ground.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Dual Purpose Pin. Data Output Clock. Left and right audio channels.
Sixth DSD Data Channel.
DST Frame.
Dual Purpose Pin. Audio Serial Clock Output.
DST Clock.
Pin No.
H15
Mnemonic
XTALP
Type
Miscellaneous
analog
H16
H17
H18
J1
J2
J3
J4
AVDD
REFN
REFP
DGND
DGND
MCLKOUT
SPDIF/DSD0A/DST
Power
Misc analog
Misc analog
Ground
Ground
Digital output
Digital output
J7
J8
J9
J10
J11
J12
J15
DVDD
DGND
DGND
DGND
AGND
AGND
XTALN
Power
Ground
Ground
Ground
Ground
Ground
Miscellaneous
analog
J16
J17
J18
K1
K2
K3
AVDD
AGND
AGND
P4
P5
LRCLK/DSD2B/DST_FF
Power
Ground
Ground
Digital video output
Digital video output
Digital output
K4
SCLK/DST_CLK
Digital output
K7
K8
K9
K10
K11
K12
K15
K16
K17
K18
L1
L2
L3
DVDD
DVDD
DGND
DGND
AGND
AVDD
AVDD
AVDD
AIN11
AIN12
P6
P7
I2S3/DSD2A/HBR3
Power
Power
Ground
Ground
Ground
Power
Power
Power
Analog video input
Analog video input
Digital video output
Digital video output
Digital output
Digital Supply Voltage (1.8 V ).
Digital Supply Voltage (1.8 V ).
Ground.
Ground.
Ground.
Analog Supply Voltage (1.8 V ).
Analog Supply Voltage (1.8 V ).
Analog Supply Voltage (1.8 V ).
Analog Video Input Channel.
Analog Video Input Channel.
Video Pixel Output Port.
Video Pixel Output Port.
Multipurpose Pin. I2 S Audio (Channel 7 and Channel 8).
Fifth DSD Data Channel.
Fourth Block of HBR Stream.
L4
I2S2/DSD1B/HBR2
Digital output
L7
L8
L9
L10
DVDD
DVDD
DGND
DGND
Power
Power
Ground
Ground
Multipurpose Pin. I2 S Audio (Channel 5 and Channel 6).
Fourth DSD Data Channel.
Third Block of HBR Stream.
Digital Supply Voltage (1.8 V ).
Digital Supply Voltage (1.8 V ).
Ground.
Ground.
Rev. D | Page 13 of 20
ADV7604
Data Sheet
Pin No.
L11
L12
L15
Mnemonic
AGND
AVDD
TRI8/VS_IN2
Type
Ground
Power
Analog input
L16
TRI7/HS_IN2
Analog input
L17
SYNC4
Analog input
L18
M1
M2
M3
M4
M7
M8
M9
M10
M11
M12
M15
AIN10
P8
DGND
DGND
DGND
DVDD
DVDD
DGND
DGND
AGND
AVDD
TRI5
Analog video input
Digital video output
Ground
Ground
Ground
Power
Power
Ground
Ground
Ground
Power
Analog input
M16
TRI6
Analog input
M17
M18
N1
N2
N3
N4
N15
AGND
AGND
P9
DVDDIO
DVDDIO
DVDDIO
TRI3
Ground
Ground
Digital video output
Power
Power
Power
Analog input
N16
TRI4
Analog input
N17
N18
P1
P2
P3
AIN8
AIN9
P10
P11
I2S0/DSD0B/HBR0
Analog video input
Analog video input
Digital video output
Digital video output
Digital output
P4
I2S1/DSD1A/HBR1
Digital output
P15
P16
P17
AVDD
AVDD
SYNC3
Power
Power
Analog input
P18
AIN7
Analog video input
Description
Ground.
Analog Supply Voltage (1.8 V ).
Dual Purpose Pin. Trilevel/bilevel input on the SCART or D-terminal connector.
Results are available via I2 C. This signal can be buffered and output to the
FB_OUT pin.
VS on Graphics Port 2. The VS input signal is used in CP mode for 5-wire timing
mode. VS_IN2 is a 3.3 V input that is 5 V tolerant.
Dual Purpose Pin. Trilevel/bilevel input on the SCART or D-terminal connector.
Results are available via I2 C. This signal can be buffered and output to the
FB_OUT pin.
HS on Graphics Port 2. The HS input signal is used in CP mode for 5-wire timing
mode. HS_IN2 is a 3.3 V input that is 5 V tolerant.
Synchronization on green or luma input (SOG/SOY). Used in embedded
synchronization mode. User configurable.
Analog Video Input Channel.
Video Pixel Output Port.
Ground.
Ground.
Ground.
Digital Supply Voltage (1.8 V ).
Digital Supply Voltage (1.8 V ).
Ground.
Ground.
Ground.
Analog Supply Voltage (1.8 V ).
Trilevel/bilevel input on the SCART or D-terminal connector. Results are
available via I2 C. This signal can be buffered and output to the FB_OUT pin.
Trilevel/bilevel input on the SCART or D-terminal connector. Results are
available via I2 C. This signal can be buffered and output to the FB_OUT pin.
Ground.
Ground.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V ).
Digital I/O Supply Voltage (3.3 V ).
Digital I/O Supply Voltage (3.3 V ).
Trilevel/bilevel input on the SCART or D-terminal connector. Results are
available via I2 C. This signal can be buffered and output to the FB_OUT pin.
Trilevel/bilevel input on the SCART or D-terminal connector. Results are
available via I2 C. This signal can be buffered and output to the FB_OUT pin.
Analog Video Input Channel.
Analog Video Input Channel.
Video Pixel Output Port.
Video Pixel Output Port.
I2 S Audio (Channel 1 and Channel 2).
Second DSD Data Channel.
First Block of HBR Stream.
I2 S Audio (Channel 3 and Channel 4).
Third DSD Data Channel.
Second Block of HBR Stream.
Analog Supply Voltage (1.8 V ).
Analog Supply Voltage (1.8 V ).
Synchronization on green or luma input (SOG/SOY). Used in embedded
synchronization mode. User configurable.
Analog Video Input Channel.
Rev. D | Page 14 of 20
Data Sheet
ADV7604
Pin No.
R1
R2
R3
R4
R5
Mnemonic
P12
P13
DGND
DGND
SCL
Type
Digital video output
Digital video output
Ground
Ground
Digital I/O
R6
R7
DVDDIO
INT1
Power
Digital output
R8
R9
R10
R11
CLAMPIN
DVDDIO
DGND
FB_OUT
External clamp
Power
Ground
Misc digital
R12
SHARED_EDID
Digital input
R13
HS_IN1
Analog input
R14
R15
R16
AGND
Y_MUX_OUT
TRI2
Ground
Analog output
Analog input
R17
R18
T1
T2
T3
T4
T5
T6
T7
T8
AGND
AGND
P14
P15
DGND
DGND
P25
DVDDIO
SDA
SYNC_OUT/INT2
Ground
Ground
Digital video output
Digital video output
Ground
Ground
Digital video output
Power
Digital I/O
Digital output
T9
T10
T11
T12
T13
DVDDIO
DGND
RESET
AVLINK
VS_IN1
Power
Ground
Digital input
Digital I/O
Analog input
T14
T15
AGND
TRI1
Ground
Analog input
T16
SYNC2
Analog input
T17
T18
U1
U2
U3
U4
U5
U6
AIN5
AIN6
P16
P17
P19
P21
P23
DGND
Analog video input
Analog video input
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Ground
Description
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Ground.
I2 C Port Serial Clock Input. Maximum clock rate of 400 kHz. SCL is the clock line
for the control port.
Digital I/O Supply Voltage (3.3 V ).
Interrupt Pin 1. This pin can be active low or active high. When status bits change,
this pin is triggered. The events that trigger an interrupt are under user control.
External Clamp Signal. This is an optional mode of operation for the ADV7604.
Digital I/O Supply Voltage (3.3 V ).
Ground.
FB Output. This is the muxed fast blank output from TRI1 to TRI8
(programmable).
EDID Flag. When high, all four HDMI ports share common EDID. When low, Port D
does not share common EDID; Port D operates with a separate EDID.
HS on Graphics Port 1. HS input signal is used in CP mode for 5-wire timing
mode. HS_IN1 is a 3.3 V input that is 5 V tolerant.
Ground.
Buffered Output of the Y Channel.
Trilevel/bilevel input on the SCART or D-terminal connector. Results are
available via I2 C. This signal can be buffered and output to the FB_OUT pin.
Ground.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Ground.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V ).
I2 C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
Dual Purpose Pin. Sliced Synchronization Output For the CP Core.
Interrupt Pin 2. This pin can be active low or active high. When status bits change,
this pin is triggered. The events that trigger an interrupt are under user control.
Digital I/O Supply Voltage (3.3 V ).
Ground.
Chip Reset. Active low. Minimum low time for a reset to take place is 5 ms.
Digital SCART Control Channel.
VS on Graphics Port 1. The VS input signal is used in CP mode for 5-wire timing
mode. VS_IN1 is a 3.3 V input that is 5 V tolerant.
Ground.
Trilevel/bilevel input on the SCART or D-terminal connector. Results are
available via I2 C. This signal can be buffered and output to the FB_OUT pin.
Synchronization on green or luma input (SOG/SOY). Used in embedded
synchronization mode. User configurable.
Analog Video Input Channel.
Analog Video Input Channel.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Rev. D | Page 15 of 20
ADV7604
Data Sheet
Pin No.
U7
U8
Mnemonic
P26
DCLKIN
U9
U10
U11
U12
U13
U14
U15
P28
DGND
P31
P33
P35
AGND
SYNC1
Type
Digital video output
External clock and
clamp
Digital video output
Ground
Digital video output
Digital video output
Digital video output
Ground
Analog input
U16
U17
U18
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
AVDD
AVDD
AIN4
DGND
P18
P20
P22
P24
DGND
P27
LLC
P29
DGND
P30
P32
P34
AGND
AIN1
AIN2
AIN3
AGND
Power
Power
Analog video input
Ground
Digital video output
Digital video output
Digital video output
Digital video output
Ground
Digital video output
Digital video output
Digital video output
Ground
Digital video output
Digital video output
Digital video output
Ground
Analog video input
Analog video input
Analog video input
Ground
Description
Video Pixel Output Port.
External Clock for ADC Sampling. This is an optional mode of operation for the
ADV7604.
Video Pixel Output Port.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Synchronization on green or luma input (SOG/SOY). Used in embedded
synchronization mode. User configurable.
Analog Supply Voltage (1.8 V ).
Analog Supply Voltage (1.8 V ).
Analog Video Input Channel.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Video Pixel Output Port.
Line Locked Output Clock for the Pixel data. Range is 13.5 MHz to 170 MHz.
Video Pixel Output Port.
Ground.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Ground.
Analog Video Input Channel.
Analog Video Input Channel.
Analog Video Input Channel.
Ground.
Rev. D | Page 16 of 20
Data Sheet
ADV7604
THEORY OF OPERATION
ANALOG FRONT END
The ADV7604 analog front end comprises three 170 MHz, 12-bit
ADCs that digitize the analog video signal before applying it to
the CP, enabling true 12-bit video decoding. The analog front
end uses differential channels to each ADC to ensure high
performance in a mixed-signal application.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7604 without
the requirement of an external mux.
Three voltage clamp control loops ensure that any dc offsets are
removed from the video signal. The voltage clamps are positioned
in front of each ADC to ensure that the video signal remains within
the range of the converter. Fine clamping of the video signals is
performed downstream by digital fine clamping in the CP.
For component 525i, 625i, 525p, and 625p sources, 2× oversampling is performed. All other video standards are 1×
oversampled. Oversampling the video signals reduces the
cost and complexity of external antialiasing filters with the
benefit of an increased signal-to-noise ratio (SNR).
HDMI RECEIVER
The HDMI receiver on the ADV7604 incorporates active
equalization of the HDMI data signals. This equalization
compensates for the high frequency losses inherent in HDMI and
DVI cabling, especially at longer lengths and higher frequencies.
The equalization is programmable. It is capable of equalizing
for cable lengths up to 30 meters to achieve robust receiver
performance at even the highest HDMI data rates. The HDMI
receiver supports all HDTV formats up to 1080p and all display
resolutions up to UXGA (1600 × 1200 at 60 Hz). The receiver
contains a programmable data island packet interrupt generator.
With the inclusion of HDCP, displays can receive encrypted video
content. The HDMI interface of the ADV7604 allows for authentication of a video receiver, decryption of encoded data at the
receiver, and renewability of that authentication during transmission as specified by the HDCP 1.3 protocol.
The HDMI receiver offers advanced audio functionality. It supports
multichannel I2S audio for up to eight channels. It also supports
a 6-DSD channel interface with each channel carrying an oversampled 1-bit representation of the audio signal as delivered on
a super audio CD (SACD). It incorporates a DST interface that
outputs audio data decoded from DST audio packets. The
ADV7604 can also receive HBR audio packet streams and
outputs them through the HBR interface in an SPDIF format
conforming to the IEC60958 standard. It supports multichannel
I2S audio for up to eight channels. The receiver also contains an
audio mute controller that can detect a variety of conditions
that may result in audible extraneous noise in the audio output.
On detection of these conditions, the audio data can be ramped
to prevent audio clicks or pops.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many
other standards.
The CP section of the ADV7604 contains an AGC block. In
cases where no embedded synchronization is present, the
video gain can be set manually. The AGC section is followed
by a digital clamp circuit that ensures that the video signal is
clamped to the correct blanking level. Automatic adjustments
within the CP include gain (contrast) and offset (brightness);
manual adjustment controls are also supported.
A fully programmable any-to-any 3 × 3 color space conversion
(CSC) matrix is placed between the analog front end and the
CP section. This enables YPrPb-to-RGB and RGB-to-YCrCb
conversions. Many other standards of color space can be
implemented using the color space converter.
The CP section contains circuitry to enable the detection of
Macrovision® encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of CGMS data is performed by the CP section
of the ADV7604 for interlaced, progressive, and high definition
scanning rates. The data extracted can be read back over the I2C
interface.
CP PIXEL DATA OUTPUT MODES
The output section of the CP is highly flexible. It can be
configured in an SDR mode with one data packet per clock
cycle or in a DDR mode where data is presented on the rising
and falling edge of the clock. In SDR mode, a 16-/20-/24-bit
4:2:2 or 24-/30-/36-bit 4:4:4 output is possible. In these modes,
the HS, VS/FIELD, and DE/FIELD (where applicable) timing
reference signals are provided. In DDR mode, the ADV7604
can be configured in an 8-/10-/12-bit 4:2:2 YCrCb or 12-bit 4:4:4
RGB/YCrCb pixel output interface with corresponding timing
signals.
Rev. D | Page 17 of 20
ADV7604
Data Sheet
RGB GRAPHICS PROCESSING
The ADV7604 provides automatic detection of synchronization
source and polarity by the SSPD block, standard identification
that is enabled by the STDI blocks, optimum pixel sample through
a 32-phase DLL, and arbitrary pixel sampling for nonstandard
video sources. A data enable (DE) output signal is supplied for
direct connection to the HDMI/DVI transmitter IC.
The following additional graphics functions are provided:
•
•
•
•
Automatic or manual clamp and gain controls for
graphics modes
Contrast and brightness controls
A 170 MSPS conversion rate that supports RGB input
resolutions up to 1600 × 1200 at 60 Hz (UXGA)
Color space conversion of RGB to YCrCb and decimation
to a 4:2:2 format for video-centric back end IC interfacing
ENHANCED STANDARD DEFINITION PROCESSOR
The ESDP is designed to provide robust synchronization
separation capability for component video input modes that are
likely to have an unstable time base. These are component signals
that have originated from CVBS signals such as noisy/weak RF
signals or VCR signals with head switches. The ESDP is available
for SD (480i, 576i) and ED (480p, 576p) component video input
modes with embedded synchronization because these are most
likely to suffer from timing impairments.
The ESDP contains circuitry for identifying characteristics of
the input signal, and these are then used within the device to
automatically configure it optimally for different inputs. It uses
digitally controlled analog clamping to maximize the range of
the video signal within the ADC. This effectively compensates
for the poor signal quality that may be present on the input.
I2C INTERFACE
The ADV7604 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. The
ADV7604 is controlled by an external I2C master device,
such as a microcontroller.
OTHER FEATURES
In addition to HS, VS, and FIELD output signals with programmable position, polarity, and width, the ADV7604 provides the
following:
•
•
•
•
Programmable interrupt request output pins: INT1 and INT2
Low power consumption: 1.8 V digital core, 1.8 V analog
and 3.3 V digital input/output, low power power-down
mode, and green PC mode
Temperature range: −40°C to +70°C
15 mm × 15 mm, RoHS-compliant BGA package
For more detailed product information about the ADV7604,
contact a local Analog Devices, Inc., sales office.
Rev. D | Page 18 of 20
Data Sheet
ADV7604
OUTLINE DIMENSIONS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
13.60
BSC SQ
0.80
BSC
BOTTOM VIEW
TOP VIEW
1.50
1.36
1.21
A1 BALL
CORNER
4 2
18 16 14 12 10 8 6
7 5 3
1
17 15 13 11 9
DETAIL A
DETAIL A
0.35 NOM
0.30 MIN
SEATING
PLANE
0.50
0.45
0.40
BALL DIAMETER
1.11
1.01
0.91
COPLANARITY
0.12
COMPLIANT TO JEDEC STANDARDS MO-275-KKAA-1.
11-22-2011-A
A1 BALL
CORNER
15.10
15.00 SQ
14.90
Figure 6. 260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-260-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2, 3
ADV7604BBCZ-5
ADV7604BBCZ-5P
EVAL-ADV7604EB1Z
EVAL-ADV7604EB2Z
Temperature Range
−40°C to +70°C
−40°C to +70°C
Package Description
260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
ADV7604BBCZ-5 Front End Evaluation Board
ADV7604BBCZ-5P Front End Evaluation Board
Package Option
BC-260-1
BC-260-1
Z = RoHS Compliant Part.
The ADV7604BBCZ-5 is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection LLC for licensing
requirements) to purchase any components with internal HDCP keys.
3 The ADV7604BBCZ-5P is not programmed with internal HDCP keys for professional applications. Customers are not required to have HDCP adopter status.
1
2
Rev. D | Page 19 of 20
ADV7604
Data Sheet
NOTES
I 2 C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and
other countries.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07971-0-9/13(D)
Rev. D | Page 20 of 20
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