ADW70015Z-0RL

Isolated Sigma-Delta Modulator AD7401A Data Sheet FEATURES GENERAL DESCRIPTION 20 MHz maximum external clock rate Second-order modulator 16 bits, no missing codes ±2 LSB INL typical at 16 bits 1 µV/°C typical offset drift On-board digital isolator On-board reference ±250 mV analog input range Low power operation: 17 mA typical at 5.5 V −40°C to +125°C operating range 16-lead SOIC package Internal clock version: AD7400A Safety and regulatory approvals UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 891 V peak Qualified for Automotive Applications The AD7401A1 is a second-order, sigma-delta (Σ-Δ) modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on the Analog Devices, Inc., iCoupler® technology. The AD7401A operates from a 5 V power supply and accepts a pseudo-differential input signal of ±250 mV (±320 mV full scale). The analog input is continuously sampled by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of up to 20 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3.3 V supply (VDD2). The serial interface is digitally isolated. High speed CMOS, combined with Analog Devices, Inc., iCoupler® technology , means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The device contains an on-chip reference. The AD7401A is offered in a 16-lead SOIC and has an operating temperature range of −40°C to +125°C. APPLICATIONS AC motor controls Shunt current monitoring Data acquisition systems Analog-to-digital and opto-isolator replacements FUNCTIONAL BLOCK DIAGRAM VDD2 VDD1 AD7401A VIN– T/H Σ-Δ ADC UPDATE ENCODE BUF REF WATCHDOG CONTROL LOGIC WATCHDOG DECODE GND1 DECODE MDAT UPDATE MCLKIN ENCODE GND2 07332-001 VIN+ Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7401A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Circuit Information .................................................................... 14 General Description ......................................................................... 1 Analog Input ............................................................................... 14 Functional Block Diagram .............................................................. 1 Differential Inputs ...................................................................... 15 Revision History ............................................................................... 2 Current Sensing Applications ................................................... 15 Specifications..................................................................................... 3 Voltage Sensing Applications .................................................... 15 Timing Specifications .................................................................. 5 Digital Filter ................................................................................ 16 Insulation and Safety-Related Specifications ............................ 6 Applications Information .............................................................. 18 Regulatory Information ............................................................... 6 Grounding and Layout .............................................................. 18 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics .............................................................................. 7 Evaluating the AD7401A Performance ................................... 18 Absolute Maximum Ratings ............................................................ 8 Outline Dimensions ....................................................................... 19 ESD Caution .................................................................................. 8 Ordering Guide .......................................................................... 19 Pin Configuration and Function Descriptions ............................. 9 Automotive Product................................................................... 19 Insulation Lifetime ..................................................................... 18 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 13 REVISION HISTORY 1/2018—Rev. C to Rev. D Changes to Features and General Description ............................. 1 Change to Power Dissipation Parameter, Table 1......................... 4 Changes to Table 3 and Table 4 ....................................................... 6 Changes to Absolute Maximum Rating Section........................... 8 Changes to Table 8 ............................................................................ 9 Changes to Terminology Section.................................................. 13 Changes to Ordering Guide .......................................................... 19 Added Automotive Product Section ............................................ 19 1/2011—Rev. 0 to Rev. A Change to Features, UL Recognition Value ...................................1 Change to Table 3, Input-to-Output Momentary Withstand Voltage Value ..................................................................................................6 Changes to Table 4, Isolation Voltage Value, and Endnote 1.......6 7/2008—Revision 0: Initial Version 7/2011—Rev. B to Rev. C Changes to Minimum External Air Gap (Clearance) Parameter, Table 3 and Minimum External Tracking (Creepage) Parameter, Table 3 ................................................................................................ 6 Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7 Description, Table 8.......................................................................... 9 3/2011—Rev. A to Rev. B Change to General Description Section ........................................ 1 Changes to Table 1 ............................................................................ 3 Rev. D | Page 2 of 20 Data Sheet AD7401A SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = −40°C to +125°C, fMCLKIN = 16 MHz maximum, 1 tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity (INL) 3 Min Y Version1, 2 Typ Max 16 ±1.5 ±2 ±1.5 ±2 ±7 ±13 ±11 ±46 ±0.9 ±.025 1 120 0.07 ±1 23 110 ±0.5 3.5 Differential Nonlinearity (DNL)3 Offset Error3 Offset Drift vs. Temperature3 Offset Drift vs. VDD13 Gain Error3 3 Gain Error Drift vs. Temperature Gain Error Drift vs. VDD13 ANALOG INPUT Input Voltage Range Dynamic Input Current DC Leakage Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-(Noise + Distortion) Ratio (SINAD)3 Signal-to-Noise Ratio (SNR)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Effective Number of Bits (ENOB)3 Isolation Transient Immunity3 LOGIC INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN Floating State Leakage Current Input Capacitance, CIN 4 ±200 ±13 ±10 0.08 ±0.01 10 ±1.5 ±250 ±18 ±15 ±0.6 Unit Test Conditions/Comments Bits LSB LSB LSB LSB LSB Filter output truncated to 16 bits VIN+ = ±200 mV, TA = −40°C to +85°C, fMCLKIN = 20 MHz max1 VIN+ = ±250 mV, TA = −40°C to +85°C, fMCLKIN = 20 MHz max1 VIN+ = ±200 mV, TA = −40°C to +125°C, fMCLKIN = 20 MHz max1 VIN+ = ±250 mV, TA = −40°C to +125°C, fMCLKIN = 20 MHz max1 Guaranteed no missed codes to 16 bits, fMCLKIN = 20 MHz max,1 VIN+ = −250 mV to +250 mV fMCLKIN = 20 MHz max,1 VIN+ = −250 mV to +250 mV mV µV/°C µV/V mV mV µV/°C µV/V mV µA µA µA µA pF 76 82 dB 71 82 dB 72 82 dB 82 dB 81 83 dB 80 82 dB 12.3 25 −90 −92 13.3 30 dB dB Bits kV/µs 0.8 × VDD2 0.2 × VDD2 ±0.5 1 10 V V µA µA pF Rev. D | Page 3 of 20 fMCLKIN = 20 MHz max,1 VIN+ = −250 mV to +250 mV For specified performance; full range ±320 mV VIN+ = 500 mV, VIN− = 0 V, fMCLKIN = 20 MHz max1 VIN+ = 400 mV, VIN− = 0 V, fMCLKIN = 20 MHz max1 VIN+ = 0 V, VIN− = 0 V, fMCLKIN = 20 MHz max1 VIN+ = 5 kHz VIN+ = ±200 mV, TA = −40°C to +85°C, fMCLKIN = 5 MHz to 20 MHz1 VIN+ = ±250 mV, TA = −40°C to +85°C, fMCLKIN = 5 MHz to 20 MHz1 VIN+ = ±200 mV, TA = −40°C to +125°C, fMCLKIN = 5 MHz to 20 MHz1 VIN+ = ±250 mV, TA = −40°C to +125°C, fMCLKIN = 5 MHz to 20 MHz1 VIN+ = ±250 mV, TA = −40°C to +125°C, fMCLKIN = 5 MHz to 20 MHz1 VIN+ = ±200 mV, TA = −40°C to +125°C, fMCLKIN = 5 MHz to 20 MHz1 fMCLKIN = 20 MHz max1, VIN+ = −250 mV to +250 mV AD7401A Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL POWER REQUIREMENTS VDD1 VDD2 IDD1 5 IDD2 6 POWER DISSIPATION (SEE Figure 17) Data Sheet Min Y Version1, 2 Typ Max VDD2 − 0.1 0.4 4.5 3 10 7 3 93.5 5.5 5.5 12 9 4 Unit Test Conditions/Comments V V IO = −200 µA IO = +200 µA V V mA mA mA mW VDD1 = 5.5 V VDD2 = 5.5 V VDD2 = 3.3 V VDD1 = VDD2 = 5.5 V For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5%, and TA = −40°C to +85°C. All voltages are relative to their respective ground. See the Terminology section. 4 Sample tested during initial release to ensure compliance. 5 See Figure 15. 6 See Figure 17. 1 2 3 Rev. D | Page 4 of 20 Data Sheet AD7401A TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Table 2. Parameter 1 fMCLKIN 2, 3 t1 4 t2 4 t3 t4 Limit at TMIN, TMAX 20 5 25 15 0.4 × tMCLKIN 0.4 × tMCLKIN Unit MHz max MHz min ns max ns min ns min ns min Description Master clock input frequency Master clock input frequency Data access time after MCLKIN rising edge Data hold time after MCLKIN rising edge Master clock low time Master clock high time Sample tested during initial release to ensure compliance. Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN ≤ 16 MHz and 48/52 to 52/48 for 16 MHz < fMCLKIN < 20 MHz. 3 VDD1 = VDD2 = 5 V ± 5% for fMCLKIN > 16 MHz to 20 MHz. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 1 2 200µA 1.6V CL 25pF 200µA 07332-002 TO OUTPUT PIN IOL IOH Figure 2. Load Circuit for Digital Output Timing Specifications t4 t1 t2 MDAT Figure 3. Data Timing Rev. D | Page 5 of 20 t3 07332-003 MCLKIN AD7401A Data Sheet INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 3. Parameter Input-to-Output Momentary Withstand Voltage Minimum External Air Gap (Clearance) Symbol VISO L(I01) Value 5000 min 7.8 min 1,2 Unit V mm Minimum External Tracking (Creepage) L(I02) 7.8 min1,2 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min > 400 II mm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 3 Material Group (DIN VDE 0110, 1/89, Table I)3 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m. Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. 3 CSA CTI rating is >400 and a Material Group II isolation group. 1 2 REGULATORY INFORMATION Table 4. UL 1 Recognized Under 1577 Component Recognition Program1 5000 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA60950-1-07 and IEC 60950-1, 780 Vrms maximum working voltage. Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 390 V rms maximum working voltage File 205078 VDE 2 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 891 V peak File 2471900-4880-0001 In accordance with UL 1577, each AD7401A is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA). In accordance with DIN V VDE V 0884-10, each AD7401A is proof tested by applying an insulation test voltage ≥1671V peak for 1 sec (partial discharge detection limit = 5 pC). Rev. D | Page 6 of 20 Data Sheet AD7401A DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 5. Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 450 V rms For Rated Mains Voltage ≤ 600 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, TABLE 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 4) Case Temperature Side 1 Current Side 2 Current INSULATION RESISTANCE AT TS, VIO = 500 V 250 SIDE #2 200 150 SIDE #1 100 50 50 100 150 CASE TEMPERATURE (°C) 200 07332-004 SAFETY-LIMITING CURRENT (mA) 300 0 Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. D | Page 7 of 20 Characteristic Unit VIORM I to IV I to II I to II 40/105/21 2 891 V peak 1671 V peak 1426 V peak 1069 V peak VTR 6000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR VPR 350 0 Symbol AD7401A Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective grounds. Table 6. Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Digital Input Voltage to GND2 Output Voltage to GND2 Input Current to Any Pin Except Supplies 1 Operating Temperature Range Storage Temperature Range Junction Temperature SOIC Package θJA Thermal Impedance 2 θJC Thermal Impedance2 Resistance (Input to Output), RI-O Capacitance (Input to Output), CI-O 3 Pb-Free Temperature, Soldering Reflow ESD 1 2 3 Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to VDD1 + 0.3 V −0.3 V to VDD1 + 0.5 V −0.3 V to VDD2 + 0.3 V ±10 mA −40°C to +125°C −65°C to +150°C 150°C 89.2°C/W 55.6°C/W 1012 Ω 1.7 pF typ 260°C 1.5 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 7. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Max 565 Unit V peak 891 V peak DC Voltage 891 V 1 Constraint 50-year minimum lifetime Maximum CSA/VDE approved working voltage Maximum CSA/VDE approved working voltage Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. ESD CAUTION Transient currents of up to 100 mA do not cause SCR to latch up. EDEC 2S2P standard board. f = 1 MHz. Rev. D | Page 8 of 20 Data Sheet AD7401A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 16 GND2 VIN+ 2 15 NC VIN– 3 14 VDD2 NC 4 NC 5 AD7401A MCLKIN TOP VIEW (Not to Scale) 12 NC NC 6 11 MDAT VDD1 /NC 7 10 NC GND1 8 9 GND2 NC = NO CONNECT 07332-005 13 Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 to 6, 10, 12, 15 7 Mnemonic VDD1 VIN+ VIN− NC Description Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7401A and is relative to GND1. Positive Analog Input. Specified range of ±250 mV. Negative Analog Input. Normally connected to GND1. No Connect. VDD1/NC 8 9, 16 11 GND1 GND2 MDAT 13 14 MCLKIN VDD2 Supply Voltage. Supply voltage (VDD1) 4.5 V to 5.5 V. VDD1 is the supply voltage for the isolated side of the AD7401A and it is relative to GND1. No Connect (NC). If desired, Pin 7 may be allowed to float. Do not be tie Pin 7 to ground. The AD7401A will operate normally provided that the supply voltage is applied to Pin 1. Ground 1. This is the ground reference point for all circuitry on the isolated side. Ground 2. This is the ground reference point for all circuitry on the nonisolated side. Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge. Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN. Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Rev. D | Page 9 of 20 AD7401A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, using 25 kHz brick-wall filter, unless otherwise noted. 100 –90 90 VDD1 = VDD2 = 5V –85 80 MCLKIN = 10MHz MCLKIN = 16MHz –80 60 50 MCLKIN = 5MHz SINAD (dB) PSRR (dB) 70 MCLKIN = 10MHz 40 MCLKIN = 16MHz –75 –70 –65 30 –60 600 700 800 900 1000 SUPPLY RIPPLE FREQUENCY (kHz) –50 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32 0.33 ± INPUT AMPLITUDE (V) Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling –90 Figure 9. SINAD vs. VIN 0.4 =V =5V VDD1 V= V DD2 = 5V DD1 DD2 0.3 –85 MCLKIN = 16MHz 0.2 DNL ERROR (LSB) –75 MCLKIN = 10MHz –70 –65 MCLKIN = 5MHz –60 0.1 0 –0.1 –0.2 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k INPUT FREQUENCY (Hz) 07332-007 0 –0.4 V + = –200mV TO +200mV IN VIN– = 0V –0.5 10k 20k 30k 0 –20 60k 0.8 VIN+ = –200mV TO +200mV VIN– = 0V 0.6 INL ERROR (LSB) –40 –60 –80 –100 –120 –140 0.4 0.2 0 –0.2 –160 –180 0 5 10 15 20 FREQUENCY (kHz) 25 30 07332-008 (dB) 60k Figure 10. Typical DNL (±200 mV Range) 4096 POINT FFT fIN = 5kHz SINAD = 81.984dB THD = –96.311dB DECIMATION BY 256 0 50k CODE Figure 7. SINAD vs. Analog Input Frequency 20 40k 07332-010 –0.3 –55 07332-011 SINAD (dB) –80 –50 07332-009 –55 07332-006 20 200mV p-p SINE WAVE ON V DD1 NO DECOUPLING 10 V = V = 5V DD1 DD2 1MHz CUTOFF FILTER 0 100 200 300 400 500 0 Figure 8. Typical FFT (±200 mV Range) –0.4 0 10k 20k 30k 40k 50k CODE Figure 11. Typical INL (±200 mV Range) Rev. D | Page 10 of 20 Data Sheet AD7401A 250 150 0.0100 0.0095 IDD1 (A) 0 –50 –100 –150 –200 VDD1 = VDD2 = 5.25V MCLKIN = 16MHz 5 15 25 35 45 55 65 75 85 95 105 0.0085 0.0080 0.0065 MCLKIN = 16MHz TA = +105°C MCLKIN = 10MHz TA = +105°C MCLKIN = 10MHz TA = +85°C MCLKIN = 5MHz TA = +85°C MCLKIN = 5MHz TA = –40°C MCLKIN = 5MHz TA = +105°C 0.0060 –0.33 –0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28 0.33 VIN DC INPUT VOLTAGE (V) Figure 15. IDD1 vs. VIN at Various Temperatures Figure 12. Offset Drift vs. Temperature for Various Supply Voltages 0.0070 200.4 VDD1 = VDD2 = 4.5V MCLKIN = 16MHz VDD1 = VDD2 = 4.5V MCLKIN = 10MHz 0.0065 200.3 VDD1 = VDD2 = 4.5V MCLKIN = 5MHz VDD1 = VDD2 = 5V MCLKIN = 5MHz 0.0060 200.2 VDD1 = VDD2 = 5V MCLKIN = 16MHz VDD1 = VDD2 = 5.25V MCLKIN = 10MHz 0.0055 200.1 VDD1 = VDD2 = 5.25V MCLKIN = 16MHz VDD1 = VDD2 = 5.25V MCLKIN = 5MHz 0.0050 200.0 VDD1 = VDD2 = 5V MCLKIN = 10MHz IDD2 (A) GAIN (mV) MCLKIN = 16MHz TA = +85°C MCLKIN = 10MHz TA = –40°C 0.0070 VDD1 = VDD2 = 5.25V MCLKIN = 5MHz TEMPERATURE (°C) 200.5 MCLKIN = 16MHz TA = –40°C 0.0075 VDD1 = VDD2 = 5.25V MCLKIN = 10MHz VDD1 = VDD2 = 5V MCLKIN = 10MHz –250 –45 –35 –25 –15 –5 VDD1 = VDD2 = 5V 0.0090 50 07332-012 OFFSET (µV) 100 VDD1 = VDD2 = 4.5V MCLKIN = 10MHz VDD1 = VDD2 = 5V MCLKIN = 5MHz 07332-015 200 0.0105 VDD1 = VDD2 = 4.5V MCLKIN = 16MHz VDD1 = VDD2 = 4.5V MCLKIN = 5MHz VDD1 = VDD2 = 5V MCLKIN = 16MHz VDD1 = VDD2 = 5V TA = 25°C MCLKIN = 16MHz MCLKIN = 10MHz 0.0045 199.9 0.0040 199.8 0.0035 199.7 0.0030 199.6 0.0025 MCLKIN = 5MHz TEMPERATURE (°C) 0.0020 –0.225 –0.125 –0.025 0.075 0.175 0.275 –0.325 –0.275 –0.175 –0.075 0.025 0.125 0.225 0.325 VIN DC INPUT VOLTAGE (V) Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages 0.0105 Figure 16. IDD2 vs. VIN DC Input Voltage 0.0070 VDD1 = VDD2 = 5V TA = 25°C 0.0100 VDD1 = VDD2 = 5V 0.0065 0.0060 0.0095 MCLKIN = 16MHz 0.0055 IDD2 (A) 0.0050 MCLKIN = 10MHz MCLKIN = 5MHz MCLKIN = 10MHz TA = –40°C 0.0025 0.0065 VIN DC INPUT VOLTAGE (V) MCLKIN = 16MHz TA = +85°C MCLKIN = 10MHz TA = +105°C MCLKIN = 5MHz TA = –40°C MCLKIN = 10MHz TA = +85°C 0.0030 0.0070 –0.33 –0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28 0.33 MCLKIN = 16MHz TA = +105°C 0.0045 0.0035 0.0075 MCLKIN = 16MHz TA = –40°C 0.0040 0.0080 07332-014 IDD1 (A) 0.0090 0.0085 07332-016 15 25 35 45 55 65 75 85 95 105 0.0020 MCLKIN = 5MHz TA = +85°C MCLKIN = 5MHz TA = +105°C –0.225 –0.125 –0.025 0.075 0.175 0.275 –0.325 –0.275 –0.175 –0.075 0.025 0.125 0.225 0.325 VIN DC INPUT VOLTAGE (V) Figure 17. IDD2 vs. VIN at Various Temperatures Figure 14. IDD1 vs. VIN DC Input Voltage Rev. D | Page 11 of 20 07332-017 5 07332-013 199.5 –45 –35 –25 –15 –5 AD7401A 8 Data Sheet 1.0 VDD1 = VDD2 = 4.5V TO 5.25V VDD1 = VDD2 = 5V 50kHz BRICK-WALL FILTER MCLKIN = 16MHz 6 0.8 MCLKIN = 10MHz 4 NOISE (mV) IIN (µA) 2 MCLKIN = 5MHz 0 –2 0.6 0.4 MCLKIN = 5MHz –4 0.2 =V =5V VDD1 = VVDD2 = 5V DD1 DD2 –20 –40 MCLKIN = 5MHz –60 MCLKIN = 10MHz –80 –120 0.1 1 10 100 RIPPLE FREQUENCY (kHz) 1000 07332-019 MCLKIN = 16MHz –100 Figure 19. CMRR vs. Common-Mode Ripple Frequency Rev. D | Page 12 of 20 0.30 07332-020 0.25 0.20 0.15 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 VIN DC INPUT (V) Figure 20. RMS Noise Voltage vs. VIN DC Input Figure 18. IIN vs. VIN− DC Input 0 –0.30 0.35 VIN– DC INPUT (V) 0 07332-018 0.30 0.25 0.20 0.15 0.10 0 0.05 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 –0.35 –8 CMRR (dB) MCLKIN = 16MHz MCLKIN = 10MHz 0.10 –6 Data Sheet AD7401A TERMINOLOGY Effective Number of Bits (ENOB) ENOB is defined by Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. ENOB = (SINAD − 1.76)/6.02 bits Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, −250 mV (VIN+ − VIN−), Code 7169 for the 16-bit level, and specified positive full scale, +250 mV (VIN+ − VIN−), Code 58366 for the 16-bit level. Offset Error Offset error is the deviation of the midscale code (32768 for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). Offset Error Drift vs. Temperature Offset error drift is a measure of the change in offset error with a change in temperature. It is expressed in μV/°C. Offset Error Drift vs. VDD1 Offset error drift is a measure of the change in offset error with a change in supply voltage. It is expressed in μV/V. Gain Error The gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (58366 for the 16-bit level) from the ideal VIN+ − VIN− (+250 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (7169 for the 16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the offset error is adjusted out. Gain error includes reference error. Gain Error Drift vs. Temperature Gain error drift is a measure of the change in gain error with a change in temperature. It is expressed in μV/°C. Gain Error Drift vs. VDD1 Gain error drift is a measure of the change in gain error with a change in supply voltage. It is expressed in μV/V. Signal-to-(Noise and Distortion) Ratio (SINAD) SINAD is the measured ratio of signal-to-noise and distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise and distortion) ratio for an ideal N-bit converter with a sine wave input is given by Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7401A, it is defined as THD(dB) = 20 log V2 2 + V32 + V4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±250 mV frequency, f, to the power of a 250 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency, fS, as CMRR (dB) = 10 .log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter’s linearity. PSRR is the maximum change in the specified full-scale (±250 mV) transition point due to a change in power supply voltage from the nominal value (see Figure 6). Isolation Transient Immunity The isolation transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. The AD7401A was tested using a transient pulse frequency of 100 kHz. Signal-to-(Noise and Distortion) = (6.02N + 1.76) dB Therefore, for a 12-bit converter, this is 74 dB. Rev. D | Page 13 of 20 AD7401A Data Sheet THEORY OF OPERATION CIRCUIT INFORMATION The AD7401A isolated Σ-Δ modulator converts an analog input signal into a high speed (20 MHz maximum), single-bit data stream; the time average single-bit data from the modulators is directly proportional to the input signal. Figure 23 shows a typical application circuit where the AD7401A is used to provide isolation between the analog input, a current sensing resistor, and the digital output, which is then processed by a digital filter to provide an N-bit word. ANALOG INPUT The differential analog input of the AD7401A is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output stream. The sample clock (MCLKIN) provides the clock signal for the conversion process as well as the output data-framing clock. This clock source is external on the AD7401A. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the analog input over time appears at the output of the converter (see Figure 21). A differential input of 320 mV results in a stream of, ideally, all 1s. This is the absolute full-scale range of the AD7401A, and 200 mV is the specified full-scale range, as shown in Table 9. Table 9. Analog Input Range Analog Input Full-Scale Range Positive Full Scale Positive Typical Input Range Positive Specified Input Range Zero Negative Specified Input Range Negative Typical Input Range Negative Full Scale Voltage Input +640 mV +320 mV +250 mV +200 mV 0 mV −200 mV −250 mV −320 mV To reconstruct the original information, this output needs to be digitally filtered and decimated. A sinc3 filter is recommended because this is one order higher than that of the AD7401A modulator. If a 256 decimation rate is used, the resulting 16-bit word rate is 62.5 kHz, assuming a 16 MHz external clock frequency. Figure 22 shows the transfer function of the AD7401A relative to the 16-bit output. MODULATOR OUTPUT 65535 +FS ANALOG INPUT SPECIFIED RANGE ADC CODE Figure 21. Analog Input vs. Modulator Output A differential signal of 0 V results (ideally) in a stream of alternating 1s and 0s at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 200 mV produces a stream of 1s and 0s that are high 81.25% of the time (for a +250 mV input, the output stream is high 89.06% of the time). A differential input of −200 mV produces a stream of 1s and 0s that are high 18.75% of the time (for a −250 mV input, the output stream is high 10.94% of the time). 12288 0 –320mV –200mV +200mV +320mV ANALOG INPUT 07332-022 ANALOG INPUT 07332-021 53248 –FS ANALOG INPUT Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic ISOLATED 5V NONISOLATED 5V/3V VDD1 INPUT CURRENT VIN+ Σ-∆ MOD/ ENCODER VDD2 VDD SINC3 FILTER* DECODER VIN– MDAT MDAT MCLKIN MCLK CS SCLK SDAT RSHUNT DECODER GND1 ENCODER GND2 GND *THIS FILTER IS IMPLEMENTED WITH AN FPGA OR DSP. Figure 23. Typical Application Circuit Rev. D | Page 14 of 20 07332-023 + AD7401A Data Sheet AD7401A DIFFERENTIAL INPUTS CURRENT SENSING APPLICATIONS The analog input to the modulator is a switched capacitor design. The analog signal is converted into charge by highly linear sampling capacitors. A simplified equivalent circuit diagram of the analog input is shown in Figure 24. A signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half MCLKIN cycle and settle to the required accuracy within the next half cycle. The AD7401A is ideally suited for current sensing applications where the voltage across a shunt resistor is monitored. The load current flowing through an external shunt resistor produces a voltage at the input terminals of the AD7401A. The AD7401A provides isolation between the analog input from the current sensing resistor and the digital outputs. By selecting the appropriate shunt resistor value, a variety of current ranges can be monitored. φA VIN– 1kΩ MCLKIN Choosing RSHUNT φB 2pF φA 2pF φB 07332-024 VIN+ 1kΩ φA φB φA φB Figure 24. Analog Input Equivalent Circuit Because the AD7401A samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common-mode noise at each input. The amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7401A. When a capacitive load is switched onto the output of an op amp, the amplitude momentarily drops. The op amp tries to correct the situation and, in the process, hits its slew rate limit. This nonlinear response, which can cause excessive ringing, can lead to distortion. To remedy the situation, a low-pass RC filter can be connected between the amplifier and the input to the AD7401A. The external capacitor at each input aids in supplying the current spikes created during the sampling process, and the resistor isolates the op amp from the transient nature of the load. The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 25. A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. The series resistor again isolates any op amp from the current spikes created during the sampling process. Recommended values for the resistors and capacitor are 22 Ω and 47 pF, respectively. VIN– R R C AD7401A When the peak sense current is known, the voltage range of the AD7401A (±200 mV) is divided by the maximum sense current to yield a suitable shunt value. If the power dissipation in the shunt resistor is too large, the shunt resistor can be reduced and less of the ADC input range is used. Using less of the ADC input range results in performance that is more susceptible to noise and offset errors because offset errors are fixed and are thus more significant when smaller input ranges are used. RSHUNT must be able to dissipate the I2R power losses. If the power dissipation rating of the resistor is exceeded, its value may drift or the resistor may be damaged, resulting in an open circuit. This can result in a differential voltage across the terminals of the AD401A in excess of the absolute maximum ratings. If ISENSE has a large high frequency component, take care to choose a resistor with low inductance. VOLTAGE SENSING APPLICATIONS The AD7401A can also be used for isolated voltage monitoring. For example, in motor control applications, it can be used to sense bus voltage. In applications where the voltage being monitored exceeds the specified analog input range of the AD7401A, a voltage divider network can be used to reduce the voltage to be monitored to the required range. 07332-025 VIN+ The shunt resistor values used in conjunction with the AD7401A are determined by the specific application requirements in terms of voltage, current, and power. Small resistors minimize power dissipation, while low inductance resistors prevent any induced voltage spikes, and good tolerance devices reduce current variations. The final values chosen are a compromise between low power dissipation and good accuracy. Low value resistors have less power dissipated in them, but higher value resistors may be required to utilize the full input range of the ADC, thus achieving maximum SNR performance. Figure 25. Differential Input RC Network Rev. D | Page 15 of 20 AD7401A Data Sheet The overall system resolution and throughput rate is determined by the filter selected and the decimation rate used. The higher the decimation rate, the greater the system accuracy, as illustrated in Figure 26. However, there is a tradeoff between accuracy and throughput rate and, therefore, higher decimation rates result in lower throughput solutions. Note that for a given bandwidth requirement, a higher MCLKIN frequency can allow for higher decimation rates to be used, resulting in higher SNR performance. 90 SINC3 80 70 SINC2 SNR (dB) 60 50 40 SINC1 30 20 0 1 10 100 1k DECIMATION RATE 07332-026 10 Figure 26. SNR vs. Decimation Rate for Different Filter Types A sinc3 filter is recommended for use with the AD7401A. This filter can be implemented on an FPGA or a DSP.  1  Z DR    H (z )  1   1  Z   3 where DR is the decimation rate. The following Verilog code provides an example of a sinc3 filter implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code can possibly be compiled for another FPGA, such as an Altera® device. Note that the data is read on the negative clock edge in this case, although it can be read on the positive edge, if preferred. /*`Data is read on negative clk edge*/ module DEC256SINC24B(mdata1, mclk1, reset, DATA); input mclk1; input reset; input mdata1; filtered*/ /*used to clk filter*/ /*used to reset filter*/ /*ip data to be output [15:0] DATA; /*filtered op*/ integer location; integer info_file; reg [23:0] ip_data1; reg [23:0] acc1; reg [23:0] acc2; reg [23:0] acc3; reg [23:0] acc3_d1; reg [23:0] acc3_d2; reg [23:0] diff1; reg [23:0] diff2; reg [23:0] diff3; reg [23:0] diff1_d; reg [23:0] diff2_d; reg [15:0] DATA; reg [7:0] word_count; reg word_clk; reg init; /*Perform the Sinc ACTION*/ always @ (mdata1) if(mdata1==0) ip_data1