ADXL312

3-Axis, ±1.5 g/±3 g/±6 g/±12 g Digital Accelerometer ADXL312 FEATURES Ultralow power: as low as 57 μA in measurement mode and 0.1 μA in standby mode at VS = 3.3 V (typical) Power consumption scales automatically with bandwidth User-selectable resolution Fixed 10-bit resolution Full resolution, where resolution increases with g range, up to 13-bit resolution at ±12 g (maintaining 2.9 mg/LSB scale factor in all g ranges) Embedded, patent pending FIFO technology minimizes host processor load Built-in motion detection functions for activity/inactivity monitoring Supply and I/O voltage range: 2.0 V to 3.6 V SPI (3- and 4-wire) and I2C digital interfaces Flexible interrupt modes mappable to either interrupt pin Measurement ranges selectable via serial command Bandwidth selectable via serial command Wide temperature range (−40 to +105°C) 10,000 g shock survival Pb free/RoHS compliant Small and thin: 5 mm × 5 mm × 1.45 mm LFCSP package Qualified for automotive applications GENERAL DESCRIPTION The ADXL312 is a small, thin, low power, 3-axis accelerometer with high resolution (13-bit) measurement up to ±12 g. Digital output data is formatted as 16-bit twos complement and is accessible through either a SPI (3- or 4-wire) or I2C digital interface. The ADXL312 is well suited for car alarm or black box applications. It measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion or shock. Its high resolution (2.9 mg/LSB) enables resolution of inclination changes of as little as 0.25°. A built-in FIFO facilitates using oversampling techniques to improve resolution to as little as 0.05° of inclination. Several special sensing functions are provided. Activity and inactivity sensing detects the presence or absence of motion and whether the acceleration on any axis exceeds a user-set level. These functions can be mapped to interrupt output pins. An integrated 32 level FIFO can be used to store data to minimize host processor intervention. Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. The ADXL312 is supplied in a small, thin 5 mm × 5 mm × 1.45 mm, 32-lead, LFCSP package. APPLICATIONS Car alarm Hill start aid (HSA) Electronic parking brake Data recorder (black box) FUNCTIONAL BLOCK DIAGRAM VS VDD I/O ADXL312 POWER MANAGEMENT SENSE ELECTRONICS 3-AXIS SENSOR ADC DIGITAL FILTER CONTROL AND INTERRUPT LOGIC INT1 INT2 32 LEVEL FIFO SDA/SDI/SDIO SERIAL I/O SDO/ALT ADDRESS 08791-001 SCL/SCLK GND CS Figure 1. ADXL312 Simplified Block Diagram Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADXL312 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Absolute Maximum Ratings............................................................ 5  Thermal Resistance ...................................................................... 5  ESD Caution.................................................................................. 5  Pin Configuration and Function Descriptions............................. 6  Typical Performance Characteristics ............................................. 7  Theory of Operation ...................................................................... 10  Power Sequencing ...................................................................... 10  Power Savings ............................................................................. 10  Serial Communications ................................................................. 12  SPI................................................................................................. 12  I C ................................................................................................. 15  2 FIFO ............................................................................................. 18  Self-Test ....................................................................................... 19  Register Map ................................................................................... 20  Register Definitions ................................................................... 21  Applications Information .............................................................. 25  Power Supply Decoupling ......................................................... 25  Mechanical Considerations for Mounting.............................. 25  Threshold .................................................................................... 25  Link Mode ................................................................................... 25  Sleep Mode vs. Low Power Mode............................................. 25  Using Self-Test ............................................................................ 26  Data Formatting of Upper Data Rates..................................... 27  Noise Performance ..................................................................... 28  Axes of Acceleration Sensitivity ............................................... 29  Solder Profile................................................................................... 30  Outline Dimensions ....................................................................... 31  Ordering Guide .......................................................................... 32  Automotive Products ................................................................. 32  Interrupts..................................................................................... 17  REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 32 ADXL312 SPECIFICATIONS TA = −40°C to +105°C, VS = VDD I/O = 3.3 V, acceleration = 0 g, unless otherwise noted. Table 1. Specifications 1 Parameter SENSOR INPUT Measurement Range Nonlinearity Inter-Axis Alignment Error Cross-Axis Sensitivity 2 OUTPUT RESOLUTION All g Ranges ±1.5 g Range ±3 g Range ±6 g Range ±12 g Range SENSITIVITY Scale Factor at XOUT, YOUT, ZOUT Scale Factor at XOUT, YOUT, ZOUT Scale Factor at XOUT, YOUT, ZOUT Scale Factor at XOUT, YOUT, ZOUT Sensitivity at XOUT, YOUT, ZOUT Sensitivity at XOUT, YOUT, ZOUT Sensitivity at XOUT, YOUT, ZOUT Sensitivity at XOUT, YOUT, ZOUT Sensitivity Change Due to Temperature 0 g BIAS LEVEL Initial 0 g Output Initial 0 g Output 0 g Output over Temperature 0 g Offset Tempco 0 g Offset Tempco NOISE PERFORMANCE Noise Density (X-, Y-axes) Noise Density (Z-axis) OUTPUT DATA RATE/BANDWIDTH Measurement Rate 3 SELF-TEST 4 Output Change in X-Axis Output Change in Y-Axis Output Change in Z-Axis POWER SUPPLY Operating Voltage Range (VS) Interface Voltage Range (VDD I/O) Supply Current Standby Mode Leakage Current Turn-On (Wale-Up) Time 5 TEMPERATURE Operating Temperature Range Conditions Each axis User selectable Percentage of full scale Min Typ ±1.5, 3, 6, 12 ±0.5 ±0.1 ±1 10 10 11 12 13 2.6 5.2 10.4 20.9 312 156 78 39 2.9 5.8 11.6 23.2 345 172 86 43 ±0.01 3.2 6.4 12.8 25.5 385 192 96 48 Max Unit g % Degrees % Bits Bits Bits Bits Bits mg/LSB mg/LSB mg/LSB mg/LSB LSB/g LSB/g LSB/g LSB/g %/°C mg mg mg mg/°C mg/°C μg/√Hz μg/√Hz Hz g g g V V μA μA μA ms °C Each axis Default resolution Full resolution enabled Full resolution enabled Full resolution enabled Full resolution enabled Each axis ±1.5 g, 10-bit or full resolution ±3 g, 10-bit resolution ±6 g, 10-bit resolution ±12 g, 10-bit resolution ±1.5 g, 10-bit or full resolution ±3 g, 10-bit resolution ±6 g, 10-bit resolution ±12 g, 10-bit resolution Each axis T = 25°C, XOUT, YOUT T = 25°C, ZOUT −40°C < T < 105°C, XOUT, YOUT, ZOUT XOUT, YOUT ZOUT −150 −250 −250 ±0.8 ±1.5 200 200 340 470 +150 +250 +250 440 595 3200 2.10 −0.20 3.40 3.6 VS 300 110 2 User selectable 6.25 Data rate ≥ 100 Hz, 2.0 ≤ VS ≤ 3.6 0.20 −2.10 0.30 2.0 1.7 100 30 Data rate > 100 Hz Data rate < 10 Hz 170 55 0.1 1.4 −40 +105 Rev. 0 | Page 3 of 32 ADXL312 1 2 All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed. Cross-axis sensitivity is defined as coupling between any two axes. 3 Bandwidth is half the output data rate. 4 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register) minus the output (g) when the SELF_TEST bit = 0 (in the DATA_FORMAT register). Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). 5 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate). Rev. 0 | Page 4 of 32 ADXL312 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VS VDD I/O All Other Pins Output Short-Circuit Duration (Any Pin to Ground) Temperature Range Powered Storage Rating 10,000 g 10,000 g −0.3 V to 3.9 V −0.3 V to 3.9 V −0.3 V to VDD I/O + 0.3 V or 3.9 V, whichever is less Indefinite THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 32-Lead LFCSP Package θJA 27.27 θJC 30 Unit °C/W ESD CAUTION −40°C to +125°C −40°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 32 ADXL312 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 NC VDD I/O NC NC NC NC SCL/SCLK NC GND RESERVED GND GND VS CS RESERVED NC 1 2 3 4 5 6 7 8 ADXL312 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 SDA/SDI/SDIO SDO/ALT ADDRESS RESERVED INT2 INT1 NC NC NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE. NC NC NC NC NC NC NC NC 9 10 11 12 13 14 15 16 Figure 2. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 to19 20 21 22 23 24 25 26 27 to 30 31 32 Mnemonic GND Reserved GND GND VS CS Reserved NC INT1 INT2 Reserved SDO/ALT ADDRESS SDA/SDI/SDIO NC SCL/SCLK NC VDD I/O NC EP Description This pin must be connected to ground. Reserved. This pin must be connected to VS or left open. This pin must be connected to ground. This pin must be connected to ground. Supply Voltage. Chip Select. Reserved. This pin must be left open. No Connect. Do not connect to this pin. Interrupt 1 Output. Interrupt 2 Output. Reserved. This pin must be connected to GND or left open. Serial Data Out, Alternate I2C Address Select. Serial Data (I2C), Serial Data In (SPI 4-Wire), Serial Data In/Out (SPI 3-Wire). No Connect. Do not connect to this pin. Serial Communications Clock. No Connect. Do not connect to this pin. Digital Interface Supply Voltage. No Connect. The exposed pad must be soldered to the ground plane. Rev. 0 | Page 6 of 32 08791-002 ADXL312 TYPICAL PERFORMANCE CHARACTERISTICS N>1000 unless otherwise noted. 40 35 PERCENT OF POPULATION (%) 40 35 PERCENT OF POPULATION (%) 08791-003 30 25 20 15 10 5 0 –150 –120 –90 30 25 20 15 10 5 0 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 ZERO g TEMPERATURE COEFFICIENT (mg/°C) Figure 3. X-Axis Zero-g Bias. 25°C, VS = VDD I/O = 3.3 V 35 30 Figure 6. X-Axis Zero-g Bias Drift, VS = VDD I/O = 3.3 V 40 35 PERCENT OF POPULATION (%) 30 25 20 15 10 5 08791-004 PERCENT OF POPULATION (%) 25 20 15 10 5 0 –150 –120 –90 0 0 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0.5 1.0 1.5 2.0 2.5 ZERO g TEMPERATURE COEFFICIENT (mg/°C) Figure 4. Y Axis Zero-g Bias, 25°C, VS = VDD I/O = 3.3 V 50 45 Figure 7. Y-Axis Zero-g Bias Drift, VS = VDD I/O = 3.3 V 25 PERCENT OF POPULATION (%) 35 30 25 20 15 10 5 08791-005 PERCENT OF POPULATION (%) 40 20 15 10 5 ZERO g TEMPERATURE COEFFICIENT (mg/°C) Figure 5. Z Axis Zero-g Bias, 25°C, VS = VDD I/O = 3.3 V Figure 8. Z-Axis Zero-g Bias Drift, VS = VDD I/O = 3.3 V Rev. 0 | Page 7 of 32 08791-008 0 –250 –200 –150 –100 –50 0 50 100 ZERO g OFFSET (mg) 0 0 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0.5 1.0 1.5 2.0 2.5 150 200 250 3.0 08791-007 –60 –30 0 30 60 ZERO g OFFSET (mg) 90 120 150 3.0 08791-006 –60 –30 0 30 60 ZERO g OFFSET (mg) 90 120 150 3.0 ADXL312 70 60 PERCENT OF POPULATION (%) 50 40 30 20 10 0 312 318 324 330 336 342 348 354 360 366 372 378 384 08791-009 30 PERCENT OF POPULATION (%) 25 20 15 10 5 0 0 0.005 0.010 0.015 0.020 0.025 –0.030 –0.025 –0.020 –0.015 –0.010 –0.005 0.030 0.030 0.030 08791-012 08791-014 08791-013 SENSITIVITY (LSB/g) SENSITIVITY TEMPERATURE COEFFICIENT (%/°C) Figure 9. X-Axis Sensitivity, VS = VDD I/O = 3.3 V, 25°C 70 60 PERCENT OF POPULATION (%) Figure 12. X-Axis Sensitivity Temperature Coefficient, VS = VDD I/O = 3.3 V 35 30 PERCENT OF POPULATION (%) 25 20 15 10 5 0 0 0.005 0.010 0.015 0.020 0.020 –0.030 –0.025 –0.020 –0.015 –0.010 08791-010 50 40 30 20 10 0 312 318 324 330 336 342 348 354 360 366 372 378 384 SENSITIVITY (LSB/g) SENSITIVITY TEMPERATURE COEFFICIENT (%/°C) Figure 10. Y-Axis Sensitivity, VS = VDD I/O = 3.3 V, 25°C 70 60 PERCENT OF POPULATION (%) 50 40 30 20 10 0 312 318 324 330 336 342 348 354 360 366 372 378 384 08791-011 Figure 13. Y-Axis Sensitivity Temperature Coefficient, VS = VDD I/O = 3.3 V 35 30 PERCENT OF POPULATION (%) 25 20 15 10 5 0 0 0.005 0.010 0.015 –0.030 –0.025 –0.020 –0.015 –0.010 –0.005 0.025 SENSITIVITY (LSB/g) SENSITIVITY TEMPERATURE COEFFICIENT (%/°C) Figure 11. Z-Axis Sensitivity, VS = VDD I/O = 3.3 V, 25°C Figure 14. Z-Axis Sensitivity Temperature Coefficient, VS = VDD I/O = 3.3 V Rev. 0 | Page 8 of 32 –0.005 0.025 ADXL312 80 70 60 50 40 30 20 10 08791-015 80 70 PERCENT OF POPULATION (%) 60 50 40 30 20 10 08791-018 PERCENT OF POPULATION (%) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SELF-TEST RESPONSE (g) 0 30 50 70 90 110 130 150 170 190 210 230 250 270 290 280 CURRENT (nA) 310 300 Figure 15. X-Axis Self-Test Delta, VS = VDD I/O = 3.3 V, 25°C 70 60 PERCENT OF POPULATION (%) Figure 18. Standby Mode Current Consumption, VS = VDD I/O = 3.3 V, 25°C 35 30 PERCENT OF POPULATION (%) 08791-016 50 40 30 20 10 0 –2.1 –1.9 –1.7 –1.5 –1.3 –1.1 –0.9 –0.7 –0.5 –0.3 25 20 15 10 5 0 100 120 140 160 180 200 220 240 260 SELF-TEST RESPONSE (g) CURRENT CONSUMPTION (µA) Figure 16. Y-Axis Self-Test Delta, VS = VDD I/O = 3.3 V, 25°C 80 70 PERCENT OF POPULATION (%) 60 50 40 30 20 10 08791-017 Figure 19. Current Consumption, Measurement Mode, Data Rate = 100 Hz, VS = VDD I/O = 3.3 V, 25°C 200 SUPPLY CURRENT (µA) 150 100 50 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 2.0 2.4 2.8 SUPPLY VOLTAGE (V) 3.2 3.6 SELF-TEST RESPONSE (g) Figure 17. Z-Axis Self-Test Delta, VS = VDD I/O = 3.3 V, 25°C Figure 20. Supply Current vs. Supply Voltage, VS at 25°C Rev. 0 | Page 9 of 32 08791-233 0 0 08791-019 ADXL312 THEORY OF OPERATION The ADXL312 is a complete 3-axis acceleration measurement system with a selectable measurement range of ±1.5 g, ±3 g, ±6 g, or ±12 g. It measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity, which allows it to be used as a tilt sensor. The sensor is a polysilicon surface-micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the beam and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phasesensitive demodulation is used to determine the magnitude and polarity of the acceleration. Table 5. Power Sequencing Condition Power Off VS Off VDD I/O Off Description The device is completely off, but there is a potential for a communication bus conflict. The device is on in standby mode, but communication is unavailable and will create a conflict on the communication bus. The duration of this state should be minimized during power-up to prevent a conflict. No functions are available, but the device will not create a conflict on the communication bus. The device is in standby mode, awaiting a command to enter measurement mode, and all sensor functions are off. After the device is instructed to enter measurement mode, all sensor functions are available. Bus Disabled On Off Bus Enabled Off On Standby or Measurement On On POWER SEQUENCING Power can be applied to VS or VDD I/O in any sequence without damaging the ADXL312. All possible power-on modes are summarized in Table 5. The interface voltage level is set with the interface supply voltage, VDD I/O, which must be present to ensure that the ADXL312 does not create a conflict on the communication bus. For single-supply operation, VDD I/O can be the same as the main supply, VS. In a dual-supply application, however, VDD I/O can differ from VS to accommodate the desired interface voltage, as long as VS is greater than or equal to VDD I/O. After VS is applied, the device enters standby mode, where power consumption is minimized and the device waits for VDD I/O to be applied and for the command to enter measurement mode to be received. (This command can be initiated by setting the measure bit in the POWER_CTL register (Address 0x2D).) In addition, any register can be written to or read from to configure the part while the device is in standby mode. It is recommended to configure the device in standby mode and then to enable measurement mode. Clearing the measure bit returns the device to the standby mode. POWER SAVINGS Power Modes The ADXL312 automatically modulates its power consumption in proportion to its output data rate, as outlined in Table 6. If additional power savings is desired, a lower power mode is available. In this mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 Hz to 400 Hz data rate range at the expense of slightly greater noise. To enter low power mode, set the LOW_POWER bit (Bit 4) in the BW_RATE register (Address 0x2C). The current consumption in low power mode is shown in Table 7 for cases where there is an advantage to using low power mode. Use of low power mode for a data rate not shown in Table 7 does not provide any advantage over the same data rate in normal power mode. Therefore, it is recommended that only data rates shown in Table 7 be used in low power mode. The current consumption values shown in Table 6 and Table 7 are for a VS of 3.3 V. Rev. 0 | Page 10 of 32 ADXL312 Table 6. Current Consumption vs. Data Rate (TA = 25°C, VS = VDD I/O = 3.3 V) Output Data Rate (Hz) 3200 1600 800 400 200 100 50 25 12.5 6.25 Bandwidth (Hz) 1600 800 400 200 100 50 25 12.5 6.25 3.125 Rate Code 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 IDD (μA) 170 115 170 170 170 170 115 82 65 57 Autosleep Mode Additional power savings can be had by having the ADXL312 automatically switch to sleep mode during periods of inactivity. To enable this feature, set the THRESH_INACT register (Address 0x25) to an acceleration threshold value. Levels of acceleration below this threshold are regarded as no activity levels. Set TIME_INACT (Address 0x26) to an appropriate inactivity time period. Then set the AUTO_SLEEP bit and the link bit in the POWER_CTL register (Address 0x2D). If the device does not detect a level of acceleration in excess of THRES_INACT for TIME_INACT seconds, then the device is transitioned to sleep mode automatically. Current consumption at the sub-8 Hz data rates used in this mode is typically 30 μA for a VS of 3.3 V. Table 7. Current Draw vs. Data Rate, Low Power Mode (TA = 25°C, VS = VDD I/O = 3.3 V) Output Data Rate (Hz) 400 200 100 50 25 12.5 Bandwidth (Hz) 200 100 50 25 12.5 6.25 Rate Code 1100 1011 1010 1001 1000 0111 IDD (μA) 115 82 65 57 50 43 Standby Mode For even lower power operation, standby mode can be used. In standby mode, current consumption is reduced to 0.1μA (typical). In this mode, no measurements are made. Standby mode is entered by clearing the measure bit (Bit 3) in the POWER_CTL register (Address 0x2D). Placing the device into standby mode preserves the contents of the FIFO. Rev. 0 | Page 11 of 32 ADXL312 SERIAL COMMUNICATIONS I2C and SPI digital communications are available. In both cases, the ADXL312 operates as a slave. I2C mode is enabled if the CS pin is tied high to VDD I/O. The CS pin should always be tied high to VDD I/O or be driven by an external controller because there is no default mode if the CS pin is left unconnected. Therefore, not taking these precautions may result in an inability to communicate with the part. In SPI mode, the CS pin is controlled by the bus master. In both SPI and I2C modes of operation, data transmitted from the ADXL312 to the master device should be ignored during writes to the ADXL312. CS is the serial port enable line and is controlled by the SPI master. This line must go low at the start of a transmission and high at the end of a transmission, as shown in Figure 23. SCLK is the serial port clock and is supplied by the SPI master. SCLK should idle high during a period of no transmission. SDI and SDO are the serial data input and output, respectively. Data is updated on the falling edge of SCLK and should be sampled on the rising edge of SCLK. To read or write multiple bytes in a single transmission, the multiple-byte bit, located after the R/W bit in the first byte transfer (MB in Figure 23 to Figure 25), must be set. After the register addressing and the first byte of data, each subsequent set of clock pulses (eight clock pulses) causes the ADXL312 to point to the next register for a read or write. This shifting continues until the clock pulses cease and CS is deasserted. To perform reads or writes on different, nonsequential registers, CS must be deasserted between transmissions, and the new register must be addressed separately. The timing diagram for 3-wire SPI reads or writes is shown in Figure 25. The 4-wire equivalents for SPI writes and reads are shown in Figure 23 and Figure 24, respectively. For correct operation of the part, the logic thresholds and timing parameters in Table 8 and Table 9 must be met at all times. Use of the 3200 Hz and 1600 Hz output data rates is only recommended with SPI communication rates greater than or equal to 2 MHz. The 800 Hz output data rate is recommended only for communication speeds greater than or equal to 400 kHz, and the remaining data rates scale proportionally. For example, the minimum recommended communication speed for a 200 Hz output data rate is 100 kHz. Operation at an output data rate below the recommended minimum may result in undesirable effects on the acceleration data, including missing samples or additional noise. SPI For SPI, either 3- or 4-wire configuration is possible, as shown in the connection diagrams in Figure 21 and Figure 22. Clearing the SPI bit in the DATA_FORMAT register (Address 0x31) selects 4-wire mode, whereas setting the SPI bit selects 3-wire mode. The maximum SPI clock speed is 5 MHz with 100 pF maximum loading, and the timing scheme follows clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to the ADXL312 before the clock polarity and phase of the host processor are configured, the CS pin should be brought high before changing the clock polarity and phase. When using 3-wire SPI, it is recommended that the SDO pin be either pulled up to VDD I/O or pulled down to GND via a 10 kΩ resistor. ADXL312 CS SDIO SDO SCLK D OUT PROCESSOR D OUT D IN/OUT 08791-021 08791-022 Figure 21. 3-Wire SPI Connection Diagram ADXL312 CS SDI SDIO SCLK PROCESSOR D OUT D OUT D IN D OUT Figure 22. 4-Wire SPI Connection Diagram Rev. 0 | Page 12 of 32 ADXL312 Table 8. SPI Digital Input/Output Parameter Digital Input Low Level Input Voltage (VIL) High Level Input Voltage (VIH) Low Level Input Current (IIL) High Level Input Current (IIH) Digital Output Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Low Level Output Current (IOL) High Level Output Current (IOH) Pin Capacitance 1 Test Conditions Min Limit1 Max 0.3 × VDD I/O Unit V V μA μA V V mA mA pF 0.7 × VDD I/O VIN = VDD I/O VIN = 0 V IOL = 10 mA IOH = −4 mA VOL = VOL, max VOH = VOH, min fIN = 1 MHz, VIN = 2.5 V 0.1 −0.1 0.2 × VDD I/O 0.8 × VDD I/O 10 −4 8 Limits based on characterization results, not production tested. Table 9. SPI Timing (TA = 25°C, VS = VDD I/O = 3.3 V)1 Limit2, 3 Parameter fSCLK tSCLK tDELAY tQUIET tDIS tCS,DIS tS tM tSETUP tHOLD tSDO tR4 t F4 1 2 Min 200 5 5 Max 5 10 150 0.3 × tSCLK 0.3 × tSCLK 5 5 40 20 20 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns Description SPI clock frequency. 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40. CS falling edge to SCLK falling edge . SCLK rising edge to CS rising edge. CS rising edge to SDO disabled. CS deassertion between SPI communications. SCLK low pulse width (space). SCLK high pulse width (mark). SDI valid before SCLK rising edge. SDI valid after SCLK rising edge. SCLK falling edge to SDO/SDIO output transition. SDO/SDIO output high to output low transition. SDO/SDIO output low to output high transition. The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation. Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested. 3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 8. 4 Output rise and fall times measured with capacitive load of 150 pF. Rev. 0 | Page 13 of 32 ADXL312 CS tDELAY SCLK tSCLK tM tS tQUIET tCS,DIS tSETUP SDI W tHOLD MB A5 A0 D7 D0 tSDO SDO X X ADDRESS BITS X X DATA BITS X tDIS 08791-129 X tR, tF Figure 23. SPI 4-Wire Write CS tDELAY SCLK tSCLK tM tS tQUIET tCS,DIS tSETUP SDI R tHOLD MB A5 A0 X X tSDO SDO X X ADDRESS BITS X X D7 tDIS D0 08791-130 tR, tF DATA BITS Figure 24. SPI 4-Wire Read CS tDELAY SCLK tSCLK tM tS tQUIET tCS,DIS tSETUP SDIO R/W tHOLD MB A5 tR, tF A0 D7 tSDO D0 ADDRESS BITS SDO NOTES 1. tSDO IS ONLY PRESENT DURING READS. DATA BITS Figure 25. SPI 3-Wire Read/Write Rev. 0 | Page 14 of 32 08791-131 ADXL312 I2C With CS tied high to VDD I/O, the ADXL312 is in I2C mode, requiring a simple 2-wire connection as shown in Figure 26. The ADXL312 conforms to the UM10204 I2C-Bus Specification and User Manual, Rev. 03—19 June 2007, available from NXP Semiconductor. It supports standard (100 kHz) and fast (400 kHz) data transfer modes if the bus parameters given in Table 10 and Table 11 are met. Single- or multiple-byte reads/writes are supported, as shown in Figure 27. With the ALT ADDRESS pin high, the 7-bit I2C address for the device is 0x1D, followed by the R/W bit. This translates to 0x3A for a write and 0x3B for a read. An alternate I2C address of 0x53 (followed by the R/W bit) can be chosen by grounding the ALT ADDRESS pin (Pin 7). This translates to 0xA6 for a write and 0xA7 for a read. Table 10. I2C Digital Input/Output Limit 1 Parameter Digital Input Low Level Input Voltage (VIL) High Level Input Voltage (VIH) Low Level Input Current (IIL) High Level Input Current (IIH) Digital Output Low Level Output Voltage (VOL) Low Level Output Current (IOL) Pin Capacitance 1 VDD I/O ADXL312 CS SDA ALT ADDRESS RP RP PROCESSOR D IN/OUT Figure 26. I2C Connection Diagram (Address 0x53) If other devices are connected to the same I2C bus, the nominal operating voltage level of these other devices cannot exceed VDD I/O by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I2C operation. Refer to the UM10204 I2C-Bus Specification and User Manual, Rev. 03—19 June 2007, when selecting pull-up resistor values to ensure proper operation. Test Conditions Min Max 0.3 × VDD I/O 08791-032 SCL D OUT Unit V V μA μA V mV mA pF 0.7 × VDD I/O VIN = VDD I/O VIN = 0 V VDD I/O < 2 V, IOL = 3 mA VDD I/O ≥ 2 V, IOL = 3 mA VOL = VOL, max fIN = 1 MHz, VIN = 2.5 V 0.1 −0.1 0.2 × VDD I/O 400 3 8 Limits based on characterization results; not production tested. SINGLE-BYTE WRITE MASTER START SLAVE SLAVE ADDRESS + WRITE ACK REGISTER ADDRESS ACK DATA ACK STOP MULTIPLE-BYTE WRITE MASTER START SLAVE SLAVE ADDRESS + WRITE ACK REGISTER ADDRESS ACK DATA ACK DATA ACK STOP SINGLE-BYTE READ MASTER START SLAVE SLAVE ADDRESS + WRITE ACK REGISTER ADDRESS ACK START1 SLAVE ADDRESS + READ ACK DATA NACK STOP MULTIPLE-BYTE READ MASTER START SLAVE SLAVE ADDRESS + WRITE ACK REGISTER ADDRESS ACK START1 SLAVE ADDRESS + READ ACK DATA ACK DATA NACK STOP Figure 27. I2C Device Addressing Rev. 0 | Page 15 of 32 08791-033 NOTES 1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START. 2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. ADXL312 Table 11. I2C Timing (TA = 25°C, VS = VDD I/O = 3.3 V) Parameter fSCL t1 t2 t3 t4 t5 t6 3, 4, 5, 6 t7 t8 t9 t10 t11 20 + 0.1 Cb 7 Cb 1 2 Min 2.5 0.6 1.3 0.6 100 0 0.6 0.6 1.3 0 Limit 1, 2 Max 400 0.9 300 250 300 400 Unit kHz μs μs μs μs ns μs μs μs μs ns ns ns ns ns pF Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT, data hold time tSU, STA, setup time for repeated start tSU, STO, stop condition setup time tBUF, bus-free time between a stop condition and a start condition tR, rise time of both SCL and SDA when receiving tR, rise time of both SCL and SDA when receiving or transmitting tF, fall time of SDA when receiving tF, fall time of both SCL and SDA when transmitting tF, fall time of both SCL and SDA when transmitting or receiving Capacitive load for each bus line Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested. All values referred to the VIH and the VIL levels given in Table 10. 3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge. 4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 5 The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal. 6 The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 − t10 − t5(min). 7 Cb is the total capacitance of one bus line in picofarads. SDA t9 t3 t10 t11 t4 SCL t4 START CONDITION t6 t2 t5 t7 REPEATED START CONDITION t1 t8 STOP CONDITION 08791-034 Figure 28. I2C Timing Diagram Rev. 0 | Page 16 of 32 ADXL312 INTERRUPTS The ADXL312 provides two output pins for driving interrupts: INT1 and INT2. Both interrupt pins are push-pull, low impedance pins with output specifications shown in Table 12. The default configuration of the interrupt pins is active high. This can be changed to active low by setting the INT_INVERT bit in the DATA_FORMAT (Address 0x31) register. All functions can be used simultaneously, with the only limiting feature being that some functions may need to share interrupt pins. Interrupts are enabled by setting the appropriate bit in the INT_ENABLE register (Address 0x2E) and are mapped to either the INT1 or INT2 pin based on the contents of the INT_MAP register (Address 0x2F). When initially configuring the interrupt pins, it is recommended that the functions and interrupt mapping be done before enabling the interrupts. When changing the configuration of an interrupt, it is recommended that the interrupt be disabled first, by clearing the bit corresponding to that function in the INT_ENABLE register, and then the function be reconfigured before enabling the interrupt again. Configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an interrupt before desired. The interrupt functions are latched and cleared by either reading the data registers (Address 0x32 to Address 0x37) until the interrupt condition is no longer valid for the data-related interrupts or by reading the INT_SOURCE register (Address 0x30) for the remaining interrupts. This section describes the interrupts that can be set in the INT_ENABLE register and monitored in the INT_SOURCE register. Table 12. Interrupt Pin Digital Output Limit 1 Parameter Digital Output Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Low Level Output Current (IOL) High Level Output Current (IOH) Pin Capacitance Rise/Fall Time Rise Time (tR) 2 Fall Time (tF) 3 1 2 DATA_READY The DATA_READY bit is set when new data is available and is cleared when no new data is available. Activity The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0x24) is experienced. Inactivity The inactivity bit is set when acceleration of less than the value stored in the THRESH_INACT register (Address 0x25) is experienced for more time than is specified in the TIME_INACT register (Address 0x26). The maximum value for TIME_INACT is 255 sec. Watermark The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits (Register FIFO_CTL, Address 0x38). The watermark bit is cleared automatically when FIFO is read, and the content returns to a value below the value stored in the samples bits. Overrun The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode. In bypass mode, the overrun bit is set when new data replaces unread data in the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). In all other modes, the overrun bit is set when FIFO is filled. The overrun bit is automatically cleared when the contents of FIFO are read. Test Conditions IOL = 300 μA IOH = −150 μA VOL = VOL, max VOH = VOH, min fIN = 1 MHz, VIN = 2.5 V CLOAD = 150 pF CLOAD = 150 pF Min Max 0.2 × VDD I/O Unit V V μA μA pF ns ns 0.8 × VDD I/O 300 −150 8 210 150 Limits based on characterization results, not production tested. Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin. 3 Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin. Rev. 0 | Page 17 of 32 ADXL312 FIFO The ADXL312 contains patent pending technology for an embedded memory management system with 32-level FIFO that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger (see Table 21). Each mode is selected by the settings of the FIFO_MODE bits in the FIFO_CTL register (Address 0x38). FIFO keeps the last n samples (where n is the value specified by the samples bits in the FIFO_CTL register) and then operates in FIFO mode, collecting new samples only when FIFO is not full. A delay of at least 5 μs should be present between the trigger event occurring and the start of reading data from the FIFO to allow the FIFO to discard and retain the necessary samples. Additional trigger events cannot be recognized until the trigger mode is reset. To reset the trigger mode, set the device to bypass mode and then set the device back to trigger mode. Note that the FIFO data should be read first because placing the device into bypass mode clears FIFO. Bypass Mode In bypass mode, FIFO is not operational and, therefore, remains empty. FIFO Mode In FIFO mode, data from measurements of the x-, y-, and z-axes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples until it is full (32 samples from measurements of the x-, y-, and z-axes) and then stops collecting data. After FIFO stops collecting data, the device continues to operate; therefore, features such as activity detection can be used after FIFO is full. The watermark interrupt continues to occur until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. Retrieving Data from FIFO The FIFO data is read through the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). When the FIFO is in FIFO, stream, or trigger mode, reads to the DATAX, DATAY, and DATAZ registers read data stored in the FIFO. Each time data is read from the FIFO, the oldest x-, y-, and z-axes data is placed into the DATAX, DATAY and DATAZ registers. If a single-byte read operation is performed, the remaining bytes of data for the current FIFO sample are lost. Therefore, all axes of interest should be read in a burst (or multiple-byte) read operation. To ensure that the FIFO has completely popped (that is, that new data has completely moved into the DATAX, DATAY, and DATAZ registers), there must be at least 5 μs between the end of reading the data registers and the start of a new read of the FIFO or a read of the FIFO_STATUS register (Address 0x39). The end of reading a data register is signified by the transition from Register 0x37 to Register 0x38 or by the CS pin going high. For SPI operation at 1.6 MHz or less, the register addressing portion of the transmission is a sufficient delay to ensure that the FIFO has completely popped. For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS pin to ensure a total delay of 5 μs; otherwise, the delay will not be sufficient. The total delay necessary for 5 MHz operation is at most 3.4 μs. This is not a concern when using I2C mode because the communication rate is low enough to ensure a sufficient delay between FIFO reads. Stream Mode In stream mode, data from measurements of the x-, y-, and zaxes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples and holds the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new data arrives. The watermark interrupt continues occurring until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. Trigger Mode In trigger mode, FIFO accumulates samples, holding the latest 32 samples from measurements of the x-, y-, and z-axes. After a trigger event occurs and an interrupt is sent to the INT1 or INT2 pin (determined by the trigger bit in the FIFO_CTL register), Rev. 0 | Page 18 of 32 ADXL312 SELF-TEST The ADXL312 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is enabled (via the SELF_TEST bit in the DATA_FORMAT register, Address 0x31), an electrostatic force is exerted on the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the device. This added electrostatic force results in an output change in the x-, y-, and z-axes. Because the electrostatic force is proportional to VS2, the output change varies with VS. This effect is shown in Figure 29. The scale factors shown in Table 13 can be used to adjust the expected self-test output limits for different supply voltages, VS. The self-test feature of the ADXL312 also exhibits a bimodal behavior. However, the limits shown in Table 1 and Table 14 to Table 17 are valid for both potential selftest values due to bimodality. Use of the self-test feature at data rates less than 100 Hz or at 1600 Hz may yield values outside these limits. Therefore, the part must be in normal power operation (LOW_POWER bit = 0 in BW_RATE register, Address 0x2C) and be placed into a data rate of 100 Hz through 800 Hz or 3200 Hz for the self-test function to operate correctly. 6 Table 13. Self-Test Output Scale Factors for Different Supply Voltages, VS Supply Voltage, VS 2.00 V 2.50 V 3.00 V 3.30 V X-, Y-Axes 0.64 1.00 1.77 2.11 Z-Axis 0.8 1.00 1.47 1.69 Table 14. Self-Test Output in LSB for ±1.5 g, 10-Bit or Full Resolution (TA = 25°C, VS = VDD I/O = 2.5 V) Axis X Y Z Min 65 −725 100 Max 725 −65 1175 Unit LSB LSB LSB Table 15. Self-Test Output in LSB for ±3 g, 10-Bit Resolution (TA = 25°C, VS = VDD I/O = 2.5 V) Axis X Y Z Min 32 −362 50 Max 362 −32 588 Unit LSB LSB LSB Table 16. Self-Test Output in LSB for ±6 g, 10-Bit Resolution (TA = 25°C, VS = VDD I/O = 2.5 V) Axis X Y Z Min 16 −181 25 Max 181 −16 294 Unit LSB LSB LSB 4 SELF-TEST SHIFT LIMIT (g) 2 0 Table 17. Self-Test Output in LSB for ±12 g, 10-Bit Resolution (TA = 25°C, VS = VDD I/O = 2.5 V) X HIGH X LOW Y HIGH Y LOW Z HIGH Z LOW 2.0 2.5 VS (V) 3.3 3.6 08791-242 –2 –4 Axis X Y Z Min 8 −90 12 Max 90 −8 147 Unit LSB LSB LSB –6 Figure 29. Self-Test Output Change Limits vs. Supply Voltage Rev. 0 | Page 19 of 32 ADXL312 REGISTER MAP Table 18. Register Map Address Hex Dec 0x00 0 0x01 to 0x1D 1 to 29 0x1E 30 0x1F 31 0x20 32 0x21 33 0x22 34 0x23 35 0x24 36 0x25 37 0x26 38 0x27 39 0x28 40 0x29 41 0x2A 42 0x2B 43 0x2C 44 0x2D 45 0x2E 46 0x2F 47 0x30 48 0x31 49 0x32 50 0x33 51 0x34 52 0x35 53 0x36 54 0x37 55 0x38 56 0x39 57 Name DEVID Reserved OFSX OFSY OFSZ Reserved Reserved Reserved THRESH_ACT THRESH_INACT TIME_INACT ACT_INACT_CTL Reserved Reserved Reserved Reserved BW_RATE POWER_CTL INT_ENABLE INT_MAP INT_SOURCE DATA_FORMAT DATAX0 DATAX1 DATAY0 DATAY1 DATAZ0 DATAZ1 FIFO_CTL FIFO_STATUS Type R R/W R/W R/W Reset Value 11100101 00000000 00000000 00000000 Description Device ID. Reserved. Do not access. X-axis offset. Y-axis offset. Z-axis offset. Reserved. Do not access. Reserved. Do not access. Reserved. Do not access. Activity threshold. Inactivity threshold. Inactivity time. Axis enable control for activity and inactivity detection. Reserved. Do not access. Reserved. Do not access. Reserved. Do not access. Reserved. Do not access. Data rate and power mode control. Power-saving features control. Interrupt enable control. Interrupt mapping control. Source of interrupts. Data format control. X-Axis Data 0. X-Axis Data 1. Y-Axis Data 0. Y-Axis Data 1. Z-Axis Data 0. Z-Axis Data 1. FIFO control. FIFO status. R/W R/W R/W R/W 00000000 00000000 00000000 00000000 R/W R/W R/W R/W R R/W R R R R R R R/W R 00001010 00000000 00000000 00000000 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Rev. 0 | Page 20 of 32 ADXL312 REGISTER DEFINITIONS Register 0x00—DEVID (Read Only) D7 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1 THRESH_ACT and THRESH_INACT to determine whether activity or inactivity is detected. In ac-coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. New samples of acceleration are then compared to this reference value and, if the magnitude of the difference exceeds the THRESH_ACT value, the device triggers an activity interrupt. Similarly, in ac-coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. After the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with THRESH_INACT. If the difference is less than the value in THRESH_INACT for the time in TIME_INACT, the device is considered inactive and the inactivity interrupt is triggered. The DEVID register holds a fixed device ID code of 0xE5. Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 11.6 mg/LSB (that is, 0x7F = +1.5 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. Register 0x24—THRESH_ACT (Read/Write) The THRESH_ACT register is eight bits and holds the threshold value for detecting activity. The data format is unsigned; therefore, the magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor is 46.4 mg/LSB. A value of 0 may result in undesirable behavior if the activity interrupt is enabled. ACT_x Enable Bits and INACT_x Enable Bits A setting of 1 enables x-, y-, or z-axis participation in detecting activity or inactivity. A setting of 0 excludes the selected axis from participation. If all axes are excluded, the function is disabled. For activity detection, all participating axes are logically OR’ed, causing the activity function to trigger when any of the participating axes exceeds the threshold. For inactivity detection, all participating axes are logically AND’ed, causing the inactivity function to trigger only if all participating axes are below the threshold for the specified period of time. Register 0x25—THRESH_INACT (Read/Write) The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity. The data format is unsigned; therefore, the magnitude of the inactivity event is compared with the value in the THRESH_INACT register. The scale factor is 46.4 mg/LSB. A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled. Register 0x2C—BW_RATE (Read/Write) D7 0 D6 0 D5 0 D4 LOW_POWER D3 D2 D1 Rate D0 Register 0x26—TIME_INACT (Read/Write) The TIME_INACT register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared. The scale factor is 1 sec/LSB. Unlike the other interrupt functions, which use unfiltered data (see the Threshold section), the inactivity function uses filtered output data. At least one output sample must be generated for the inactivity interrupt to be triggered. This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate. A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register. LOW_POWER Bit A setting of 0 in the LOW_POWER bit selects normal operation, and a setting of 1 selects reduced power operation, which has somewhat higher noise (see the Power Modes section for details). Rate Bits These bits select the device bandwidth and output data rate (see Table 6 and Table 7 for details). The default value is 0x0A, which translates to a 100 Hz output data rate. An output data rate should be selected that is appropriate for the communica-tion protocol and frequency selected. Selecting too high of an output data rate with a low communication speed results in samples being discarded. Register 0x27—ACT_INACT_CTL (Read/Write) D7 ACT ac/dc D3 INACT ac/dc D6 ACT_X enable D2 INACT_X enable D5 ACT_Y enable D1 INACT_Y enable D4 ACT_Z enable D0 INACT_Z enable Register 0x2D—POWER_CTL (Read/Write) D7 0 D6 0 D5 Link D4 AUTO_SLEEP D3 Measure D2 Sleep D1 D0 Wakeup Link Bit A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is detected. After activity is detected, inactivity detection begins, preventing the detection of activity. This bit serially links the activity and inactivity functions. When this bit is set to 0, ACT AC/DC and INACT AC/DC Bits A setting of 0 selects dc-coupled operation, and a setting of 1 enables ac-coupled operation. In dc-coupled operation, the current acceleration magnitude is compared directly with Rev. 0 | Page 21 of 32 ADXL312 the inactivity and activity functions are concurrent. Additional information can be found in the Link Mode section. When clearing the link bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. Wake-Up Bits These bits control the frequency of readings in sleep mode as described in Table 19. Table 19. Frequency of Readings in Sleep Mode D1 0 0 1 1 Setting D0 0 1 0 1 D6 N/A D2 N/A Frequency (Hz) 8 4 2 1 D5 N/A D1 Watermark D4 Activity D0 Overrun AUTO_SLEEP Bit If the link bit is set, a setting of 1 in the AUTO_SLEEP bit sets the ADXL312 to switch to sleep mode when inactivity is detected (that is, when acceleration has been below the THRESH_INACT value for at least the time indicated by TIME_INACT). A setting of 0 disables automatic switching to sleep mode. See the description of the sleep bit in this section for more information. When clearing the AUTO_SLEEP bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the AUTO_SLEEP bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. Register 0x2E—INT_ENABLE (Read/Write) D7 DATA_READY D3 Inactivity Setting bits in this register to a value of 1 enables their respective functions to generate interrupts, whereas a value of 0 prevents the functions from generating interrupts. The DATA_READY, watermark, and overrun bits enable only the interrupt output; the functions are always enabled. It is recommended that interrupts be configured before enabling their outputs. Register 0x2F—INT_MAP (Read/Write) D7 DATA_READY D3 Inactivity D6 N/A D2 N/A D5 N/A D1 Watermark D4 Activity D0 Overrun Measure Bit A setting of 0 in the measure bit places the part into standby mode, and a setting of 1 places the part into measurement mode. The ADXL312 powers up in standby mode with minimum power consumption. Sleep Bit A setting of 0 in the sleep bit puts the part into the normal mode of operation, and a setting of 1 places the part into sleep mode. Sleep mode suppresses DATA_READY (see Register 0x2E, Register 0x2F, and Register 0x30), stops transmission of data to FIFO, and switches the sampling rate to one specified by the wake-up bits. In sleep mode, only the activity function can be used. When clearing the sleep bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the sleep bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. Any bits set to 0 in this register send their respective interrupts to the INT1 pin, whereas bits set to 1 send their respective interrupts to the INT2 pin. All selected interrupts for a given pin are OR’ed. Register 0x30—INT_SOURCE (Read Only) D7 DATA_READY D3 Inactivity D6 N/A D2 N/A D5 N/A D1 Watermark D4 Activity D0 Overrun Bits set to 1 in this register indicate that their respective functions have triggered an event, whereas a value of 0 indicates that the corresponding event has not occurred. The DATA_READY, watermark, and overrun bits are always set if the corresponding events occur, regardless of the INT_ENABLE register settings, and are cleared by reading data from the DATAX, DATAY, and DATAZ registers. The DATA_READY and watermark bits may require multiple reads, as indicated in the FIFO mode descriptions in the FIFO section. Other bits, and the corresponding interrupts, are cleared by reading the INT_SOURCE register. Rev. 0 | Page 22 of 32 ADXL312 Register 0x31—DATA_FORMAT (Read/Write) D7 SELF_TEST D6 SPI D5 INT_INVERT D4 0 D3 FULL_RES D2 Justify D1 D0 Range The DATA_FORMAT register controls the presentation of data to Register 0x32 through Register 0x37. All data, except that for the ±12 g range, must be clipped to avoid rollover. The output data is twos complement, with DATAx0 as the least significant byte and DATAx1 as the most significant byte, where x represent X, Y, or Z. The DATA_FORMAT register (Address 0x31) controls the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data between reads of sequential registers. SELF_TEST Bit A setting of 1 in the SELF_TEST bit applies a self-test force to the sensor, causing a shift in the output data. A value of 0 disables the self-test force. Register 0x38—FIFO_CTL (Read/Write) D7 D6 FIFO_MODE D5 Trigger D4 D3 D2 D1 Samples D0 FIFO_MODE Bits These bits set the FIFO mode, as described in Table 21. Table 21. FIFO Modes Setting D7 D6 0 0 0 1 Mode Bypass FIFO Function FIFO is bypassed. FIFO collects up to 32 values and then stops collecting data, collecting new data only when FIFO is not full. FIFO holds the last 32 data values. When FIFO is full, the oldest data is overwritten with newer data. When triggered by the trigger bit, FIFO holds the last data samples before the trigger event and then continues to collect data until full. New data is collected only when FIFO is not full. SPI Bit A value of 1 in the SPI bit sets the device to 3-wire SPI mode, and a value of 0 sets the device to 4-wire SPI mode. INT_INVERT Bit A value of 0 in the INT_INVERT bit sets the interrupts to active high, and a value of 1 sets the interrupts to active low. FULL_RES Bit When this bit is set to a value of 1, the device is in full resolution mode, where the output resolution increases with the g range set by the range bits to maintain a 2.9 mg/LSB scale factor. When the FULL_RES bit is set to 0, the device is in 10-bit mode, and the range bits determine the maximum g range and scale factor. 1 0 Stream 1 1 Trigger Justify Bit A setting of 1 in the justify bit selects left (MSB) justified mode, and a setting of 0 selects right justified mode with sign extension. Trigger Bit A value of 0 in the trigger bit links the trigger event of trigger mode INT1, and a value of 1 links the trigger event to INT2. Range Bits These bits set the g range as described in Table 20. Table 20. g Range Setting D1 0 0 1 1 Setting D0 0 1 0 1 g Range ±1.5 g ±3 g ±6 g ±12 g Samples Bits The function of these bits depends on the FIFO mode selected (see Table 22). Entering a value of 0 in the samples bits immediately sets the watermark status bit in the INT_SOURCE register, regardless of which FIFO mode is selected. Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used. Table 22. Samples Bits Functions FIFO Mode Bypass FIFO Stream Trigger Samples Bits Function None. Specifies how many FIFO entries are needed to trigger a watermark interrupt. Specifies how many FIFO entries are needed to trigger a watermark interrupt. Specifies how many FIFO samples are retained in the FIFO buffer before a trigger event. Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) These six bytes (Register 0x32 to Register 0x37) are eight bits each and hold the output data for each axis. Register 0x32 and Register 0x33 hold the output data for the x-axis, Register 0x34 and Register 0x35 hold the output data for the y-axis, and Register 0x36 and Register 0x37 hold the output data for the z-axis. Rev. 0 | Page 23 of 32 ADXL312 0x39—FIFO_STATUS (Read Only) D7 FIFO_TRIG D6 0 D5 D4 D3 D2 Entries D1 D0 Entries Bits These bits report how many data values are stored in FIFO. Access to collect the data from FIFO is provided through the DATAX, DATAY, and DATAZ registers. FIFO reads must be done in burst or multiple-byte mode because each FIFO level is cleared after any read (single- or multiple-byte) of FIFO. FIFO stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device. FIFO_TRIG Bit A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring, and a 0 means that a FIFO trigger event has not occurred. Rev. 0 | Page 24 of 32 ADXL312 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING A 1 μF tantalum capacitor (CS) at VS and a 0.1 μF ceramic capacitor (CI/O) at VDD I/O placed close to the ADXL312 supply pins is recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, a resistor or ferrite bead, no larger than 100 Ω, in series with VS may be helpful. Additionally, increasing the bypass capacitance on VS to a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor may also improve noise. Care should be taken to ensure that the connection from the ADXL312 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through VS. It is recommended that VS and VDD I/O be separate supplies to minimize digital clocking noise on the VS supply. If this is not possible, additional filtering of the supplies as previously mentioned may be necessary. VS CS VS VDD I/O SDA/SDI/SDIO INTERRUPT CONTROL INT1 SDO/ALT ADDRESS SCL/SCLK INT2 GND CS VDD I/O CI/O THRESHOLD The lower output data rates are achieved by decimating a common sampling frequency inside the device. The activity detection function is performed using undecimated data. Because the bandwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data, the high frequency and high g data that are used to determine activity may not be present if the output of the accelerometer is examined. This may result in functions triggering when acceleration data does not appear to meet the conditions set by the user for the corresponding function. LINK MODE The function of the link bit is to reduce the number of activity interrupts that the processor must service by setting the device to look for activity only after inactivity. For proper operation of this feature, the processor must still respond to the activity and inactivity interrupts by reading the INT_SOURCE register (Address 0x30) and, therefore, clearing the interrupts. If an activity interrupt is not cleared, the part cannot go into autosleep mode. ADXL312 3-WIRE OR 4-WIRE SPI OR I2C INTERFACE SLEEP MODE VS. LOW POWER MODE In applications where a low data rate and low power consumption are desired (at the expense of noise performance), it is recommended that low power mode be used. The use of low power mode preserves the functionality of the DATA_READY interrupt and the FIFO for postprocessing of the acceleration data. Sleep mode, while offering a low data rate and power consumption, is not intended for data acquisition. However, when sleep mode is used in conjunction with the autosleep mode and the link mode, the part can automatically switch to a low power, low sampling rate mode when inactivity is detected. To prevent the generation of redundant inactivity interrupts, the inactivity interrupt is automatically disabled and activity is enabled. When the ADXL312 is in sleep mode, the host processor can also be placed into sleep mode or low power mode to save significant system power. Once activity is detected, the accelerometer automatically switches back to the original data rate of the application and provides an activity interrupt that can be used to wake up the host processor. Similar to when inactivity occurs, detection of activity events is disabled and inactivity is enabled. Figure 30. Application Diagram MECHANICAL CONSIDERATIONS FOR MOUNTING The ADXL312 should be mounted on the PCB in a location close to a hard mounting point of the PCB to the case. Mounting the ADXL312 at an unsupported PCB location, as shown in Figure 31, may result in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the accelerometer’s mechanical sensor resonant frequency and, therefore, effectively invisible to the accelerometer. Multiple mounting points, close to the sensor, and/or a thicker PCB also help to reduce the effect of system resonance on the performance of the sensor. ACCELEROMETERS PCB MOUNTING POINTS Figure 31. Incorrectly Placed Accelerometers 08791-036 Rev. 0 | Page 25 of 32 08791-035 ADXL312 USING SELF-TEST The self-test change is defined as the difference between the acceleration output of an axis with self-test enabled and the acceleration output of the same axis with self-test disabled (see Endnote 4 of Table 1). This definition assumes that the sensor does not move between these two measurements because, if the sensor moves, a non-self-test related shift corrupts the test. Proper configuration of the ADXL312 is also necessary for an accurate self-test measurement. The part should be set with a data rate greater than or equal to 100 Hz. This is done by ensuring that a value greater than or equal to 0x0A is written into the rate bits (Bit D3 through Bit D0) in the BW_RATE register (Address 0x2C). The part also must be placed into normal power operation by ensuring the LOW_POWER bit in the BW_RATE register is cleared (LOW_POWER bit = 0) for accurate self-test measurements. It is recommended that the part be set to full-resolution, 12 g mode to ensure that there is sufficient dynamic range for the entire self-test shift. This is done by setting Bit D3 of the DATA_FORMAT register (Address 0x31) and writing a value of 0x03 to the range bits (Bit D1 and Bit D0) of the DATA_FORMAT register (Address 0x31). This results in a high dynamic range for measurement and a 2.9 mg/LSB scale factor. After the part is configured for accurate self-test measurement, several samples of x-, y-, and z-axis acceleration data should be retrieved from the sensor and averaged together. The number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data, which corresponds to 10 samples at 100 Hz data rate. The averaged values should be stored and labeled appropriately as the self-test disabled data, that is, XST_OFF, YST_OFF, and ZST_OFF. Next, self-test should be enabled by setting Bit D7 of the DATA_FORMAT register (Address 0x31). The output needs some time (about four samples) to settle after enabling self-test. After allowing the output to settle, several samples of the x-, y-, and z-axis acceleration data should be taken again and averaged. It is recommended that the same number of samples be taken for this average as was previously taken. These averaged values should again be stored and labeled appropriately as the value with selftest enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then be disabled by clearing Bit D7 of the DATA_FORMAT register (Address 0x31). With the stored values for self-test enabled and disabled, the self-test change is as follows: XST = XST_ON − XST_OFF YST = YST_ON − YST_OFF ZST = ZST_ON − ZST_OFF Because the measured output for each axis is expressed in LSBs, XST, YST, and ZST are also expressed in LSBs. These values can be converted to g’s of acceleration by multiplying each value by the 2.9 mg/LSB scale factor, if configured for full-resolution mode. Additionally, Table 14 through Table 17 correspond to the selftest range converted to LSBs and can be compared with the measured self-test change when operating at a VS of 3.3 V. For other voltages, the minimum and maximum self-test output values should be adjusted based on (multiplied by) the scale factors shown in Table 13. If the part was placed into ±1.5 g, 10-bit or full-resolution mode, the values listed in Table 14 should be used. Although the fixed 10-bit mode or a range other than 12 g can be used, a different set of values, as indicated in Table 15 through Table 17, must be used. Using a range below 6 g may result in insufficient dynamic range and should be considered when selecting the range of operation for measuring self-test. If the self-test change is within the valid range, the test is considered successful. Generally, a part is considered to pass if the minimum magnitude of change is achieved. However, a part that changes by more than the maximum magnitude is not necessarily a failure. Rev. 0 | Page 26 of 32 ADXL312 DATA FORMATTING OF UPPER DATA RATES Formatting of output data at the 3200 Hz and 1600 Hz output data rates changes depending on the mode of operation (fullresolution or fixed 10-bit) and the selected output range. When in full-resolution or ±1.5 g, 10-bit operation, the LSB of the output data-word is always 0. When data is right justified, this corresponds to Bit D0 of the DATAx0 register, as shown in Figure 32. When data is left justified and the part is operating in ±1.5 g, 10-bit mode, the LSB of the output data-word is Bit D6 of the DATAx0 register. In full-resolution operation when data is left justified, the location of the LSB changes according to the selected output range. For a range of ±1.5 g, the LSB is Bit D6 of DATAx1 REGISTER the DATAx0 register; for ±3 g, Bit D5 of the DATAx0 register; for ±6 g, Bit D4 of the DATAx0 register; and for ±12 g, Bit D3 of the DATAx0 register. This is shown in Figure 33. The use of 3200 Hz and 1600 Hz output data rates for fixed 10-bit operation in the ±3 g, ±6 g, and ±12 g output ranges provides an LSB that is valid and that changes according to the applied acceleration. Therefore, in these modes of operation, Bit D0 is not always 0 when output data is right justified, and Bit D6 is not always 0 when output data is left justified. Operation at any data rate of 800 Hz or lower also provides a valid LSB in all ranges and modes that changes according to the applied acceleration. DATAx0 REGISTER D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 0 OUTPUT DATA-WORD FOR ±12g, FULL-RESOLUTION MODE. OUTPUT DATA-WORD FOR ±1.5g, 10-BIT AND ±1.5g, FULL-RESOLUTION MODES. Figure 32. Data Formatting of Full-Resolution and ±1.5 g, 10-Bit Modes of Operation When Output Data Is Right Justified DATAx1 REGISTER DATAx0 REGISTER D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 0 MSB FOR ALL MODES OF OPERATION WHEN LEFT JUSTIFIED. LSB FOR ±1.5g, FULL-RESOLUTION AND ±1.5 g, 10-BIT MODES. LSB FOR ±3g, FULL-RESOLUTION MODE. LSB FOR ±6g, FULL-RESOLUTION MODE. LSB FOR ±12g, FULL-RESOLUTION MODE. 08791-146 FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0. ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT DATA IS LEFT JUSTIFIED. Figure 33. Data Formatting of Full-Resolution and ±1.5 g, 10-Bit Modes of Operation When Output Data Is Left Justified Rev. 0 | Page 27 of 32 08791-145 THE ±3g AND ±6g FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE ±1.5g AND ±12 g FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND BIT D3 OF THE DATAx1 REGISTER FOR ±3g AND ±6 g, RESPECTIVELY. ADXL312 NOISE PERFORMANCE The specification of noise shown in Table 1 corresponds to the best case noise of the ADXL312 in normal power operation (LOW_POWER bit = 0 in BW_RATE register, Address 0x2C). For normal power operation at data rates below 100 Hz, the noise of the ADXL312 is equivalent to the noise at 100 Hz ODR in LSBs. For data rates greater than 100 Hz, the noise increases roughly by a factor of √2 per doubling of the data rate. For example, at 400 Hz ODR, the noise on the x- and y-axes is typically less than 2.0 LSB rms and the noise on the z-axis is typically less than 3.0 LSB rms. For low power operation (LOW_POWER bit = 1 in BW_RATE register, Address 0x2C) the noise of the ADXL312 is constant for all valid data rates shown in Table 7. This value is typically less than 2.4 LSB rms for the x- and y-axes and typically less than 3.5 LSB rms for the z-axis. PERCENTAGE OF NORMALIZED NOISE (%) 10k X-AXIS Y-AXIS Z-AXIS ALLAN DEVIATION (µg) 1k 100 0.1 1 10 100 (s) 1k 10k AVERAGING PERIOD, Figure 34. Root Allan Deviation 130 Figure 34 shows the typical Allan deviation for the ADXL312. The 1/f corner of the device, as shown in this figure, is very low, allowing absolute resolution of approximately 100 μg (assuming there is sufficient integration time). The figure also shows that the noise density is 340 μg/√Hz for the x- and y-axes and 470 μg/√Hz for the z-axis. 120 X-AXIS Y-AXIS Z-AXIS 110 100 90 80 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE, VS (V) Figure 35. Normalized Noise vs. Supply Voltage, VS Rev. 0 | Page 28 of 32 08791-252 70 2.0 08791-251 10 0.01 ADXL312 AXES OF ACCELERATION SENSITIVITY AZ AY AX Figure 36. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis) XOUT = +1g YOUT = 0g ZOUT = 0g TOP GRAVITY XOUT = 0g YOUT = –1g ZOUT = 0g XOUT = 0g YOUT = +1g ZOUT = 0g TOP Figure 37. Output Response vs. Orientation to Gravity Rev. 0 | Page 29 of 32 08791-043 XOUT = –1g YOUT = 0g ZOUT = 0g XOUT = 0g YOUT = 0g ZOUT = +1g 08791-042 TOP TOP XOUT = 0g YOUT = 0g ZOUT = –1g ADXL312 SOLDER PROFILE SUPPLIER TP ≥ TC USER TP ≤ TC TC TC –5°C SUPPLIER tP USER tP TP MAXIMUM RAMP UP RATE = 3°C/s MAXIMUM RAMP DOWN RATE = 6°C/s TL tP TC –5°C TEMPERATURE tL TSMAX PREHEAT AREA TSMIN tS TIME 25°C TO PEAK TIME Figure 38: Recommended Soldering Profile Table 23: Recommended Soldering Profile 1 , 2 Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (tS) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous (TL) Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5°C of Actual Peak Temperature (tP) Ramp-Down Rate Time 25°C to Peak Temperature 1 2 Sn63/Pb37 Condition Pb-Free 3°C/second maximum 150°C 200°C 60 to 180 seconds 3°C/second 100°C 150°C 60 to 120 seconds 183°C 217°C 60 to 150 seconds 60 to 150 seconds 240°C + 0°C/−5°C 260°C + 0°C/−5°C 10 to 30 seconds 20 to 40 seconds 6°C/second maximum 6 minutes maximum 8 minutes maximum Based on JEDEC standard J-STD-020D.1 For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used. Rev. 0 | Page 30 of 32 08791-038 25 ADXL312 OUTLINE DIMENSIONS PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.30 0.25 0.18 25 24 32 1 PIN 1 INDICATOR 0.50 BSC EXPOSED PAD 3.70 3.60 SQ 3.50 17 8 16 9 TOP VIEW 1.55 1.45 1.35 0.45 0.40 0.35 BOTTOM VIEW 0.20 MIN SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.05 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-254-LJJD. Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_LQ] 5 mm × 5 mm Body, Thick Quad (CP-32-17) Dimensions shown in millimeters 5.34 mm 0.57 mm 0.30 mm 3.60 mm 0.30 mm 0.30 mm 0.50 mm Figure 40. Sample Solder Pad Layout (Land Pattern) Rev. 0 | Page 31 of 32 08791-038 12-03-2010-B ADXL312 ORDERING GUIDE Model1, 2 ADXL312WACPZ ADXL312WACPZ-RL ADXL312ACPZ ADXL312ACPZ-RL EVAL-ADXL312Z EVAL-ADXL312Z-M EVAL-ADXL312Z-S 1 2 Measurement Range ±1.5 g, ±3 g, ±6 g, ±12 g ±1.5 g, ±3 g, ±6 g, ±12 g ±1.5 g, ±3 g, ±6 g, ±12 g ±1.5 g, ±3 g, ±6 g, ±12 g Specified Voltage (V) 3.3 3.3 3.3 3.3 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_LQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_LQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_LQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_LQ] Evaluation Board Evaluation Board Evaluation Board Package Option CP-32-17 CP-32-17 CP-32-17 CP-32-17 Z = RoHS Compliant Part W = Qualified for Automotive Applications AUTOMOTIVE PRODUCTS The ADXL312W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08791-0-12/10(0) Rev. 0 | Page 32 of 32