ADXRS450

Preliminary Technical Data FEATURES Complete rate gyroscope on a single chip ±300°/sec angular rate sensing High vibration rejection over a wide frequency range Excellent 25°/hr null offset stability Internally temperature compensated 2000 g powered shock survivability SPI digital output with 16-bit data-word Low noise and low power 3.3 V and 5V operation −40°C to +105°C operation Ultra small, light, and RoHS compliant Two package options Low cost SOIC_CAV package for yaw rate (Z-axis) response Innovative ceramic vertical mount package, which can be oriented for pitch, roll, or yaw response High Performance, Digital Output Gyroscope ADXRS450 GENERAL DESCRIPTION The ADXRS450 is an angular rate sensor (gyroscope) intended for industrial, medical, instrumentation, stabilization, and other high performance applications. An advanced, differential, quad sensor design rejects the influence of linear acceleration, enabling the ADXRS450 to operate in exceedingly harsh environments where shock and vibration are present. The ADXRS450 utilizes an internal, continuous self-test architecture. The integrity of the electromechanical system is checked by applying a high frequency electrostatic force to the sense structure to generate a rate signal that can be differentiated from the baseband rate data and internally analyzed. The ADXRS450 is capable of sensing angular rate of up to ±300°/sec. Angular rate data is presented as a 16-bit word, as part of a 32-bit SPI message. The ADXRS450 is available in a cavity plastic 16-lead SOIC (SOIC_CAV) and an SMT-compatible vertical mount package (LCC_V), and is capable of operating across both a wide voltage range (3.3 V to 5 V) and temperature range (−40°C to +105°C). APPLICATIONS Rotation sensing medical applications Rotation sensing industrial and instrumentation High performance platform stabilization FUNCTIONAL BLOCK DIAGRAM CP5 VX HIGH VOLTAGE GENERATION ADXRS450 PDD LDO REGULATOR HV DRIVE CLOCK PHASE DIVIDER LOCKED LOOP AMPLITUDE DETECT BAND-PASS FILTER ALU REGISTERS/MEMORY DVDD AVDD DECIMATION FILTER TEMPERATURE CALIBRATION ADC 12 DEMOD SPI INTERFACE MOSI MISO SCLK CS Z-AXIS ANGULAR RATE SENSOR Q DAQ P DAQ Q FILTER ST CONTROL FAULT DETECTION DVSS PSS 08952-001 EEPROM AVSS Figure 1. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADXRS450 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Specifications..................................................................................... 3  Absolute Maximum Ratings............................................................ 4  Thermal Resistance ...................................................................... 4  Rate Sensitive Axis ........................................................................ 4  ESD Caution .................................................................................. 4  Pin Configurations and Function Descriptions ........................... 5  Typical Performance Characteristics ............................................. 7  Theory of Operation ........................................................................ 9  Continuous Self-Test .................................................................... 9  Applications Information .............................................................. 10  Calibrated Performance ............................................................. 10  Mechanical Considerations for Mounting .............................. 10  Preliminary Technical Data Applications Circuits ................................................................. 10  ADXRS450 Signal Chain Timing ............................................. 10  SPI Communication Protocol ....................................................... 12  Command/response ................................................................... 12  SPI Communications Characteristics...................................... 13  SPI Applications .......................................................................... 14  SPI Rate Data Format..................................................................... 19  Memory Map and Registers .......................................................... 20  Memory Map .............................................................................. 20  Memory Register Definitions ................................................... 21  Package Orientation and Layout information ............................ 23  Solder Profile .............................................................................. 25  Package Marking Codes ............................................................ 26  Outline Dimensions ....................................................................... 27  Ordering Guide .......................................................................... 28  Rev. PrA | Page 2 of 28 Preliminary Technical Data SPECIFICATIONS ADXRS450 Specification conditions @ TA = TMIN to TMAX, PDD = 5 V, angular rate = 0°/sec, bandwidth = 80 Hz ±1 g, continuous self-test on. Table 1. Parameter MEASUREMENT RANGE SENSITIVITY Nominal Sensitivity Sensitivity Tolerance Nonlinearity 1 Cross-Axis Sensitivity 2 NULL Null Accuracy NOISE PERFORMANCE Rate Noise Density LOW-PASS FILTER Cut-Off (−3dB) Frequency Group Delay 3 SHOCK AND VIBRATION IMMUNITY Sensitivity to Linear Acceleration Vibration Rectification SELF-TEST Magnitude Fault Register Threshold Sensor Data Status Threshold Frequency ST Low-Pass Filter −3 dB Frequency Group Delay3 SPI COMMUNICATIONS Clock Frequency Voltage Input High Voltage Input Low Output Voltage Low Output Voltage High Pull up Current MEMORY REGISTERS Temperature Sensor Value at 45°C Scale Factor Quad, ST, Rate, DNC Registers Scale Factor POWER SUPPLY Supply Voltage Quiescent Supply Current Turn-On Time TEMPERATURE RANGE 1 2 Test Conditions/Comments Full-scale range See Figure 2 Symbol FSR Min ±300 Typ Max ±400 Unit °/sec LSB/°/sec % % FSR rms % °/sec °/sec/√Hz Hz ms °/sec/g °/sec/g2 LSB LSB LSB Hz Hz ms MHz V V V V μA μA Best fit straight line 80 ±3 0.05 ±3 ±3 0.25 TA = 25°C f0/200, see Figure 6 f = 0 Hz DC to 5 kHz See Continuous Self-Test fLP tLP 0.015 80 4 0.03 0.003 2559 3.25 4.75 Compared to LOCST data Compared to LOCST data f0/32 f0/800, see Figure 7 2239 1279 fST 500 2 64 2879 3839 52 76 8.08 PDD + 0.3 PDD × 0.15 0.5 MOSI, CS, SCLK MOSI, CS SCLK MISO, current = 3 mA MISO, current = −2 mA CS, PDD = 3.3 V, CS = 0.75 × PDD CS, PDD = 5 V, CS = 0.75 × PDD See Memory Register Definitions 0.85 × PDD −0.3 PDD − 0.5 50 70 200 300 0 5 80 PDD IDD Power on to 0.5°/sec of final Independent of package type TMIN, TMAX 3.15 6.0 100 −40 5.25 10.0 +105 LSB LSB/°C LSB/°/sec V mA ms °C Maximum limit is guaranteed through ADI characterization. Cross-axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB). 3 Minimum and maximum limits are guaranteed by design. Rev. PrA | Page 3 of 28 ADXRS450 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) Supply Voltage (PDD) Output Short-Circuit Duration (Any Pin to Ground) Temperature Range Operating LCC_V Package SOIC_CAV Package Storage LCC_V Package SOIC_CAV Package Rating 2000 g 2000 g −0.3 V to +6.0 V Indefinite Preliminary Technical Data RATE SENSITIVE AXIS The ADXRS450 is available in two package options. The SOIC_CAV package configuration is for applications that require a Z-axis (yaw) rate sensing device. The device transmits a positive going LSB count for clockwise rotation about the axis normal to the package top. Conversely, a negative going LSB count is transmitted for counterclockwise rotation about the Z-zxis. The vertical mount package (LCC_V) option is for applications that require rate sensing in the axes parallel to the plane of the PCB (pitch and roll). The same principles of LSB count transmission for clockwise and counterclockwise rotation about the parallel axes apply to the LCC_V option. See Figure 2 for details. RATE AXIS Z-AXIS LONGITUDINAL AXIS −40°C to +125°C −40°C to +125°C −65°C to +150°C −40°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. + 7 1 + 7 1 VMP PACKAGE 8 08952-002 A1 ABCDEFG LATERAL AXIS RATE AXIS Figure 2. Rate Signal Increases with Clockwise Rotation THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, for a device soldered in a printed circuit board (PCB) for surface-mount packages. Table 3. Thermal Resistance Package Type 16-Lead SOIC_CAV 14-Lead Ceramic LCC_V θJA 191.5 185.5 θJC 25 23 Unit °C/W °C/W ESD CAUTION Rev. PrA | Page 4 of 28 Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DVDD RSVD RSVD CS MISO PDD PSS VX 1 2 3 4 5 6 7 8 16 15 14 ADXRS450 SCLK MOSI AVDD DVSS RSVD AVSS RSVD CP5 08952-003 ADXRS450 TOP VIEW (Not to Scale) 13 12 11 10 9 Figure 3. SOIC_CAV Pin Configuration Table 4. 14-Lead SOIC_CAV Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic DVDD RSVD NC CS MISO PDD PSS VX CP5 NC AVSS NC DVSS AVDD MOSI SCLK Description Digital Regulated Voltage. See Figure 21 for the applications circuit diagram. Reserved. This pin must be connected to DVSS. Reserved. This pin must be connected to DVSS. Chip Select. Master In/Slave Out. Supply Voltage. Switching Regulator Ground. High Voltage Switching Node. See Figure 21 for the applications circuit diagram. High Voltage Supply. See Figure 21 for the applications circuit diagram. Reserved. This pin must be connected to DVSS. Analog Ground. Reserved. This pin must be connected to DVSS. Digital Signal Ground. Analog Regulated Voltage. See Figure 21 for the applications circuit diagram. Master Out/Slave In. SPI Clock. Rev. PrA | Page 5 of 28 ADXRS450 RSVD MOSI DVSS PDD PSS CS VX 14 13 12 11 10 9 8 Preliminary Technical Data RSVD SCLK DVDD MISO AVDD 2 7 6 543 1 2 3 4 5 6 7 MISO SCLK RSVD AVSS AVDD DVDD CP5 TOP VIEW (Not to Scale) 08952-005 RSVD CS DVSS MOSI PSS Figure 4. LCC_V Pin Configuration PDD VX NC = NO CONNECT 8 9 10 11 12 13 AVSS 1 14 CP5 BACK VIEW (Not to Scale) Figure 5. LCC_V Pin Configuration, Horizontal Layout Table 5. 14_Lead LCC_V Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic AVSS AVDD MISO DVDD SCLK CP5 RSVD RSVD VX CS DVSS MOSI PSS PDD Description Analog Ground. Analog Regulated Voltage. See Figure 22 for the applications circuit diagram. Master In/Slave Out. Digital Regulated Voltage. See Figure 22 for the applications circuit diagram. SPI Clock. High Voltage Supply. See Figure 22 for the applications circuit diagram. Reserved. This pin must be connected to DVSS. Reserved. This pin must be connected to DVSS. High Voltage Switching Node. See Figure 22 for the applications circuit diagram. Chip Select. Digital Signal Ground. Master Out/Slave In. Switching Regulator Ground. Supply Voltage. Rev. PrA | Page 6 of 28 08952-037 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.18 0.16 ADXRS450 0.40 0.35 0.30 % OF POPULATION % OF POPULATION 0.14 0.12 0.10 0.08 0.06 0.04 0.02 08952-006 0.25 0.20 0.15 0.10 0.05 08952-009 0 –0.8 –2.0 –1.6 –1.2 –0.4 0.4 0.8 1.2 1.6 2.0 0 –2.0 0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 ERROR (°/sec) ERROR (°/sec) Figure 6. SOIC_CAV Null Error @ 25°C 0.30 0.30 Figure 9. LCC_V Null Error @ 25°C 0.25 0.25 % OF POPULATION 0.20 % OF POPULATION 0.20 0.15 0.15 0.10 0.10 0.05 0.05 08952-007 ERROR (°/sec) ERROR (°/sec) Figure 7. SOIC_CAV Null Drift over Temperature 0.25 Figure 10. LCC_V Null Drift over Temperature 0.25 0.20 % OF POPULATION % OF POPULATION 0.20 0.15 0.15 0.10 0.10 0.05 0.05 0 0.5 1.0 1.5 2.0 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 2.5 0 0 0 0.005 0.010 0.015 0.020 0.025 –0.030 –0.025 –0.020 –0.015 –0.010 08952-008 –0.005 0.030 3.0 CHANGE IN SENSITIVITY (%) CHANGE IN SENSITIVITY (%) Figure 8. SOIC_CAV Sensitivity Error @ 25°C Figure 11. LCC_V Sensitivity Error @ 25°C Rev. PrA | Page 7 of 28 08952-029 08952-010 0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 –3.0 0 1.0 1.5 2.0 2.5 –2.5 –2.0 –1.5 –1.0 –0.5 –3.0 –0.5 3.0 0 ADXRS450 0.30 Preliminary Technical Data 0.45 0.40 0.25 0.35 % OF POPULATION 0.20 % OF POPULATION 0.30 0.25 0.20 0.15 0.10 0.15 0.10 0.05 0.05 0 08952-030 DRIFT (%) CHANGE IN SENSITIVITY (%) Figure 12. SOIC_CAV Sensitivity Drift over Temperature 1 40 30 20 0.1 (g2/Hz) Figure 15. LCC_V Sensitivity Drift over Temperature 60 DUT1 DUT2 DUT AVERAGE (°/s) REF 50 INPUT ACCELERATION (g) 08952-035 08952-034 40 30 20 10 0 –10 –20 0.40 GYRO OUTPUT (°/s) 10 0 –10 –20 –30 0.01 08952-031 0.001 0 1k 2k 3k 4k 5k 6k VIBRATION FREQUENCY (Hz) –40 0.1 0.15 0.20 0.25 TIME (sec) 0.30 0.35 Figure 13. Typical Response to Random Vibration, 15 g rms, 50 Hz to 5 kHz 3 N = 16 2 2 3 Figure 16. Typical Shock Response N = 16 1 % ERROR (°/sec) 1 0 0 –1 –1 –2 –2 –30 –10 10 30 50 70 90 110 08952-032 –3 –50 –3 –50 –30 –10 10 30 50 70 90 110 DUT TEMPERATURE (°C) DUT TEMPERATURE (°C) Figure 14. Null Output over Temperature, Device Soldered on PCB Figure 17. Sensitivity over Temperature, Device Soldered to PCB Rev. PrA | Page 8 of 28 08952-033 0 0 1 2 –3 –2 –3 –2 –1 –1 1 2 0 3 3 Preliminary Technical Data THEORY OF OPERATION The ADXRS450 operates on the principle of a resonator gyroscope. Figure 18 shows a simplified version of one of four polysilicon sensing structures. Each sensing structure contains a dither frame that is electrostatically driven to resonance. This produces the necessary velocity element to produce a Coriolis force when experiencing angular rate. In the SOIC_CAV package, the ADXRS450 is designed to sense a Z-axis (yaw) angular rate; whereas the vertical mount package orients the device such that it can sense pitch or roll angular rate on the same PCB. When the sensing structure is exposed to angular rate, the resulting Coriolis force couples into an outer sense frame, which contains movable fingers that are placed between fixed pickoff fingers. This forms a capacitive pickoff structure that senses Coriolis motion. The resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. The quad sensor design rejects linear and angular acceleration, including external g-forces and vibration. This is achieved by mechanically coupling the four sensing structures such that external g-forces appear as common-mode signals that can be removed by the fully differential architecture implemented in the ADXRS450. ADXRS450 CONTINUOUS SELF-TEST The ADXRS450 gyroscope utilizes a complete electromechanical self test. An electrostatic force is applied to the gyroscope frame, resulting in a deflection of the capacitive sense fingers. This deflection is exactly equivalent to deflection that occurs as a result of external rate input. The output from the beam structure is processed by the same signal chain as a true rate output signal, providing complete coverage of both the electrical and mechanical components. The electromechanical self test is performed continuously during operation at a rate higher than the output bandwidth of the device. The self-test routine generates equivalent positive and negative rate deflections. This information can then be filtered with no overall effect on the demodulated rate output. RATE SIGNAL WITH CONTINUOUS SELF TEST SIGNAL. SELF TEST AMPLITUDE. INTERNALLY COMPARED TO THE SPECIFICATION TABLE LIMITS. LOW FREQUENCY RATE INFORMATION. Figure 19. Continuous Self-Test Demodulation X Y Z Figure 18. Simplified Gyroscope Sensing Structure The resonator requires 22.5 V (typical) for operation. Because only 5 V is typically available in most applications, a switching regulator is included on-chip. The difference amplitude between the positive and negative self-test deflections is filtered to 2 Hz, and continuously monitored and compared to hardcoded self-test limits. If the measured amplitude exceeds these limits (listed in Table 1), one of two error conditions is asserted depending on the magnitude of self-test error. For less severe self-test error magnitudes, the CST bit of the fault register is asserted; however, the status bits (ST[1:0]) in the sensor data response remain set to 0b01 for valid sensor data. For more severe self-test errors, the CST bit of the fault register is asserted and the status bits (ST[1:0]) in the sensor data response are set to 0b00 for invalid sensor data. The thresholds for both of these failure conditions are listed in Table 1. If desired, the user can access the self-test information by issuing a read command to the self-test memory register (Address 0x04). See the SPI Communication Protocol section for more information about error reporting. Rev. PrA | Page 9 of 28 08952-011 08952-012 ADXRS450 APPLICATIONS INFORMATION CALIBRATED PERFORMANCE Each ADXRS450 gyroscope uses internal EEPROM memory to store its temperature calibration information. The calibration information is encoded into the device during factory test. The calibration data is used to perform offset, gain, and self-test corrections over temperature. By storing this information internally, it removes the burden from the customer of performing system level temperature calibration. 1µF Preliminary Technical Data 1 DVDD RSVD RSVD GND CS MISO PDD SCLK 16 MOSI 1µF AVDD DVSS RSVD AVSS RSVD 100nF CP5 GND 08952-014 3.3V TO 5V 1µF PSS MECHANICAL CONSIDERATIONS FOR MOUNTING Mount the ADXRS450 in a location close to a hard mounting point of the PCB to the case. Mounting the ADXRS450 at an unsupported PCB location (that is, at the end of a lever, or in the middle of a trampoline), as shown in Figure 20, can result in apparent measurement errors, as the gyroscope is subject to the resonant vibration of the PCB. Locating the gyroscope near a hard mounting point helps to ensure that any PCB resonances at the gyroscope are above the frequency at which harmful aliasing with the internal electronics can occur. To ensure that aliased signals do not couple into the baseband measurement range, design the module wherein the first system level resonance occurs at a frequency higher than 800 Hz. GYROSCOPE PCB VX 470µH GND DIODE >24V BREAKDOWN Figure 21. Recommended Applications Circuit, SOIC_CAV Package 3.3V TO 5V TOP VIEW 1 AVSS 1µF AVDD MISO 1µF DVDD SCLK 100nF CP5 RSVD VX RSVD 470µH DVSS CS GND PSS MOSI PDD 1µF 14 GND 08952-013 MOUNTING POINTS APPLICATIONS CIRCUITS Figure 21 and Figure 22 show the recommended application circuits for the ADXRS450 gyroscope. These application circuits provide a connection reference for the available package types. Note that DVDD, AVDD, and PDD are all individually connected to ground through 1 μF capacitors; do not connect these supplies together. Additionally, an external diode and inductor must be connected for proper operation of the internal shunt regulator. These components allow for the internal resonator drive voltage to reach its required level, as listed in the Specifications section. Table 6. Component Inductor Diode Capacitor Capacitor Qty 1 1 3 1 Description 470 μH >24 V breakdown voltage 1 μF 100 nF DIODE >24V BREAKDOWN Figure 22. Recommended Applications Circuit, Ceramic LCC_V Package ADXRS450 SIGNAL CHAIN TIMING The ADXRS450 primary signal chain is shown in Figure 23. It is the series of necessary functional circuit blocks through which the rate data is generated and processed. This sequence of electromechanical elements determines how quickly the device is capable of translating an external rate input stimulus into an SPI word to be sent to the master device. The group delay, which is a function of the filter characteristic, is the time required for the output of the low-pass filter to be within 10% of the external rate input, and is seen to be ~4 ms. Additional delay can be observed due to the timing of SPI transactions and the population of the rate data into the internal device registers. Figure 23 anatomizes this delay, wherein the delay through each element of the signal chain is presented. Rev. PrA | Page 10 of 28 08952-015 Figure 20. Incorrectly Placed Gyroscope GND Preliminary Technical Data The transfer function for the Rate Data LPF is given as ADXRS450 The transfer function for the Continuous Self-Test LPF is given as 1 64 − 63Z −1 where: 16 T= = 1ms (typ) f0 ⎡ 1 − Z −64 ⎤ ⎢ −1 ⎥ ⎣ 1− Z ⎦ where: T= 2 1 1 = f 0 16 kHz (typ) PRIMARY SIGNAL CHAIN 4ms GROUP DELAY