ADZS-UCM3029EZLITE

Ultra Low Power Arm Cortex-M3 MCU with Integrated Power Management ADuCM3027/ADuCM3029 Data Sheet FEATURES Digital peripherals 3 SPI interfaces to enable glueless interface to sensors, radios, and converters I2C and UART interfaces SPORT for natively interfacing with converters and radios Programmable GPIOs (44 in LFCSP and 34 in WLCSP) 3 general-purpose timers with PWM support RTC and FLEX_RTC with SensorStrobe and time stamping Programmable beeper 25-channel DMA controller Clocking features 26 MHz clock: on-chip oscillator, external crystal oscillator 32 kHz clock: on-chip oscillator, low power crystal oscillator Integrated PLL with programmable divider Analog peripherals 12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital comparator EEMBC ULPMark™-CP score: 245.5 Ultra low power active and hibernate mode Active mode dynamic current: 30 μA/MHz (typical) Flexi mode: 300 μA (typical) Hibernate mode: 750 nA (typical) Shutdown mode: 60 nA (typical) ARM Cortex-M3 processor with MPU Up to 26 MHz with serial wire debug interface Power management Single-supply operation (VBAT): 1.74 V to 3.6 V Optional buck converter for improved efficiency Memory options 128 kB/256 kB of embedded flash memory with ECC 4 kB of cache memory to reduce active power 64 kB of configurable system SRAM with parity up to 32 kB of SRAM retained in hibernate mode Safety Watchdog with dedicated on-chip oscillator Hardware CRC with programmable polynomial Multiparity bit protected SRAM ECC protected embedded flash Security TRNG User code protection Hardware cryptographic accelerator supporting AES-128, AES-256, and SHA-256 APPLICATIONS Internet of Things (IoT) Electronic shelf label (ESL) and signage Smart infrastructure Smart lock Asset tracking Smart machine, smart metering, smart building, smart city, and smart agriculture Wearables Fitness and clinical Machine learning and neural network FUNCTIONAL BLOCK DIAGRAM 26MHz CORE RATE PLL SERIAL WIRE INSTRUCTION RAM/CACHE (32kB) HFXTAL LFXTAL ARM CORTEX-M3 HFOSC NVIC LFOSC REF BUFFER TEMPERATURE SENSOR ADC WIC MPU MULTILAYER AMBA BUS MATRIX SPORT SRAM0 (16kB) POWER MANAGEMENT BUCK SRAM1 (16kB) DMA CRYPTO (AES 128/256, SHA 256) FLASH (256kB) UART TMR0 TMR1 RTC0 RTC1 TMR2 TRNG BEEPER GPIO PROGRAMMABLE CRC POLYNOMIAL SPI SPI SPI I2C WDT 14168-001 AHB-APB BRIDGE Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved. Technical Support http://www.analog.com ADuCM3027/ADuCM3029 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ARM Cortex-M3 Processor ...................................................... 22 Applications ....................................................................................... 1 Memory Architecture ................................................................ 23 Functional Block Diagram .............................................................. 1 Cache Controller ........................................................................ 24 Revision History ............................................................................... 2 System and Integration Features .............................................. 24 General Description ......................................................................... 3 On-Chip Peripheral Features .................................................... 28 Product Highlights ....................................................................... 3 Development Support ................................................................ 29 Specifications..................................................................................... 4 Additional Information ............................................................. 29 Operating Conditions and Electrical Characteristics.............. 4 Reference Designs ...................................................................... 29 Embedded Flash Specifications .................................................. 4 MCU Test Conditions ................................................................ 29 Power Supply Current Specifications......................................... 5 Driver Types ................................................................................ 29 ADC Specifications ...................................................................... 7 EEMBC ULPMark™-CP Score .................................................. 30 System Clocks ............................................................................... 8 GPIO Multiplexing ......................................................................... 31 Timing Specifications .................................................................. 9 Applications Information .............................................................. 33 Absolute Maximum Ratings.......................................................... 15 About ADuCM3027/ADuCM3029 Silicon Anomalies ............ 36 Thermal Resistance .................................................................... 15 Functionality Issues.................................................................... 36 ESD Caution ................................................................................ 15 Outline Dimensions ....................................................................... 38 Pin Configuration and Function Descriptions ........................... 16 Ordering Guide .......................................................................... 39 Typical Performance Characteristics ........................................... 20 Theory of Operation ...................................................................... 22 REVISION HISTORY 5/2019—Rev. A to Rev. B Change to Features Section ............................................................. 1 Changes to General Description Section ...................................... 3 Change to VBAT_ADC Current (IVBAT_ADC) Parameter ,Table 7....... 7 Added Crystal Equivalent Series Resistance Parameter, Table 8 ..... 8 Change to SPT_CLK Period Parameter, Table 12 ........................ 9 Changes to Figure 5 and Figure 6 ................................................. 10 Changed Timer PWM_OUT Cycle Timing Section to Timer Pulse-Width Modulation (PWM) Output Cycle Timing Section ................................................................................ 14 Change to Figure 13 Caption ........................................................ 14 Change to Table 19 ......................................................................... 15 Changes to Figure 14 and Table 20............................................... 16 Changes to Figure 15 and Table 21............................................... 18 Changes to Figure 16 to Figure 19 ................................................ 20 Changes to Figure 20 and Figure 21 ............................................. 21 Change to MMRs (Peripheral Control and Status) Section ..... 23 Changes to Cache Controller Section and Booting Section ..... 24 Changes to Programmable GPIOs Section ................................. 26 Changes to I2C Section .................................................................. 28 Changes to Additional Information Section............................... 29 Changes to Figure 26...................................................................... 33 Changes to Figure 27...................................................................... 34 Changes to Figure 28...................................................................... 35 Added About ADuCM3027/ADuCM3029 Silicon Anomalies Section, Table 30, Table 31, and Table 32; Renumbered Sequentially ..................................................................................... 36 Added Table 33 ............................................................................... 37 Changes to Ordering Guide .......................................................... 39 12/2018—Revision A: Initial Version Rev. B | Page 2 of 39 Data Sheet ADuCM3027/ADuCM3029 GENERAL DESCRIPTION The ADuCM3027/ADuCM3029 microcontroller units (MCUs) are ultra low power microcontroller systems with integrated power management for processing, control, and connectivity. The MCU system is based on the ARM® Cortex®-M3 processor, a collection of digital peripherals, embedded SRAM and flash memory, and an analog subsystem which provides clocking, reset, and power management capability in addition to an analog-to-digital converter (ADC) subsystem. For a feature comparison across the ADuCM3027/ADuCM3029 product offerings, see Table 1. Table 1. Product Flash Memory Options Device ADuCM3029 ADuCM3027 Embedded Flash Memory Size 256 kB 128 kB • • • • • • • • • • • • • • • The ADuCM3029-1 and ADuCM3029-2 MCU models share the same features and functionality as that of the ADuCM3029 MCU. All specifications pertaining to the ADuCM3027 and ADuCM3029 are also applicable to the ADuCM3029-1 and ADuCM3029-2. For full details on the ADuCM3027/ADuCM3029 MCUs, refer to the ADuCM302x Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management Hardware Reference Manual. PRODUCT HIGHLIGHTS System features that are common across the ADuCM3027/ ADuCM3029/ADuCM3029-1/ADuCM3029-2 MCUs include the following: • • To support low dynamic and hibernate power management, the ADuCM3027/ADuCM3029 MCUs provide a collection of power modes and features, such as dynamic and software controlled clock gating and power gating. Up to 26 MHz ARM Cortex-M3 processor Up to 256 kB of embedded flash memory with error correction code (ECC) Optional 4 kB cache for lower active power 64 kB system SRAM with parity Power management unit (PMU) Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Beeper interface Serial port (SPORT), serial peripheral interface (SPI), inter-integrated circuit (I2C), and universal asynchronous receiver/transmitter (UART) peripheral interfaces Cryptographic hardware support with advanced encryption standard (AES) and secure hash algorithm (SHA)-256 Real-time clock (RTC) General-purpose and watchdog timers Programmable general-purpose input/output (GPIO) pins Hardware cyclic redundancy check (CRC) calculator with programmable generator polynomial Power-on reset (POR) and power supply monitor (PSM) 12-bit successive approximation register (SAR) ADC True random number generator (TRNG) 1. 2. 3. 4. 5. Rev. B | Page 3 of 39 Industry leading ultralow power consumption. Robust operation, including full voltage monitoring in deep sleep modes, ECC support on flash, and parity error detection on SRAM memory. Leading edge security. Fast encryption provides read protection to customer algorithms. Write protection prevents device reprogramming by unauthorized code. Failure detection of 32 kHz LFXTAL via interrupt. SensorStrobe™ for precise time synchronized sampling of external sensors. Works in hibernate mode, resulting in drastic current reduction in system solutions. Current consumption reduces by 10 times when using, for example, the ADXL363 accelerometer. Software intervention is not required after setup. No pulse drift due to software execution. ADuCM3027/ADuCM3029 Data Sheet SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS Table 2. Parameter EXTERNAL BATTERY SUPPLY VOLTAGE 1, 2 INPUT VOLTAGE High Level Low Level ADC SUPPLY VOLTAGE OUTPUT VOLTAGE 3 High Level Low Level INPUT CURRENT PULL-UP 4 High Level Low Level THREE-STATE LEAKAGE CURRENT High Level 5 Pull-Up 6 Pull-Down 7 Low Level5 Pull-Up6 Pull-Down7 INPUT CAPACITANCE JUNCTION TEMPERATURE Symbol VBAT Min 1.74 VIH VIL VBAT_ADC 2.5 VOH VOL 1.4 1.74 Typ 3.0 Max 3.6 Unit V Test Conditions/Comments V V V VBAT = 3.6 V VBAT = 1.74 V 3.0 0.45 3.6 0.4 V V VBAT = 1.74 V, IOH = −1.0 mA VBAT = 1.74 V, IOL = 1.0 mA IIHPU IILPU 0.01 0.2 100 µA µA VBAT = 3.6 V, VIN = 3.6 V VBAT =3.6 V, VIN = 0 V IOZH IOZHPU IOZHPD IOZL IOZLPU IOZLPD CIN TJ 0.01 0.15 0.30 100 0.15 100 0.15 µA µA µA µA µA µA pF °C VBAT = 3.6 V, VIN = 3.6 V VBAT = 3.6 V, VIN = 3.6 V VBAT = 3.6 V, VIN = 3.6 V VBAT = 3.6 V, VIN = 0 V VBAT = 3.6 V, VIN = 0 V VBAT = 3.6 V, VIN = 0 V TJ = 25°C TAMBIENT = -40°C to +85°C Unit Test Conditions/Comments 0.01 10 −40 +85 Value applies to VBAT_ANA1, VBAT_ANA2, VBAT_DIG1, and VBAT_DIG2 pins. Must remain powered (even if the associated function is not used). 3 Applies to the output and bidirectional pins: P0_00 to P0_15, P1_00 to P1_15, and P2_00 to P2_11. 4 Applies to the SYS_HWRST input pin with pull-up. 5 Applies to the three-state pins: P0_00 to P0_05, P0_08 to P0_15, P1_00 to P1_15, and P2_00 to P2_11. 6 Applies to the three-state pins with pull-ups: P0_00 to P0_05, P0_07 to P0_15, and P1_00 to P1_11. 7 Applies to the P0_06 three-state pin with pull-down. 1 2 EMBEDDED FLASH SPECIFICATIONS Table 3. Parameter FLASH Endurance Data Retention Symbol Min Typ 10,000 10 Rev. B | Page 4 of 39 Max Cycles Years Data Sheet ADuCM3027/ADuCM3029 POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Table 4. Parameter ACTIVE MODE 3 Buck Enabled Min Typ 1 Max 2 Unit Dynamic Current 0.40 0.98 1.28 0.95 1.08 2.71 1.29 1.64 1.36 1.43 1.37 1.78 1.08 30 1.75 2.34 1.78 1.99 1.49 2.55 3.29 2.03 60 2.74 8.05 3.0 2.48 2.67 Test Conditions/Comments Current consumption when VBAT = 3.0 V mA Code executing from flash, cache enabled, peripheral clocks off, HCLK = 6.5 MHz mA Code executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz mA Code executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz mA Code executing from SRAM, peripheral clocks off, HCLK = 26 MHz Code executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz, mA PCLK = 26 MHz Code executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz, mA PCLK = 26 MHz mA Code executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz µA/MHz Code executing from flash, cache enabled mA Code executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz mA Code executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz mA Code executing from SRAM, peripheral clocks off, HCLK = 26 MHz Code executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz, mA PCLK = 26 MHz Code executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz, mA PCLK = 26 MHz mA Code executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz µA/MHz Code executing from flash, cache enabled TJ = 25°C. TJ = 85°C. 3 The code being executed is a prime number generation in a continuous loop, with HFOSC as the system clock source. 1 2 Flexi Mode Table 5. Parameter FLEXI™ MODE Buck Enabled Buck Disabled 1 2 Min Typ 1 Max 2 Unit 0.3 0.39 0.52 0.7 0.67 0.80 1.11 1.38 mA mA mA mA Test Conditions/Comments Current consumption when VBAT = 3.0 V Peripheral clocks off Peripheral clocks on, PCLK = 26 MHz Peripheral clocks off Peripheral clocks on, PCLK = 26 MHz TJ = 25°C. TJ = 85°C. Rev. B | Page 5 of 39 ADuCM3027/ADuCM3029 Data Sheet Deep Sleep Modes—VBAT = 3.0 V Table 6. Parameter HIBERNATE MODE TJ = 25°C TJ = 85°C SHUTDOWN MODE 1 TJ = 25°C TJ = 85°C 1 Min Typ 0.75 0.77 0.79 0.81 0.78 0.83 0.93 2.0 2.4 2.6 3.0 2.05 2.1 2.25 0.31 0.056 0.49 0.26 Max Unit Test Conditions/Comments VBAT = 3.0V µA RTC1 and RTC0 disabled, 8 kB SRAM retained, LFXTAL off µA RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off µA RTC1 and RTC0 disabled, 24 kB SRAM retained, LFXTAL off µA RTC1 and RTC0 disabled, 32 kB SRAM retained, LFXTAL off µA RTC1 enabled, 8 kB SRAM retained, LFOSC as source for RTC1 µA RTC1 enabled, 8 kB SRAM retained, LFXTAL as source for RTC1 µA RTC1 and RTC0 enabled, 8 kB SRAM retained, LFXTAL as source for RTC1 and RTC0 6.05 µA RTC1 and RTC0 disabled, 8 kB SRAM retained, LFXTAL off 6.4 µA RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off 6.75 µA RTC1 and RTC0 disabled, 24 kB SRAM retained, LFXTAL off 7.1 µA RTC1 and RTC0 disabled, 32 kB SRAM retained, LFXTAL off 6.1 µA RTC1 enabled, 8 kB SRAM retained, LFOSC as source for RTC1 6.15 µA RTC1 enabled, 8 kB SRAM retained, LFXTAL as source for RTC1 6.3 µA RTC1 and RTC0 enabled, 8 kB SRAM retained, LFXTAL as source for RTC1 and RTC0 VBAT = 3.0 V µA RTC0 enabled, LFXTAL as source for RTC0 µA RTC0 disabled 1.180 µA RTC0 enabled, LFXTAL as source for RTC0 0.95 µA RTC0 disabled Buck enable/disable does not affect power consumption. Rev. B | Page 6 of 39 Data Sheet ADuCM3027/ADuCM3029 ADC SPECIFICATIONS Table 7. Parameter1, 2 INTEGRAL NONLINEARITY ERROR 64-Lead LFCSP 64-Lead LFCSP 54-Ball WLCSP DIFFERENTIAL NONLINEARITY ERROR 64-Lead LFCSP 64-Lead LFCSP 54-Ball WLCSP OFFSET ERROR 64-Lead LFCSP 64-Lead LFCSP 54-Ball WLCSP GAIN ERROR 64-Lead LFCSP 64-Lead LFCSP 54-Ball WLCSP VBAT_ADC CURRENT (IVBAT_ADC)5 64-Lead LFCSP 64-Lead LFCSP 54-Ball WLCSP INTERNAL REFERENCE VOLTAGE INTEGRAL NONLINEARITY ERROR 64-Lead LFCSP 64-Lead LFCSP 54-Ball WLCSP 54-Ball WLCSP ADC SAMPLING FREQUENCY (fS)8 Min 1.22 2.45 1.22 2.45 0.01 Typ3 Unit Test Conditions/Comments ±1.6 ±1.4 ±1.8 LSB LSB LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 3.0 V (VBAT)/2.5 V (internal/external VREF)4 1.8 V (VBAT)/1.25 V (internal/external VREF)4 −0.7 to +1.15 −0.7 to +1.1 −0.75 to +1.2 LSB LSB LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 3.0 V (VBAT)/2.5 V (internal/external VREF)4 1.8 V (VBAT)/1.25 V (internal/external VREF)4 ±0.5 ±0.5 ±0.5 LSB LSB LSB 1.8 V (VBAT)/1.25 V (external VREF)4 3.0 V (VBAT)/2.5 V (external VREF)4 1.8 V (VBAT)/1.25 V (external VREF)4 ±2.5 ±0.5 ±3.0 LSB LSB LSB 1.8 V (VBAT)/1.25 V (external VREF)4 3.0 V (VBAT)/2.5 V (external VREF)4 1.8 V (VBAT)/1.25 V (external VREF)4 104 131 108 1.25 2.50 μA μA μA V V 1.8 V (VBAT)/1.25 V (internal VREF)6 3.0 V (VBAT)/2.5 V (internal VREF)6 1.8 V (VBAT)/1.25 V (internal VREF)6 Internal reference, 1.25 V selected Internal reference, 2.5 V selected V V V V MSPS 1.25 V (internal)7 2.5 V (internal) 1.25 V (internal) 2.5 V (internal) 1.25 2.5 1.25 2.5 Max 1.275 2.545 1.275 2.545 1.8 1 The ADC is characterized in standalone mode without core activity and minimal or no switching on the adjacent ADC channels and digital inputs/outputs. The specifications are characterized after performing internal ADC offset calibration. TJ = 25°C. 4 fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode, 400,000 samples end point method used. 5 Current consumption from VBAT_ADC supply when ADC is performing the conversion. 6 fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode. 7 No load current, CL = 0.1 μF and 4.7 μF, reference buffer low power mode is enabled. 8 Effects of analog source impedance must be considered when selecting ADC sampling frequency. 2 3 Rev. B | Page 7 of 39 ADuCM3027/ADuCM3029 Data Sheet SYSTEM CLOCKS External Crystal Oscillator Specifications Table 8. Parameter LOW FREQUENCY EXTERNAL CRYSTAL OSCILLATOR (LFXTAL) Frequency External Capacitance from SYS_LFXTAL_IN Pin to Ground and from SYS_LFXTAL_OUT Pin to Ground Crystal Equivalent Series Resistance HIGH FREQUENCY EXTERNAL CRYSTAL OSCILLATOR (HFXTAL) Frequency External Capacitance from SYS_HFXTAL_IN Pin to Ground and from SYS_HFXTAL_OUT Pin to Ground Crystal Equivalent Series Resistance Symbol Min fLFXTAL CLFXTAL 6 Typ Max Unit 10 Hz pF 30 kΩ 20 MHz pF 50 Ω 32,768 ESRLFXTAL fHFXTAL CHFXTAL 26 ESRHFXTAL Test Conditions/Comments External capacitors on SYS_LFXTAL_IN and SYS_LFXTAL_OUT pins must be selected considering the printed circuit board (PCB) trace capacitance due to routing External capacitors on SYS_HFXTAL_IN and SYS_HFXTAL_OUT pins must be selected considering the PCB trace capacitance due to routing On-Chip RC Oscillator Specifications Table 9. Parameter LOW FREQUENCY RC OSCILLATOR (LFOSC) Frequency HIGH FREQUENCY RC OSCILLATOR (HFOSC) Frequency Symbol Min Typ Max Unit fLFOSC 30,800 32,768 34,407 Hz fHFOSC 25.09 26 26.728 MHz Symbol Min Typ Max Unit fPLLIN fPLLOUT fPCLK fHCLK 16 16 0.8125 0.8125 26 60 26 26 MHz MHz MHz MHz System Clocks and PLL Specifications Table 10. Parameter PLL SPECIFICATIONS PLL Input Clock Frequency1 PLL Output Clock Frequency2, 3 System Peripheral Clock (PCLK) Frequency Advanced High Performance Bus Clock (HCLK) Frequency 1 The input to the PLL can come from either the high frequency external crystal (HFXTAL), SYS_CLKIN pin or from the high frequency internal RC oscillator (HFOSC). For the maximum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 16, PLL_DIV2 = 1 for PLL input clock = 26 MHz; and PLL_MSEL = 13, PLL_NSEL = 26, PLL_DIV2 = 1 for PLL input clock = 16 MHz. 3 For the minimum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 30, PLL_DIV2 = 0 for PLL input clock = 26 MHz; and PLL_MSEL = 8, PLL_NSEL = 30, PLL_DIV2 = 0 for 16 MHz. 2 Rev. B | Page 8 of 39 Data Sheet ADuCM3027/ADuCM3029 TIMING SPECIFICATIONS Reset Timing Table 11. Parameter RESET TIMING REQUIREMENTS SYS_HWRST Asserted Pulse Width Low 1 1 Symbol Min tWRST 4 Typ Max Unit µs Applies after power-up sequence is complete. 14168-002 tWRST SYS_HWRST Figure 2. Reset Timing Serial Ports Timing Table 12. Parameter EXTERNAL CLOCK SERIAL PORTS Timing Requirements Frame Sync Setup Before SPT_CLK 1 Frame Sync Hold After SPT_CLK1 Receive Data Setup Before Receive SPT_CLK1 Receive Data Hold After SPT_CLK1 SPT_CLK Width 2 SPT_CLK Period2 Switching Characteristics 3 Frame Sync Delay After SPT_CLK Frame Sync Hold After SPT_CLK Transmit Data Delay After Transmit SPT_CLK Transmit Data Hold After Transmit SPT_CLK INTERNAL CLOCK SERIAL PORTS Timing Requirements1 Receive Data Setup Before SPT_CLK Receive Data Hold After SPT_CLK Switching Characteristics Frame Sync Delay After SPT_CLK 3 Frame Sync Hold After SPT_CLK 3 Transmit Data Delay After SPT_CLK3 Transmit Data Hold After SPT_CLK3 SPT_CLK Width SPT_CLK Period ENABLE AND THREE-STATE SERIAL PORTS Switching Characteristics Data Enable from Internal Transmit SPT_CLK3 Data Disable from Internal Transmit SPT_CLK3 Symbol Min tSFSE Unit Test Conditions/Comments 5 ns tHFSE 5 ns Externally generated frame sync in transmit or receive mode Externally generated frame sync in transmit or receive mode tSDRE tHDRE tSCLKW tSPTCLK 5 8 38.5 77 ns ns ns ns tDFSE Typ Max 20 ns tHOFSE 2 tDDTE tHDTE 1 ns ns tSDRI tHDRI 25 0 ns ns 20 tDFSI 20 tHOFSI −8 tDDTI tHDTI tSCLKIW tSPTCLK −7 tPCLK − 1.5 (2 × tPCLK) − 1 tDDTIN tDDTTI ns ns ns 20 5 160 ns ns ns ns Internally generated frame sync in transmit or receive mode Internally generated frame sync in transmit or receive mode Internally generated frame sync in transmit or receive mode Internally generated frame sync in transmit or receive mode Not shown in Figure 3 to Figure 7 ns ns This specification is referenced to the sample edge. This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK. 3 These specifications are referenced to the drive edge. 1 2 Rev. B | Page 9 of 39 ADuCM3027/ADuCM3029 Data Sheet DRIVE EDGE SAMPLE EDGE tSCLKIW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSI tHOFSI SPT_0AFS/SPT_0BFS (FRAME SYNC) tHDRI 14168-003 tSDRI SPT_AD0/SPT_BD0 (DATA CHANNEL A/B) Figure 3. Serial Ports (Data Receive Mode through Internal Clock) DRIVE EDGE SAMPLE EDGE tSCLKIW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSI tHOFSI SPT_0AFS/SPT_0BFS (FRAME SYNC) 14168-004 tDDTI tHDTI SPT_AD0/SPT_BD0 (DATA CHANNEL A/B) Figure 4. Serial Ports (Data Transmit Mode through Internal Clock) DRIVE EDGE SAMPLE EDGE tSCLKW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSE tHOFSE tSFSE tHFSE tSDRE tHDRE 14168-005 SPT0_AFS/SPT0_BFS (FRAME SYNC) SPT0_AD0/SPT0_BD0 (DATA CHANNEL A/B) Figure 5. Serial Ports (Data Receive Mode through External Clock) DRIVE EDGE SAMPLE EDGE tSCLKW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSE tHOFSE tSFSE tHFSE SPT_0AFS/SPT_0BFS (FRAME SYNC) 14168-006 tDDTE tHDTE SPT_AD0/SPT_BD0 (DATA CHANNEL A/B) Figure 6. Serial Ports (Data Transmit Mode through External Clock) Rev. B | Page 10 of 39 Data Sheet ADuCM3027/ADuCM3029 DRIVE EDGE DRIVE EDGE SPT0_ACLK/SPT0_BCLK (SPORT CLOCK INTERNAL) tDDTIN tDDTTI 14168-007 SPT0_AD0/SPT0/BD0 (DATA CHANNEL A/B) Figure 7. Enable and Three-State Serial Ports Rev. B | Page 11 of 39 ADuCM3027/ADuCM3029 Data Sheet SPI Timing Table 13. Parameter1 SPI MASTER MODE TIMING Timing Requirements Chip Select (CS) to Serial Clock (SCLK) Edge SCLK Low Pulse Width SCLK High Pulse Width Data Input Setup Time Before SCLK Edge Data Input Hold Time After SCLK Edge Switching Characteristics Data Output Valid After SCLK Edge Data Output Setup Before SCLK Edge CS High After SCLK Edge SPI SLAVE MODE TIMING Timing Requirements CS to SCLK Edge SCLK Low Pulse Width SCLK High Pulse Width Data Input Setup Time Before SCLK Edge Data Input Hold Time After SCLK Edge Switching Characteristics Data Output Valid After SCLK Edge Data Output Valid After CS Edge CS High After SCLK Edge Min Typ Max Unit tCS tSL tSH tDSU tDHD (0.5 × tPCLK) − 3 tPCLK − 3.5 tPCLK − 3.5 5 20 tDAV tDOSU tSFS tPCLK − 2.2 (0.5 × tPCLK) − 3 ns ns ns tCS tSL tSH tDSU tDHD 38.5 38.5 38.5 6 8 ns ns ns ns ns ns ns ns ns ns 25 tDAV tDOCS tSFS 20 20 ns ns ns 38.5 These specifications are characterized with respect to double drive strength. CS tSFS tCS SCLK (POLARITY = 0) tSH tSL SCLK (POLARITY = 1) tDAV MSB MOSI MSB IN MISO BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN 14168-008 1 Symbol tDSU tDHD Figure 8. SPI Master Mode Timing (Phase Mode = 1) Rev. B | Page 12 of 39 Data Sheet ADuCM3027/ADuCM3029 CS tSFS tCS SCLK (POLARITY = 0) tSH tSL SCLK (POLARITY = 1) tDAV tDOSU MOSI MSB BIT 6 TO BIT 1 BIT 6 TO BIT 1 tDSU LSB IN 14168-009 MSB IN MISO LSB tDHD Figure 9. SPI Master Mode Timing (Phase = 0) CS tSFS tCS SCLK (POLARITY = 0) tSH tSL SCLK (POLARITY = 1) tDAV MISO MSB MOSI BIT 6 TO BIT 1 LSB LSB IN BIT 6 TO BIT 1 14168-010 MSB IN tDSU tDHD Figure 10. SPI Slave Mode Timing (Phase Mode = 1) CS tSFS tCS SCLK (POLARITY = 0) tSH tSL SCLK (POLARITY = 1) tDAV tDOCS MOSI MSB MSB IN BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN 14168-011 MISO tDSU tDHD Figure 11. SPI Slave Mode Timing (Phase Mode = 0) Rev. B | Page 13 of 39 ADuCM3027/ADuCM3029 Data Sheet I2C Specifications Table 14. Parameter I2C SCLK FREQUENCY Standard Mode Fast Mode Symbol Min Typ Max Unit 100 400 kHz kHz General-Purpose Port Timing Table 15. Parameter TIMING REQUIREMENTS General-Purpose Port Pin Input Pulse Width Symbol Min tWFI 4 × tPCLK Typ Max Unit ns 14168-012 tWFI GPIO INPUT Figure 12. General-Purpose Timing RTC1 (FLEX_RTC) Specifications Table 16. Parameter SENSORSTROBE Minimum Output Frequency Maximum Output Frequency RTC1 ALARM Minimum Time Resolution Symbol Min Typ Max Unit 0.5 16.384 Hz kHz 30.52 µs Timer Pulse-Width Modulation (PWM) Output Cycle Timing Table 17. Symbol Min tPWMO (4 × tPCLK) − 6 PWM OUTPUTS tPWMO Figure 13. Timer PWM Output Cycle Timing Rev. B | Page 14 of 39 Typ Max Unit 256 × (216 − 1) ns 14168-013 Parameter SWITCHING REQUIREMENTS Timer Pulse Width Output Data Sheet ADuCM3027/ADuCM3029 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 18. Parameter Supply VBAT_ANA1, VBAT_ANA2, VBAT_ADC, VBAT_DIG1, VBAT_DIG2, and VREF_ADC Analog VDCDC_CAP1N, VDCDC_CAP1P, VDCDC_OUT, VDCDC_CAP2N, and VDCDC_CAP2P VLDO_OUT, SYS_HFXTAL_IN, SYS_ HFXTAL_OUT, SYS_LFXTAL_IN, and SYS_LFXTAL_OUT Digital Input/Output P0_xx, P1_xx, P2_xx, and SYS_HWRST Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJA can be used for a first-order approximation of TJ by the following equation: Rating −0.3 V to +3.6 V TJ = TA + (θJA × PD) −0.3 V to +1.32 V where: TJ is junction temperature (°C). TA is ambient temperature (°C). PD is power dissipation (to calculate power dissipation). −0.3 V to +3.6 V Package Type CP-64-16 −0.3 V to +3.6 V Table 19. Thermal Resistance Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. B | Page 15 of 39 θJA 26.3 θJC 1.0 Unit °C/W ADuCM3027/ADuCM3029 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 12 VBAT_ADC 8 6 11 9 7 VLDO_OUT VDCDC_ CAP2N VDCDC_ CAP1P 13 4 2 5 3 SYS_ LFXTAL_IN SYS_ HFXTAL_OUT 1 VBAT_ANA1 A VREF_ADC P2_03 SYS_ LFXTAL_OUT VDCDC_ CAP1N VDCDC_ CAP2P SYS_ HFXTAL_IN P0_00 B P2_05 GND_ VREFADC VDCDC_OUT VBAT_ANA2 P0_02 P0_03 P0_01 C P0_05 P2_06 P2_04 P1_10 P0_11 GND_ANA P0_10 D P0_06 P0_07 P0_04 SYS_HWRST GND_DIG P1_03 P1_02 E P1_07 P1_09 P1_08 P1_04 P1_05 P2_01 F VBAT_DIG1 P1_06 P2_11 P1_01 P0_15 P0_13 VBAT_DIG2 G P0_12 P0_09 P0_08 P1_14 P1_14 P1_00 BOTTOM VIEW (BALL SIDE UP) Not to Scale 14168-014 H Figure 14. ADuCM3027/ADuCM3029 54-Ball WLCSP Configuration Table 20. ADuCM3027/ADuCM3029 54-Ball WLCSP Pin Function Descriptions Pin No. A1 A3 A5 A7 A9 A11 Mnemonic VBAT_ANA1 SYS_HFXTAL_OUT SYS_LFXTAL_IN VDCDC_CAP1P VDCDC_CAP2N VLDO_OUT Signal Name Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable A13 B1 B3 B5 B7 B9 B11 B13 C1 VBAT_ADC P0_00 SYS_HFXTAL_IN SYS_LFXTAL_OUT VDCDC_CAP1N VDCDC_CAP2P VREF_ADC P2_03 P0_03 C3 C5 C7 P0_01 P0_02 VBAT_ANA2 Not Applicable SPI0_CLK/SPT0_BCLK/GPIO00 Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable ADC0_VIN0/GPIO35 SPI0_CS0/SPT0_BCNV/ SPI2_RDY/GPIO03 SPI0_MOSI/SPT0_BFS/GPIO01 SPI0_MISO/SPT0_BD0/GPIO02 Not Applicable Description External Supply for Analog Circuits in the MCU. High Frequency Crystal Output. High Frequency Crystal Input. Buck Converter Capacitor 1 Positive Terminal. Buck Converter Capacitor 2 Negative Terminal. Low Drop Out Regulator Output. This pin is only for connecting the decoupling capacitor. Do not connect this pin to the external load. External Supply for Internal ADC. GPIO. See the GPIO Multiplexing section for more information. High Frequency Crystal Input. Low Frequency Crystal Output. Buck Converter Capacitor 1 Negative Terminal. Buck Converter Capacitor 2 Positive Terminal. External Reference Voltage for Internal ADC. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. External Supply for Analog Circuits in the MCU. Rev. B | Page 16 of 39 Data Sheet ADuCM3027/ADuCM3029 Pin No. C9 Mnemonic VDCDC_OUT Signal Name Not Applicable C11 C13 D1 D3 GND_VREFADC P2_05 P0_10 P1_10 D5 D7 D9 D11 D13 E1 E3 E5 E7 E9 E11 E13 F2 F4 F6 F8 F10 F12 G1 G3 G5 G7 G9 G11 P0_11 GND_ANA P2_04 P2_06 P0_05 P1_03 P1_02 GND_DIG SYS_HWRST P0_04 P0_07 P0_06 P2_01 P1_05 P1_04 P1_09 P1_08 P1_07 VBAT_DIG2 P0_15 P0_13 P1_01 P1_06 P2_11 G13 H2 H4 H6 H8 H10 H12 VBAT_DIG1 P1_00 P0_14 P1_14 P0_08 P0_09 P0_12 Not Applicable ADC0_VIN2/GPIO37 UART0_TX/GPIO10 SPI0_CS1/SYS_CLKIN/ SPI1_CS3/GPIO26 UART0_RX/GPIO11 Not Applicable ADC0_VIN1/GPIO36 ADC0_VIN3/GPIO38 I2C0_SDA/GPIO05 SPI2_MOSI/GPIO19 SPI2_CLK/GPIO18 Not Applicable Not Applicable I2C0_SCL/GPIO04 GPIO07/SWD0_DATA GPIO06/SWD0_CLK XINT0_WAKE3/TMR2_OUT/GPIO33 SPI2_CS0/GPIO21 SPI2_MISO/GPIO20 SPI1_CS0/GPIO25 SPI1_MISO/GPIO24 SPI1_MOSI/GPIO23 Not Applicable XINT0_WAKE0/GPIO15 XINT0_WAKE2/GPIO13 GPIO17/SYS_BMODE0 SPI1_CLK/GPIO22 SPI1_CS1/SYS_CLKOUT/GPIO43/ RTC1_SS1 Not Applicable XINT0_WAKE1/GPIO16 TMR0_OUT/SPI1_RDY/GPIO14 SPI0_RDY/GPIO30 BPR0_TONE_N/GPIO08 BPR0_TONE_P/SPI2_CS1/GPIO09 SPT0_AD0/GPIO12/ UART0_SOUT_EN Description Buck Converter Output. This pin is only for connecting the decoupling capacitor. Do not connect this pin to the external load. Ground for Internal ADC. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. Ground Reference for Analog Circuits in the MCU. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. Ground Reference for Digital Circuits in the MCU. Hardware Reset Pin. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. External Supply for Digital Circuits in the MCU. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. External Supply for Digital Circuits in the MCU. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. GPIO. See the GPIO Multiplexing section for more information. Rev. B | Page 17 of 39 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND_ANA P0_00 P0_01 P0_02 P0_03 P1_10 P0_10 P0_11 P1_02 P1_03 P1_04 P1_05 P2_01 P0_13 P0_15 VBAT_DIG2 ADuCM3027/ADuCM3029 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ADuCM3027/ADuCM3029/ ADuCM3029-1/ADuCM3029-2 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND_DIG P1_00 P0_14 P2_02 P1_14 P1_13 P1_12 P1_11 P0_08 P0_09 P1_01 P1_15 P2_00 P0_12 VBAT_DIG1 P2_11 NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE GROUNDED. 14168-015 P2_04 P2_05 P2_06 P2_07 P2_08 P2_09 P2_10 P0_05 SYS_HWST P0_04 P0_07 P0_06 P1_09 P1_08 P1_07 P1_06 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VBAT_ANA1 SYS_HFXTAL_IN SYS_HFXTAL_OUT SYS_LFXTAL_IN SYS_LFXTAL_OUT VDCDC_CAP1N VDCDC_CAP1P VBAT_ANA2 VDCDC_OUT VDCDC_CAP2N VDCDC_CAP2P VLDO_OUT VREF_ADC VBAT_ADC GND_VREFADC P2_03 Figure 15. ADuCM3027/ADuCM3029/ADuCM3029-1/ADuCM3029-2 64-Lead LFCSP Configuration Table 21. ADuCM3027/ADuCM3029/ADuCM3029-1/ADuCM3029-2, 64-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic VBAT_ANA1 SYS_HFXTAL_IN SYS_HFXTAL_OUT SYS_LFXTAL_IN SYS_LFXTAL_OUT VDCDC_CAP1N VDCDC_CAP1P VBAT_ANA2 VDCDC_OUT Signal Name Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable 10 11 12 VDCDC_CAP2N VDCDC_CAP2P VLD0_OUT Not applicable Not applicable Not applicable 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VREF_ADC VBAT_ADC GND_VREFADC P2_03 P2_04 P2_05 P2_06 P2_07 P2_08 P2_09 P2_10 P0_05 SYS_HWRST P0_04 P0_07 P0_06 Not applicable Not applicable Not applicable ADC0_VIN0/GPIO35 ADC0_VIN1/GPIO36 ADC0_VIN2/GPIO37 ADC0_VIN3/GPIO38 ADC0_VIN4/SPI2_CS3/GPIO39 ADC0_VIN5/SPI0_CS2/GPIO40 ADC0_VIN6/SPI0_CS3/GPIO41 ADC0_VIN7/SPI2_CS2/GPIO42 I2C0_SDA/GPIO05 Not applicable I2C0_SCL/GPIO04 GPIO07/SWD0_DATA GPIO06/SWD0_CLK Description External Supply for Analog Circuits in the MCU. High Frequency Crystal Input. High Frequency Crystal Output. Low Frequency Crystal Input. Low Frequency Crystal Output. Buck Converter Capacitor 1 Negative Terminal. Buck Converter Capacitor 1 Positive Terminal. External Supply for Analog Circuits in the MCU Buck Converter Output. This pin is only for connecting the decoupling capacitor. Do not connect this pin to the external load. Buck Converter Capacitor 2 Negative Terminal. Buck Converter Capacitor 2 Positive Terminal. Low Drop Out Regulator Output. This pin is only for connecting the decoupling capacitor. Do not connect this pin to the external load. External Reference Voltage for Internal ADC. External Supply for Internal ADC. Ground for Internal ADC. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. Hardware Reset Pin. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. Rev. B | Page 18 of 39 Data Sheet Pin No. 29 30 31 32 33 Mnemonic P1_09 P1_08 P1_07 P1_06 P2_11 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 VBAT_DIG1 P0_12 P2_00 P1_15 P1_01 P0_09 P0_08 P1_11 P1_12 P1_13 P1_14 P2_02 P0_14 P1_00 GND_DIG VBAT_DIG2 P0_15 P0_13 P2_01 P1_05 P1_04 P1_03 P1_02 P0_11 P0_10 P1_10 60 P0_03 61 62 63 64 P0_02 P0_01 P0_00 GND_ANA EPAD ADuCM3027/ADuCM3029 Signal Name SPI1_CS0/GPIO25 SPI1_MISO/GPIO24 SPI1_MOSI/GPIO23 SPI1_CLK/GPIO22 SPI1_CS1/SYS_CLKOUT/GPIO43/ RTC1_SS1 Not applicable SPT0_AD0/GPIO12 SPT0_AFS/GPIO32 SPT0_ACLK/GPIO31 GPIO17/SYS_BMODE0 BPR0_TONE_P/SPI2_CS1/GPIO09 BPR0_TONE_N/GPIO08 TMR1_OUT/GPIO27 GPIO28 GPIO29 SPI0_RDY/GPIO30 SPT0_ACNV/SPI1_CS2/GPIO34 TMR0_OUT/SPI1_RDY/GPIO14 XINT0_WAKE1/GPIO16 Not applicable Not applicable XINT0_WAKE0/GPIO15 XINT0_WAKE2/GPIO13 XINT0_WAKE3/TMR2_OUT/GPIO33 SPI2_CS0/GPIO21 SPI2_MISO/GPIO20 SPI2_MOSI/GPIO19 SPI2_CLK/GPIO18 UART0_RX/GPIO11 UART0_TX/GPIO10 SPI0_CS1/SYS_CLKIN/SPI1_CS3/ GPIO26 SPI0_CS0/SPT0_BCNV/SPI2_RDY/ GPIO03 SPI0_MISO/SPT0_BD0/GPIO02 SPI0_MOSI/SPT0_BFS/GPIO01 SPI0_CLK/SPT0_BCLK/GPIO00 Not applicable Description GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. External Supply for Digital Circuits in the MCU. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. Ground Reference for Digital Circuits in the MCU. External Supply for Digital Circuits in the MCU. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. GPIO. See the GPIO Multiplexing section. Ground Reference for Analog Circuits in the MCU. Exposed Pad. The exposed pad must be grounded. Rev. B | Page 19 of 39 ADuCM3027/ADuCM3029 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Figure 16 through Figure 21 show the typical current voltage characteristics for the output drivers of the MCU. The curves represent the current drive capability of the output drivers as a function of output voltage. VOH (V) VOH (V) 1.4 1.5 1.6 2.70 5 1.8 1.7 5 SOURCE/SINK VBAT CURRENT (mA) SOURCE/SINK VBAT CURRENT (mA) 2 1 0 –1 –2 VOL TYPE A VOL TYPE B VOL TYPE C VOL TYPE D –3 –4 2.85 2.90 4 VOH TYPE A VOH TYPE B VOH TYPE C VOH TYPE D 3 2.80 3.00 VOH TYPE A VOH TYPE B VOH TYPE C VOH TYPE D 3 2 1 0 –1 –2 VOL TYPE A VOL TYPE B VOL TYPE C VOL TYPE D –3 –4 VOL, VBAT = 3.0V VOL, VBAT = 1.74V 0 0.1 0.2 0.3 0.4 0.6 0.5 VOL (V) 14168-016 –5 –5 Figure 16. Output Double Drive Strength Characteristics (VBAT = 1.74 V) 0.05 0 0.10 0.15 1.3 1.4 0.20 VOH (V) 1.5 1.6 1.7 2.75 2.5 2.80 2.85 2.90 VOH, VBAT = 1.74V 2.0 2.0 1.0 SOURCE/SINK VBAT CURRENT (mA) 1.5 0.5 0 –0.5 VOL TYPE A VOL TYPE B VOL TYPE C VOL TYPE D –2.0 2.95 3.00 VOH, VBAT = 3.0V VOH TYPE A VOH TYPE B VOH TYPE C VOH TYPE D –1.5 0.30 Figure 18. Output Double Drive Strength Characteristics (VBAT = 3.0 V) 2.5 –1.0 0.25 VOL (V) VOH (V) 1.2 SOURCE/SINK VBAT CURRENT (mA) 2.95 VOH, VBAT = 3.0V VOH, VBAT = 1.74V 4 2.75 14168-018 1.3 VOH TYPE A VOH TYPE B VOH TYPE C VOH TYPE D 1.5 1.0 0.5 0 –0.5 VOL TYPE A VOL TYPE B VOL TYPE C VOL TYPE D –1.0 –1.5 –2.0 VOL, VBAT = 1.74V VOL, VBAT = 3.0V 0 0.1 0.2 0.3 VOL (V) 0.4 0.5 0.6 14168-017 –2.5 –2.5 Figure 17. Output Single Drive Strength Characteristics (VBAT = 1.74 V) Rev. B | Page 20 of 39 0 0.05 0.10 0.15 0.20 0.25 VOL (V) Figure 19. Output Single Drive Strength Characteristics (VBAT = 3.0 V) 14168-019 1.2 Data Sheet ADuCM3027/ADuCM3029 VOH (V) 3.35 3.40 VOH (V) 3.45 3.50 3.55 3.60 3.38 2.5 3.40 3.42 3.44 3.46 3.48 3.50 VOH, VBAT = 3.6V 2.0 VOH TYPE A VOH TYPE B VOH TYPE C VOH TYPE D 3 2 SOURCE/SINK VBAT CURRENT (mA) SOURCE/SINK VBAT CURRENT (mA) 4 1 0 –1 –2 VOL TYPE A VOL TYPE B VOL TYPE C VOL TYPE D –3 –4 3.56 3.58 1.0 0.5 0 –0.5 –1.0 VOL TYPE A VOL TYPE B VOL TYPE C VOL TYPE D –1.5 VOL, VBAT = 3.6V 0.10 0.15 VOL (V) 0.20 0.25 14168-020 0.05 3.54 VOH TYPE A VOH TYPE B VOH TYPE C VOH TYPE D 1.5 –2.0 VOL, VBAT = 3.6V –5 0 3.52 VOH, VBAT = 3.6V Figure 20. Output Double Drive Strength Characteristics (VBAT = 3.6 V) Rev. B | Page 21 of 39 –2.5 0 0.05 0.10 0.15 0.20 0.25 VOL (V) Figure 21. Output Single Drive Strength Characteristics (VBAT = 3.6 V) 14168-021 3.30 5 ADuCM3027/ADuCM3029 Data Sheet THEORY OF OPERATION ARM CORTEX-M3 PROCESSOR Code Region The ARM Cortex-M3 core is a 32-bit reduced instruction set computer (RISC). The length of the data can be 8 bits, 16 bits, or 32 bits. The length of the instruction word is 16 bits or 32 bits. The processor has the following features: Accesses in this region (0x0000 0000 to 0x0001 FC00 for the ADuCM3027 and 0x0000 0000 to 0x0003 FFFF for the ADuCM3029) are performed by the core and target the memory and cache resources.  SRAM Region   Cortex-M3 architecture  Thumb-2 instruction set architecture (ISA) technology  Three-stage pipeline with branch speculation  Low latency interrupt processing with tail chaining  Single-cycle multiply  Hardware divide instructions  Nested vectored interrupt controller (NVIC) (64 interrupts and 8 priorities)  Two hardware breakpoints and one watchpoint (unlimited software breakpoints using Segger JLink) Memory protection unit (MPU)  Eight region MPU with subregions and background region  Programmable clock generator unit Configurable for ultra low power operation  Deep sleep mode, dynamic power management  Programmable clock generator unit ARM Cortex-M3 Memory Subsystem Accesses in this region (0x2000 0000 to 0x2004 7FFF) are performed by the ARM Cortex-M3 core. The SRAM region of the core can otherwise act as a data region for an application.    System Region Accesses in this region (0xE000 0000 to 0xF7FF FFFF) are performed by the ARM Cortex-M3 core and are handled within the Cortex-M3 platform.  The memory map of the ADuCM3027/ADuCM3029 is based on the Cortex-M3 model from ARM. By retaining the standardized memory mapping, it is easier to port applications across M3 platforms. Internal SRAM data region. This space can contain read/write data. Internal SRAM can be partitioned between code and data (SRAM region in M3 space) in 32 kB blocks. Access to this region occurs at core clock speed with no wait states. It also supports read/write access by the ARM Cortex-M3 core and read/write DMA access by system devices. It supports exclusive memory accesses via the global exclusive access monitor within the Cortex-M3 platform. System memory mapped registers (MMRs). Various system MMRs reside in this region.  The ADuCM3027/ADuCM3029 application development is based on memory blocks across code/SRAM regions. Internal memory is available via internal SRAM and internal flash. Rev. B | Page 22 of 39 CoreSight™ ROM. The read-only memory (ROM) table entries point to the debug components of the processor. ARM APB Peripheral. This space is defined by ARM and occupies the bottom 256 kB/128 kB of the system (SYS) region (0xE000 0000 to 0xE004 0000) depending on the device used. The space supports read/write access by the M3 core to the internal peripherals of the ARM core (NVIC, system control space (SCS), wake-up interrupt controller (WIC)), and CoreSight ROM. It is not accessible by system DMA. Data Sheet ADuCM3027/ADuCM3029 MEMORY ARCHITECTURE MMRs (Peripheral Control and Status) The internal memory of the ADuCM3027/ADuCM3029 is shown in Figure 22. The internal memory incorporates up to 256 kB of embedded flash memory for program code and nonvolatile data storage, 32 kB of data SRAM, and 32 kB of SRAM (configured as instruction space or data space). For the address space containing MMRs, refer to Figure 22. These registers provide control and status for on-chip peripherals of the ADuCM3027/ADuCM3029. For more information about the MMRs, refer to the ADuCM302x Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management Hardware Reference. SRAM Region This memory space contains the application instructions and literal (constant) data that must be accessed in real-time. It supports read/write access by the ARM Cortex-M3 core and read/write DMA access by system peripherals. Byte, half-word, and word accesses are supported. SRAM is divided into 32 kB data SRAM and 32 kB instruction SRAM. If instruction SRAM is not enabled, then the associated 32 kB can be mapped as data SRAM, resulting in 64 kB of data SRAM. Parity bit error detection (optional) is available on all SRAM memories. Two parity bits are associated with each 32-bit word. When the cache controller is enabled, 4 kB of the instruction SRAM is reserved as cache memory. Flash Memory The ADuCM3027/ADuCM3029 MCUs include 128 kB to 256 kB of embedded flash memory, which is accessed using a flash controller. For memory available on each product, see Table 1. The flash controller is coupled with a cache controller. A prefetch mechanism is implemented in the flash controller to optimize code performance. Flash writes are supported by a key hole mechanism via advanced peripheral bus (APB) writes to MMRs. The flash controller provides support for DMA-based key hole writes. With respect to flash integrity, the devices support the following:  Users can select the SRAM configuration modes depending on the instruction SRAM and cache needed.  In hibernate mode, 8 kB to 32 kB of the SRAM can be retained in increments of 8 kB. 8 kB of data SRAM is always retained. Users can additionally retain    16 kB out of 32 kB of instruction SRAM 8 kB out of 32 kB of data SRAM  Rev. B | Page 23 of 39 A fixed user key required for running protected commands, including mass erase and page erase. An optional and user definable user failure analysis key (FAA key). Analog Devices personnel need this key while performing failure analysis. An optional and user definable write protection for user accessible memory. 8-bit ECC. ADuCM3027/ADuCM3029 Data Sheet 0x4001 0FE0 0x4001 0000 0x4000 1000 0x4000 0824 0x4000 0800 0x4000 0424 0x4000 0400 0x4000 0424 0x4000 0400 RESERVED 0x4000 70C4 REAL-TIME CLOCK 0 (RTC 0) 0x4000 7000 RESERVED 0x4000 5C0C GENERAL-PURPOSE TIMER 2 0x4000 5C00 0x2004 0000 0x2000 3FFF 0x2000 0000 0x0003 FFFC 0x0000 0000 POWER MGT, EXT IRQ, CLOCKING, MISC MMR 0x4004 C000 RESERVED 0x4004 406C BEEPER 0 0x4004 4000 RESERVED RESERVED 0x4000 5030 GENERAL-PURPOSE TIMER 1 0x4000 5000 RESERVED 0x4000 4438 GENERAL-PURPOSE TIMER 0 0x4000 4400 0x4004 0414 UART 0 0x4004 0400 RESERVED 0x4000 3058 0x4000 3000 0x4000 2C18 INSTRUCTION SRAM (32kB) 0x4000 2C00 I2C 0 MASTER/SLAVE RESERVED 0x4000 2040 0x4000 2000 SYSTEM ID AND DEBUG ENABLE 0x4002 00B4 0x4002 0000 SPIH 0 MASTER/SLAVE GPIO RESERVED 0x4001 8088 0x4001 8000 RESERVED 0x4000 1444 0x4002 4038 0x4002 4000 RESERVED WATCHDOG TIMER RESERVED 256kB FLASH MEMORY SPORT 0 RESERVED RESERVED RESERVED 0x4003 8078 0x4003 8000 RESERVED RAM BANK 0 (16kB) PROGRAMMABLE CRC ENGINE RESERVED SPI 0 MASTER/SLAVE 0x4000 4000 0x4004 000C 0x4004 0000 RESERVED RAM BANK 1 (16kB) RANDOM NUMBER GENERATOR RESERVED SPI 1 MASTER/SLAVE 0x4000 4038 CRYPTO RESERVED RESERVED 0x1000 7FFF 0x1000 0000 RESERVED 0x4004 C80C RESERVED RESERVED 0x2004 3FFF 0x400F FFFF ADC0 FLASH CONTROLLER RESERVED REAL-TIME CLOCK 1 (RTC1) 0x4000 1400 14168-022 0x4000 1044 DMA0 RESERVED Figure 22. ADuCM3027/ADuCM3029 Memory Map—SRAM Mode 0 Table 22. Boot Modes CACHE CONTROLLER The ADuCM3027/ADuCM3029 MCUs have an optional 4 kB instruction cache. In certain applications, enabling the cache and executing the code can result in lower power consumption rather than operating directly from flash. When enabling the cache controller, 4 kB of instruction SRAM is reserved as cache memory. In hibernate mode, the cache memory is not retained. SYSTEM AND INTEGRATION FEATURES The ADuCM3027/ADuCM3029 MCUs provide several features that ease system integration. Reset There are four types of resets: external, power-on, watchdog timeout, and software system reset. The software system reset is provided as part of the ARM Cortex-M3 core. The SYS_HWRST pin is toggled to perform a hardware reset. Booting The ADuCM3027/ADuCM3029 MCUs support two boot modes: booting from internal flash and upgrading software through UART download. If SYS_BMODE0 (Pin P1_01) is pulled low during power-up or a hard reset, the MCU enters into serial download mode. In serial download mode, an on-chip routine initiates in the kernel, which configures the UART port and communicates with the host to manage the firmware upgrade via a specific serial download protocol. Boot Mode 0 1 Description UART download mode. Flash boot. Boot from integrated flash memory. Power Management The ADuCM3027/ADuCM3029 MCUs have an integrated power management system that optimizes performance and extends battery life of the devices. The power management system consists of the following: • • Integrated 1.2 V low dropout regulator (LDO) and optional capacitive buck regulator Integrated power switches for low standby current in hibernate and shutdown modes. Additional power management features include the following: • • • • • • Customized clock gating for active and Flexi™ modes Power gating to reduce leakage in hibernate and shutdown modes Flexible sleep modes Shutdown mode with no retention Optional high efficiency buck converter to reduce power Integrated low power oscillators Power Modes The PMU provides control of the ADuCM3027/ADuCM3029 power modes and allows the ARM Cortex-M3 to control the clocks and power gating to reduce the power consumption. Rev. B | Page 24 of 39 Data Sheet ADuCM3027/ADuCM3029 Several power modes are available. Each mode provides an additional low power benefit with a corresponding reduction in functionality. VBAT VDCDC_CAP1P VDCDC_CAP1N BUCK ENABLED Active Mode 0.1µF VDCDC_OUT 0.47µF VDCDC_CAP2P In active mode, all peripherals can be enabled. Active power is managed by optimized clock management. See Table 4 for details on active mode power. VDCDC_CAP2N Flexi Mode 0.1µF VLDO_OUT 0.47µF LDO NOTES 1. FOR DESIGNS IN WHICH THE OPTIONAL BUCK IS NOT USED, THE FOLLOWING PINS MUST BE LEFT UNCONNECTED: VDCDC_CAP1P, VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, AND VDCDC_CAP2N Hibernate Mode Figure 23. Buck Enabled Design This mode provides state retention, configurable SRAM and port pin retention, a limited number of wake-up interrupts (XINT0_WAKEn and UART0_RX), and, optionally, two RTCs—RTC0 and RTC1 (FLEX_RTC). For designs in which the optional buck is not used, the following pins must be left unconnected: VDCDC_CAP1P, VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, and VDCDC_CAP2N. Shutdown Mode Security Features This mode is the deepest sleep mode, in which all the digital and analog circuits are powered down with an option to wake from four possible wake-up sources: three external interrupts and RTC0. The RTC0 can be optionally enabled in this mode and the device can be periodically woken up by the RTC0 interrupt. See Table 6 for deep sleep (hibernate and shutdown) mode specifications. The ADuCM3027/ADuCM3029 MCUs provide a combination of hardware and software protection mechanisms that lock out access to the devices in secure mode but grant access in open mode. These mechanisms include password protected slave boot mode (UART), as well as password protected serial wire debug (SWD) interfaces. The following features are available for power management and control: • • • • • A voltage range of 1.74 V to 3.6 V using a single supply (such as the CR2032 coin cell battery). GPIOs are driven directly from the battery. The pin state is retained in hibernate and shutdown modes. The GPIO configuration is only retained in hibernate mode. Wake-up from external interrupt (via GPIOs), UART0_RX interrupt, and RTCs for hibernate mode. Wake-up from external interrupt (via GPIOs) and RTC0 for shutdown mode. Optional high power buck converter for 1.2 V full on support (for MCU use only). See Figure 23 for the suggested external circuitry. Mechanisms are provided to protect the device contents (flash, SRAM, CPU registers, and peripheral registers) from being read through an external interface by an unauthorized user, which is referred to as read protection. It is possible to protect the device from being reprogrammed in circuit with unauthorized code. This is referred to as in circuit write protection. The devices can be configured with no protection, read protection, or read and in circuit write protection. It is not necessary to provide in circuit write protection without read protection. Cryptographic Accelerator The cryptographic accelerator is a 32-bit APB DMA capable peripheral. There are two 32-bit buffers provided for data input/output operations. These buffers read in or read out 128 bits in four data accesses. Big endian and little endian data formats are supported, as are the following modes: • • • • • • Rev. B | Page 25 of 39 Electronic code book (ECB) mode—AES mode Counter (CTR) mode Cipher block chaining (CBC) mode Message authentication code (MAC) mode Cipher block chaining-message authentication code (CCM/CCM*) mode SHA-256 modes 14168-023 In Flexi mode, the ARM Cortex-M3 core is clock gated, but the remainder of the system is active. No instructions can be executed in this mode, but DMA transfers can continue between peripherals and memory as well as memory to memory. See Table 5 for details on Flexi mode power. ADuCM3027/ADuCM3029 Data Sheet True Random Number Generator (TRNG) Timers The TRNG is used during operations where nondeterministic values are required. These operations can include generating challenges for secure communication or keys for an encrypted communication channel. The generator can run multiple times to generate a sufficient number of bits for the strength of the intended operation. The TRNG can seed a deterministic random bit generator. The ADuCM3027/ADuCM3029 MCUs have three generalpurpose timers and a watchdog timer. Reliability and Robustness Features The ADuCM3027/ADuCM3029 MCUs provide a number of features that can enhance or help achieve certain levels of system safety and reliability. While the level of safety is mainly dominated by system considerations, the following features are provided to enhance robustness. ECC Enabled Flash Memory The entire flash array can be protected to either correct singlebit errors or detect two-bit errors per 64-bit flash data. Multiparity Bit Protected SRAM Each word of the SRAM and cache memory is protected by multiple parity bits to allow detection of random soft errors. Software Watchdog The on-chip watchdog timer can provide software-based supervision of the ADuCM3027/ADuCM3029. Cyclic Redundancy Check (CRC) Accelerator The CRC accelerator computes the CRC for a block of memory locations. The exact memory location can be in the SRAM, flash, or any combination of MMRs. The CRC accelerator generates a checksum that can be compared with an expected signature. The main features of the CRC include the following:        Generates a CRC signature for a block of data. Supports programmable polynomial length of up to 32 bits. Operates on 32 bits of data at a time. Supports MSB first and LSB first CRC implementations. Various data mirroring capabilities. Initial seed to be programmed by user. DMA controller (memory to memory transfer) used for data transfer to offload the MCU. General-Purpose Timers The ADuCM3027/ADuCM3029 MCUs have three identical general-purpose timers, each with a 16-bit up and down counter. The up and down counter can be clocked from one of four user selectable clock sources. Any selected clock source can be scaled down using a prescaler of 1, 16, 64, or 256. Watchdog Timer (WDT) The WDT is a 16-bit count down timer with a programmable prescaler. The prescaler source is selectable and can be scaled by a factor of 1, 16, or 256. The WDT is clocked by the 32 kHz onchip oscillator (LFOSC) and recovers from an illegal software state. The WDT requires periodic servicing to prevent it from forcing a reset or interrupt to the MCU. Analog-to-Digital Converter (ADC) Subsystem The ADuCM3027/ADuCM3029 MCUs integrate a 12-bit SAR ADC with up to eight external channels. Conversions can be performed in single or autocycle mode. In single mode, the ADC can be configured to convert on a particular channel by selecting one of the channels. Autocycle mode is provided to reduce MCU overhead of sampling and reading individual channel registers. The ADC can also be used for temperature sensing and measuring battery voltage using dedicated channels. Temperature sensing and battery monitoring cannot be included with external channels in autocycle mode. A digital comparator triggers an interrupt if ADC input is above or below a programmable threshold. The ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3 input channels can be used with the digital comparator. Use the ADC in DMA mode to reduce MCU overhead by moving ADC results directly into SRAM with a single interrupt asserted when the required number of ADC conversions has been completely logged to memory. Programmable GPIOs The ADuCM3027 and ADuCM3029 MCUs have 44 and 34 GPIO pins in the LFCSP and WLCSP packages, respectively. Note that the ADuCM3029-1 and ADuCM3029-2 models have 44 GPIO pins and are available in the LFCSP only. These GPIO pins have multiple, configurable functions defined by user code. They can be configured as an input/output and have programmable pull-up resistors. All GPIO pins are functional over the full supply range. In deep sleep mode, the GPIO pins retain their state. On reset, the GPIO pins tristate. Rev. B | Page 26 of 39 Data Sheet ADuCM3027/ADuCM3029 The main features of the ADC subsystem include the following:      Clocking         12-bit resolution. Programmable ADC update rate from 10 KSPS to 1.8 MSPS. Integrated input multiplexer that supports up to eight channels. Temperature sensing support. Battery monitoring support. Software selectable on-chip reference voltage generation— 1.25 V and 2.5 V. Software selectable internal or external reference. Autocycle mode—ability to automatically select a sequence of input channels for conversion. Averaging function—converted data on single-channel or multiple channels can be averaged up to 256 samples. Alert function—internal digital comparator for ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3 channels. An interrupt is generated if the digital comparator detects an ADC result above or below a user defined threshold. Dedicated DMA channel support. Each channel, including temperature sensor and battery monitoring, has a data register for conversion result. The ADuCM3027/ADuCM3029 MCUs have the following clocking options:   26 MHz  Internal oscillator—HFOSC (26 MHz)  External crystal oscillator—HFXTAL (26 MHz or 16 MHz)  GPIO clock in—SYS_CLKIN 32 kHz  Internal oscillator—LFOSC  External crystal oscillator—LFXTAL The clock options have software configurability with the following exceptions:   HFOSC cannot be disabled when using an internal buck regulator. LFOSC cannot be disabled even if using LFXTAL. Table 23. RTC Features Features Resolution of Time Base (Prescaling) Source Clock RTC0 Counts time at 1 Hz in units of seconds. Operationally, RTC0 always prescales to 1 Hz (for example, divide by 32,768) and always counts real time in units of seconds. LFXTAL. Wake-Up Timer Number of Alarms SensorStrobe Mechanism Wake-up time is specified in units of seconds. Input Capture Not available. One alarm only. Uses an absolute, nonrepeating alarm time, specified in units of 1 sec. Not available. RTC1 (FLEX_RTC) Can prescale the clock by any power of two from 0 to 15. It can count time in units of any of these 16 possible prescale settings. For example, the clock can be prescaled by 1, 2, 4, 8, …, 16,384, or 32,768. Depending on the low frequency multiplexer (LFMUX) configuration, the RTC is clocked by the LFXTAL or the LFOSC. Supports alarm times down to a resolution of 30.52 μs, that is, where the time is specified down to a specific 32 kHz clock cycle. Two alarms. One absolute alarm time and one periodic alarm, repeating every 60 prescaled time units. SensorStrobe is an alarm mechanism in the RTC that sends an output pulse via GPIOs to an external device to instruct the device to take a measurement or perform some action at a specific time. SensorStrobe events are schedule data specific target time relative to the real-time count of the RTC. SensorStrobe can be enabled in active, Flexi, and hibernate modes. Input capture takes a snapshot of the RTC when an external device signals an event via a transition on one of the GPIO inputs to the ADuCM3027/ADuCM3029. Typically, an input-capture event is triggered by an autonomous measurement or action on such a device, which then signals to the ADuCM3027/ ADuCM3029 that the RTC must take a snapshot of time corresponding to the event. Taking the snapshot can wake up the ADuCM3027/ADuCM3029 and cause an interrupt to the CPU. The CPU can subsequently obtain information from the RTC on the exact 32 kHz cycle on which the input capture event occurred. Rev. B | Page 27 of 39 ADuCM3027/ADuCM3029 Data Sheet Beeper Driver The ADuCM3027/ADuCM3029 MCUs have an integrated audio driver for a beeper. The beeper driver module in the ADuCM3027/ADuCM3029 MCUs generate a differential square wave of programmable frequency. It drives an external piezoelectric sound component with two terminals that connect to the differential square wave output. The beeper driver consists of a module that can deliver frequencies ranging from 8 kHz to approximately 0.25 kHz; the minimum frequency is determined by the maximum value of a divide register that can be programmed to 127. This results in a beeper frequency of 32.768 kHz/127 = 0.25802 kHz The beeper driver allows programmable tone durations in 4 ms increments. Pulse (single-tone) and sequence (multitone) modes provide versatile playback options. In sequence mode, the beeper can be programmed to play any number of tone pairs from 1 to 254 (2 tones to 508 tones) or be programmed to play forever (until stopped by the user). Interrupts are available to indicate the start or end of any beep, the end of a sequence, or when the sequence is nearing completion. Debug Capability The ADuCM3027/ADuCM3029 MCUs support SWD. The ADuCM3027/ADuCM3029 MCUs have a reduced flash patch and breakpoint (FPB) unit with support for up to two hardware breakpoints. ON-CHIP PERIPHERAL FEATURES The ADuCM3027/ADuCM3029 MCUs have a rich set of peripherals connected to the core via several concurrent high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see Figure 1). The ADuCM3027/ADuCM3029 MCUs contain high speed serial ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the MCU and system to many application scenarios. Serial Ports (SPORT) The ADuCM3027/ADuCM3029 MCUs provide two single direction half SPORTs or one bidirectional full SPORT. The synchronous serial ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices audio codecs, ADCs, and DACs. The serial ports contain two data lines, a clock, and a frame sync. The data lines can be programmed to either transmit or receive, and each data line has a dedicated DMA channel. channels. The frame sync and clock can be shared. Some of the ADCs and DACs require two control signals for their conversion process. To interface with such devices, the SPT0_ACNV and SPT0_BCNV signals are provided. To use these signals, enable the timer enable mode. In this mode, a PWM timer inside the module generates the programmable SPT0_ACNV and SPT0_BCNV signals. Serial ports operate in two modes: • • Standard digital signal processor (DSP) serial mode Timer enable mode SPI Ports The ADuCM3027/ADuCM3029 MCUs provide three SPIs. SPI is an industry standard, full-duplex, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received. Each SPI incorporates two DMA channels that interface with the DMA controller. One DMA channel transmits and the other receives. The SPI on the MCU eases interfacing to external serial flash devices. The SPI features include the following: • • • • • • • • • Serial clock phase mode and serial clock polarity mode Loopback mode Continuous and repeated transfer mode Wired OR output mode Read command mode for half-duplex operation (transmit followed by receive) Flow control support in read command mode Support for 3-pin SPI in read command mode Multiple CS line support CS software override support UART Port The ADuCM3027/ADuCM3029 MCUs provide a full-duplex UART port, which is fully compatible with PC standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA, and asynchronous transfers of serial data. The UART port includes support for five to eight data bits, and none, even, or odd parity. A frame is terminated by one, one and a half, or two stop bits. I2C The ADuCM3027/ADuCM3029 MCUs provide an I2C bus peripheral that has two pins for data transfer. SCL (Pin P0_04) is a serial clock pin, and SDA (Pin P0_05) is a serial data pin. The pins are configured in a wired AND format that allows arbitration in a multimaster system. A master device can be configured to generate the serial clock. The frequency is programmed by the user in the serial clock divisor register. The master channel can operate in fast mode (400 kHz) or standard mode (100 kHz). Serial port data can be automatically transferred to and from on-chip memory or external memory via dedicated DMA Rev. B | Page 28 of 39 Data Sheet ADuCM3027/ADuCM3029 MCU TEST CONDITIONS Development support for the ADuCM3027/ADuCM3029 MCU includes documentation, evaluation hardware, and development software tools. The ac signal specifications (timing parameters) appearing in this data sheet include output disable time, output enable time, and others. Timing is measured on signals when they cross the voltage threshold (VMEAS) level as described in Figure 24. All delays (in nanoseconds or microseconds) are measured between the point that the first signal reaches VMEAS and the point that the second signal reaches VMEAS. The value of VMEAS is set to VBAT/2. The tester pin electronics is shown in Figure 25. Documentation The ADuCM302x Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management Hardware Reference details the functionality of each block on the ADuCM3027/ADuCM3029 MCUs. It includes power management, clocking, memories, and peripherals. INPUT OR OUTPUT Hardware The EV-COG-AD3029LZ is available to prototype sensor configurations with the ADuCM3027/ADuCM3029 MCUs. Figure 24. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Software VLOAD The EV-COG-AD3029LZ includes a complete development and debug environment for the ADuCM3027/ADuCM3029 MCUs. The device family pack (DFP) for the ADuCM3027/ ADuCM3029 is provided for the IAR Embedded Workbench for ARM, Keil™, and CrossCore® embedded studio (CCES) environments. 4pF The applicable documentation for programming the ARM Cortex-M3 processor include the following:     14168-025 DRIVER TYPES Table 24 shows the driver types. Table 24. Driver Types Driver Type1, 2, 3 Type A 1 The Circuits from the Lab® page provides the following for the ADuCM3027/ADuCM3029 reference design:  Figure 25. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Type C Type D REFERENCE DESIGNS ZO = 50Ω (IMPEDANCE) TD = 4.04ns ± 1.18ns NOTES 1. THE WORST-CASE TRANSMISSION LINE DELAY (TD) IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. TRANSMISSION LINE IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. 2. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM CAN INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Type B ARM Cortex-M3 Devices Generic User Guide ARM Cortex-M3 Technical Reference Manual 2pF 0.5pF DUT OUTPUT 400Ω The following documentation that describe the ADuCM3027/ ADuCM3029 MCUs can be ordered from any Analog Devices sales office or accessed electronically on the Analog Devices website: This data sheet describes the ARM Cortex-M3 core and memory architecture used on the ADuCM3027/ADuCM3029 MCUs but does not provide detailed programming information for the ARM processor. For more information about programming the ARM processor, visit the ARM Infocenter web page. T1 45Ω 50Ω ADDITIONAL INFORMATION ADuCM302x Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management Hardware Reference. 50Ω 70Ω The DFP also includes operating system (OS) aware drivers and example code for all the peripherals on the devices.  VMEAS VMEAS 14168-024 DEVELOPMENT SUPPORT Associated Pins P0_00 to P0_03, P0_07, P0_10 to P0_13, P0_15, P1_00 to P1_10, P1_15, P2_00, P2_01, P2_04 to P2_14, P3_00 to P3_03, and SYS_HWRST. P0_08, P0_09, P0_14, P1_11 to P1_14, and P2_02 P0_04 and P0_05 P0_06 In single drive mode, the maximum source/sink capacity is 2 mA. In double drive mode, the maximum source/sink capacity is 4 mA. 3 At maximum drive capacity, only 16 GPIOs are allowed to switch at any given point of time. 2 Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications Drill down links for components in each chain to selection guides and application information Reference designs applying best practice design techniques Rev. B | Page 29 of 39 ADuCM3027/ADuCM3029 Data Sheet EEMBC ULPMARK™-CP SCORE Table 26. EEMBC ULPMark™-CP Profile Configuration Using the software configuration and the profile configuration shown in the following tables, the EEMBC ULPMark-CP score is 245.5. Profile Configuration Wakeup Timer Module Wakeup Timer Clock Source Wakeup Timer Frequency Wakeup Timer Accuracy Active Power Mode Name Active Mode Clock Configuration Active Mode Voltage Integrity Inactive Power Mode Name Inactive Clock Configuration Inactive Mode Voltage Integrity Table 25. EEMBC ULPMark™-CP Software Configuration Software Configuration Compiler Name and Version Compiler Flags Value IAR EWARM 7.50.2.10505 ULPBench Profile and Version EnergyMonitor Software Version Core Profile v1.1 V1.1.3 -Ohs -endian=little -cpu=Cortex-M3 -D __ADuCM3029__ Rev. B | Page 30 of 39 Value RTC1 External crystal 32768 Hz 20 PPM Active mode 26 MHz (CPU), 32 kHz (RTC) 1.74 V Hibernate Off (CPU), 32 kHz (RTC) 1.74 V Data Sheet ADuCM3027/ADuCM3029 GPIO MULTIPLEXING Table 27 through Table 29 show the signal multiplexing options for the GPIO pins. Table 27. Signal Multiplexing for PORT 0 Pin P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 P0_14 P0_15 Availability WLCSP LFCSP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Multiplexed Function 0 GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 SWD0_CLK SWD0_DATA GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13/XINT0_WAKE2 GPIO14 GPIO15/XINT0_WAKE0 Multiplexed Function 1 SPI0_CLK SPI0_MOSI SPI0_MISO SPI0_CS0 I2C0_SCL I2C0_SDA GPIO06 GPIO07 BPR0_TONE_N BPR0_TONE_P UART0_TX UART0_RX SPT0_AD0 Not available TMR0_OUT Not available Multiplexed Function 2 SPT0_BCLK SPT0_BFS SPT0_BD0 SPT0_BCNV Not available Not available Not available Not available Not available SPI2_CS1 Not available Not available Not available Not available SPI1_RDY Not available Multiplexed Function 3 Not available Not available Not available SPI2_RDY Not available Not available Not available Not available Not available Not available Not available Not available UART0_SOUT_EN Not available Not available Not available Multiplexed Function 1 Not available GPIO17 SPI2_CLK SPI2_MOSI SPI2_MISO SPI2_CS0 SPI1_CLK SPI1_MOSI SPI1_MISO SPI1_CS0 SPI0_CS1 Not available Not available Not available Not available SPT0_ACLK Multiplexed Function 2 Not available Not available Not available Not available Not available Not available Not available Not available Not available Not available SYS_CLKIN TMR1_OUT Not available Not available SPI0_RDY Not available Multiplexed Function 3 Not available Not available Not available Not available Not available Not available Not available Not available Not available Not available SPI1_CS3 Not available Not available Not available Not available Not available Table 28. Signal Multiplexing for PORT 1 Pin P1_00 P1_01 P1_02 P1_03 P1_04 P1_05 P1_06 P1_07 P1_08 P1_09 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 Availability WLCSP LFCSP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes Yes Yes No Yes Multiplexed Function 0 GPIO16/XINT0_WAKE1 SYS_BMODE0 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 Rev. B | Page 31 of 39 ADuCM3027/ADuCM3029 Data Sheet Table 29. Signal Multiplexing for PORT 2 Pin P2_00 P2_01 P2_02 P2_03 P2_04 P2_05 P2_06 P2_07 P2_08 P2_09 P2_10 P2_11 Availability WLCSP LFCSP No Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes No Yes Yes Yes Multiplexed Function 0 GPIO32 GPIO33/XINT0_WAKE3 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 Multiplexed Function 1 SPT0_AFS Not available SPT0_ACNV ADC0_VIN0 ADC0_VIN1 ADC0_VIN2 ADC0_VIN3 ADC0_VIN4 ADC0_VIN5 ADC0_VIN6 ADC0_VIN7 SPI1_CS1 Rev. B | Page 32 of 39 Multiplexed Function 2 Not available TMR2_OUT SPI1_CS2 Not available Not available Not available Not available SPI2_CS3 SPI0_CS2 SPI0_CS3 SPI2_CS2 SYS_CLKOUT Multiplexed Function 3 Not available Not available Not available Not available Not available Not available Not available Not available Not available Not available Not available RTC1_SS1 Data Sheet ADuCM3027/ADuCM3029 APPLICATIONS INFORMATION This section contains circuit diagrams that show the recommended external components for proper operation of the ADuCM3027/ADuCM3029 in example application scenarios. VBAT 0.1µF 0.1µF 1 14 VBAT_ADC 2 SYS_HFXTAL_IN 4 SYS_LFXTAL_IN VBAT_ANA1 IO 0.1µF 0.1µF 8 34 49 VBAT_ANA2 VBAT_DIG1 VBAT_DIG2 13 VREF_ADC 25 SYS_HWRST 0.1µF 6 VDCDC_CAP1N 7 VDCDC_CAP1P 0.1µF ADuCM3027/ADuCM3029/ ADuCM3029-1/ADuCM3029-2 SYS_HFXTAL_OUT 3 SYS_LFXTAL_OUT 5 VDCDC_OUT 9 0.47µF VLDO_OUT 12 0.47µF P1_09 29 P1_08 30 10 VDCDC_CAP2N P1_06 32 11 VDCDC_CAP2P P2_11 33 16 P2_03 RTC1_SS1 IO P1_07 31 17 P2_04 P1_05 53 18 P2_05 P1_04 54 19 P2_06 P1_03 55 20 P2_07 P1_02 56 21 P2_08 22 P2_09 P0_12 35 23 P2_10 P2_00 36 P1_15 37 39 P0_09 P2_02 45 40 P0_08 P1_00 47 28 P0_06 P0_15 50 27 P0_07 P0_13 51 38 P1_01 P2_01 52 42 P1_12 P1_11 41 43 p1_13 P0_14 46 24 P0_05 26 P0_04 P0_11 57 P0_14 58 44 P1_14 59 P1_10 P0_01 62 60 P0_03 P0_00 63 61 P0_02 GND_ANA GND_DIG GND_VREFADC 64 48 15 PAD 14168-026 0.1µF Figure 26. Recommended External Components when Using the Internal Buck Converter Rev. B | Page 33 of 39 ADuCM3027/ADuCM3029 Data Sheet VBAT LFXTAL_IN HFCLK CRYSTAL 26.000MHz IO LFCLK CRYSTAL 32.7680kHz LFXTAL_OUT 8pF HFXTAL_IN 8pF 14 SYS_HFXTAL_IN 4 SYS_LFXTAL_IN VBAT_ANA1 0.1µF 8 34 49 VBAT_DIG1 VBAT_DIG2 13 VREF_ADC 25 SYS_HWRST 6 VDCDC_CAP1N 7 VDCDC_CAP1P ADuCM3027/ADuCM3029/ ADuCM3029-1/ADuCM3029-2 18pF 0.1µF VBAT_ANA2 1 VBAT_ADC 0.1µF 0.1µF 0.1µF 2 HFXTAL_OUT 18pF SYS_HFXTAL_OUT 3 SYS_LFXTAL_OUT 5 VDCDC_OUT 9 VLDO_OUT 12 0.47µF P1_09 29 P1_08 30 10 VDCDC_CAP2N P1_06 32 11 VDCDC_CAP2P P2_11 33 16 P2_03 RTC1_SS1 IO P1_07 31 17 P2_04 P1_05 53 18 P2_05 P1_04 54 19 P2_06 P1_03 55 20 P2_07 P1_02 56 21 P2_08 22 P2_09 P0_12 35 23 P2_10 P2_00 36 P1_15 37 39 P0_09 P2_02 45 40 P0_08 P1_00 47 28 P0_06 P0_15 50 27 P0_07 P0_13 51 38 P1_01 P2_01 52 42 P1_12 P1_11 41 43 p1_13 P0_14 46 24 P0_05 26 P0_04 P0_11 57 P0_14 58 44 P1_14 59 P1_10 P0_01 62 60 P0_03 P0_00 63 61 P0_02 GND_DIG GND_VREFADC 64 48 15 PAD 14168-027 GND_ANA Figure 27. Recommended External Components when Using LFXTAL and HFXTAL Rev. B | Page 34 of 39 Data Sheet ADuCM3027/ADuCM3029 VBAT 0.1µF 0.1µF 14 1 VBAT_ADC VREF_ADC IO 2 SYS_HFXTAL_IN 4 SYS_LFXTAL_IN 0.1µF 0.1µF 8 34 49 VBAT_DIG1 VBAT_DIG2 ADuCM3027/ADuCM3029/ ADuCM3029-1/ADuCM3029-2 4.7µF 6 VDCDC_CAP1N 0.1µF VBAT_ANA2 13 VREF_ADC 25 SYS_HWRST 0.1µF VBAT_ANA1 IO SYS_HFXTAL_OUT 3 SYS_LFXTAL_OUT 5 VDCDC_OUT 9 VLDO_OUT 12 0.47µF P1_09 29 7 VDCDC_CAP1P P1_08 30 10 VDCDC_CAP2N P1_06 32 11 VDCDC_CAP2P ANALOG_IN 33Ω IO P2_11 33 16 P2_03 RTC1_SS1 IO P1_07 31 0.0056µF 17 P2_04 P1_05 53 18 P2_05 P1_04 54 19 P2_06 P1_03 55 20 P2_07 P1_02 56 21 P2_08 22 P2_09 P0_12 35 23 P2_10 P2_00 36 P1_15 37 39 P0_09 P2_02 45 40 P0_08 P1_00 47 28 P0_06 P0_15 50 27 P0_07 P0_13 51 38 P1_01 P2_01 52 42 P1_12 43 p1_13 P1_11 41 P0_14 46 24 P0_05 26 P0_04 P0_11 57 P0_14 58 44 P1_14 59 P1_10 P0_01 62 60 P0_03 P0_00 63 61 P0_02 GND_DIG GND_VREFADC 64 48 15 PAD 14168-028 GND_ANA Figure 28. Recommended External Components on VREF_ADC Pin and ADC Input Channel (ADC0_VIN0 Used as Example) when Using the Internal ADC Rev. B | Page 35 of 39 ADuCM3027/ADuCM3029 Data Sheet ABOUT ADuCM3027/ADuCM3029 SILICON ANOMALIES This anomaly list describes the known bugs, anomalies, and workarounds for the ADuCM3027/ADuCM3029. These anomalies represent the currently known differences between revisions of the ADuCM3027/ADuCM3029 product(s) and the functionality specified in the ADuCM3027/ADuCM3029 data sheet(s) and the Hardware Reference manual. Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended workarounds outlined in this section. ADuCM30297/ADuCM3029 FUNCTIONALITY ISSUES Silicon Revision Identifier 1.2 Silicon Status Released No. of Reported Anomalies 4 (21000011, 21000015, 21000016, 21000017) A silicon revision number with the form x.y is branded on all devices. The silicon revision can be electronically determined by reading Bits[3:0] of the SYS_CHIPID register. SYS_CHIPID = 0x4 indicates Silicon Revision 1.2. FUNCTIONALITY ISSUES Table 30 through Table 33 detail all known silicon anomalies for the ADuCM3027/ADuCM3029 including a description, workaround, and identification of applicable silicon revisions. Table 30. 21000011—I2C Master Mode Fails to Generate Clock Background Issue Workaround Related Issues When the I2C clock dividers are configured in master mode such that the sum of the LOW bit in the I2C_DIV register and the HIGH bit in the I2C_DIV register is less than 16, the I2C fails to generate a clock. The I2C master mode fails to generate clock when clock dividers are too small. Program the I2C clock dividers such that I2C_DIV.LOW + I2C_DIV.HIGH ≥ 16. None. Table 31. 21000015—Pin P2_11 Not Retained Background Issue Workaround Related Issues The state of the P2_11 pin is not retained after waking up from shutdown mode. Pin P2_11 is not retained after shutdown wake up. None. To retain the pin state through shutdown, use any other GPIO pin instead of P2_11. None. Table 32. 21000016—Data Loss with I2C Automatic Clock Stretching Background Issue Workaround Related Issues When the I2C Rx FIFO is full and new I2C data is received, a data overflow occurs. When automatic clock stretching is enabled, the transaction is paused by holding the SCL line low. This pause function works as expected when the next read happens after the clock is stretched (for example, after the overflow is detected). However, if the read occurs after the last bit of the I2C data is received but before the clock is stretched, the received data is not written to the Rx FIFO and is lost. Possible receive data loss with I2C automatic clock stretching. After I2C automatic clock stretching is enabled, read the FIFO only after the overflow flag is set in the status register to ensure the Rx FIFO is never read at the same time the overflow is asserted. None. Rev. B | Page 36 of 39 Data Sheet ADuCM3027/ADuCM3029 Table 33. 21000017—SPI Read Command Mode Does Not Work Background Issue Workaround Related Issues When the SPI master is enabled and uses the DMA mode with SPI_CNT = 1, the read command mode may not function properly. Consider the following configurations: SPI_RD_CTL = 0x07, SPI_CNT = 1, and the Tx and Rx DMA channels configured for one half-word. In this configuration, the read command sent in the first byte on the MOSI output is repeated in the second byte (in the address slot); thus, the slave device responds on the MISO line with whatever content is at the address equivalent to the read command value (for example, if the read command is 0xB, the response is the data read from Slave Address 0xB). SPI read command mode does not work properly when SPI_CNT is 1 and DMA is enabled. Use the overlap mode to align the transmit/receive SPI operations and discard the junk bytes, as follows: Set the OVERLAP bit in the SPI_RD_CTL register = 1 to enable overlap mode. Set the TXBYTES bit in the SPI_RD_CTL register = 1 to configure a single transmit byte (8-bit address register). Set SPI_CNT.VALUE = 3 to configure the transfer count: one byte for the address register, one byte for the command, and one dummy byte to obtain the read value, and on the receive side, discard the first two bytes received during the transfer of the address and command bytes before processing the actual read value in the third byte. Do not use Tx DMA operation on the SPI transmit side, as follows: enable only the SPI Rx DMA requests, fill the SPI Tx FIFO by using core accesses to write to the SPI_TX register, and perform a dummy read of the SPI_RX register to start the SPI transfers. None. Rev. B | Page 37 of 39 ADuCM3027/ADuCM3029 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR AREA DETAIL A (JEDEC 95) 9.10 9.00 SQ 8.90 0.30 0.25 0.20 49 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 64 1 48 0.50 BSC 4.60 4.50 SQ 4.40 EXPOSED PAD 16 33 0.80 0.75 0.70 END VIEW PKG-004540 SEATING PLANE 32 0.50 0.40 0.30 17 0.20 MIN BOTTOM VIEW 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 08-29-2018-A TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WMMD Figure 29. 64-Lead Frame Chip Scale Package [LFCSP] 9 mm × 9 mm Body and 0.75 mm Package Height (CP-64-16) Dimensions shown in millimeters 2.800 2.760 SQ 2.720 0.210 0.108 13 12 11 10 9 8 7 6 5 4 3 2 1 A 0.35 BSC BALL A1 IDENTIFIER B C D E 0.303 BSC F G 0.350 BSC (BALL SIDE UP) (BALL SIDE DOWN) PKG-004742 SEATING PLANE END VIEW 0.103 0.320 0.290 0.260 COPLANARITY 0.05 0.280 0.240 0.200 0.210 0.180 0.150 Figure 30. 54-Ball Wafer Level Chip Scale Package [WLCSP] (CB-54-1) Dimensions shown in millimeters Rev. B | Page 38 of 39 07-30-2015-A 0.530 0.470 0.410 H BOTTOM VIEW TOP VIEW Data Sheet ADuCM3027/ADuCM3029 ORDERING GUIDE Model1 ADuCM3027BCBZ-RL ADuCM3027BCBZ-R7 ADuCM3027BCPZ ADuCM3027BCPZ-RL ADuCM3027BCPZ-R7 ADuCM3029BCBZ-RL ADuCM3029BCBZ-R7 ADuCM3029BCPZ ADuCM3029BCPZ-RL ADuCM3029BCPZ-R7 ADuCM3029-1BCPZ ADuCM3029-1BCPZ-R7 ADuCM3029-2BCPZ ADuCM3029-2BCPZ-R7 EV-COG-AD3029LZ EV-COG-AD3029WZ 1 2 Description ULP ARM Cortex-M3 with 128 kB Embedded Flash ULP ARM Cortex-M3 with 128 kB Embedded Flash ULP ARM Cortex-M3 with 128 kB Embedded Flash ULP ARM Cortex-M3 with 128 kB Embedded Flash ULP ARM Cortex-M3 with 128 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ULP ARM Cortex-M3 with 256 kB Embedded Flash ADuCM3029 LFCSP Development Board ADuCM3029 WLCSP Development Board Temperature2 −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 54-Ball WLCSP, 13" Reel 54-Ball WLCSP, 7” Reel 64-Lead LFCSP 64-Lead LFCSP, 13” Reel 64-Lead LFCSP, 7” Reel 54-Ball WLCSP, 13” Reel 54-Ball WLCSP, 7” Reel 64-Lead LFCSP 64-Lead LFCSP, 13” Reel 64-Lead LFCSP, 7” Reel 64-Lead LFCSP 64-Lead LFCSP, 7” Reel 64-Lead LFCSP 64-Lead LFCSP, 7” Reel Package Option CB-54-1 CB-54-1 CP-64-16 CP-64-16 CP-64-16 CB-54-1 CB-54-1 CP-64-16 CP-64-16 CP-64-16 CP-64-16 CP-64-16 CP-64-16 CP-64-16 Z = RoHS Compliant Part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Absolute Maximum Ratings section for junction temperature (TJ) specification which is the only temperature specification. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14168-0-5/19(B) Rev. B | Page 39 of 39