AMP01FX

Low Noise, Precision Instrumentation Amplifier AMP01 Data Sheet changes have minimal effect on offset; TCVIOS is typically 0.15 μV/°C. Excellent low frequency noise performance is achieved with a minimal compromise on input protection. The bias current is very low, less than 10 nA over the military temperature range. High common-mode rejection of 130 dB, 16-bit linearity at a gain of 1000, and 50 mA peak output current are achievable simultaneously. This combination takes the instrumentation amplifier one step further towards the ideal amplifier. FEATURES Low offset voltage: 50 μV maximum Very low offset voltage drift: 0.3 μV/°C maximum Low noise: 0.12 μV p-p (0.1 Hz to 10 Hz) Excellent output drive: ±10 V at ±50 mA Capacitive load stability: up to 1 μF Gain range: 0.1 to 10,000 Excellent linearity: 16-bit at G = 1000 High CMR: 125 dB minimum (G = 1000) Low bias current: 4 nA maximum Can be configured as a precision op amp Output-stage thermal shutdown Available in die form AC performance complements the superb dc specifications. The AMP01 slews at 4.5 V/μs into capacitive loads of up to 15 nF, settles in 50 μs to 0.01% at a gain of 1000, and boasts a healthy 26 MHz gain bandwidth product. These features make the AMP01 ideal for high speed data acquisition systems. GENERAL DESCRIPTION The gain is set by the ratio of two external resistors over a range of 0.1 to 10,000. A very low gain temperature coefficient of 10 ppm/°C is achievable over the whole gain range. Output voltage swing is guaranteed with three load resistances: 50 Ω, 500 Ω, and 2 kΩ. Loaded with 500 Ω, the output delivers ±13.0 V minimum. A thermal shutdown circuit prevents destruction of the output transistors during overload conditions. The AMP011 is a monolithic instrumentation amplifier designed for high-precision data acquisition and instrumentation applications. The design combines the conventional features of an instrumentation amplifier with a high current output stage. The output remains stable with high capacitance loads (1 μF), a unique ability for an instrumentation amplifier. Consequently, the AMP01 can amplify low level signals for transmission through long cables without requiring an output buffer. The output stage can be configured as a voltage or current generator. The AMP01 can also be configured as a high performance operational amplifier. In many applications, the AMP01 can be used in place of op amp/power buffer combinations. Input offset voltage is very low (20 μV), which generally eliminates the external null potentiometer. Temperature FUNCTIONAL BLOCK DIAGRAM V+ VIOS NULL +VOP A1 –IN +IN OUTPUT 250Ω 250Ω –VOP Q1 Q2 REFERENCE R1 47.5kΩ R3 47.5kΩ RG A2 SENSE A3 R2 2.5kΩ VOOS NULL R4 2.5kΩ V– 14335-004 RS Figure 1. 1 Protected under U.S. Patents 4,471,321 and 4,503,381. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AMP01 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Input Bias and Offset Currents ................................................. 18  General Description ......................................................................... 1  Gain .............................................................................................. 18  Functional Block Diagram .............................................................. 1  Common-Mode Rejection ........................................................ 19  Revision History ............................................................................... 2  Active Guard Drive .................................................................... 19  Specifications..................................................................................... 3  Grounding ................................................................................... 19  Electrical Characteristics ............................................................. 3  Sense and Reference Terminals ................................................ 20  Dice Characteristics ..................................................................... 8  Driving 50 Ω Loads .................................................................... 21  Wafer Test Limits (AMP01NBC) ............................................... 9  Heatsinking ................................................................................. 22  Absolute Maximum Ratings.......................................................... 10  Overvoltage Protection .............................................................. 22  Thermal Resistance .................................................................... 10  Power Supply Considerations ................................................... 22  ESD Caution ................................................................................ 10  Applications Circuits...................................................................... 23  Pin Configurations and Function Descriptions ......................... 11  Outline Dimensions ....................................................................... 29  Typical Performance Characteristics ........................................... 13  Ordering Guide .......................................................................... 29  Theory of Operation ...................................................................... 18  Input and Output Offset Voltages ............................................ 18  REVISION HISTORY 12/2019—Rev. E to Rev. F Changes to Table 7 .......................................................................... 10 Changes to Ordering Guide .......................................................... 29 1/2017—Rev. D to Rev. E Updated Format .................................................................. Universal Deleted E-28A Package ...................................................... Universal Changed R-20 Package to RW-20 Package ...................... Universal Deleted Pin Connections Section and Figure 1 to Figure 3; Renumbered Sequentially................................................................ 1 Added Functional Block Diagram Section and Figure 1; Renumbered Sequentially................................................................ 1 Changes to Figure 2 .......................................................................... 8 Changes to Table 5 ............................................................................ 9 Deleted Figure 5 .................................................................................9 Deleted Table 6; Renumbered Sequentially ................................ 10 Added Table 6 and Table 7; Renumbered Sequentially ............. 10 Added Pin Configurations and Function Descriptions Section, Figure 3, and Table 8 ...................................................................... 11 Added Figure 4 and Table 9 .......................................................... 12 Changes to Input and Output Offset Voltages Section and Gain Section .................................................................................... 18 Changes to Power Supply Considerations Section .................... 22 Added Applications Circuits Section ........................................... 29 Updated Package Drawings .......................................................... 29 Changes to Ordering Guide .......................................................... 29 Rev. F | Page 2 of 29 Data Sheet AMP01 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = ±15 V, RS = 10 kΩ, RL = 2 kΩ, TA = 25°C, unless otherwise noted. Table 1. Parameter OFFSET VOLTAGE Input Offset Voltage Symbol Test Conditions/Comments VIOS Min AMP01A Typ Max Min AMP01B Typ Max Unit Input Offset Voltage Drift Output Offset Voltage TCVIOS VOOS Output Offset Voltage Drift TCVOOS Offset Referred to Input vs. Positive Supply PSR TA = 25°C −55°C ≤ TA ≤ +125°C −55°C ≤ TA ≤ +125°C TA = 25°C −55°C ≤ TA ≤ +125°C RG = ∞ −55°C ≤ TA ≤ +125°C V+ = +5 V to +15 V 120 110 95 75 130 130 110 90 110 100 90 70 120 120 100 80 dB dB dB dB 120 110 95 75 130 130 110 90 110 100 90 70 120 120 100 80 dB dB dB dB PSR G = 1000 G = 100 G = 10 G=1 −55°C ≤ TA ≤ +125°C G = 1000 G = 100 G = 10 G=1 V− = −5 V to −15 V G = 1000 G = 100 G = 10 G=1 −55°C ≤ TA ≤ +125°C G = 1000 G = 100 G = 10 G=1 VS = ±4.5 V to ±18 V1 VS = ±4.5 V to ±18 V1 105 90 70 50 125 105 85 65 105 90 70 50 115 95 75 60 dB dB dB dB 105 90 70 50 125 105 85 85 ±6 ±100 105 90 70 50 115 95 75 60 ±6 ±100 dB dB dB dB mV mV Offset Referred to Input vs. Negative Supply Input Offset Voltage Trim Range Output Offset Voltage Trim Range INPUT CURRENT Input Bias Current IB Input Bias Current Drift Input Offset Current TCIB IOS Input Offset Current Drift TCIOS TA = 25°C −55°C ≤ TA ≤ +125°C −55°C ≤ TA ≤ +125°C TA = 25°C −55°C ≤ TA ≤ +125°C −55°C ≤ TA ≤ +125°C Rev. F | Page 3 of 29 20 40 0.15 1 3 50 80 0.3 3 6 40 60 0.3 2 6 100 150 1.0 6 10 μV μV μV°C mV mV 20 50 50 120 μV/°C 1 4 40 0.2 0.5 3 4 10 1.0 3.0 2 6 50 0.5 1.0 5 6 15 2.0 6.0 nA nA pA/°C nA nA pA/°C AMP01 Parameter INPUT Input Resistance 1 2 Data Sheet Symbol Test Conditions/Comments RIN Differential, G = 1000 Differential, G ≤ 100 Common mode, G = 1000 TA = 25°C2 −55°C ≤ TA ≤ +125°C VCM = ±10 V, 1 kΩ source imbalance G = 1000 G = 100 G = 10 G=1 −55°C ≤ TA ≤ +125°C G = 1000 G = 100 G = 10 G=1 Input Voltage Range IVR Common-Mode Rejection CMR VIOS and VOOS nulling have minimal effect on TCVIOS and TCVOOS, respectively. Refer to the Common-Mode Rejection section. Rev. F | Page 4 of 29 Min AMP01A Typ Max Min 1 10 20 ±10.5 ±10.0 AMP01B Typ Max Unit 1 10 20 GΩ GΩ GΩ V V ±10.5 ±10.0 125 120 100 85 130 130 120 100 115 110 95 75 125 125 110 90 dB dB dB dB 120 115 95 80 125 125 115 95 110 105 90 75 120 120 105 90 dB dB dB dB Data Sheet AMP01 VS = ±15 V, RS = 10 kΩ, RL = 2 kΩ, TA = 25°C, −25°C ≤ TA ≤ +85°C for E and F grades, 0°C ≤ TA ≤ 70°C for G grade, unless otherwise noted. Table 2. Parameter OFFSET VOLTAGE Input Offset Voltage Symbol Test Conditions/Comments VIOS Min AMP01E Typ Max AMP01F/AMP01G Min Typ Max Unit Input Offset Voltage Drift Output Offset Voltage TCVIOS VOOS Output Offset Voltage Drift TCVOOS Offset Referred to Input vs. Positive Supply PSR TA = 25°C TMIN ≤ TA ≤ TMAX TMIN ≤ TA ≤ TMAX1 TA = 25°C TMIN ≤ TA ≤ TMAX RG = ∞1 −55°C ≤ TA ≤ +125°C V+ = +5 V to +15 V 120 110 95 75 130 130 110 90 110 100 90 70 120 120 100 80 dB dB dB dB 120 110 95 75 130 130 110 90 110 100 90 70 120 120 100 80 dB dB dB dB PSR G = 1000 G = 100 G = 10 G=1 TMIN ≤ TA ≤ TMAX G = 1000 G = 100 G = 10 G=1 V− = −5 V to −15 V G = 1000 G = 100 G = 10 G=1 TMIN ≤ TA ≤ TMAX G = 1000 G = 100 G = 10 G=1 VS = ±4.5 V to ±18 V2 VS = ±4.5 V to ±18 V2 110 95 75 55 125 105 85 65 105 90 70 50 115 95 75 60 dB dB dB dB 110 95 75 55 125 105 85 85 ±6 ±100 105 90 70 50 115 95 75 60 ±6 ±100 dB dB dB dB mV mV Offset Referred to Input vs. Negative Supply Input Offset Voltage Trim Range Output Offset Voltage Trim Range INPUT CURRENT Input Bias Current IB Input Bias Current Drift Input Offset Current TCIB IOS Input Offset Current Drift TCIOS TA = 25°C TMIN ≤ TA ≤ TMAX TMIN ≤ TA ≤ TMAX TA = 25°C TMIN ≤ TA ≤ TMAX TMIN ≤ TA ≤ TMAX Rev. F | Page 5 of 29 20 40 0.15 1 3 50 80 0.3 3 6 40 60 0.3 2 6 100 150 1.0 6 10 μV μV μV°C mV mV 20 100 50 120 μV/°C 1 4 40 0.2 0.5 3 4 10 1.0 3.0 2 6 50 0.5 1.0 5 6 15 2.0 6.0 nA nA pA/°C nA nA pA/°C AMP01 Parameter INPUT Input Resistance 1 2 3 Data Sheet Symbol Test Conditions/Comments RIN Differential, G = 1000 Differential, G ≤ 100 Common mode, G = 1000 TA = 25°C3 TMIN ≤ TA ≤ TMAX VCM = ±10 V, 1 kΩ source imbalance G = 1000 G = 100 G = 10 G=1 TMIN ≤ TA ≤ TMAX G = 1000 G = 100 G = 10 G=1 Input Voltage Range IVR Common-Mode Rejection CMR Sample tested. VIOS and VOOS nulling has minimal effect on TCVIOS and TCVOOS, respectively. Refer to the Common-Mode Rejection section. Rev. F | Page 6 of 29 Min AMP01E Typ Max AMP01F/AMP01G Min Typ Max 1 10 20 ±10.5 ±10.0 Unit 1 10 20 GΩ GΩ GΩ V V ±10.5 ±10.0 125 120 100 85 130 130 120 100 115 110 95 75 125 125 110 90 dB dB dB dB 120 115 95 80 125 125 115 95 110 105 90 75 120 120 105 90 dB dB dB dB Data Sheet AMP01 VS = ±15 V, RS = 10 kΩ, RL = 2 kΩ, TA = 25°C, unless otherwise noted. Table 3. Parameter GAIN Gain Equation Accuracy Gain Range Nonlinearity Temperature Coefficient OUTPUT RATING Output Voltage Swing Positive Current Limit Negative Current Limit Capacitive Load Stability Thermal Shutdown Temperature NOISE Voltage Density, RTI Noise Current Density, RTI Input Noise Voltage Input Noise Current DYNAMIC RESPONSE Small-Signal Bandwidth (−3 dB) Slew Rate Settling Time Symbol Test Conditions/Comments AMP01A/AMP01E Min Typ Max G = (20 × RS)/RG, accuracy measured from G = 1 to 100 G GTC VOUT en 0.3 0.1 G = 10001 G = 1001 G = 101 G = 11 1 ≤ G ≤ 10001, 2 0.0007 5 RL= 2 kΩ RL= 500 kΩ RL= 50 kΩ RL= 2 kΩ over temperature RL= 500 kΩ3 Output to ground short Output to ground short 1 ≤ G ≤ 1000, no oscillations1 Junction temperature ±13.0 ±13.0 ±2.5 ±12.0 ±12.0 60 60 0.1 ±13.8 ±13.5 ±4.0 ±13.8 ±13.5 100 90 1 AMP01B/AMP01F/AMP01G Min Typ Max 0.6 10,000 0.005 0.005 0.005 0.010 10 120 120 0.5 0.1 0.0007 5 ±13.0 ±13.0 ±2.5 ±12.0 ±12.0 60 60 0.1 ±13.8 ±13.5 ±4.0 ±13.8 ±13.5 100 90 1 Unit 0.8 % 10,000 0.005 0.005 0.007 0.015 15 V/V % % % % ppm°C 120 120 V V V V V mA mA μF 165 165 °C 5 10 59 540 0.15 5 10 59 540 0.15 nV/√Hz nV/√Hz nV/√Hz nV/√Hz pV/√Hz 0.12 0.16 1.4 13 2 0.12 0.16 1.4 13 2 μV p-p μV p-p μV p-p μV p-p pV p-p in p-p fO = 1 kHz G = 1000 G = 100 G = 10 G=1 fO = 1 kHz, G = 1000 0.1 Hz to 10 Hz G = 1000 G = 100 G = 10 G=1 0.1 Hz to 10 Hz, G = 1000 BW G=1 570 570 kHz G = 10 G = 100 G = 1000 G = 10 To 0.01%, 20 V step G=1 G = 10 G = 100 G = 1000 100 82 26 4.5 100 82 26 4.5 kHz kHz kHz V/μs 12 13 15 50 μs μs μs μs in en p-p 3.5 12 13 15 50 1 Guaranteed by design. Gain temperature coefficient does not include the effects of gain and scale resistor temperature coefficient match. 3 −55°C ≤ TA ≤ +125°C for A and B grades, −25°C ≤ TA ≤ +85°C for E and F grades, 0°C ≤ TA ≤ 70°C for G grade. 2 Rev. F | Page 7 of 29 3.0 AMP01 Data Sheet VS = ±15 V, RS = 10 kΩ, RL = 2 kΩ, TA = 25°C, unless otherwise noted. Table 4. Parameter SENSE INPUT Input Resistance Input Current Voltage Range1 REFERENCE INPUT Input Resistance Input Current Voltage Range1 Gain to Output POWER SUPPLY 1 Symbol Test Conditions/Comments RIN IIN Referenced to V− AMP01A/AMP01E Min Typ Max AMP01B/AMP01F/AMP01G Min Typ Max 35 65 35 +15 −10.5 65 35 +15 −10.5 50 280 −10.5 RIN IIN 35 50 280 Referenced to V− −10.5 50 280 +15 50 280 Supply Voltage Range VS Quiescent Current IQ ±4.5 ±4.5 3.0 3.4 1 ±18 ±18 4.8 4.8 ±4.5 ±4.5 3.0 3.4 Guaranteed by design. V+ V+ (OUTPUT) RS RS VIOS NULL DICE CHARACTERISTICS VIOS NULL V– V– (OUTPUT) OUTPUT +INPUT REFERENCE RG RG –INPUT * MAKE NO ELECTRICAL CONNECTION. Figure 2. Die Size 0.111 in × 0.149 in, 16,539 sq. mils (2.82 mm × 3.78 mm, 10.67 sq. mm) 14335-102 TEST PIN* VOOS NULL VOOS NULL SENSE Rev. F | Page 8 of 29 65 +15 1 –25°C ≤ TA ≤ +85°C for E and F grades, –55 C ≤ TA ≤ +125°C for A and B grades +V linked to +VOP −V linked to −VOP +V linked to +VOP −V linked to −VOP 65 ±18 ±18 4.8 4.8 Unit kΩ μA V kΩ μA V V/V V V mA mA Data Sheet AMP01 WAFER TEST LIMITS (AMP01NBC) VS = ±15 V, RS = 10 kΩ, RL = 2 kΩ, TA = 25°C, unless otherwise noted. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult the factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. Table 5. Parameter OFFSET VOLTAGE Input Offset Voltage Input Offset Voltage Drift Output Offset Voltage Output Offset Voltage Drift Offset Referred to Input vs. Positive Supply Offset Referred to Input vs. Negative Supply INPUT CURRENT Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Input Voltage Range Common-Mode Rejection GAIN Gain Equation Accuracy OUTPUT RATING Output Voltage Swing Symbol VIOS TCVIOS VOOS TCVOOS PSR PSR NOISE Nonlinearity Voltage Noise Density Current Noise Density Voltage Noise Current Noise DYNAMIC RESPONSE Small-Signal Bandwidth (−3 dB) Slew Rate Settling Time Min IVR CMR Typ IQ Unit 60 μV μV/°C mV μV/°C 4 RG = ∞ V+ = 5 V to 15 V G = 1000 G = 100 G = 10 G=1 V– = –5 V to –15 V G = 1000 G = 100 G = 10 G=1 20 120 110 95 75 dB dB dB dB 105 90 70 50 dB dB dB dB 4 40 1 3 Guaranteed by CMR tests VCM = ±10 V G = 1000 G = 100 G = 10 G=1 ±10 125 120 100 85 RL = 2 kΩ RL = 500 kΩ RL = 50 kΩ Output to ground short Output to ground short +V linked to +VOP −V linked to −VOP nA pA/°C nA pA/°C V min dB dB dB dB G = (20 × RS)/RG VOUT Max 0.15 IB TCIB IOS TCIOS Output Current Limit Quiescent Current Test Conditions/Comments −13 −13 −2.5 −60 −120 0.6 % +13 +13 +2.5 +60 +120 4.8 4.8 V V V mA mA mA mA en in en p-p in p-p BW G = 1000 G = 1000, fO = 1 kHz G = 1000, fO = 1 kHz G = 1000, 0.1 Hz to 10 Hz G = 1000, 0.1 Hz to 10 Hz 0.0007 5 0.15 0.12 2 % nV/√Hz pA/√Hz μV p-p pA p-p SR tS G = 1000 G = 10 To 0.01%, 20 V step, G = 1000 26 4.5 50 kHz V/μs μs Rev. F | Page 9 of 29 AMP01 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Supply Voltage Internal Power Dissipation1 Common-Mode Input Voltage Differential Input Voltage RG ≥ 2 kΩ RG ≤ 2 kΩ Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range AMP01A, AMP01B AMP01E, AMP01F Lead Temperature (Soldering, 60 sec) Dice Junction Temperature (TJ) 1 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating ±18 V 500 mW Supply voltage Table 7. Thermal Resistance Package Type Q-18 (100°C Maximum Ambient) RW-20 ±20 V ±10 V Indefinite −65°C to +150°C ESD CAUTION −55°C to +125°C −25°C to +85°C 300°C −65°C to +150°C See Table 7 for maximum ambient temperature rating and derating factor Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. F | Page 10 of 29 θJA 70.4 73.7 θJC 10.2 23.9 Unit °C/W °C/W Data Sheet AMP01 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 18 +IN RG 2 17 VIOS NULL –IN 3 16 VIOS NULL VOOS NULL 4 15 RS VOOS NULL 5 14 RS TEST PIN* 6 13 +VOP SENSE 7 12 V+ 8 11 V– OUTPUT 9 10 –VOP REFERENCE TOP VIEW (Not to Scale) *MAKE NO ELECTRICAL CONNECTION. 14335-001 AMP01 RG 1 Figure 3. 18-Lead CERDIP Table 8. 18-Lead CERDIP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Mnemonic RG RG −IN VOOS NULL VOOS NULL TEST PIN SENSE REFERENCE OUTPUT −VOP V− V+ +VOP RS RS VIOS NULL VIOS NULL +IN Description Gain Resistor Pin. Install a resistor between 200 kΩ and 100 Ω to Pin 2. Gain Resistor Pin. Install a resistor between 200 kΩ and 100 Ω to Pin 1. Inverting Signal Input. Output Offset Voltage Null. Connect a 100 kΩ trimmer across Pin 4 and Pin 5 with wiper to negative supply voltage. Output Offset Voltage Null. Connect a 100 kΩ trimmer across Pin 4 and Pin 5 with wiper to negative supply voltage. Test Pin. Pin 6 is reserved for factory test. Do not connect. This pin completes the feedback loop for the inverting input amplifier. Normally connected to the output. This pin shifts the output CMV. Normally connected to ground. Output of the In-Amp. Negative Supply Voltage for Output Amplifier. Negative Supply Voltage for Input Amplifiers. Positive Supply Voltage for Input Amplifiers. Positive Supply Voltage for Output Amplifier. Scale Resistor. See the Gain section and Figure 32 for value. Scale Resistor. See the Gain section and Figure 32 for value. Input Offset Voltage Null. Connect a 100 kΩ trimmer across Pin 16 and Pin 17 with wiper to negative supply voltage. Input Offset Voltage Null. Connect a 100 kΩ trimmer across Pin 16 and Pin 17 with wiper to negative supply voltage. Noninverting Signal Input. Rev. F | Page 11 of 29 AMP01 Data Sheet RG 1 20 RG TEST PIN* 2 19 TEST PIN* –IN 3 18 +IN VOOS NULL 4 17 VIOS NULL 16 VIOS NULL REFERENCE 8 13 +VOP OUTPUT 9 12 V+ –VOP 10 11 V– VOOS NULL 5 AMP01 *MAKE NO ELECTRICAL CONNECTION 14335-003 TOP VIEW TEST PIN* 6 (Not to Scale) 15 RS SENSE 7 14 RS Figure 4. 20-Lead SOIC Table 9. 20-Lead SOIC Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic RG TEST PIN −IN VOOS NULL VOOS NULL TEST PIN SENSE REFERENCE OUTPUT −VOP V− V+ + VOP RS RS VIOS NULL VIOS NULL +IN TEST PIN RG Description Gain Resistor Pin. Install a resistor between 200 kΩ and 100 Ω to Pin 20. Test Pin. Pin 2 is reserved for factory test. Do not connect. Inverting Signal Input Output Offset Voltage Null. Connect a 100 kΩ trimmer across Pin 4 and Pin 5 with wiper to negative supply voltage. Output Offset Voltage Null. Connect a 100 kΩ trimmer across Pin 4 and Pin 5 with wiper to negative supply voltage. Test Pin. Pin 6 is reserved for factory test. Do not connect. This pin completes the feedback loop for the inverting input amplifier. Normally connected to the output. This pin shifts the output CMV. Normally connected to ground. Output of the In-Amp. Negative Supply Voltage for Output Amplifier. Negative Supply Voltage for Input Amplifiers. Positive Supply Voltage for Input Amplifiers. Positive Supply Voltage for Output Amplifier. Scale Resistor. See the Gain section and Figure 32 for value. Scale Resistor. See the Gain section and Figure 32 for value. Input Offset Voltage Null. Connect a 100 kΩ trimmer across Pin 16 and Pin 17 with wiper to negative supply voltage. Input Offset Voltage Null. Connect a 100 kΩ trimmer across Pin 16 and Pin 17 with wiper to negative supply voltage. Noninverting Signal Input. Test Pin. Pin 19 is reserved for factory test. Do not connect. Gain Resistor Pin. Install a resistor between 200 kΩ and 100 Ω to Pin 1. Rev. F | Page 12 of 29 Data Sheet AMP01 TYPICAL PERFORMANCE CHARACTERISTICS 50 2.5 OUTPUT OFFSET VOLTAGE CHANGE (mV) VS = ±15V 30 20 10 0 –10 –20 1.0 0.5 0 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) –1.0 ±15 ±25 ±20 5 TA = +25°C VS = ±15V INPUT BIAS CURRENT (nA) 4 4 UNIT NO. 1 2 2 0 –2 3 4 –4 3 2 1 0 ±10 ±5 ±15 ±20 –2 –75 14335-006 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 6. Input Offset Voltage vs. Supply Voltage 14335-009 –1 POWER SUPPLY VOLTAGE (V) Figure 9. Input Bias Current vs. Temperature 2.0 VS = ±15V 4 TA = +25°C 1.5 INPUT BIAS CURRENT (nA) 3 2 1 0 –1 –2 1.0 0.5 0 –0.5 –3 –1.0 –4 –5 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 150 14335-007 OUTPUT OFFSET VOLTAGE (mV) ±10 Figure 8. Output Offset Voltage Change vs. Supply Voltage 6 5 ±5 POWER SUPPLY VOLTAGE (V) Figure 5. Input Offset Voltage vs. Temperature 8 0 14335-008 –50 14335-005 –40 –75 INPUT OFFSET VOLTAGE (µV) 1.5 –0.5 –30 –6 TA = +25°C 2.0 Figure 7. Output Offset Voltage vs. Temperature –1.5 0 ±5 ±10 ±15 POWER SUPPLY VOLTAGE (V) Figure 10. Input Bias Current vs. Supply Voltage Rev. F | Page 13 of 29 ±20 14335-010 INPUT OFFSET VOLTAGE (µV) 40 AMP01 Data Sheet 16 VDM = 0 VS = ±15V COMMON-MODE INPUT VOLTAGE (V) 0.4 0.2 0 –0.2 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) POWER SUPPLY REJECTION (dB) 10 100 10k 1k VS = ±5V 2 –50 –25 75 100 POWER SUPPLY REJECTION (dB) G = 1000 120 G = 100 100 80 60 G = 10 G=1 40 1k 10k FREQUENCY (Hz) 100k 14335-013 VCM = 2V p-p VS = ±15V TA = +25°C 100 125 150 VS = ±15V TA = +25°C ΔVS = ±1V G = 1000 100 G = 100 80 60 G = 10 40 G=1 20 1 10 140 10 50 100 1k 10k 100k Figure 15. Positive Power Supply Rejection (PSR) vs. Frequency 140 1 25 FREQUENCY (Hz) Figure 12. Common-Mode Rejection vs. Voltage Gain 20 0 120 0 14335-012 COMMON-MODE REJECTION (dB) 110 VOLTAGE GAIN (G) COMMON-MODE REJECTION (dB) 4 140 120 0 6 TEMPERATURE (°C) VS = ±15V TA = +25°C 1 VS = ±10V 8 Figure 14. Common-Mode Voltage Range vs. Temperature 130 100 10 0 –75 Figure 11. Input Offset Current vs. Temperature 140 VS = ±15V 12 14335-015 –0.6 –75 14335-011 –0.4 14 Figure 13. Common-Mode Rejection vs. Frequency VS = ±15V TA = +25°C ΔVS = ±1V G = 1000 120 G = 100 100 G = 10 G=1 80 60 40 20 0 1 10 100 1k 10k FREQUENCY (Hz) Figure 16. Negative PSR vs. Frequency Rev. F | Page 14 of 29 100k 14335-016 INPUT OFFSET CURRENT (nA) 0.6 14335-014 0.8 Data Sheet 18 AMP01 80 VS = ±15V VS = ±15V TA = +25°C 16 G = 1000 60 VOLTAGE GAIN (dB) OUITPUT VOLTAGE (V) 14 12 10 8 6 G = 100 40 G = 10 20 G=1 0 4 –20 10k LOAD RESISTANCE (Ω) –40 1 10 TOTAL HARMONIC DISTORTION (%) 20 15 10 5 10k 100k 1M FREQUENCY (Hz) 0.07 0.05 G = 1000 0.04 0.03 G = 10 G = 100 0.02 G=1 0.01 0.02 TOTAL HARMONIC DISTORTION (%) OUTPUT IMPEDANCE (Ω) G = 1000 1.0 G=1 0.1 1k 10k 100k FREQUENCY (Hz) 1M 14335-019 0.01 100 1k 10k FREQUENCY (Hz) VS = ±15V IOUT = 20mA p-p 10 100 Figure 21. Total Harmonic Distortion vs. Frequency 10 0.001 1M 0.06 Figure 18. Maximum Output Swing vs. Frequency 100 100k VS = ±15V RL = 600Ω VOUT = 20V p-p 0 10 14335-018 PEAK-TO-PEAK AMPLITUDE (V) 0.08 25 1k 10k Figure 20. Closed-Loop Voltage Gain vs. Frequency VS = ±15V RL = 2kΩ 0 100 1k FREQUENCY (Hz) Figure 17. Maximum Output Voltage vs. Load Resistance 30 100 14335-021 1k Figure 19. Closed-Loop Output Impedance vs. Frequency VS = ±15V G = 100 f = 1kHz VOUT = 20V p-p 0.01 0 100 1k LOAD RESISTANCE (Ω) Figure 22. Total Harmonic Distortion vs. Load Resistance Rev. F | Page 15 of 29 10k 14335-022 100 14335-017 0 10 14335-020 2 AMP01 6 Data Sheet 15 VS = ±15V G = 1000 VOLTAGE NOISE (nV/√Hz) SLEW RATE (V/µs) 5 4 3 2 10 5 1 10 100 1k VOLTAGE GAIN (G) 0 14335-023 0 1 100 10k 1k FREQUENCY (Hz) Figure 23. Slew Rate vs. Voltage Gain 6 10 14335-026 1 Figure 26. Voltage Noise Density vs. Frequency 1k VS = ±15V VS = ±15V f = 1kHz VOLTAGE NOISE (nV/√Hz) SLEW RATE (V/µs) 5 4 3 2 100 10 10n 100n 1µ LOAD CAPACITANCE (F) 1 1 8 VS = ±15V 20V STEP ±20 TA = +25°C 7 POSITIVE SUPPLY CURRENT (mA) 50 40 30 20 6 5 4 3 2 1 1 10 100 VOLTAGE GAIN (G) 1k 14335-025 SETTLING TIME (µs) 1k Figure 27. RTI Voltage Noise Density vs. Gain 60 10 100 VOLTAGE GAIN (G) Figure 24. Slew Rate vs. Load Capacitance 70 10 14335-027 1n 14335-024 0 100p 14335-028 1 Figure 25. Settling Time to 0.01% vs. Voltage Gain 0 0 ±5 ±10 ±15 POWER SUPPLY VOLTAGE (V) Figure 28. Positive Supply Current vs. Supply Voltage Rev. F | Page 16 of 29 Data Sheet AMP01 –6 –7 NEGATIVE SUPPLY CURRENT (mA) NEGATIVE SUPPLY CURRENT (mA) TA = +25°C –6 –5 –4 –3 –2 0 0 ±10 ±5 ±15 ±20 POWER SUPPLY VOLTAGE (V) 14335-029 –1 Figure 29. Negative Supply Current vs. Supply Voltage 5 4 3 2 1 –25 0 25 50 75 100 125 TEMPERATURE (°C) 150 14335-030 POSITIVE SUPPLY CURRENT (mA) VS = ±15V –50 –5 –4 –3 –2 –1 0 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 31. Negative Supply Current vs. Temperature 6 0 –75 VS = ±15V VSENSE = VREF = 0V Figure 30. Positive Supply Current vs. Temperature Rev. F | Page 17 of 29 150 14335-031 –8 AMP01 Data Sheet THEORY OF OPERATION INPUT AND OUTPUT OFFSET VOLTAGES INPUT BIAS AND OFFSET CURRENTS Instrumentation amplifiers have independent offset voltages associated with the input and output stages. Still, temperature variations cause offset shifts regardless of initial zero adjustments. Systems with auto-zero correct for offset errors, rendering initial adjustment unnecessary. However, many high gain applications do not have auto-zero. For such applications, both offsets can be nulled, which has minimal effect on TCVIOS and TCVOOS. Input transistor bias currents are additional error sources that can degrade the input signal. Bias currents flowing through the signal source resistance appear as an additional offset voltage. Equal source resistance on both inputs of an instrumentation amplifier (IA) minimizes offset changes due to bias current variations with signal voltage and temperature. However, the difference between the two bias currents, the input offset current, produces a nontrimmable error. The magnitude of the error is the offset current times the source resistance. The input offset component is directly multiplied by the amplifier gain, whereas output offset is independent of gain. Therefore, at low gain, output offset errors dominate, whereas at high gain, input offset errors dominate. The overall offset voltage, VOS, referred to the output (RTO) is calculated as follows: VOS (RTO) = (VIOS × G) + VOOS (1) A current path must always be provided between the differential inputs and analog ground to ensure correct amplifier operation. Floating inputs, such as thermocouples, must be grounded close to the signal source for best common-mode rejection. GAIN where: VIOS is the input offset voltage specification. VOOS is the output offset voltage specification. G is the amplifier gain. The AMP01 uses two external resistors for setting voltage gain over the range of 0.1 to 10,000. The magnitudes of the scale resistor, RS, and the gain set resistor, RG, are related by the formula G = 20 × RS/RG, where G is the selected voltage gain (see Figure 32). Input offset nulling alone is recommended with amplifiers having fixed gain above 50. Output offset nulling alone is recommended when gain is fixed at 50 or below. V+ RS TCVOOS G (3) 100 V / C 1000 15 13 SENSE 12 AMP01 3 10 20 RS RG 7 9 8 11 REFERENCE V– OUTPUT Figure 32. Basic AMP01 Connections for Gains of 0.1 to 10,000 For example, the maximum input referred drift of an AMP01EX set to G = 1000 becomes, TCVOS (RTI )  0.3 V / C  –IN 2 VOLTAGE GAIN, G = Frequently, the amplifier drift is referred back to the input (RTI), which is then equivalent to an input signal change: TCVOS (RTI )  TCVIOS RG (2) where: TCVIOS is the input offset voltage drift. TCVOOS is the output offset voltage specification. 14 1 The overall offset voltage drift, TCVOS, referred to the output is a combination of input and output drift specifications. Input offset voltage drift is multiplied by the amplifier gain, G, and summed with the output offset drift: TCVOS (RTO) = (TCVIOS × G) + TCVOOS 18 +IN 14335-032 In applications requiring both initial offsets to be nulled, the input offset is nulled first by short circuiting RG, then the output offset is nulled with the short removed.  0.4 V / C max The magnitude of RS affects linearity and output referred errors. Circuit performance is characterized using RS = 10 kΩ when operating on ±15 V supplies and driving a ±10 V output. RS can be reduced to 5 kΩ in many applications, particularly when operating on ±5 V supplies, or if the output voltage swing is limited to ±5 V. Bandwidth is improved with RS = 5 kΩ, increasing the common-mode rejection by approximately 6 dB at low gain. Reducing the value below 5 kΩ can cause instability in some circuit configurations and usually has no advantage. High voltage gains between 2 and 10,000 require very low values of RG. For RS = 10 kΩ and AV = 2000, RG = 100 Ω; this value is the practical lower limit for RG. Below 100 Ω, mismatch of wire bond and resistor temperature coefficients (TCs) introduce significant gain TC errors. Therefore, for gains above 2000, RG must be kept constant at 100 Ω and RS increased. The maximum gain of 10,000 is obtained with RS set to 50 kΩ. Rev. F | Page 18 of 29 Data Sheet AMP01 Metal film or wire wound resistors are recommended for best results. The absolute values and TCs are not too important, only the ratiometric parameters. by small resistances in series with the reference input. A slight but trimmable output offset voltage change results from resistance in series with the reference input. AC amplifiers require good gain stability with temperature and time, but dc performance is unimportant. Therefore, low cost metal film types with TCs of 50 ppm/°C are usually adequate for RS and RG. Realizing the full potential of the offset voltage and gain stability of the AMP01 requires precision metal film or wire wound resistors. Achieving a 15 ppm/°C gain TC at all gains requires RS and RG temperature coefficient matching to 5 ppm/°C or better. The common-mode input voltage range (CMVR) for linear operation can be calculated from the formula, 1M VS = ±15V (4) where: IVR is the data sheet specification for the input voltage range. VOUT is the maximum output signal. G is the chosen voltage gain. For example, at 25°C, IVR is specified as ±10.5 V minimum with ±15 V supplies. Using a ±10 V maximum swing output and substituting the figures in Equation 4 simplifies the formula to 100k RESISTANCE (Ω) |V |  CMVR    IVR  OUT  2G   5 CMVR   10.5   G  RS 10k For all gains greater than or equal to 10, CMVR is ±10 V minimum; at gains below 10, CMVR is reduced. RG 1k (5) 100 1 10 100 VOLTAGE GAIN 1k 10k 14335-033 ACTIVE GUARD DRIVE Figure 33. RG and RS Selection Gain accuracy is determined by the ratio accuracy of RS and RG combined with the gain equation error of the AMP01 (0.6% maximum for A and E grades). All instrumentation amplifiers require attention to layout so that thermocouple effects are minimized. Thermocouples formed between copper and dissimilar metals can destroy the TCVOS performance of the AMP01, which is typically 0.15 μV/°C. Resistors themselves can generate thermoelectric EMFs when mounted parallel to a thermal gradient. Vishay resistors are recommended because a maximum value for thermoelectric generation is specified. However, where thermal gradients are low and gain TCs of 20 ppm to 50 ppm are sufficient, generalpurpose metal film resistors can be used for RG and RS. COMMON-MODE REJECTION Ideally, an instrumentation amplifier responds only to the difference between the two input signals and rejects commonmode voltages and noise. In practice, there is a small change in output voltage when both inputs experience the same commonmode voltage change; the ratio of these voltages is called the common-mode gain. Common-mode rejection (CMR) is the logarithm of the ratio of differential-mode gain to commonmode gain, expressed in dB. CMR specifications are normally measured with a full-range input voltage change and a specified source resistance unbalance. The current feedback design used in the AMP01 inherently yields high common-mode rejection. Unlike resistive feedback designs, typified by the 3-op-amp IA, the CMR is not degraded Rejection of common-mode noise and line pickup can be improved by using shielded cable between the signal source and the IA. Shielding reduces pickup, but increases input capacitance, which in turn degrades the settling-time for signal changes. Furthermore, any imbalance in the source resistance between the inverting and noninverting inputs, when capacitively loaded, converts the common-mode voltage into a differential voltage. This effect reduces the benefits of shielding. AC common-mode rejection is improved by bootstrapping the input cable capacitance to the input signal, a technique called guard driving. This technique effectively reduces the input capacitance. A single guard-driving signal is adequate at gains above 100 and must be the average value of the two inputs. The value of the external gain resistor, RG, is split between two resistors, RG1 and RG2; the center tap provides the required signal to drive the buffer amplifier (see Figure 34). GROUNDING The majority of instruments and data acquisition systems have separate grounds for analog and digital signals. Analog ground can also be divided into two or more grounds that are tied together at one point, usually the analog power-supply ground. In addition, the digital and analog grounds can be joined, normally at the analog ground pin on the analog-to-digital converter (ADC). Following this basic grounding practice is essential for good circuit performance (see Figure 35). Mixing grounds causes interactions between digital circuits and the analog signals. Because the ground returns have finite resistance and inductance, hundreds of millivolts can be developed between the system ground and the data acquisition components. Using separate ground returns minimizes the current flow in the sensitive analog return path to the system Rev. F | Page 19 of 29 AMP01 Data Sheet ground point. Consequently, noisy ground currents from logic gates do not interact with the analog signals. SENSE AND REFERENCE TERMINALS The sense terminal completes the feedback path for the instrumentation amplifier output stage and is normally connected directly to the output. The output signal is specified with respect to the reference terminal, which is normally connected to analog ground. Inevitably, two or more circuits are joined together with their grounds at differential potentials. In these situations, the differential input of an instrumentation amplifier, with its high CMR, can accurately transfer analog information from one circuit to another. VOLTAGE GAIN, G = 20 RS RG1 RS 10kΩ AV = 500 WITH COMPONENTS SHOWN * RS +15V 7 6 GUARD DRIVE 2 RG3 200Ω 3 RG2 200Ω 741 1 RG1 400Ω 4 –15V –IN 6 SENSE 13 3 RG 17 R1 1MΩ 9 V– R5 8 5 OUTPUT * 11 VOOS NULL VIOS NULL 7 V+ 10 *SOLDER LINK 4 16 R2 1MΩ * 12 RG AMP01 2 10µF 14 RS 18 + C5 C1 0.047µF R4 NC 15 +IN +15V C3 0.047µF * VR2 100kΩ REFERENCE VR1 100kΩ R3 * C4 0.047µF + C6 GROUND C2 0.047µF 10µF 14335-034 SIGNAL GROUND –15V Figure 34. AMP01 Evaluation Circuit Showing Guard-Drive Connection ANALOG POWER SUPPLY +15V DIGITAL POWER SUPPLY 0V –15V 0V +5V 4.7µF + C C 7 AMP01 9 DIGITAL GROUND C SMP-11 SAMPLE AND HOLD C C C ANALOG GROUND DIGITAL GROUND ADC 8 OUTPUT REFERENCE DIGITAL DATA OUTPUT HOLD CAPACITOR C = 0.047µF CERAMIC CAPACITORS Figure 35. Basic Grounding Practice Rev. F | Page 20 of 29 14335-035 C Data Sheet AMP01 If heavy output currents are expected and the load is situated some distance from the amplifier, voltage drops due to track or wire resistance cause errors. Voltage drops are particularly troublesome when driving 50 Ω loads. Under these conditions, the sense and reference terminals can be used to remote sense the load, as shown in Figure 36. This method of connection puts the I × R drops inside the feedback loop and virtually eliminates the error. An unbalance in the lead resistances from the sense and reference pins does not degrade CMR, but does change the output offset voltage. For example, a large unbalance of 3 Ω changes the output offset by only 1 mV. DRIVING 50 Ω LOADS Output currents of 50 mA are guaranteed into loads of up to 50 Ω and 26 mA into 500 Ω. In addition, the output is stable and free from oscillation even with a high load capacitance. The combination of these unique features in an instrumentation amplifier allows low level transducer signals to be conditioned and directly transmitted through long cables in voltage or current form. Increased output current brings increased internal dissipation, especially with 50 Ω loads. For this reason, the power-supply connections are split into two pairs; Pin 10 and Pin 13 connect to the output stage only, and Pin 11 and Pin 12 provide power to the input and following stages. Dual supply pins allow dropper resistors to be connected in series with the output stage so excess power is dissipated outside the package. Additional decoupling is necessary between Pin 10 and Pin 13 to ground to maintain stability when dropper resistors are used. Figure 37 shows a complete circuit for driving 50 Ω loads. V+ RS * IN4148 DIODES ARE OPTIONAL. DIODES LIMIT THE OUTPUT VOLTAGE EXCURSION IF SENSE AND/OR REFERENCE LINES BECOME DISCONNECTED FROM THE LOAD. 14 18 15 SENSE 12 1 13 * 7 RG AMP01 2 10 8 REFERENCE REMOTE LOAD TWISTED PAIRS 11 3 * OUTPUT GROUND V– Figure 36. Remote Load Sensing POWER BANDWIDTH, G = 100, 130kHz POWER BANDWIDTH, G = 10, 200kHz THD: ~0.04% AT 1kHz, 2V rms +15V R1 130Ω 1W RS 5kΩ 0.047µF C1 0.047µF 14 18 +IN 15 12 SENSE 13 1 7 8 2 VOLTAGE GAIN, G = 10 20 C2 0.047µF R2 130Ω 1W RS 50Ω LOAD REFERENCE 11 3 –IN VOUT ±3V MAX 9 AMP01 RG 0.047µF –15V 14335-037 –IN 9 14335-036 +IN RG R1 AND R2 RESISTORS REDUCE IC DISSIPATION Figure 37. Driving 50 Ω Loads Rev. F | Page 21 of 29 AMP01 Data Sheet HEATSINKING To maintain high reliability, the die temperature of any IC must be kept as low as practicable, preferably below 100°C. Although most AMP01 application circuits produce very little internal heat—little more than the quiescent dissipation of 90 mW— some circuits raise that to several hundred milliwatts (for example, the 4 mA to 20 mA current transmitter application; see Figure 40). Excessive dissipation causes thermal shutdown of the output stage, thus protecting the device from damage. A heatsink is recommended in power applications to reduce the die temperature. Several appropriate heatsinks are available; the Thermalloy 6010B is especially easy to use and is inexpensive. Intended for dual-in-line packages, the heatsink can be attached with a cyanoacrylate adhesive. This heatsink reduces the thermal resistance between the junction and ambient environment to approximately 80°C/W. Junction (die) temperature can then be calculated by using the following relationship: TJ  TA External series resistors can be added to guard against higher voltage levels at the input, but resistors alone increase the input noise and degrade the signal-to-noise ratio, especially at high gains. Protection can also be achieved by connecting back to back 9.1 V Zener diodes across the differential inputs. This technique does not affect the input noise level and can be used down to a gain of 2 with minimal increase in input current. Although voltage-clamping elements look like short circuits at the limiting voltage, the majority of signal sources provide less than 50 mA, producing power levels that are easily handled by low power Zener diodes. Simultaneous connection of the differential inputs to a low impedance signal above 10 V during normal circuit operation is unlikely. However, additional protection involves adding 100 Ω current-limiting resistors in each signal path prior to the voltage clamp, the resistors increase the input noise level to just 5.4 nV/√Hz (refer to Figure 38). θ JA where: Pd is the internal dissipation of the device. TJ is the junction temperature. TA is the ambient temperature. θJA is the thermal resistance from junction to ambient. Input components, whether multiplexers or resistors, should be carefully selected to prevent the formation of thermocouple junctions that would degrade the input signal. OVERVOLTAGE PROTECTION Instrumentation amplifiers invariably sit at the front end of instrumentation systems where there is a high probability of exposure to overloads. Voltage transients, failure of a transducer, or removal of the amplifier power supply while the signal source is connected can destroy or degrade the performance of an unprotected amplifier. Although it is impractical to protect an IC internally against connection to power lines, it is relatively easy to provide protection against typical system overloads. The AMP01 is internally protected against overloads for gains of up to 100. At higher gains, the protection is reduced and some external measures may be required. Limited internal overload protection is used so that noise performance is not significantly degraded. AMP01 noise level approaches the theoretical noise floor of the input stage, which is 4 nV/√Hz at 1 kHz when the gain is set at 1000. Noise is the result of shot noise in the input devices and Johnson noise in the resistors. Resistor noise is calculated from the values of RG (200 Ω at a gain of 1000) and the input protection resistors (250 Ω). Active loads for the input transistors contribute less than 1 nV/√Hz of noise. The measured noise level is typically 5 nV/√Hz. +15V +IN DIFFERENTIAL PROTECTION TO ±30V 100Ω 1W* 9.1V 1W ZENERS –IN LINEAR INPUT RANGE, ±5V MAXIMUM AMP01 VOUT 100Ω 1W* –15V *OPTIONAL PROTECTION RESISTORS, SEE TEXT. 14335-038 Pd  Diodes across the input transistor’s base-emitter junctions, combined with 250 Ω input resistors and RG, protect against differential inputs of up to ±20 V for gains of up to 100. The diodes also prevent avalanche breakdown that degrade the IB and IOS specifications. Decreasing the value of RG for gains above 100 limits the maximum input overload protection to ±10 V. Figure 38. Input Overvoltage Protection for Gains of 2 to 10,000 POWER SUPPLY CONSIDERATIONS Achieving the rated performance of precision amplifiers in a practical circuit requires careful attention to external influences. For example, supply noise and changes in the nominal voltage directly affect the input offset voltage. A PSR of 80 dB means that a change of 100 mV on the supply produces a 10 μV input offset change. Consequently, care must be taken in choosing a power source with low output noise, good line and load regulation, and good temperature stability. Rev. F | Page 22 of 29 Data Sheet AMP01 APPLICATIONS CIRCUITS +15V COMPLIANCE, TYPICALLY ±10V LINEARITY ~0.01% OUTPUT RESISTANCE AT 20mA ~5MΩ POWER BANDWIDTH (–3dB) ~60kHz INTO 500Ω LOAD 0.047µF 18 1 VIN ROUT TRIM 12 V+ RG 13 SENSE 7 RG 2kΩ 9 AMP01 2 R1 100Ω IOUT 8 RG V– RS 10 REFERENCE 11 RS 15 3 –IN R2 200Ω IOUT = VIN 14 0.047µF RS R1 R1 = 100Ω FOR IOUT = ±20mA VIN = ±100mV FOR ±20mA FULL SCALE –15V RS 2kΩ 20 RG 14335-039 +IN Figure 39. High Compliance Bipolar Current Source with 13-Bit Linearity ALL RESISTORS 1% METAL FILM RS 2kΩ 18 +IN 14 RS 15 RS RG RG 2.75kΩ 13 7 9 AMP01 2 8 RG V– 10 11 3 R4 100Ω R2 200Ω ROUT TRIM 2 4 REF-02 R5 2.21kΩ 6 R6 500Ω ZERO TRIM 0V 0.047µF R1 100Ω IOUT 4mA TO 20mA –5V COMPLIANCE OF IOUT, +20V WITH +30V SUPPLY (OUTPUT WITH REGARDS TO 0V) DIFFERENTIAL INPUT OF 100mV FOR 16mA SPAN OUTPUT RESISTANCE ~5MΩ AT IOUT = 20mA LINEARITY 0.01% OF SPAN Figure 40. 13-Bit Linear 4 mA to 20 mA Transmitter Constructed by Adding a Voltage Reference; Thermocouple Signals can be Accepted Without Preamplification Rev. F | Page 23 of 29 14335-040 –IN R3 100Ω 12 V+ 1 +15V TO +30V 0.047µF AMP01 Data Sheet +15V + 10µF 0.047µF 10kΩ 14 RS 18 +IN 1 2N4921 15 RS 12 V+ 0.047µF 13 SENSE 7 9 RG AMP01 RG 2 VOUT (±10V INTO 10Ω) 8 REFERENCE RG 10 V– 11 3 –IN 100Ω 2N4918 GND 14335-041 0.047µF VOLTAGE GAIN, G = 100 POWER BANDWIDTH (–3dB), 60kHz QUIESCENT CURRENT, 4mA LINEARITY ~0.01% AT FULL OUTPUT INTO 10Ω 10uF –15V Figure 41. Adding Two Transistors Increases Output Current to ±1 A Without Affecting the Quiescent Current of 4 mA; Power Bandwidth is 60 kHz Q1, Q2...........J110 Q3, Q4, Q5....J107 IC1 ...............CMP-04 IC2 ...............OP15GZ 18 +IN 1 –IN 200kΩ 20kΩ 2kΩ Q5 Q3 47kΩ 12 V+ 2 3 3 2 2 1 14 RG VIOS NULL VOOS NULL V– 17 10 5 11 2.7kΩ + + + + GND 100kΩ IC1 LINEARITY ~0.005%, G = 10 AND 100 ~0.02%, G = 1 AND 1000 12 GAIN ACCURACY, UNTRIMMED ~0.5% 5 7 G1 G10 9 G100 11 –15V G1000 SETTLING TIME TO 0.01%, ALL GAINS, LESS THAN 75µs GAIN SWITCHING TIME, LESS THAN 100µs TTL-COMPATIBLE INPUTS Figure 42. AMP01 Makes an Excellent Programmable-Gain Instrumentation Amplifier; Combined Gain-Switching and Settling Time to 13 Bits Falls Below 100 μs; Linearity is Better than 12 Bits over a Gain Range of 1 to 1000 Rev. F | Page 24 of 29 14335-042 +15V 27kΩ 3 4 6 8 10 REFERENCE 0.047µF –15V 100kΩ OUT 8 4 16 13 SENSE 7 9 13 AMP01 Q1 +15V 4 15 RS Q2 47kΩ IC2 RG 0.047µF Q4 47kΩ 7 14 RS 196Ω 47kΩ 6 +15V RS 10kΩ Data Sheet AMP01 RS 10kΩ +15V 0.047µF 18 +IN *5kΩ RS 15 RS 1 *MATCHED TO 0.1% 0V 14 12 V+ 13 7 9 AMP01 RG 2 1.5kΩ SENSE RG *5kΩ 2 470pF 8 RG REFERENCE 10 V– 11 3 7 6 OP37 4 3 –IN 0.047µF 0V 20 –15V RS RG RL MAXIMUM OUTPUT, 20V p-p INTO 600Ω THD: 0.01% AT 1kHz, 20V p-p INTO 600Ω, G = 10 + OUTPUT DIFFERENTIAL COMMON-MODE OUTPUT REFERENCE (±5V MAX) 14335-043 VOLTAGE GAIN, G = Figure 43. A Differential Input Instrumentation Amplifier with Differential Output Replaces a Transformer in Many Applications; Output Drives a 600 Ω Load at Low Distortion (0.01%) +15V 8 REF 0.047µF 1 12 V+ 13 RG 9 AMP01 R1 390Ω 2 RG RS 3 RS 14 NC V– 11 VOUT 10 R2 4.95kΩ 15 0.047µF NC + CL RL 10µF –15V R3 50Ω CLOSED-LOOP VOLTAGE GAIN MUST BE GREATER THAN 50 FOR STABLE OPERATION NC = NO CONNECT 10µF 7 SENSE VIN TOTAL HARMONIC DISTORTION~0.006% AT 1kHz, 20V p-p INTO 500Ω // 1000pF + VOLTAGE GAIN, G = 1 + R2 R3 Figure 44. Configuring the AMP01 as a Noninverting Operational Amplifier Provides Exceptional Performance; Output Handles Low Load Impedances at Very Low Distortion (0.006%) Rev. F | Page 25 of 29 14335-044 18 POWER BANDWIDTH (–3dB)~150kHz AMP01 Data Sheet NC VIN R1 NC 14 RS 3 0.01µF 2 7 8 SENSE REF 9 AMP01 1 R3 15 RS RG R4 4.7kΩ R2 220kΩ RG V+ 12 18 10 V– 11 20V p-p INTO 500Ω // 1000pF. TOTAL HARMONIC DISTORTION: