CED1Z

8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC AD7606/AD7606-6/AD7606-4 FEATURES 8/6/4 simultaneously sampled inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 16-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Performance 7 kV ESD rating on analog input channels 95.5 dB SNR, −107 dB THD ±0.5 LSB INL, ±0.5 LSB DNL Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package APPLICATIONS Power-line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions SingleEnded Inputs AD7608 AD7606 AD7606-6 AD7606-4 AD7607 True Differential Inputs AD7609 Number of Simultaneous Sampling Channels 8 8 6 4 8 Resolution 18 Bits 16 Bits 14 Bits FUNCTIONAL BLOCK DIAGRAM AVCC 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF AVCC REGCAP REGCAP REFCAPB REFCAPA V1 V1GND CLAMP CLAMP T/H 2.5V LDO 2.5V LDO REFIN/REFOUT T/H 2.5V REF T/H REF SELECT AGND OS 2 OS 1 OS 0 T/H SERIAL 8:1 MUX T/H 16-BIT SAR DIGITAL FILTER PARALLEL/ SERIAL INTERFACE DOUTA DOUTB RD/SCLK CS PAR/SER/BYTE SEL VDRIVE T/H PARALLEL DB[15:0] V2 V2GND CLAMP CLAMP V3 V3GND CLAMP CLAMP V4 V4GND CLAMP CLAMP V5 V5GND CLAMP CLAMP V6 V6GND CLAMP CLAMP AD7606 T/H CLK OSC BUSY FRSTDATA 08479-001 V7 V7GND CLAMP CLAMP V8 V8GND CLAMP CLAMP T/H CONTROL INPUTS AGND CONVST A CONVST B RESET RANGE Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD7606/AD7606-6/AD7606-4 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  General Description ......................................................................... 3  Specifications..................................................................................... 4  Timing Specifications .................................................................. 7  Absolute Maximum Ratings.......................................................... 11  Thermal Resistance .................................................................... 11  ESD Caution ................................................................................ 11  Pin Configurations and Function Descriptions ......................... 12  Typical Performance Characteristics ........................................... 17  Terminology .................................................................................... 21  Theory of Operation ...................................................................... 22  Converter Details........................................................................ 22  Analog Input ............................................................................... 22  ADC Transfer Function ............................................................. 23  Internal/External Reference ...................................................... 24  Typical Connection Diagram ................................................... 25  Power-Down Modes .................................................................. 25  Conversion Control ................................................................... 26  Digital Interface .............................................................................. 27  Parallel Interface (PAR/SER/BYTE SEL = 0).......................... 27  Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) ............... 27  Serial Interface (PAR/SER/BYTE SEL = 1) ............................. 27  Reading During Conversion ..................................................... 28  Digital Filter ................................................................................ 29  Layout Guidelines....................................................................... 32  Outline Dimensions ....................................................................... 34  Ordering Guide .......................................................................... 34  REVISION HISTORY 5/10—Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD7606/AD7606-6/AD7606-4 GENERAL DESCRIPTION The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous sampling, analog-to-digital data acquisition systems (DAS) with eight, six, and four channels, respectively. Each part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7606/AD7606-6/AD7606-4 operate from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V. The AD7606 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth. 1 Patent pending. Rev. 0 | Page 3 of 36 AD7606/AD7606-6/AD7606-4 SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2, 3 Test Conditions/Comments fIN = 1 kHz sine wave unless otherwise noted Oversampling by 16; ±10 V range; fIN = 130 Hz Oversampling by 16; ±5 V range; fIN = 130 Hz No oversampling; ±10 V Range No oversampling; ±5 V range No oversampling; ±10 V range No oversampling; ±5 V range No oversampling; ±10 V range No oversampling; ±5 V range Min 94 93 88.5 87.5 88 87 Typ 95.5 94.5 90 89 90 89 90.5 90 −107 −108 −110 −106 −95 23 15 10 5 11 15 16 ±0.5 ±0.5 ±6 ±12 ±8 ±8 ±2 ±7 5 16 ±1 ±3 10 5 1 6 ±8 ±8 ±4 ±8 5 16 ±0.99 ±2 Max Unit dB dB dB dB dB dB dB dB dB dB dB dB dB kHz kHz kHz kHz μs μs Bits LSB 4 LSB LSB LSB LSB LSB ppm/°C ppm/°C LSB LSB LSB LSB μV/°C μV/°C LSB LSB LSB LSB ppm/°C ppm/°C LSB LSB Signal-to-(Noise + Distortion) (SINAD)2 Dynamic Range Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation2 ANALOG INPUT FILTER Full Power Bandwidth −95 fa = 1 kHz, fb = 1.1 kHz fIN on unselected channels up to 160 kHz −3 dB, ±10 V range −3 dB, ±5 V range −0.1 dB, ±10 V range −0.1 dB, ±5 V range ±10 V Range ±5 V Range No missing codes tGROUP DELAY DC ACCURACY Resolution Differential Nonlinearity2 Integral Nonlinearity2 Total Unadjusted Error (TUE) Positive Full-Scale Error2, 5 Positive Full-Scale Error Drift Positive Full-Scale Error Matching2 Bipolar Zero Code Error2, 6 Bipolar Zero Code Error Drift Bipolar Zero Code Error Matching2 Negative Full-Scale Error2, 5 Negative Full-Scale Error Drift Negative Full-Scale Error Matching2 ±10 V range ±5 V range External reference Internal reference External reference Internal reference ±10 V range ±5 V range ±10 V range ± 5 V range ±10 V range ± 5 V range ±10 V range ±5 V range External reference Internal reference External reference Internal reference ±10 V range ±5 V range ±32 32 40 ±6 ±12 8 22 ±32 32 40 Rev. 0 | Page 4 of 36 AD7606/AD7606-6/AD7606-4 Parameter ANALOG INPUT Input Voltage Ranges Analog Input Current Input Capacitance 7 Input Impedance REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance7 Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)7 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVCC VDRIVE ITOTAL Normal Mode (Static) Test Conditions/Comments RANGE = 1 RANGE = 0 10 V; see Figure 31 5 V; see Figure 31 See the Analog Input section See the ADC Transfer Function section REF SELECT = 1 REFIN/REFOUT 2.475 Min Typ Max ±10 ±5 5.4 2.5 5 1 2.5 7.5 2.49/ 2.505 ±10 0.9 × VDRIVE 0.1 × VDRIVE ±2 5 ISOURCE = 100 μA ISINK = 100 μA VDRIVE − 0.2 ±1 5 Twos complement All eight channels included; see Table 3 Per channel, all eight channels included 4.75 2.3 Digital inputs = 0 V or VDRIVE AD7606 AD7606-6 AD7606-4 fSAMPLE = 200 kSPS AD7606 AD7606-6 AD7606-4 16 14 12 20 18 15 5 2 4 1 200 5.25 5.25 22 20 17 27 24 21 8 6 μs μs kSPS V V mA mA mA mA mA mA mA μA 0.2 ±20 2.525 ±1 Unit V V μA μA pF MΩ V μA pF V ppm/°C V V μA pF V V μA pF Normal Mode (Operational)8 Standby Mode Shutdown Mode Rev. 0 | Page 5 of 36 AD7606/AD7606-6/AD7606-4 Parameter Power Dissipation Normal Mode (Static) Normal Mode (Operational) 8 Test Conditions/Comments AD7606 fSAMPLE = 200 kSPS AD7606 AD7606-6 AD7606-4 Min Typ 80 100 90 75 25 10 Max 115.5 142 126 111 42 31.5 Unit mW mW mW mW mW μW Standby Mode Shutdown Mode 1 2 3 Temperature range for the B version is −40°C to +85°C. See the Terminology section. This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 4 LSB means least significant bit. With ±5 V input range, 1 LSB = 152.58 μV. With ±10 V input range, 1 LSB = 305.175 μV. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode. Rev. 0 | Page 6 of 36 AD7606/AD7606-6/AD7606-4 TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE Limit at TMIN, TMAX Min Typ Max Unit Description 1/throughput rate Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 4.75 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines Serial mode reading during conversion; VDRIVE = 3.3 V Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines Conversion time Oversampling off; AD7606 Oversampling off; AD7606-6 Oversampling off; AD7606-4 Oversampling by 2; AD7606 Oversampling by 4; AD7606 Oversampling by 8; AD7606 Oversampling by 16; AD7606 Oversampling by 32; AD7606 Oversampling by 64; AD7606 STBY rising edge to CONVST x rising edge; power-up time from standby mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode RESET high pulse width BUSY to OS x pin setup time BUSY to OS x pin hold time CONVST x high to BUSY high Minimum CONVST x low pulse Minimum CONVST x high pulse BUSY falling edge to CS falling edge setup time Maximum delay allowed between CONVST A, CONVST B rising edges Maximum time between last CS rising edge and BUSY falling edge Minimum delay between RESET low to CONVST x high 5 5 9.7 tCONV 2 3.45 4 3 2 4.15 μs μs μs μs μs μs μs μs μs μs μs μs μs 7.87 16.05 33 66 133 257 tWAKE-UP STANDBY tWAKE-UP SHUTDOWN Internal Reference External Reference tRESET tOS_SETUP tOS_HOLD t1 t2 t3 t4 t5 3 t6 t7 PARALLEL/BYTE READ OPERATION t8 t9 t10 50 20 20 9.1 18.8 39 78 158 315 100 30 13 ms ms ns ns ns ns ns ns ns ms ns ns 40 25 25 0 0.5 25 25 0 0 16 21 25 32 15 22 ns ns ns ns ns ns ns ns t11 t12 CS to RD setup time CS to RD hold time RD low pulse width VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V RD high pulse width CS high pulse width (see Figure 5); CS and RD linked Rev. 0 | Page 7 of 36 AD7606/AD7606-6/AD7606-4 Parameter t13 Limit at TMIN, TMAX Min Typ Max 16 20 25 30 t144 16 21 25 32 t15 t16 t17 SERIAL READ OPERATION fSCLK 23.5 17 14.5 11.5 t18 15 20 30 t19 4 17 23 27 34 t20 t21 t22 t23 FRSTDATA OPERATION t24 15 20 25 30 t25 15 20 25 30 t26 16 20 25 30 ns ns ns ns ns ns ns ns ns ns ns ns ns 0.4 tSCLK 0.4 tSCLK 7 22 ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz 6 6 22 ns ns ns ns ns ns ns Unit ns ns ns ns Description Delay from CS until DB[15:0] three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data access time after RD falling edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data hold time after RD falling edge CS to DB[15:0] hold time Delay from CS rising edge to DB[15:0] three-state enabled Frequency of serial read clock VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE = 2.3 V to 2.7 V Data access time after SCLK rising edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V SCLK low pulse width SCLK high pulse width SCLK rising edge to DOUTA/DOUTB valid hold time CS rising edge to DOUTA/DOUTB three-state enabled Delay from CS falling edge until FRSTDATA three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS falling edge until FRSTDATA high, serial mode VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from RD falling edge to FRSTDATA high VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Rev. 0 | Page 8 of 36 AD7606/AD7606-6/AD7606-4 Parameter t27 Limit at TMIN, TMAX Min Typ Max 19 24 t28 17 22 24 ns ns ns Unit ns ns Description Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25V VDRIVE = 2.3 V to 2.7V Delay from 16th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25V VDRIVE = 2.3 V to 2.7V Delay from CS rising edge until FRSTDATA three-state enabled t29 1 2 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N × tCONV) + ((N − 1) × 1 μs)). N is the oversampling ratio. For the AD7606-6, tCONV = 3 μs; and for the AD7606-4, tCONV = 2 μs. 3 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a 3.3 V, the SNR is reduced by ~1.5 dB when reading during a conversion. ±10V RANGE ±5V RANGE ATTENUATION (dB) INPUT FREQUENCY (Hz) Figure 37. Analog Antialiasing Filter Frequency Response 18 16 14 12 PHASE DELAY (µs) ±5V RANGE ADC TRANSFER FUNCTION The output coding of the AD7606/AD7606-6/AD7606-4 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is FSR/65,536 for the AD7606. The ideal transfer characteristic for the AD7606/AD7606-6/AD7606-4 is shown in Figure 39. ±10V CODE = VIN × 32,768 × 10V VIN ±5V CODE = × 32,768 × 5V REF 2.5V REF 2.5V 10 8 6 4 2 0 –2 ±10V RANGE 08479-036 10k 100k ADC CODE –4 AVCC, VDRIVE = 5V FSAMPLE = 200kSPS –6 TA = 25°C –8 10 1k 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 INPUT FREQUENCY (Hz) LSB = +FS – (–FS) 216 Figure 38. Analog Antialias Filter Phase Response Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7606/AD7606-6/ AD7606-4 allow the ADC to accurately acquire an input sine wave of full-scale amplitude to 16-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. The aperture time for the track-and- –FS + 1/2LSB 0V – 1/2LSB +FS – 3/2LSB ANALOG INPUT 08479-037 +FS ±10V RANGE +10V ±5V RANGE +5V MIDSCALE 0V 0V –FS –10V –5V LSB 305µV 152µV Figure 39. AD7606/AD7606-6/AD7606-4 Transfer Characteristics The LSB size is dependent on the analog input range selected. Rev. 0 | Page 23 of 36 AD7606/AD7606-6/AD7606-4 INTERNAL/EXTERNAL REFERENCE The AD7606/AD7606-6/AD7606-4 contain an on-chip 2.5 V bandgap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7606/AD7606-6/AD7606-4. An externally applied reference of 2.5 V is also gained up to 4.5 V, using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC. The REF SELECT pin is a logic input pin that allows the user to select between the internal reference or an external reference. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. The internal reference buffer is always enabled. After a reset, the AD7606/AD7606-6/AD7606-4 operate in the reference mode selected by the REF SELECT pin. Decoupling is required on the REFIN/REFOUT pin for both the internal and external reference options. A 10 μF ceramic capacitor is required on the REFIN/REFOUT pin. The AD7606/AD7606-6/AD7606-4 contain a reference buffer configured to gain the REF voltage up to ~4.5 V, as shown in Figure 40. The REFCAPA and REFCAPB pins must be shorted together externally, and a ceramic capacitor of 10 μF applied to REFGND, to ensure that the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. When the AD7606/AD7606-6/AD7606-4 are configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. For applications using multiple AD7606 devices, the following configurations are recommended, depending on the application requirements. External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7606 devices (see Figure 41). In this configuration, each REFIN/REFOUT pin of the AD7606/AD7606-6/AD7606-4 should be decoupled with at least a 100 nF decoupling capacitor. Internal Reference Mode One AD7606/AD7606-6/AD7606-4 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7606/AD7606-6/AD7606-4 devices, which are configured to operate in external reference mode (see Figure 42). The REFIN/ REFOUT pin of the AD7606/AD7606-6/AD7606-4, configured in internal reference mode, should be decoupled using a 10 μF ceramic decoupling capacitor. The other AD7606/AD7606-6/ AD7606-4 devices, configured in external reference mode, should use at least a 100 nF decoupling capacitor on their REFIN/REFOUT pins. REFIN/REFOUT SAR BUF REFCAPA 10µF REFCAPB 2.5V REF Figure 40. Reference Circuitry AD7606 REF SELECT REFIN/REFOUT AD7606 REF SELECT REFIN/REFOUT AD7606 REF SELECT REFIN/REFOUT 100nF 100nF 08479-038 100nF 0.1µF Figure 41. Single External Reference Driving Multiple AD7606/AD7606-6/ AD7606-4 REFIN Pins VDRIVE AD7606 REF SELECT REFIN/REFOUT AD7606 REF SELECT REFIN/REFOUT AD7606 REF SELECT REFIN/REFOUT + Figure 42. Internal Reference Driving Multiple AD7606/AD7606-6/AD7606-4 REFIN Pins Rev. 0 | Page 24 of 36 08479-039 10µF 100nF 100nF 08479-040 ADR421 AD7606/AD7606-6/AD7606-4 TYPICAL CONNECTION DIAGRAM Figure 43 shows the typical connection diagram for the AD7606/ AD7606-6/AD7606-4. There are four AVCC supply pins on the part, and each of the four pins should be decoupled using a 100 nF capacitor at each supply pin and a 10 μF capacitor at the supply source. The AD7606/AD7606-6/AD7606-4 can operate with the internal reference or an externally applied reference. In this configuration, the AD7606 is configured to operate with the internal reference. When using a single AD7606/AD7606-6/ AD7606-4 device on the board, the REFIN/REFOUT pin should be decoupled with a 10 μF capacitor. Refer to the Internal/External Reference section when using an application with multiple AD7606/AD7606-6/AD7606-4 devices. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 μF ceramic capacitor. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the output logic signals. For layout, decoupling, and grounding hints, see the Layout Guidelines section. The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the configurations required to choose the desired power-down mode. When the AD7606/AD7606-6/AD7606-4 are placed in standby mode, the current consumption is 8 mA maximum and powerup time is approximately 100 μs because the capacitor on the REFCAPA and REFCAPB pins must charge up. In standby mode, the on-chip reference and regulators remain powered up, and the amplifiers and ADC core are powered down. When the AD7606/AD7606-6/AD7606-4 are placed in shutdown mode, the current consumption is 6 μA maximum and power-up time is approximately 13 ms (external reference mode). In shutdown mode, all circuitry is powered down. When the AD7606/ AD7606-6/AD7606-4 are powered up from shutdown mode, a RESET signal must be applied to the AD7606/AD7606-6/ AD7606-4 after the required power-up time has elapsed. Table 7. Power-Down Mode Selection Power-Down Mode Standby Shutdown STBY 0 0 RANGE 1 0 POWER-DOWN MODES Two power-down modes are available on the AD7606/AD7606-6/ AD7606-4: standby mode and shutdown mode. The STBY pin controls whether the AD7606/AD7606-6/AD7606-4 are in normal mode or in one of the two power-down modes. ANALOG SUPPLY VOLTAGE 5V1 + DIGITAL SUPPLY VOLTAGE +2.3V TO +5.25V 10µF 1µF 100nF 100nF REFCAPA 10µF + REFCAPB REFGND V1 V1GND V2 V2GND V3 V3GND V4 V4GND V5 V5GND V6 V6GND V7 V7GND V8 V8GND CONVST A, CONVST B CS RD BUSY AD7606 RESET OS 2 OS 1 OS 0 REF SELECT PAR/SER SEL RANGE STBY AGND DB0 TO DB15 PARALLEL INTERFACE EIGHT ANALOG INPUTS V1 TO V8 OVERSAMPLING VDRIVE VDRIVE Figure 43. AD7606 Typical Connection Diagram Rev. 0 | Page 25 of 36 08479-041 1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). MICROPROCESSOR/ MICROCONVERTER/ DSP REFIN/REFOUT REGCAP2 AVCC VDRIVE AD7606/AD7606-6/AD7606-4 CONVERSION CONTROL Simultaneous Sampling on All Analog Input Channels The AD7606/AD7606-6/AD7606-4 allow simultaneous sampling of all analog input channels. All channels are sampled simultaneously when both CONVST pins (CONVST A, CONVST B) are tied together. A single CONVST signal is used to control both CONVST x inputs. The rising edge of this common CONVST signal initiates simultaneous sampling on all analog input channels (V1 to V8 for the AD7606, V1 to V6 for the AD7606-6, and V1 to V4 for the AD7606-4). The AD7606 contains an on-chip oscillator that is used to perform the conversions. The conversion time for all ADC channels is tCONV. The BUSY signal indicates to the user when conversions are in progress, so when the rising edge of CONVST is applied, BUSY goes logic high and transitions low at the end of the entire conversion process. The falling edge of the BUSY signal is used to place all eight track-and-hold amplifiers back into track mode. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus (DB[15:0]), the DOUTA and DOUTB serial data lines, or the parallel byte bus, DB[7:0]. transformers. In a 50 Hz system, this allows for up to 9° of phase compensation; and in a 60 Hz system, it allows for up to 10° of phase compensation. This is accomplished by pulsing the two CONVST pins independently and is possible only if oversampling is not in use. CONVST A is used to initiate simultaneous sampling of the first set of channels (V1 to V4 for the AD7606, V1 to V3 for the AD7606-6, and V1 and V2 for the AD7606-4); and CONVST B is used to initiate simultaneous sampling on the second set of analog input channels (V5 to V8 for the AD7606, V4 to V6 for the AD7606-6, and V3 and V4 for the AD7606-4), as illustrated in Figure 44. On the rising edge of CONVST A, the track-andhold amplifiers for the first set of channels are placed into hold mode. On the rising edge of CONVST B, the track-and-hold amplifiers for the second set of channels are placed into hold mode. The conversion process begins once both rising edges of CONVST x have occurred; therefore BUSY goes high on the rising edge of the later CONVST x signal. In Table 3, Time t5 indicates the maximum allowable time between CONVST x sampling points. There is no change to the data read process when using two separate CONVST x signals. Connect all unused analog input channels to AGND. The results for any unused channels are still included in the data read because all channels are always converted. Simultaneously Sampling Two Sets of Channels The AD7606/AD7606-6/AD7606-4 also allow the analog input channels to be sampled simultaneously in two sets. This can be used in power-line protection and measurement systems to compensate for phase differences introduced by PT and CT V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD CONVST A t5 CONVST B BUSY AD7606 CONVERTS ON ALL 8 CHANNELS tCONV CS/RD DATA: DB[15:0] V1 V2 V3 V7 V8 08479-042 FRSTDATA Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Mode Rev. 0 | Page 26 of 36 AD7606/AD7606-6/AD7606-4 DIGITAL INTERFACE The AD7606/AD7606-6/AD7606-4 provide three interface options: a parallel interface, a high speed serial interface, and a parallel byte interface. The required interface mode is selected via the PAR/SER/BYTE SEL and DB15/BYTE SEL pins. Table 8. Interface Mode Selection PAR/SER/BYTE SEL 0 1 1 DB15 0 0 1 Interface Mode Parallel interface mode Serial interface mode Parallel byte interface mode When the RD signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (DSP, FPGA). When there is only one AD7606/AD7606-6/AD7606-4 in a system/board and it does not share the parallel bus, data can be read using just one control signal from the digital host. The CS and RD signals can be tied together, as shown in Figure 5. In this case, the data bus comes out of three-state on the falling edge of CS/RD. The combined CS and RD signal allows the data to be clocked out of the AD7606/AD7606-6/AD7606-4 and to be read by the digital host. In this case, CS is used to frame the data transfer of each data channel. Operation of the interface modes is discussed in the following sections. PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0) Data can be read from the AD7606/AD7606-6/AD7606-4 via the parallel data bus with standard CS and RD signals. To read the data over the parallel bus, the PAR/SER/BYTE SEL pin should be tied low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB0, leave their high impedance state when both CS and RD are logic low. AD7606 BUSY 14 CS 13 RD/SCLK 12 DB[15:0] [22:16] [33:24] PARALLEL BYTE (PAR/SER/BYTE SEL = 1, DB15 = 1) Parallel byte interface mode operates much like the parallel interface mode, except that each channel conversion result is read out in two 8-bit transfers. Therefore, 16 RD pulses are required to read all eight conversion results from the AD7606. For the AD7606-6, 12 RD pulses are required; and on the AD7606-4, eight RD pulses are required to read all the channel results. To configure the AD7606/AD76706-6/AD7606-4 to operate in parallel byte mode, the PAR/SER/BYTE SEL and BYTE SEL/ DB15 pins should be tied to logic high (see Table 8). In parallel byte mode, DB[7:0] are used to transfer the data to the digital host. DB0 is the LSB of the data transfer, and DB7 is the MSB of the data transfer. In parallel byte mode, DB14 acts as an HBEN pin. When DB14/HBEN is tied to logic high, the most significant byte (MSB) of the conversion result is output first, followed by the LSB of the conversion result. When DB14 is tied to logic low, the LSB of the conversion result is output first, followed by the MSB of the conversion result. The FRSTDATA pin remains high until the entire 16 bits of the conversion result from V1 are read from the AD7606/AD7606-6/AD7606-4. INTERRUPT Figure 45. AD7606 Interface Diagram—One AD7606 Using the Parallel Bus, with CS and RD Shorted Together The rising edge of the CS input signal three-states the bus, and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines; it is the function that allows multiple AD7606/ AD7606-6/ AD7606-4 devices to share the same parallel data bus. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results as shown in Figure 4. A read operation of new data can take place after the BUSY signal goes low (see Figure 2); or, alternatively, a read operation of data from the previous conversion process can take place while BUSY is high (see Figure 3). The RD pin is used to read data from the output conversion results register. Applying a sequence of RD pulses to the RD pin of the AD7606/AD7606-6/AD7606-4 clocks the conversion results out from each channel onto the Parallel Bus DB[15:0] in ascending order. The first RD falling edge after BUSY goes low clocks out the conversion result from Channel V1. The next RD falling edge updates the bus with the V2 conversion result, and so on. On the AD7606, the eighth falling edge of RD clocks out the conversion result for Channel V8. 08479-043 DIGITAL HOST SERIAL INTERFACE (PAR/SER/BYTE SEL = 1) To read data back from the AD7606 over the serial interface, the PAR/SER/BYTE SEL pin must be tied high. The CS and SCLK signals are used to transfer data from the AD7606. The AD7606/ AD7606-6/AD7606-4 have two serial data output pins, DOUTA and DOUTB. Data can be read back from the AD7606/AD767066/AD7606-4 using one or both of these DOUT lines. For the AD7606, conversion results from Channel V1 to Channel V4 first appear on DOUTA, and conversion results from Channel V5 to Channel V8 first appear on DOUTB. For the AD7606-6, conversion results from Channel V1 to Channel V3 first appear on DOUTA, and conversion results from Channel V4 to Channel V6 first appear on DOUTB. For the AD7606-4, conversion results from Channel V1 and Channel V2 first appear on DOUTA, and conversion results from Channels V3 and Channel V4 first appear on DOUTB. Rev. 0 | Page 27 of 36 AD7606/AD7606-6/AD7606-4 The CS falling edge takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. The CS input can be held low for the entire serial read operation, or it can be pulsed to frame each channel read of 16 SCLK cycles. Figure 46 shows a read of eight simultaneous conversion results using two DOUT lines on the AD7606. In this case, a 64 SCLK transfer is used to access data from the AD7606, and CS is held low to frame the entire 64 SCLK cycles. Data can also be clocked out using just one DOUT line, in which case it is recommended that DOUTA be used to access all conversion data because the channel data is output in ascending order. For the AD7606 to access all eight conversion results on one DOUT line, a total of 128 SCLK cycles is required. These 128 SCLK cycles can be framed by one CS signal, or each group of 16 SCLK cycles can be individually framed by the CS signal. The disadvantage of using just one DOUT line is that the throughput rate is reduced if reading occurs after conversion. The unused DOUT line should be left unconnected in serial mode. For the AD7606, if DOUTB is to be used as a single DOUT line, the channel results are output in the following order: V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA indicator returns low after V5 is read on DOUTB. For the AD7606-6 and the AD7606-4, if DOUTB is to be used as a single DOUT line, the channel results are output in the following order: V4, V5, V6, V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for the AD7606-4. Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7606/AD7606-6/ AD7606-4 in serial mode. The SCLK input signal provides the clock source for the serial read operation. The CS goes low to access the data from the AD7606/AD7606-6/AD7606-4. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 16-bit conversion result. This MSB is valid on the first falling edge of the SCLK after the CS falling edge. The subsequent 15 data bits are clocked out of the AD7606/ AD7606-6/AD7606-4 on the SCLK rising edge. Data is valid on the SCLK falling edge. To access each conversion result, 16 clock cycles must be provided to the AD7606/AD7606-6/AD7606-4. The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of CS takes FRSTDATA out of three-state and sets the FRSTDATA pin high, indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 16th SCLK falling edge. If all channels are read on DOUTB, the FRSTDATA output does not go high when V1 is being output on this serial data output pin. It goes high only when V1 is available on DOUTA (and this is when V5 is available on DOUTB for the AD7606). READING DURING CONVERSION Data can be read from the AD7606/AD7606-6/AD7606-4 while BUSY is high and the conversions are in progress. This has little effect on the performance of the converter, and it allows a faster throughput rate to be achieved. A parallel, parallel byte, or serial read can be performed during conversions and when oversampling may or may not be in use. Figure 3 shows the timing diagram for reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved when using the serial interface with VDRIVE above 4.75 V. Data can be read from the AD7606 at any time other than on the falling edge of BUSY because this is when the output data registers are updated with the new conversion data. Time t6, as outlined in Table 3, should be observed in this condition. CS 64 SCLK DOUTA DOUTB V1 V2 V3 V4 08479-044 V5 V6 V7 V8 Figure 46. AD7606 Serial Interface with Two DOUT Lines Rev. 0 | Page 28 of 36 AD7606/AD7606-6/AD7606-4 DIGITAL FILTER The AD7606/AD7606-6/AD7606-4 contain an optional digital first-order sinc filter that should be used in applications where slower throughput rates are used or where higher signal-to-noise ratio or dynamic range is desirable. The oversampling ratio of the digital filter is controlled using the oversampling pins, OS [2:0] (see Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB control bit. Table 9 provides the oversampling bit decoding to select the different oversample rates. The OS pins are latched on the falling edge of BUSY. This sets the oversampling rate for the next conversion (see Figure 48). In addition to the oversampling function, the output result is decimated to 16-bit resolution. If the OS pins are set to select an OS ratio of eight, the next CONVST x rising edge takes the first sample for each channel, and the remaining seven samples for all channels are taken with an internally generated sampling signal. These samples are then averaged to yield an improvement in SNR performance. Table 9 shows typical SNR performance for both the ±10 V and the ±5 V range. As Table 9 shows, there is an improvement in SNR as the OS ratio increases. As the OS ratio increases, the 3 dB frequency is reduced, and the allowed sampling frequency is also reduced. In an application where the required sampling frequency is 10 kSPS, an OS ratio of up to 16 can be used. In this case, the application sees an improvement in SNR, but the input 3 dB bandwidth is limited to ~6 kHz. The CONVST A and CONVST B pins must be tied/driven together when oversampling is turned on. When the oversampling function is turned on, the BUSY high time for the conversion process extends. The actual BUSY high time depends on the oversampling rate that is selected: the higher the oversampling rate, the longer the BUSY high, or total conversion time (see Table 3). CONVST A AND CONVST B CONVERSION N BUSY OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 CONVERSION N + 1 CONVST A AND CONVST B tCYCLE tCONV 19µs 9µs 4µs BUSY OS = 0 OS = 2 OS = 4 t4 CS t4 t4 RD DATA: DB[15:0] 08479-046 Figure 47. AD7606—No Oversampling, Oversampling × 2, and Oversampling × 4 While Using Read After Conversion Figure 47 shows that the conversion time extends as the oversampling rate is increased, and the BUSY signal lengthens for the different oversampling rates. For example, a sampling frequency of 10 kSPS yields a cycle time of 100 μs. Figure 47 shows OS × 2 and OS × 4; for a 10 kSPS example, there is adequate cycle time to further increase the oversampling rate and yield greater improvements in SNR performance. In an application where the initial sampling or throughput rate is at 200 kSPS, for example, and oversampling is turned on, the throughput rate must be reduced to accommodate the longer conversion time and to allow for the read. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the BUSY high time. The falling edge of BUSY is used to update the output data registers with the new conversion data; therefore, the reading of conversion data should not occur on this edge. tOS_HOLD OS x 08479-045 tOS_SETUP Figure 48. OS x Pin Timing Table 9. Oversample Bit Decoding OS[2:0] 000 001 010 011 100 101 110 111 OS Ratio No OS 2 4 8 16 32 64 Invalid SNR 5 V Range (dB) 89 91.2 92.6 94.2 95.5 96.4 96.9 SNR 10 V Range (dB) 90 92 93.6 95 96 96.7 97 3 dB BW 5 V Range (kHz) 15 15 13.7 10.3 6 3 1.5 Rev. 0 | Page 29 of 36 3 dB BW 10 V Range (kHz) 22 22 18.5 11.9 6 3 1.5 Maximum Throughput CONVST Frequency (kHz) 200 100 50 25 12.5 6.25 3.125 AD7606/AD7606-6/AD7606-4 Figure 49 to Figure 55 illustrate the effect of oversampling on the code spread in a dc histogram plot. As the oversample rate is increased, the spread of the codes is reduced. 1000 NO OVERSAMPLING 900 FSAMPLE = 200kSPS AVCC = 5V 800 VDRIVE = 2.5V 700 600 500 200 400 –3 131 0 –3 3 –2 –1 0 CODE (LSB) 1 2 97 2 08479-047 1400 OVERSAMPLING BY 8 FSAMPLE = 25kSPS 1200 AVCC = 5V VDRIVE = 2.5V NUMBER OF OCCURENCES 1263 1000 800 600 400 783 928 887 NUMBER OF OCCURENCES –2 –1 0 CODE (LSB) 1 2 3 200 100 0 Figure 52. Histogram of Codes—OS × 8 (Three Codes) 1400 3 OVERSAMPLING BY 16 FSAMPLE = 12.5kSPS 1200 AVCC = 5V VDRIVE = 2.5V NUMBER OF OCCURENCES 1453 Figure 49. Histogram of Codes—No OS (Six Codes) 1400 OVERSAMPLING BY 2 FSAMPLE = 100kSPS 1200 AVCC = 5V VDRIVE = 2.5V NUMBER OF OCCURENCES 1000 800 600 400 200 1148 595 1000 800 600 804 400 200 80 08479-048 –3 –2 –1 0 CODE (LSB) 1 2 3 Figure 53. Histogram of Codes—OS × 16 (Two Codes) 0 –3 0 –2 –1 0 CODE (LSB) 1 16 2 0 3 1600 OVERSAMPLING BY 32 FSAMPLE = 6.125kSPS 1400 AVCC = 5V VDRIVE = 2.5V 1417 0 Figure 50. Histogram of Codes—OS × 2 (Four Codes) 1400 OVERSAMPLING BY 4 FSAMPLE = 50kSPS 1200 AVCC = 5V VDRIVE = 2.5V NUMBER OF OCCURENCES NUMBER OF OCCURENCES 1200 1000 800 631 600 400 200 1262 1000 800 600 400 200 764 –3 –2 –1 0 CODE (LSB) 1 2 3 Figure 54. Histogram of Codes—OS × 32 (Two Codes) 1600 08479-049 0 0 –3 0 –2 19 –1 0 CODE (LSB) 1 3 2 0 3 OVERSAMPLING BY 64 FSAMPLE = 3kSPS 1400 AVCC = 5V VDRIVE = 2.5V 1679 NUMBER OF OCCURENCES 1200 1000 800 600 400 200 0 0 –3 0 –2 0 –1 0 CODE (LSB) 1 0 2 0 3 08479-153 Figure 51. Histogram of Codes—OS × 4 (Four Codes) 369 Figure 55. Histogram of Codes—OS × 64 (Two Codes) Rev. 0 | Page 30 of 36 08479-152 0 0 0 0 0 0 08479-151 0 0 0 0 0 0 08479-050 300 0 0 0 2 0 0 AD7606/AD7606-6/AD7606-4 When the oversampling mode is selected for the AD7606/ AD7606-6/AD7606-4, it has the effect of adding a digital filter function after the ADC. The different oversampling rates and the CONVST sampling frequency produce different digital filter frequency profiles. Figure 56 to Figure 60 show the digital filter frequency profiles for the different oversampling rates. The combination of the analog antialiasing filter and the oversampling digital filter can be used to eliminate and reduce the complexity of the design of any filter before the AD7606/AD7606-6/AD7606-4. The digital filtering combines steep roll-off and linear phase response. 0 –10 –20 ATTENUATION (dB) 0 –10 –20 ATTENUATION (dB) AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 16 –30 –40 –50 –60 –70 –80 –90 08479-154 08479-156 08479-155 –100 100 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 2 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 59. Digital Filter Response for OS 16 0 –10 –20 ATTENUATION (dB) –30 –40 –50 –60 –70 –80 08479-051 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 32 –30 –40 –50 –60 –70 –80 –90 –100 100 –90 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 56. Digital Filter Response for OS 2 0 –10 –20 ATTENUATION (dB) 1k 10k 100k 1M 10M AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 4 FREQUENCY (Hz) Figure 60. Digital Filter Response for OS 32 0 –10 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 64 –30 –40 –20 –50 –60 –70 –80 –90 08479-052 ATTENUATION (dB) –30 –40 –50 –60 –70 –80 –90 –100 100 –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 57. Digital Filter Response for OS 4 0 –10 –20 ATTENUATION (dB) AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 8 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 61. Digital Filter Response for OS 64 –30 –40 –50 –60 –70 –80 –90 08479-053 –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 58. Digital Filter Response for OS 8 Rev. 0 | Page 31 of 36 AD7606/AD7606-6/AD7606-4 LAYOUT GUIDELINES The printed circuit board that houses the AD7606/AD7606-6/ AD7606-4 should be designed so that the analog and digital sections are separated and confined to different areas of the board. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7606/AD7606-6/AD7606-4. If the AD7606/AD7606-6/AD7606-4 are in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point: a star ground point that should be established as close as possible to the AD7606/AD7606-6/AD7606-4. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be allowed to run under the AD7606/AD7606-6/AD7606-4 to avoid noise coupling. Fast switching signals like CONVST A, CONVST B, or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AVCC and VDRIVE pins on the AD7606/AD7606-6/AD7606-4 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make good connections between the AD7606 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply impedance presented to the AD7606/AD7606-6/AD7606-4 and to reduce the magnitude of the supply spikes. The decoupling capacitors should be placed close to (ideally, right up against) these pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7606/ AD7606-6/AD7606-4 pins; and, where possible, they should be placed on the same side of the board as the AD7606 device. 08479-055 08479-054 Figure 62 shows the recommended decoupling on the top layer of the AD7606 board. Figure 63 shows bottom layer decoupling, which is used for the four AVCC pins and the VDRIVE pin decoupling. Where the ceramic 100 nF caps for the AVCC pins are placed close to their respective device pins, a single 100 nF capacitor can be shared between Pin 37 and Pin 38. Figure 62. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins Figure 63. Bottom Layer Decoupling Rev. 0 | Page 32 of 36 AD7606/AD7606-6/AD7606-4 To ensure good device-to-device performance matching in a system that contains multiple AD7606/AD7606-6/AD7606-4 devices, a symmetrical layout between the AD7606/AD7606-6/ AD7606-4 devices is important. Figure 64 shows a layout with two AD7606/AD7606-6/AD7606-4 devices. The AVCC supply plane runs to the right of both devices, and the VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between the two devices, and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 of U2. A solid ground plane is used. These symmetrical layout principles can also be applied to a system that contains more than two AD7606/AD7606-6/AD7606-4 devices. The AD7606/AD7606-6/AD7606-4 devices can be placed in a north-south direction, with the reference voltage located midway between the devices and the reference track running in the north-south direction, similar to Figure 64. U1 U2 AVCC AVCC Figure 64. Layout for Multiple AD7606 Devices—Top Layer and Supply Plane Layer Rev. 0 | Page 33 of 36 08479-056 AD7606/AD7606-6/AD7606-4 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 1 PIN 1 12.20 12.00 SQ 11.80 64 49 48 TOP VIEW (PINS DOWN) 10.20 10.00 SQ 9.80 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 16 17 32 33 0.08 COPLANARITY VIEW A VIEW A ROTATED 90° CCW 0.50 BSC LEAD PITCH 0.27 0.22 0.17 051706-A COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 65. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7606BSTZ AD7606BSTZ-RL AD7606BSTZ-6 AD7606BSTZ-6RL AD7606BSTZ-4 AD7606BSTZ-4RL EVAL-AD7606EDZ 2 EVAL-AD7606-6EDZ2 EVAL-AD7606-4EDZ2 CED1Z 3 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board for the AD7606 Evaluation Board for the AD7606-6 Evaluation Board for the AD7606-4 Converter Evaluation Development Package Option ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 Z = RoHS Compliant Part. This board can be used as a standalone evaluation board or in conjunction with the CED1Z for evaluation/demonstration purposes. 3 This board allows the PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the EDZ designator. Rev. 0 | Page 34 of 36 AD7606/AD7606-6/AD7606-4 NOTES Rev. 0 | Page 35 of 36 AD7606/AD7606-6/AD7606-4 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08479-0-5/10(0) Rev. 0 | Page 36 of 36