8-Bit, High Speed, Multiplying
D/A Converter
DAC08
Data Sheet
FEATURES
Direct interface to all popular logic families with full noise
immunity is provided by the high swing, adjustable threshold
logic input.
Fast settling output current: 85 ns
Full-scale current prematched to ±1 LSB
Direct interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% maximum over temperature range
High output impedance and compliance: −10 V to +18 V
Complementary current outputs
Wide range multiplying capability: 1 MHz bandwidth
Low FS current drift: ±10 ppm/°C
Wide power supply range: ±4.5 V to ±18 V
Low power consumption: 33 mW at ±5 V
Low cost
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential operation
to effectively double the peak-to-peak output swing. In many
applications, the outputs can be directly converted to voltage
without the need for an external op amp. All DAC08 series models
guarantee full 8-bit monotonicity, and nonlinearities as tight as
±0.1% over the entire operating temperature range are available.
Device performance is essentially unchanged over the ±4.5 V to
±18 V power supply range, with 33 mW power consumption
attainable at ±5 V supplies.
GENERAL DESCRIPTION
The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.
The DAC08 series of 8-bit monolithic digital-to-analog converters provide very high speed performance coupled with low cost
and outstanding applications flexibility.
DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, LCD display drivers, high speed modems, and other
applications where low cost, high speed, and complete
input/output versatility are required.
Advanced circuit design achieves 85 ns settling times with very
low glitch energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20 to 1 reference
current range. Matching to within 1 LSB between reference and
full-scale currents eliminates the need for full-scale trimming in
most applications.
FUNCTIONAL BLOCK DIAGRAM
V+
13
VLC
(MSB)
B1
1
5
B2
6
B3
7
B4
B5
8
9
B6
10
B7
11
(LSB)
B8
12
DAC08
VREF (+)
VREF (–)
BIAS
NETWORK
CURRENT
SWITCHES
14
4
2
IOUT
IOUT
15
16
3
COMP
V–
00268-C-001
REFERENCE
AMPLIFIER
Figure 1.
Rev. D
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DAC08
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Application Information ................................................................ 14
General Description ......................................................................... 1
Reference Amplifier Setup ........................................................ 14
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Reference Amplifier Compensation for Multiplying
Applications ................................................................................ 14
Specifications..................................................................................... 3
Logic Inputs................................................................................. 14
Electrical Characteristics ............................................................. 3
Analog Output Currents ........................................................... 14
Typical Electrical Characteristics ............................................... 4
Power Supplies ............................................................................ 15
Absolute Maximum Ratings............................................................ 5
Temperature Performance......................................................... 15
Thermal Resistance ...................................................................... 5
Multiplying Operation ............................................................... 15
ESD Caution .................................................................................. 5
Settling Time ............................................................................... 15
Pin Configuration and Function Descriptions ............................. 6
Analog Devices Current Output DACs ....................................... 17
Test and Burn-In Circuits ................................................................ 7
Outline Dimensions ....................................................................... 18
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 19
Basic Connections .......................................................................... 11
REVISION HISTORY
3/16—Rev. C to Rev. D
Added Thermal Resistance Section ............................................... 5
Changes to Table 4 ............................................................................ 5
Change to Figure 29 ....................................................................... 12
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 10
2/02—Rev. A to Rev. B
Edits to Specifications .......................................................................2
Edits to Absolute Maximum Ratings ..............................................3
Edits to Ordering Guide ...................................................................3
Edits to Wafer Test Limits ................................................................5
Edit to Figure 13 ................................................................................8
Edits to Figures 14 and 15 ................................................................9
11/04—Rev. B to Rev. C
Changed SO to SOIC ......................................................... Universal
Removed DIE ...................................................................... Universal
Changes to Figure 30, Figure 31, Figure 32 ................................. 12
Change to Figure 33 ....................................................................... 15
Added Table 4.................................................................................. 16
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
Rev. D | Page 2 of 21
Data Sheet
DAC08
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = ±15 V, IREF = 2.0 mA, –55°C ≤ TA ≤ +125°C for DAC08/DAC08A, 0°C ≤ TA ≤ +70°C for DAC08E and DAC08H, −40°C to +85°C for
DAC08C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT.
Table 1.
Parameter
RESOLUTION
MONOTONICITY
NONLINEARITY
SETTLING TIME
PROPAGATION DELAY
Each Bit
All Bits Switched
FULL-SCALE TEMPCO1
DAC08A/DAC08H
Symbol Test Conditions/Comments Min Typ
Max
8
8
NL
±0.1
tS
To ±1/2 LSB, all bits switched
85
135
on or off, TA = 25°C 1
tPLH
tPHL
TCIFS
TA = 25°C1
35
35
±10
DAC08E
DAC08C
Min Typ
Max Min Typ
Max
8
8
8
8
±0.19
±0.39
85
150
85
150
60
60
±50
35
35
±10
DAC08E
OUTPUT VOLTAGE
Compliance
(True Compliance)
VOC
FULL RANGE CURRENT IFR4
FULL RANGE
IFRS
SYMMETRY
ZERO-SCALE CURRENT IZS
OUTPUT CURRENT
IOR1
RANGE
IOR2
OUTPUT CURRENT
NOISE
LOGIC INPUT LEVELS
Logic 0
Logic 1
LOGIC INPUT CURRENT
Logic 0
Logic 1
LOGIC INPUT SWING
LOGIC THRESHOLD
RANGE
REFERENCE BIAS
CURRENT
REFERENCE INPUT
SLEW RATE
VIL
VIL
IIL
IIH
VIS
VTHR
Full-scale current
Change
20 MΩ typ
VREF = 10.000 V R14, R15 =
5.000 kΩ TA = 25°C
IFR4 − IFR2
R14, R15 = 5.000 kΩ
VREF = +15.0 V, V− = −10 V
VREF = +25.0 V,
V− = −12 V
IREF = 2 mA
ns
ns
ppm/°C
−10
+18
–10
+18
V
1.984 1.992
2.000 1.94 1.99
2.04
1.94 1.99
2.04
mA
±0.5
±4
±1
±8
±2
±16
µA
0.1
1
0.2
2
0.2
4
2.1
2.1
2.1
µA
mA
4.2
4.2
4.2
mA
25
25
0.8
2
REQ = 200 Ω
RL = 100 Ω
CC = 0 pF. See Figure 7.1
60
60
±80
+18
4
25
0.8
2
nA
0.8
V
V
2
−2
0.002
−10
−2
10
0.002
+18 −10
+13.5 −10
−10
−2
10
0.002
+18 −10
+13.5 −10
−10
10
+18
+13.5
µA
µA
V
V
−1
−3
−3
−3
µA
−10
−10
I15
dI/dt
35
35
±10
−10
VLC = 0 V
VLC = 0 V
VIN = −10 V to +0.8 V
VIN = 2.0 V to 18 V
V− = −15 V
VS = ±15 V1
60
60
±80
±50
Unit
Bits
Bits
%FS
ns
8
Rev. D | Page 3 of 21
−1
4
8
−1
4
8
mA/µs
DAC08
Parameter
POWER SUPPLY
SENSITIVITY
POWER SUPPLY
CURRENT
POWER DISSIPATION
1
Data Sheet
DAC08A/DAC08H
DAC08E
DAC08C
Symbol Test Conditions/Comments Min Typ
Max Min Typ
Max Min Typ
Max Unit
PSSIFS+ V+ = 4.5 V to 18 V
±0.0003 ±0.01
±0.0003 ±0.01
±0.0003 ±0.01 %∆IO/
%∆V+
PSSIFS– V− = −4.5 V to −18 V
±0.002 ±0.01
±0.002 ±0.01
±0.002 ±0.01 %∆IO/
%∆V−
IREF = 1.0 mA
I+
VS = ±5 V, IREF = 1.0 mA
2.3
3.8
2.3
3.8
2.3
3.8
mA
I−
I+
I−
I+
I−
PD
VS = +5 V, −15 V
IREF = 2.0 mA
VS = ±15 V
IREF = 2.0 mA
±5 V, IREF = 1.0 mA +5 V,
−15 V
IREF = 2.0 mA ±15 V, IREF =
2.0 mA
−4.3
2.4
−6.4
2.5
−6.5
33
−5.8
3.8
−7.8
3.8
−7.8
48
−4.3
2.4
−6.4
2.5
−6.5
33
−5.8
3.8
−7.8
3.8
−7.8
48
−4.3
2.4
−6.4
2.5
−6.5
33
−5.8
3.8
−7.8
3.8
−7.8
48
mA
mA
mA
mA
mA
mW
108
136
103
136
108
136
mW
135
174
135
174
135
174
mW
Guaranteed by design.
TYPICAL ELECTRICAL CHARACTERISTICS
VS = ±15 V, and IREF = 2.0 mA, unless otherwise noted. Output characteristics apply to both IOUT and IOUT.
Table 2.
Parameter
REFERENCE INPUT SLEW RATE
PROPAGATION DELAY
SETTLING TIME
Symbol
dI/dt
tPLH, tPHL
tS
Test Conditions/Comments
TA = 25°C, any bit
To ±1/2 LSB, all bits switched on or
off, TA = 25°C
Rev. D | Page 4 of 21
All Grades Typical
8
35
85
Unit
mA/µs
ns
ns
Data Sheet
DAC08
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Operating Temperature
DAC08AQ, DAC08Q
DAC08HQ, DAC08EQ, DAC08CQ
DAC08CP, DAC08CS
Junction Temperature (TJ)
Storage Temperature Q Package
Storage Temperature P Package
Lead Temperature (Soldering, 60 sec)
V+ Supply to V− Supply
Logic Inputs
VLC
Analog Current Outputs (at VS− = 15 V)
Reference Input (V14 to V15)
Reference Input Differential Voltage
(V14 to V15)
Reference Input Current (I14)
Rating
−55°C to +125°C
0°C to +70°C
−40°C to +85°C
−65°C to +150°C
−65°C to +150°C
−65°C to +125°C
300°C
36 V
V− to V− + 36 V
V− to V+
4.25 mA
V− to V+
θJA is specified for worst case mounting conditions, that is, θJA is
specified for device in socket for CERDIP, PDIP, and LCC
packages; θJA is specified for device soldered to printed circuit
board for SOIC package.
Table 4. Thermal Resistance
Package Type
16-Lead CERDIP (Q)
16-Lead PDIP (P)
20-Terminal LCC (RC)
16-Lead SOIC (S)
ESD CAUTION
±18 V
5.0 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 5 of 21
θJA
100
82
76
111
θJC
16
39
36
35
Unit
°C/W
°C/W
°C/W
°C/W
DAC08
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VLC 1
16
COMP
IOUT 2
15
VREF (–)
V– 3
14
VREF (+)
DAC08
V+
TOP VIEW
(MSB) B1 5 (Not To Scale) 12 B8 (LSB)
13
B2 6
11
B7
B3 7
10
B6
B4 8
9
B5
00268-C-002
IOUT 4
Figure 2. 16-Lead Dual In-Line Package (PDIP and CERDIP)
V+ 1
16
VREF (+) 2
15
B7
VREF (–) 3
14
B6
B8 (LSB)
DAC08 13 B5
TOP VIEW
VLC 5 (Not To Scale) 12 B4
IOUT 6
11
B3
V– 7
10
B2
IOUT 8
9
B1 (MSB)
00268-C-003
COMP 4
NC
COMP
3
2
1
VREF (–)
IOUT
VLC
Figure 3. 16-Lead Standard Small Outline Package (SOIC_N)
20 19
V– 4
18
IOUT 5
TOP VIEW
16 NC
(Not To Scale)
15 B8 (LSB)
14 B7
B6
B5
NC
B3
B4
9 10 11 12 13
NC = NO CONNECT
00268-C-004
NC 6
(MSB) B1 7
B2 8
VREF (+)
17 V+
DAC08
Figure 4. DAC08RC/883 20-Terminal Ceramic Leadless Chip Carrier (LCC)
Rev. D | Page 6 of 21
Data Sheet
DAC08
TEST AND BURN-IN CIRCUITS
+VREF
RREF OPTIONAL RESISTOR
FOR OFFSET INPUTS
RL
RIN
15
RL
2
16
00268-C-006
RP
TYPICAL VALUES:
RIN = 5kΩ
+VIN = 10V
NO CAP
Figure 5. Pulsed Reference Operation
C2
R1 = 9kΩ
C1 = 0.001µF
C2, C3 = 0.01µF
+18V
C1
R1
16 15 14 13 12 11 10
9
DAC08
1
2
3
4
5
6
7
8
C3
–18V MIN
Figure 6. Burn-In Circuit
Rev. D | Page 7 of 21
00268-C-007
0V
4
14
REQ ≈
200Ω
DAC08
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
ALL BITS SWITCHED ON
1V
2.4V
1V
2.5V
0.4V
0.5V
–1/2LSB
OUTPUT
0V
SETTLING +1/2LSB
–0.5mA
–2.5mA
100mV
200ns
REQ ≈ 200Ω
RL = 100Ω
CC = 0
50ns
10mV
200ns/DIVISION
50ns/DIVISION
SETTLING TIME FIXTURE
IFS = 2mA, RL = 1kΩ
1/2LSB = 4µA
Figure 7. Fast Pulsed Reference Operation
00268-C-011
00268-C-008
IOUT
Figure 10. Full-Scale Settling Time
5
TA = TMIN TO TMAX
ALL BITS HIGH
IFS, OUTPUT CURRENT (mA)
IOUT
1.0mA
IOUT
00268-C-009
2.0mA
(0000|0000)
3
2
LIMIT FOR
V– = –5V
1
0
(1111|1111)
IREF = 2mA
4
0
Figure 8. True and Complementary Output Operation
5mV
1
5
2
3
4
IREF, REFERENCE CURRENT (mA)
00268-C-012
0mA
LIMIT FOR
V– = –15V
Figure 11. Full-Scale Current vs. Reference Current
500
2V
2.4V
PROPAGATION DELAY (ns)
400
0.4V
0V
8µA
200
1LSB = 7.8µA
100
1LSB = 61nA
0
50ns/DIVISION
0.005 0.01 0.02
0.05 0.10 0.20
0.50 1.00 2.00
IFS, OUTPUT FULL-SCALE CURRENT (mA)
Figure 12. LSB Propagation Delay vs. IFS
Figure 9. LSB Switching
Rev. D | Page 8 of 21
5.00 10.00
00268-C-013
50ns
100mV
00268-C-010
0
300
Data Sheet
DAC08
2.0
10
R14 = R15 = 1kΩ
RL ≤ 500V
ALL BITS ON
VR15 = 0V
8
4
1.6
2
–2
1
0.8
CC = 15pF, VIN = 2.0V p-p
CENTERED AT +1.0V
LARGE SIGNAL
–6
–8
–10
0.4
CC = 15pF, VIN = 50mV p-p
CENTERED AT +200mV
SMALL SIGNAL
–12
–14
0.1
0.5
2.0
1.0
FREQUENCY (MHz)
0.2
10.0
5.0
0
–50
100
50
TEMPERATURE (°C)
0
150
Figure 16. VTH − VLC vs. Temperature
Figure 13. Reference Input Frequency Response
4.0
4.0
TA = TMIN TO TMAX
ALL BITS ON
TA = TMIN TO TMAX
ALL BITS ON
3.6
3.6
3.2
OUTPUT CURRENT (mA)
3.2
NOTE: POSITIVE COMMON-MODE
RANGE IS ALWAYS (V+) –1.5V
2.8
2.4
V– = –15V
V– = –5V
V+ = +15V
2.0
IREF = 2mA
1.6
IREF = 1mA
1.2
0.8
2.8
2.4
V– = –15V
V– = –5V
IREF = 2mA
2.0
1.6
IREF = 1mA
1.2
0.8
IREF = 0.2mA
0
–14
–10
IREF = 0.2mA
0.4
–6
18
–2
2
6
10
14
V15, REFERENCE COMMON-MODE VOLTAGE (V)
00268-C-015
0.4
0
–14
–10
–6
–2
2
6
OUTPUT VOLTAGE (V)
10
14
18
00268-C-018
OUTPUT CURRENT (mA)
00268-C-017
–4
1.2
VTH–VLC (V)
2
0
00268-C-014
RELATIVE OUTPUT (dB)
6
Figure 17. Output Current vs. Output Voltage (Output Voltage Compliance)
Figure 14. Reference Amplifier Common-Mode Range
28
10
24
20
OUTPUT VOLTAGE (V)
6
4
16
12
8
4
0
SHADED AREA INDICATES PERMISSIBLE
OUTPUT VOLTAGE RANGE FOR V– = –15V.
IREF ≤ 2.0mA.
FOR OTHER V– OR IREF,
SEE OUTPUT CURRENT VS. OUTPUT
VOLTAGE CURVE.
–4
2
0
–12
–8
–4
0
4
8
LOGIC INPUT VOLTAGE (V)
12
16
–12
–50
0
50
100
TEMPERATURE (°C)
150
Figure 18. Output Voltage Compliance vs. Temperature
Figure 15. Logic Input Current vs. Input Voltage
Rev. D | Page 9 of 21
00268-C-019
–8
00268-C-016
LOGIC INPUT (µA)
8
DAC08
Data Sheet
1.8
10
1.6
9
POWER SUPPLY CURRENT (mA)
BITS MAY BE HIGH OR LOW
1.2
B1
1.0
IREF = 2.0mA
0.8
0.6
B2
0.4
B4
V– = –5V
B5
B3
����
V–
= –15V
0
–12
–8
8
7
I– WITH IREF = 2mA
6
5
I– WITH IREF = 1mA
4
I– WITH IREF = 0.2mA
3
2
I+
1
–4
0
4
8
LOGIC INPUT VOLTAGE (V)
12
16
0
0
–2
–10 –12 –14 –16
–8
–6
–4
V–, NEGATIVE POWER SUPPLY (V dc)
–18
–20
00268-C-022
0.2
00268-C-020
OUTPUT CURRENT (mA)
1.4
NOTE:
B1 THROUGH B8 HAVE IDENTICAL TRANSFER
CHARACTERISTICS. BITS ARE FULLY SWITCHED WITH LESS
THAN 1/2 LSB ERROR, AT LESS THAN ±100mV FROM ACTUAL
THRESHOLD. THESE SWITCHING POINTS ARE GUARANTEED
TO LIE BETWEEN 0.8V AND 2.0V OVER THE OPERATING
TEMPERATURE RANGE (VLC = 0.0V).
Figure 21. Power Supply Current vs. V−
Figure 19. Bit Transfer Characteristics
10
10
ALL BITS HIGH OR LOW
ALL BITS HIGH OR LOW
POWER SUPPLY CURRENT (mA)
9
8
7
I–
6
5
4
3
I+
2
1
8
7
V– = –15V
6
IREF = 2.0mA
I–
5
4
3
V+ = +15V
I+
2
0
2
4
6
8
12
14
16
10
V+, POSITIVE POWER SUPPLY (V dc)
18
20
0
–50
0
50
100
TEMPERATURE (°C)
150
Figure 22. Power Supply Current vs. Temperature
Figure 20. Power Supply vs. V+
Rev. D | Page 10 of 21
00268-C-023
1
0
00268-C-021
POWER SUPPLY CURRENT (mA)
9
Data Sheet
DAC08
BASIC CONNECTIONS
+VREF
RREF
IIN
VIN
IREF
14
RIN
15
IREF ≥ PEAK NEGATIVE SWING OF IIN
RREF
RREF ≈ R15 +V
REF
14
R15
(OPTIONAL)
VIN
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
00268-C-024
15
HIGH INPUT
IMPEDANCE
Figure 23. Accommodating Bipolar References
LSB
MSB
B1 B2 B3 B4 B5 B6 B7 B8
VREF (+)
14 5 6 7 8 9 10 11 12
RREF
(R14)
VREF (–)
IO
4
2
15
16
3
13
1
IO
R15
V–
V+
CC
COMP
0.1µF
+VREF 255 0.1µF
×
RREF 256
IO + IO = IFR FOR
ALL LOGIC STATES
IFR =
V–
V+
VLC
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:
VREF = 10.000V
RREF = 5.000kΩ
R15 = RREF
CC = 0.01µF
VLC = 0V (GROUND)
00268-C-025
IREF
+VREF
IO
IREF = 2.000mA
EO
5.000kΩ
4
14
5.000kΩ
2
IO
FULL RANGE
HALF SCALE +LSB
HALF SCALE
HALF SCALE –LSB
ZERO SCALE +LSB
ZERO SCALE
EO
EO
IO
IO
B1 B2 B3 B4 B5 B6 B7 B8
1 1 1 1 1 1 1 1 1.992 0.000 –9.960 –0.000
1 0 0 0 1 0 0 1 1.008 0.984 –5.040 –4.920
1 0 0 0 1 0 0 0 1.000 0.992 –5.000 –4.960
0 1 1 1 0 1 1 1 0.992 1.000 –4.960 –5.000
0 0 0 0 0 0 0 1 0.008 1.984 –0.040 –9.920
0 0 0 0 0 0 0 0 0.000 1.992 0.000 –9.960
EO
Figure 25. Basic Unipolar Negative Operation
10V
10kΩ
IO
IREF = 2.000mA
4
14
EO
2
IO
EO
10kΩ
POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO SCALE +LSB
ZERO SCALE
ZERO SCALE –LSB
NEG. FULL SCALE +LSB
NEG. FULL SCALE
B1 B2 B3 B4 B5 B6 B7 B8
EO
1 1 1 1 1 1 1 1 –9.920
1 1 1 1 1 1 1 0 –9.840
1 0 0 0 0 0 0 1 –0.080
0.000
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 +0.080
0 0 0 0 0 0 0 1 +9.920
0 0 0 0 0 0 0 0 +10.000
Figure 26. Basic Bipolar Output Operation
Rev. D | Page 11 of 21
EO
+10.000
+9.920
+0.160
+0.080
0.000
–9.840
–9.920
00268-C-027
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
00268-C-026
Figure 24. Basic Positive Reference Operation
LSB
MSB
B1 B2 B3 B4 B5 B6 B7 B8
DAC08
Data Sheet
LOW T.C.
4.5kΩ
VREF
10V
14
IREF (+) ≈ 2mA
39kΩ
≈1V
15
00268-C-028
10kΩ
POT
APPROX
5kΩ
Figure 27. Recommended Full-Scale Adjustment Circuit
RREF
IO
14
IO
R15
2
15
NOTE
RREF SETS IFS; R15 IS FOR
BIAS CURRENT CANCELLATION.
–VREF
RREF
00268-C-029
–VREF
IFS ≈
4
Figure 28. Basic Negative Reference Operation
10kΩ
5.0kΩ
15V
VO
REF01*
6
5.000kΩ
IO
+15V
4
5
POS. FULL RANGE
EO ZERO SCALE
NEG. FULL SCALE +1LSB
NEG. FULL SCALE
AD8671
5.0kΩ
V+
–V
CC
VLC
IO
2
B1
1
1
0
0
B2
1
0
0
0
4
+15V –15V
–15V
Figure 29. Offset Binary Operation
RL
IO
4
EO
AD8671
IO
2
0 TO –IFR × RL
255
I
256 REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2): CONNECT IO (PIN 4)
TO GROUND.
00268-C-031
IFR =
Figure 30. Positive Low Impedance Output Operation
4
2
AD8671
IO
IO
RL
EO
0 TO –IFR × RL
IFR =
255
I
256 REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT NONINVERTING INPUT OF OP AMP TO IO (PIN 2): CONNECT IO (PIN 4)
TO GROUND.
Figure 31. Negative Low Impedance Output Operation
Rev. D | Page 12 of 21
00268-C-032
*OR ADR01
B3
1
0
0
0
B4
1
0
0
0
B5
1
0
0
0
B6
1
0
0
0
B7
1
0
0
0
B8
1
0
1
0
EO
+4.960
0.000
–4.960
–5.000
00268-C-030
2
10V
LSB
MSB
B1 B2 B3 B4 B5 B6 B7 B8
Data Sheet
DAC08
CMOS, HTL, NMOS
V+
ECL
TTL, DTL,
VTH = 1.4V
20kΩ
13kΩ
9.1kΩ
VLC
VLC
1
6.2kΩ
2N3904
2N3904
2N3904
"A"
0.1µF
3kΩ
39kΩ
TO PIN 1
VLC
6.2kΩ
–5.2V
2N3904
3kΩ
20kΩ
TO PIN 1
VLC
R3
400µA
TEMPERATURE COMPENSATING VLC CIRCUITS
Figure 32. Interfacing with Various Logic Families
Rev. D | Page 13 of 21
"A"
00268-C-033
VTH = VLC 1.4V
15V CMOS
15V VTH = 7.6V
DAC08
Data Sheet
APPLICATION INFORMATION
REFERENCE AMPLIFIER SETUP
The DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input reference
current. The reference current may be fixed or may vary from
nearly zero to 4.0 mA. The full-scale output current is a linear
function of the reference current and is given by
I FR
255
I REF
256
where IREF = I14
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal (Pin 14)
of the reference amplifier. Alternatively, a negative reference may be
applied to VREF(–) at Pin 15; reference current flows from ground
through R14 into VREF(+) as in the positive reference case. This
negative reference connection has the advantage of a very high
impedance presented at Pin 15. The voltage at Pin 14 is equal to
and tracks the voltage at Pin 15 due to the high gain of the internal
reference amplifier. R15 (nominally equal to R14) cancels bias
current errors; R15 may be eliminated with only a minor
increase in error.
Bipolar references may be accommodated by offsetting VREF or
Pin 15. The negative common-mode range of the reference
amplifier is given by VCM – = V− plus (IREF × 1 kΩ) plus 2.5 V.
The positive common-mode range is V+ less 1.5 V.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5.0 V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R14 must be split into two resistors with the junction bypassed
to ground with a 0.1 μF capacitor.
For most applications, the tight relationship between IREF and IFS
eliminates the need for trimming IREF. If required, full-scale
trimming can be accomplished by adjusting the value of R14, or
by using a potentiometer for R14. An improved method of fullscale trimming that eliminates potentiometer T.C. effects is shown
in the recommended full-scale adjustment circuit (Figure 27).
Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative commonmode range. The recommended range for operation with a dc
reference current is 0.2 mA to 4.0 mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications require the reference amplifier to be
compensated using a capacitor from Pin 16 to V−. The value of
this capacitor depends on the impedance presented to Pin 14;
for R14 values of 1.0 kΩ, 2.5 kΩ, and 5.0 kΩ, minimum values
of CC are 15 pF, 37 pF, and 75 pF. Larger values of R14 require
proportionately increased values of CC for proper phase margin,
so the ratio of CC (pF) to R14 (kΩ) = 15.
For fastest response to a pulse, low values of R14 enabling small
CC values must be used. If Pin 14 is driven by a high impedance
such as a transistor current source, none of the preceding values
suffice, and the amplifier must be heavily compensated, which
decreases overall bandwidth and slew rate. For R14 = 1 kΩ and
CC = 15 pF, the reference amplifier slews at 4 mA/μs, enabling a
transition from IREF = 0 to IREF = 2 mA in 500 ns.
Operation with pulse inputs to the reference amplifier can be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 14 is 200 Ω
and CC = 0. This yields a reference slew rate of 16 mA/μs, which
is relatively independent of the RIN and VIN values.
LOGIC INPUTS
The DAC08 design incorporates a unique logic input circuit that
enables direct interface to all popular logic families and provides
maximum noise immunity. This feature is made possible by the
large input swing capability, 2 μA logic input current, and
completely adjustable logic threshold voltage. For V− = −15 V, the
logic inputs may swing between −10 V and +18 V. This enables
direct interface with 15 V CMOS logic, even when the DAC08
is powered from a 5 V supply. Minimum input logic swing and
minimum logic threshold voltage are given by
V− + (IREF × 1 kΩ) + 2.5 V
The logic threshold may be adjusted over a wide range by
placing an appropriate voltage at the logic threshold control pin
(Pin 1, VLC). Figure 16 shows the relationship between VLC and
VTH over the temperature range, with VTH nominally 1.4 above
VLC. For TTL and DTL interface, simply ground Pin 1. When
interfacing ECL, an IREF = 1 mA is recommended. For interfacing
other logic families, see Figure 32. For general set-up of the logic
control circuit, note that Pin 1 sources 100 μA typical; external
circuitry must be designed to accommodate this current.
Fastest settling times are obtained when Pin 1 sees a low
impedance. If Pin 1 is connected to a 1 kΩ divider, for example,
it must be bypassed to ground by a 0.01 μF capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where IO + IO = IFS. Current appears at the true (IO) output when
a 1 (logic high) is applied to each logic input. As the binary count
increases, the sink current at Pin 4 increases proportionally, in
the fashion of a positive logic DAC. When a 0 is applied to any
input bit, that current is turned off at Pin 4 and turned on at Pin 2.
A decreasing logic count increases IO as in a negative or inverted
logic DAC. Both outputs may be used simultaneously.
Rev. D | Page 14 of 21
Data Sheet
DAC08
If one of the outputs is not required, it must be connected to
ground or to a point capable of sourcing IFS; do not leave an
unused output pin open.
Both outputs have an extremely wide voltage compliance
enabling fast direct current to voltage conversion through a
resistor tied to ground or other voltage source. Positive compliance is 36 V above V− and is independent of the positive supply.
Negative compliance is given by
V− + (IREF × 1 kΩ) + 2.5 V
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.
POWER SUPPLIES
The DAC08 operates over a wide range of power supply voltages
from a total supply of 9 V to 36 V. When operating at supplies
of ±5 V or lower, IREF ≤ 1 mA is recommended. Low reference
current operation decreases power consumption and increases
negative compliance (Figure 11), reference amplifier negative
common-mode range (Figure 14), negative logic input range
(Figure 15), and negative logic threshold range (Figure 16). For
example, operation at −4.5 V with IREF = 2 mA is not recommended
because negative output compliance reduces to near zero.
Operation from lower supplies is possible; however, at least
8 V total must be applied to ensure turn on of the internal bias
network.
Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible because no ground connection is required; however, an
artificial ground can ensure logic swings, etc., remain between
acceptable limits. Power consumption is calculated as follows:
PD = ( I + ) (V + ) + ( I − ) (V − )
A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states. This is useful in
cryptographic applications and further reduces the size of the
power supply bypass capacitors.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is low, typically ±10 ppm/°C,
with zero-scale output current and drift essentially negligible
compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 must
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approximately
10% at –55°C. At +125°C, an increase of about 15% is typical.
The reference amplifier must be compensated by using a capacitor
from Pin 16 to V−. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
refer to the Reference Amplifier Compensation for Multiplying
Applications section.
MULTIPLYING OPERATION
The DAC08 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range of
4 µA to 4 mA. Monotonic operation is maintained over a typical
range of IREF from 100 µA to 4.0 mA.
SETTLING TIME
The DAC08 is capable of extremely fast settling times, typically
85 ns at IREF = 2.0 mA. Judicious circuit design and careful board
layout must obtain full performance potential during testing
and application. The logic switch design enables propagation
delays of only 35 ns for each of the 8 bits. Settling time to within
1/2 LSB of the LSB is therefore 35 ns, with each progressively
larger bit taking successively longer. The MSB settles in 85 ns, thus
determining the overall settling time of 85 ns. Settling to 6-bit
accuracy requires about 65 ns to 70 ns. The output capacitance
of the DAC08, including the package, is approximately 15 pF;
therefore the output RC time constant dominates settling time if
RL > 500 Ω.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
Measuring the settling time requires the ability to accurately
resolve ±4 µA; therefore a 1 kΩ load is needed to provide adequate
drive for most oscilloscopes. The settling time fixture shown in
Figure 33 uses a cascade design to permit driving a 1 kΩ load
with less than 5 pF of parasitic capacitance at the measurement
node. At IREF values of less than 1.0 mA, excessive RC damping
of the output is difficult to prevent while maintaining adequate
sensitivity. However, the major carry from 01111111 to 10000000
provides an accurate indicator of settling time. This code change
does not require the normal 6.2 time constants to settle to within
±0.2% of the final value, and thus settling time is observed at
lower values of IREF.
DAC08 switching transients or “glitches” are very low and can
be further reduced by small capacitive loads at the output at a
minor sacrifice in settling time. Fastest operation can be obtained
by using short leads, minimizing output capacitance and load
resistor values, and by adequate bypassing at the supply, reference,
and VLC terminals. Supplies do not require large electrolytic bypass
capacitors because the supply current drain is independent of
input logic states; 0.1 µF capacitors at the supply pins provide
full transient protection.
Rev. D | Page 15 of 21
DAC08
Data Sheet
VL
FOR TURN-ON, VL = 2.7V
FOR TURN-OFF, VL = 0.7V
1kΩ
+5V
1µF
50µF
MINIMUM
CAPACITANCE
VOUT 1×
PROBE
1kΩ
VCL
0.7V
Q1
VIN
0.1µF
RREF
1µF
14 5 6 7 8 9 10 11 12
100kΩ
4
15
15kΩ
–0.4V
0.1µF
IOUT
DAC08
R15
2kΩ
+0.4V
0V
0V
2
13
3
–15V
16
0.01µF
00268-C-034
+VREF
Q2
0.1µF
0.1µF
+15V
–15V
Figure 33. Settling Time Measurement
Rev. D | Page 16 of 21
Data Sheet
DAC08
ANALOG DEVICES, INC., CURRENT OUTPUT DACs
Table 4 lists the latest DACs available from Analog Devices.
Table 5.
Model
AD5425
AD5426
AD5450
AD5424
AD5429
AD5428
AD5432
AD5451
AD5433
AD5439
AD5440
AD5443
AD5452
AD5445
AD5444
AD5449
AD5415
AD5447
AD5405
AD5453
AD5553
AD5556
AD5446
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Bits
8
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
Outputs
1
1
1
1
2
2
1
1
1
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
1
1
2
2
Interface
SPI, 8-bit load
SPI
SPI
Parallel
SPI
Parallel
SPI
SPI
Parallel
SPI
Parallel
SPI
SPI
Parallel
SPI
SPI
SPI
Parallel
Parallel
SPI
SPI
Parallel
SPI
SPI
Parallel
SPI
Parallel
SPI
Parallel
Package
MSOP-10
MSOP-10
SOT23-8
TSSOP-16
TSSOP-16
TSSOP-20
MSOP-10
SOT23-8
TSSOP-20
TSSOP-16
TSSOP-24
MSOP-10
SOT23-8
TSSOP-20
MSOP-10
TSSOP-16
TSSOP-24
TSSOP-24
LFCSP-40
SOT23-8
MSOP-8
TSSOP-28
MSOP-10
TSSOP-16
TSSOP-38
MSOP-8
TSSOP-28
TSSOP-16
TSSOP-38
Comments
Fast 8-bit load; see also AD5426
See also AD5425 fast load
See also AD5425 fast load
See also AD5452 and AD5444
Higher accuracy version of AD5443; see also AD5444
Higher accuracy version of AD5443; see also AD5452
Uncommitted resistors
Uncommitted resistors
MSOP version of AD5453; compatible with AD5443, AD5432, and AD5426
Rev. D | Page 17 of 21
DAC08
Data Sheet
OUTLINE DIMENSIONS
0.775
0.755
0.735
PIN 1
INDICATOR
1
8
0.280
0.250
0.240
TOP VIEW
0.100
BSC
0.210
MAX
SIDE VIEW
0.325
0.310
0.300
0.195
0.130
0.115
0.015
MIN
0.150
0.130
0.115
0.022
0.018
0.015
0.070
0.045 0.060
0.039 0.055
0.030
0.015
GAUGE
PLANE
END VIEW
SEATING
PLANE
0.021
0.016
0.011
0.012
0.010
0.008
0.430
MAX
03-07-2014-D
9
16
COMPLIANT TO JEDEC STANDARDS MS-001-BB
Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches
0.005 (0.13) MIN
0.098 (2.49) MAX
16
9
1
PIN 1
0.310 (7.87)
0.220 (5.59)
8
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
0.070 (1.78) PLANE
0.030 (0.76)
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 35. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
Rev. D | Page 18 of 21
Data Sheet
DAC08
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
0.100 (2.54)
0.064 (1.63)
0.200 (5.08)
REF
0.100 (2.54) REF
0.015 (0.38)
MIN
0.075 (1.91)
REF
0.095 (2.41)
0.075 (1.90)
19
18
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.088 (2.24)
0.054 (1.37)
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
3
20
4
0.028 (0.71)
0.022 (0.56)
1
BOTTOM
VIEW
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
8
14
13
9
45° TYP
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 37. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model 1, 2, 3
DAC08AQ
DAC08AQ/883C
DAC08HQ
DAC08Q
DAC08RC/883C
DAC08EQ
DAC08ES
DAC08ESZ
DAC08ESZ-REEL
DAC08CP
DAC08CPZ
DAC08CS
DAC08CS-REEL
DAC08CSZ
DAC08CSZ-REEL
DAC08EPZ
1
2
3
NL
±0.10%
±0.10%
±0.10%
±0.19%
±0.19%
±0.19%
±0.19%
±0.19%
±0.19%
±0.39%
±0.39%
±0.39%
±0.39%
±0.39%
±0.39%
±0.19%
Temperature Range
−55°C to +125°C
−55°C to +125°C
0°C to 70°C
−55°C to +125°C
−55°C to +125°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
Package Description
16-Lead CERDIP
16-Lead CERDIP
16-Lead CERDIP
16-Lead CERDIP
20-Terminal LCC
16-Lead CERDIP
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead PDIP
16-Lead PDIP
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead PDIP
Devices processed in total compliance to MIL-STD-883. Consult the factory for the 883 data sheet.
For availability and burn-in information on the SOIC package, contact your local sales office.
Z = RoHS Compliant Part.
Rev. D | Page 19 of 21
Package Option
Q-16
Q-16
Q-16
Q-16
E-20-1
Q-16
R-16
R-16
R-16
N-16
N-16
R-16
R-16
R-16
R-16
N-16
No. Parts Per Container
25
25
25
25
55
25
47
47
2500
25
25
47
2500
47
2500
25
DAC08
Data Sheet
NOTES
Rev. D | Page 20 of 21
Data Sheet
DAC08
NOTES
©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00268-0-3/16(D)
Rev. D | Page 21 of 21
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