DAC8043FZ

a FEATURES 12-Bit Accuracy in an 8-Pin Mini-DIP Fast Serial Data Input Double Data Buffers Low 61/2 LSB Max INL and DNL Max Gain Error: 61 LSB Low 5 ppm/8C Max Tempco ESD Resistant Low Cost Available in Die Form 12-Bit Serial Input Multiplying CMOS D/A Converter DAC8043 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Autocalibration Systems Process Control and Industrial Automation Programmable Amplifiers and Attenuators Digitally-Controlled Filters PIN CONNECTIONS GENERAL DESCRIPTION The DAC8043 is a high accuracy 12-bit CMOS multiplying DAC in a space-saving 8-pin mini-DIP package. Featuring serial data input, double buffering, and excellent analog performance, the DAC8043 is ideal for applications where PC board space is at a premium. Also, improved linearity and gain error performance permit reduced parts count through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output. The circuit consists of a 12-bit serial-in, parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC, and control logic. Serial data is clocked into the input register on the rising edge of the CLOCK pulse. When the new data word has been clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the D/A converter. The DAC8043’s fast interface timing may reduce timing design considerations while minimizing microprocessor wait states. For applications requiring an asynchronous CLEAR function or more versatile microprocessor interface logic, refer to the PM-7543. Operating from a single +5 V power supply, the DAC8043 is the ideal low power, small size, high performance solution to many application problems. It is available in plastic and cerdip packages that are compatible with auto-insertion equipment. 8-Pin Epoxy DIP (P-Suffix) 8-Pin Cerdip (Z-Suffix) 16-Lead Wide-Body SOL (S-Suffix) N.C. 1 16 N.C. N.C. 2 15 N.C. VREF 3 14 VDD RFB 4 DAC8043 13 CLK TOP VIEW IOUT 5 (Not to Scale) 12 SRI GND 6 11 LD GND 7 10 N.C. N.C. 8 9 N.C. NC = NO CONNECT REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 DAC8043–SPECIFICATIONS (@ V = +5 V; V ELECTRICAL CHARACTERISTICS Parameter STATIC ACCURACY Resolution Nonlinearity (Note 1) Differential Nonlinearity (Note 2) Gain Error (Note 3) Gain Tempco (∆ Gain/∆ Temp) (Note 5) Power Supply Rejection Ratio (∆ Gain/∆ VDD) Output Leakage Current (Note 4) Zero Scale Error (Notes 7, 12) Input Resistance (Note 8) AC PERFORMANCE Output Current Settling Time (Notes 5, 6) Digital to Analog Glitch Energy (Note 5, 10) Feedthrough Error (VREF to IOUT) (Note 5, 11) Total Harmonic Distortion (Note 5) Output Noise Voltage Density (Note 5, 13) DIGITAL INPUTS Digital Input HIGH Digital Input LOW Input Leakage Current (Note 9) Input Capacitance (Note 5, 11) ANALOG OUTPUTS Output Capacitance (Note 5) Symbol N INL DNL GFSE DD REF = +10 V; IOUT = GND = 0 V; TA = Full Temperature Range specified under Absolute Maximum Ratings unless otherwise noted). Conditions Min DAC8043 Typ Max Units ± 1/2 1 ± 1/2 ±1 Bits LSB LSB LSB LSB 1 2 LSB LSB 2 LSB ±5 ppm/°C ± 0.002 %/% ±5 nA ± 100 ± 25 0.03 nA nA LSB 0.61 0.15 LSB LSB 11 15 kΩ 0.25 1 µs 2 20 nVs 0.7 1 mV p-p 12 DAC8043A/E/G DAC8043F DAC8043A/E DAC8043F/G TA = +25°C DAC8043A/E DAC8043F/G TA = Full Temperature Range All Grades TCGFS PSRR ∆VDD = ± 5% ILKG TA = +25°C TA = Full Temperature Range DAC8043A DAC8043E/F/G TA = +25°C TA = Full Temperature Range DAC8043A DAC8043E/F/G IZSE ± 0.0006 RIN tS Q FT THD en 7 TA = +25°C VREF = 0 V IOUT Load = 100 Ω CEXT = 13 pF DAC Register Loaded Alternately with All 0s and All 1s VREF = 20 V p-p @ f = 10 kHz Digital Input = 0000 0000 0000 TA = +25°C VREF = 6 V rms @ 1 kHz DAC Register Loaded with All 1s 10 Hz to 100 kHz between RFB and IOUT –85 dB 17 2.4 VIN nV/√Hz V VIL IIL VIN = 0 V to +5 V 0.8 ±1 V µA CIN VIN = 0 V 8 pF COUT Digital Inputs = VIH Digital Inputs = VIL 110 80 pF pF –2– REV. C DAC8043 DAC8043 Parameter Symbol TIMING CHARACTERISTICS (NOTES 5, 14) Data Setup Time tDS Data Hold Time tDH Clock Pulse Width High tCH Clock Pulse Width Low tCL Load Pulse Width tLD LSB Clock Into Input Register to Load DAC Register Time tASB POWER SUPPLY Supply Voltage Supply Current Conditions Min Typ TA = Full Temperature Range TA = Full Temperature Range TA = Full Temperature Range TA = Full Temperature Range TA = Full Temperature Range 40 80 90 120 120 ns ns ns ns ns TA = Full Temperature Range 0 ns 4.75 VDD IDD 5 Digital Inputs = VIH or VIL Digital Inputs = 0 V or VDD Max 5.25 500 100 Units V µA max µA max NOTES 11 ± 1/2 LSB = ± 0.012% of full scale. 12 All grades are monotonic to 12-bits over temperature. 13 Using internal feedback resistor. 14 Applies to I OUT; All digital inputs = 0 V. 15 Guaranteed by design and not tested. 16 IOUT Load = 100 Ω, CEXT = 13 pF, digital input = 0 V to V DD or VDD to 0 V. Extrapolated to 1/2 LSB; t S = propagation delay (t PD) + 9τ where τ = measured time constant of the final RC decay. 17 VREF = +10 V, all digital inputs = 0 V. 18 Absolute temperature coefficient is less than +300 ppm/°C. 19 Digital inputs are CMOS gates; I IN is typically 1 nA at +25°C. 10 VREF = 0 V, all digital inputs = 0 V to V DD or VDD to 0 V. 11 All digit inputs = 0 V. 12 Calculated from worst case R REF: IZSE (in LSBs) = (RREF × ILKG × 4096)/VREF. 13 Calculations from en = √4K TRB where: K = Boltzmann constant, J/°K, R = resistance, Ω, T = resistor temperature, °K, B = bandwidth, Hz. 14 Tested at VIN = 0 V or VDD. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS CAUTION (TA = +25°C unless otherwise noted) 1. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF (Pin 1) and RFB (Pin 2). 2. The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper antistatic handling procedures. 4. Absolute Maximum Ratings apply to both packaged devices and DICE. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+17 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 25 V Digital Input Voltage Range . . . . . . . . . . . . . . . –0.3 V to VDD Output Voltage (Pin 3) . . . . . . . . . . . . . . . . . . . –0.3 V to VDD Operating Temperature Range AZ Versions . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C EZ/FZ/FP Versions . . . . . . . . . . . . . . . . . . . –40°C to +85°C GP Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C ORDERING GUIDE1 Package Type uJA* uJC Units Model Relative Accuracy Temperature Range Package Option 8-Pin Hermetic DIP (Z) 8-Pin Plastic DIP (P) 134 96 12 37 °C/W °C/W DAC8043AZ2 DAC8043AZ/8832 DAC8043EZ DAC8043FS DAC8043FZ DAC8043FP DAC8043GP DAC8043HP ± 1/2 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB –55°C to +125°C –55°C to +125°C –40°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C 8-Pin Cerdip 8-Pin Cerdip 8-Pin Cerdip 16-Lead (Wide) SOL 8-Pin Cerdip 8-Pin Epoxy DIP 8-Pin Epoxy DIP 8-Pin Epoxy DIP *uJA is specified for worst case mounting conditions, i. e., uJA is specified for device in socket for cerdip and P-DIP packages. NOTES 1 All commercial and industrial temperature range parts are available with burn-in. 2 For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. REV. C –3– DAC8043 WAFER TEST LIMITS @ V DD = +5 V, VREF = +10 V; IOUT = GND = 0 V, TA = +258C. Parameter Symbol STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Power Supply Rejection Ratio Output Leakage Current (IOUT) N INL DNL GFSE PSRR ILKG REFERENCE INPUT Input Resistance DAC8043GBC Limit Conditions Units 12 ±1 ±1 ±2 ± 0.002 ±5 Bits min LSB max LSB max LSB max %/% max nA max RIN 7/15 kΩ min/max DIGITAL INPUTS Digital Input HIGH Digital Input LOW Input Leakage Current VIH VIL IIL VIN = 0 V to VDD 2.4 0.8 ±1 V min V max µA max POWER SUPPLY Supply Current IDD Digital Inputs = VIN or VIL Digital Inputs = 0 V or VDD 500 100 µA max µA max Using Internal Feedback Resistor ∆VDD = ± 5% Digital Inputs = VIL NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. DICE CHARACTERISTICS 1. VREF 2. RFB 3. IOUT 4. GND 5. LD 6. SRI 7. CLK 8. VDD Substate (die backside) is internally connected to VDD. DIE SIZE 0.116 × 0.109 inch, 12,644 sq. mils (2.95 × 2.77 mm, 8.17 sq. mm) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8043 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. C DAC8043 TYPICAL PERFORMANCE CHARACTERISTICS Gain vs. Frequency (Output Amplifier: OP42) Supply Current vs. Logic Input Voltage Total Harmonic Distortion vs. Frequency (Multiplying Mode) Linearity Error vs. Digital Code Logic Threshold Voltage vs. Supply Voltage REV. C Linearity Error vs. Reference Voltage DNL Error vs. Reference Voltage –5– DAC8043 PARAMETER DEFINITIONS INTEGRAL NONLINEARITY (INL) This is the single most important DAC specification. ADI measures INL as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. It is expressed as a percent of full-scale range or in terms of LSBs. Refer to PMI 1988 Data Book section 11 for additional digitalto-analog converter definitions. INTERFACE LOGIC INFORMATION The DAC8043 has been designed for ease of operation. The timing diagram illustrates the input register loading sequence. Note that the most significant bit (MSB) is loaded first. Figure 1. Digital Input Protection The digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift register and then transferred, in parallel, to the 12-bit DAC register. Once the input register is full, the data is transferred to the DAC register by taking LD momentarily low. DIGITAL SECTION A simplified circuit of the DAC8043 is shown in Figure 2. An inverted R-2R ladder network consisting of silicon-chrome, highly-stable (+50 ppm/°C) thin-film resistors, and twelve pairs of NMOS current-steering switches. The DAC8043’s digital inputs, SRI, LD, and CLK, are TTL compatible. The input voltage levels affect the amount of current drawn from the supply; peak supply current occurs as the digital input (VIN) passes through the transition region. See the Supply Current vs. Logic Input Voltage graph located under the typical performance characteristics curves. Maintaining the digital input voltage levels as close as possible to the supplies, VDD and GND, minimizes supply current consumption. These switches steer binarily weighted currents into either IOUT or GND; this yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resistance at VREF equal to R. The VREF input may be driven by any reference voltage or current, ac or dc that is within the limits stated in the Absolute Maximum Ratings. The DAC8043’s digital inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 1 shows the input protection diodes and series resistor; this input structure is duplicated on each digital input. High voltage static charges applied to the inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions. The twelve output current-steering NMOS FET switches are in series with each R-2R resistor, they can introduce bit errors if all are of the same RON resistance value. They were designed such that the switch “ON” resistance be binarily scaled so that the voltage drop across each switch remains constant. If, for example, switch 1 of Figure 2 was designed with an “ON” resistance of 10 Ω, switch 2 for 20 Ω, etc., a constant 5 mV drop will then be maintained across each switch. GENERAL CIRCUIT INFORMATION The DAC8043 is a 12-bit multiplying D/A converter with a very low temperature coefficient. It contains an R-2R resistor ladder network, data input and control logic, and two data registers. Write Cycle Timing Diagram –6– REV. C DAC8043 To further insure accuracy across the full temperature range, permanently “ON” MOS switches were included in series with the feedback resistor and the R-2R ladder’s terminating resistor. The “Simplified DAC Circuit,” Figure 2, shows the location of the series switches. These series switches are equivalently scaled to two times switch 1 (MSB) and to switch 12 (LSB) respectively to maintain constant relative voltage drops with varying temperature. During any testing of the resistor ladder or RFEEDBACK (such as incoming inspection), VDD must be present to turn “ON” these series switches. DYNAMIC PERFORMANCE OUTPUT IMPEDANCE The DAC8043’s output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT terminal, may be between 10 kΩ (the feedback resistor alone when all digital inputs are LOW) and 7.5 kΩ (the feedback resistor in parallel with approximate 30 kΩ of the R-2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be affected by these variations. This variation is best illustrated by using the circuit of Figure 4 and the equation:  R  VERROR = VOS 1+ FB  RO   where RO is a function of the digital code, and: RO = 10 kΩ for more than four bits of logic 1. RO = 30 kΩ for any single bit of logic 1. Therefore, the offset gain varies as follows: at code 0011 1111 1111,   VERROR1 = VOS 1+ 10 kΩ = 2 VOS 10 kΩ at code 0100 0000 0000,   VERROR2 = VOS 1+ Figure 2. Simplified DAC Circuit EQUIVALENT CIRCUIT ANALYSIS Figure 3 shows an equivalent analog circuit for the DAC8043. The (D × VREF)/R current source is code dependent and is the current generated by the DAC. The current source ILKG consists of surface and junction leakages and doubles approximately every 10°C. COUT is the output capacitance; it is the result of the N-channel MOS switches and varies from 80 pF to 110 pF depending on the digital input code. RO is the equivalent output resistance that also varies with digital input code. R is the nominal R-2R resistor ladder resistance. 10 kΩ  = 4/3 VOS 30 kΩ The error difference is 2/3 VOS. Since one LSB has a weight (for VREF = +10 V) of 2.4 mV for the DAC8043, it is clearly important that VOS be minimized, either using the amplifier’s nulling pins, an external nulling network, or by selection of an amplifier with inherently low VOS. Amplifiers with sufficiently low VOS include ADI’s OP77, OP07, OP27, and OP42. Figure 3. Equivalent Analog Circuit Figure 4. Simplified Circuit REV. C –7– DAC8043 The gain and phase stability of the output amplifier, board layout, and power supply decoupling will all affect the dynamic performance. The use of a small compensation capacitor may be required when high-speed operational amplifiers are used. It may be connected across the amplifier’s feedback resistor to provide the necessary phase compensation to critically damp the output. The DAC8043’s output capacitance and the RFB resistor form a pole that must be outside the amplifier’s unity gain crossover frequency. The considerations when using high-speed amplifiers are: 1. Phase compensation (see Figures 5 and 6). 2. Power supply decoupling at the device socket and use of proper grounding techniques. Figure 6. Unipolar Operation with Fast Op Amp and Gain Error Trimming (2-Quadrant) the analog output is shown in Table I. The limiting parameters for the VREF range are the maximum input voltage range of the op amp or ± 25 V, whichever is lowest. APPLICATIONS INFORMATION APPLICATION TIPS In most applications, linearity depends upon the potential of IOUT and GND (pins 3 and 4) being exactly equal to each other. In most applications, the DAC is connected to an external op amp with its noninverting input tied to ground (see Figures 5 and 6). The amplifier selected should have a low input bias current and low drift over temperature. The amplifier’s input offset voltage should be nulled to less than +200 µV (less than 10% of 1 LSB). Gain error may be trimmed by adjusting R1 as shown in Figure 6. The DAC register must first be loaded with all 1s. R1 may then be adjusted until VOUT = –VREF (4095/4096). In the case of an adjustable VREF, R1 and R2 may be omitted, with VREF adjusted to yield the desired full-scale output. The operational amplifier’s noninverting input should have a minimum resistance connection to ground; the usual bias current compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a varying output error. All grounded pins should tie to a single common ground point, avoiding ground loops. The VDD power supply should have a low noise level with no transients greater than +17 V. Table I. Unipolar Code Table In most applications the DAC8043’s negligible zero scale error and very low gain error permit the elimination of the trimming components (R1 and the external R2) without adverse effects on circuit performance. Digital Input MSB LSB Nominal Analog Output (VOUT as shown in Figures 5 and 6) 1111 1111 1111  4095  –VREF    4096  1000 0000 0001 –VREF    4096  1000 0000 0000  2048 VREF –VREF  = –  4096 2 0111 1111 1111  2047 –VREF    4096 0000 0000 0001 –VREF  1  4096 0000 0000 0000 –VREF UNIPOLAR OPERATION (2-QUADRANT) The circuit shown in Figures 5 and 6 may be used with an ac or dc reference voltage. The circuit’s output will range between 0 V and approximately –VREF (4095/4096) depending upon the digital input code. The relationship between the digital input and  2049     0   4096  = 0   NOTES 1 Nominal full scale for the circuits of Figures 5 and 6 is given by  4095   4096  FS = –VREF  Figure 5. Unipolar Operation with High Accuracy Op Amp (2-Quadrant) 2 Nominal LSB magnitude for the circuits of Figures 5 and 6 is given by  1   or VREF (2–n).  4096  LSB = VREF  –8– REV. C DAC8043 Table II. Bipolar (Offset Binary) Code Table Digital Input MSB LSB Nominal Analog Output (VOUT as Shown in Figure 7) 1111 1111 1111  2047  +VREF  2048    1000 0000 0001  1  +VREF  2048    1000 0000 0000 0 0111 1111 1111 –VREF  2048    0000 0000 0001 –VREF  2048    0000 0000 0000  2048  –VREF  2048     1  2 Calibration is performed by loading the DAC register with 1000 0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be omitted, adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full scale can be adjusted by loading the DAC register with 1111 1111 1111 and either adjusting the amplitude of VREF or the value of R5 until the desired VOUT is achieved. ANALOG/DIGITAL DIVISION The transfer function for the DAC8043 connected in the multiplying mode as shown in Figures 5, 6 and 7 is:  2047  NOTES 1 Nominal full scale for the circuit of Figure 7 is given by FS = VREF Resistors R3, R4, and R5 must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient matching. Mismatching between R3 and R4 causes offset and full scale errors while an R5 to R4 and R3 mismatch will result in full-scale error.  2047   2048  .  A1 A2 A3 A12  VO = –VIN  1 + 2 + 3 +... 12  2  2 2 2 where AX assumes a value of 1 for an “ON” bit and 0 for an “OFF” bit. The transfer function is modified when the DAC is connected in the feedback of an operational amplifier as shown in Figure 8 and becomes:   –V IN   VO =  A1 A2 A3 A12   1 + 2 + 3 +... 4  2 2 2 2  Nominal LSB magnitude for the circuit of Figure 7 is given by LSB = VREF  1   2048  . BIPOLAR OPERATION (4-QUADRANT) Figure 7 details a suggested circuit for bipolar, or offset binary operation. Table II shows the digital input to analog output relationship. The circuit uses offset binary coding. Two’s complement code can be converted to offset binary by software inversion of the MSB or by the addition of an external inverter to the MSB input. The above transfer function is the division of an analog voltage (VREF) by a digital word. The amplifier goes to the rails with all bits “OFF” since division by zero is infinity. With all bits “ON,” the gain is 1 (± 1 LSB). The gain becomes 4096 with the LSB, bit 12 “ON.” Figure 7. Bipolar Operation (4-Quadrant, Offset Binary) REV. C –9– DAC8043 DAC8043 INTERFACE TO THE 8085 The DAC8043’s interface to the 8085 microprocessor is shown in Figure 10. Note that the microprocessor’s SOD line is used to present data serially to the DAC. Data is clocked into the DAC8043 by executing memory write instructions. The clock input is generated by decoding address 8000 and WR. Data is loaded into the DAC register with a memory write instruction to address A000. Serial data supplied to the DAC8043 must be present in the right justified format in registers H and L of the microprocessor. Figure 8. Analog/Digital Divider INTERFACING TO THE MC6800 As shown in Figure 9, the DAC8043 may be interfaced to the 6800 by successively executing memory WRITE instructions while manipulating the data between WRITEs, so that each WRITE presents the next bit. In this example the most significant bits are found in memory location 0000 and 0001. The four MSBs are found in the lower half of 0000, the eight LSBs in 0001. The data is taken from the DB7 line. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE to memory location 2000, R/W, and φ2. A WRITE to address 4000 transfers data from input register to DAC register. Figure 10. DAC8043-8085 Interface DAC8043 TO 68000 INTERFACING The DAC8043 interfacing to the 68000 microprocessor is shown in Figure 11. Again, serial data to the DAC is taken from one of the microprocessor’s data bus lines. Figure 11. DAC8043–68000 µ P Interface Figure 9. DAC8043–MC6800 Interface –10– REV. C –11– –12– PRINTED IN U.S.A. 000000000