DAC8420ES

FEATURES FUNCTIONAL BLOCK DIAGRAM Guaranteed monotonic over temperature Excellent matching between DACs Unipolar or bipolar operation Buffered voltage outputs High speed serial digital interface Reset-to-zero scale or midscale Wide supply range, +5 V only to ±15 V Low power consumption (35 mW maximum) Available in 16-Lead PDIP, SOIC, and CERDIP packages 1 SDI 10 REG A DAC A 7 VOUTA REG B DAC B 6 VOUTB REG C DAC C 3 VOUTC REG D DAC D 2 VOUTD 12 CS 12 CLK 11 SHIFT REGISTER 4 Software controlled calibration Servo controls Process control and automation ATE VDD 5 DAC8420 NC 13 APPLICATIONS VREFHI DECODE LD 14 2 9 GND 16 15 CLSEL CLR 4 8 VREFLO VSS 00275-001 Data Sheet Quad 12-Bit Serial Voltage Output DAC DAC8420 Figure 1. GENERAL DESCRIPTION The DAC8420 is a quad, 12-bit voltage-output DAC with serial digital interface in a 16-lead package. Utilizing BiCMOS technology, this monolithic device features unusually high circuit density and low power consumption. The simple, easy-to-use serial digital input and fully buffered analog voltage outputs require no external components to achieve a specified performance. The 3-wire serial digital input is easily interfaced to microprocessors running at 10 MHz with minimal additional circuitry. Each DAC is addressed individually by a 16-bit serial word consisting of a 12-bit data word and an address header. Rev. C The user-programmable reset control CLR forces all four DAC outputs to either zero scale or midscale, asynchronously overriding the current DAC register values. The output voltage range, determined by the inputs VREFHI and VREFLO, is set by the user for positive or negative unipolar or bipolar signal swings within the supplies, allowing considerable design flexibility. The DAC8420 is available in 16-lead PDIP, SOIC, and CERDIP packages. Operation is specified with supplies ranging from +5 V only to ±15 V, with references of +2.5 V to ±10 V, respectively. Power dissipation when operating from ±15 V supplies is less than 255 mW (maximum) and only 35 mW (maximum) with a +5 V supply. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com DAC8420 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Correct Operation of CS and CLK........................................... 13 Applications ....................................................................................... 1 Using CLR and CLSEL............................................................... 13 Functional Block Diagram .............................................................. 1 Programming the Analog Outputs .......................................... 13 General Description ......................................................................... 1 VREFHI Input Requirements ................................................... 15 Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 15 Specifications..................................................................................... 3 Applications..................................................................................... 16 Electrical Characteristics ............................................................. 3 Power Supply Bypassing and Grounding ................................ 16 Absolute Maximum Ratings ............................................................ 6 Analog Outputs .......................................................................... 16 Thermal Resistance ...................................................................... 6 Reference Configuration ........................................................... 17 ESD Caution .................................................................................. 6 Isolated Digital Interface ........................................................... 18 Pin Configurations and Function Descriptions ........................... 8 Dual Window Comparator ....................................................... 19 Typical Performance Characteristics ............................................. 9 MC68HC11 Microcontroller Interfacing ................................ 19 Theory of Operation ...................................................................... 13 DAC8420 to M68HC11 Interface Assembly Program .......... 20 Introduction ................................................................................ 13 Outline Dimensions ....................................................................... 21 Digital Interface Operation ....................................................... 13 Ordering Guide .......................................................................... 22 REVISION HISTORY 9/2016—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 5/2007—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Endnote 3 ...................................................................... 4 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 2 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 23 9/2003—Rev. 0 to Rev. A Changes to General Description .................................................... 1 Deleted Wafer Test Limits table ...................................................... 4 Deleted Dice Characteristics ........................................................... 4 Updated Ordering Guide ................................................................. 4 Added Power-Up Sequence section ............................................. 12 Updated Outline Dimensions ....................................................... 17 Rev. C | Page 2 of 23 Data Sheet DAC8420 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 1 At VDD = +5.0 V ± 5%, VSS = 0 V, VVREFHI = +2.5 V, VVREFLD = 0 V, and VSS = −5.0 V ± 5%, VVREFLO = −2.5 V, −40°C ≤ TA ≤ +85°C unless otherwise noted. 2 Table 1. Parameter STATIC ACCURACY Integral Linearity E Grade Integral Linearity E Grade Integral Linearity F Grade Integral Linearity F Grade Differential Linearity Zero-Scale Error Full-Scale Error Zero-Scale Error Full-Scale Error Zero-Scale Temperature Coefficient Full-Scale Temperature Coefficient MATCHING PERFORMANCE Linearity Matching REFERENCE Positive Reference Input Range 5 Negative Reference Input Range5 Negative Reference Input Range Reference High Input Current Reference Low Input Current AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current Input Capacitance4 LOGIC TIMING CHARACTERISTICS4, 7 Data Setup Time Data Hold Clock Pulse Width High Clock Pulse Width Low Select Time Deselect Delay Load Disable Time Load Delay Load Pulse Width Clear Pulse Width Symbol INL INL INL INL DNL ZSE FSE ZSE FSE TCZSE TCFSE Test Conditions/Comments Min VSS = 0 V 3 VSS = 0 V3 Monotonic over temperature RL = 2 kΩ, VSS = −5 V RL = 2 kΩ, VSS = −5 V RL = 2 kΩ, VSS = 0 V3 RL = 2 kΩ, VSS = 0 V3 RL = 2 kΩ, VSS = −5 V 4 RL = 2 kΩ, VSS = −5 V4 VVREFHI VVREFLO VVREFLO IVREFHI IVREFLO VSS = 0 V5 Code 0x000, Code 0x555 Code 0x000, Code 0x555, VSS = −5 V IOUT tS SR VSS = −5 V To 0.01% 6 10% to 90%6 VVREFLO + 2.5 VSS 0 −0.75 −1.0 Typ Max Unit ±¼ ±½ ±¾ ±1 ±¼ ±1 ±3 ±2 ±4 ±1 ±4 ±4 ±8 ±8 ±10 ±10 LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C ppm/°C ±1 LSB ±0.25 −0.6 −1.25 VDD − 2.5 VVREFHI − 2.5 VVREFHI − 2.5 +0.75 V V V mA mA +1.25 mA μs V/μs 8 1.5 VINH VINL IIN CIN 2.4 tDS tDH tCH tCL tCSS tCSH tLD1 tLD2 tLDW tCLRW 25 55 90 120 90 5 130 35 80 150 0.8 10 13 Rev. C | Page 3 of 23 V V μA pF ns ns ns ns ns ns ns ns ns ns DAC8420 Parameter SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation Data Sheet Symbol PSRR IDD ISS PDISS Test Conditions/Comments Min −6 VSS = 0 V Typ Max Unit 0.002 4 −3 20 0.01 7 %/% mA mA mW Typical values indicate performance measured at 25°C. All supplies can be varied ±5% and operation is guaranteed. Device is tested with VDD = 4.75 V. For single-supply operation (VVREFLO = 0 V, VSS = 0 V), due to internal offset errors INL and DNL are measured beginning at Code 0x005. 4 Guaranteed, but not tested. 5 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 6 VOUT swing between +2.5 V and −2.5 V with VDD = 5.0 V. 7 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 1 2 3 Rev. C | Page 4 of 23 35 Data Sheet DAC8420 At VDD = +15.0 V ± 5%, VSS = −15.0 V ± 5%, VVREFHI = +10.0 V, VVREFLO = −10.0 V, −40°C ≤ TA ≤ +85°C unless otherwise noted. 1, 2 Table 2. Parameter STATIC ACCURACY Integral Linearity E Grade Integral Linearity F Grade Differential Linearity Zero-Scale Error Full-Scale Error Zero-Scale Temperature Coefficient Full-Scale Temperature Coefficient MATCHING PERFORMANCE Linearity Matching REFERENCE Positive Reference Input Range 4 Negative Reference Input Range4 Reference High Input Current Reference Low Input Current AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate DYNAMIC PERFORMANCE Analog Crosstalk3 Digital Feedthrough3 Large Signal Bandwidth Glitch Impulse LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current Input Capacitance3 LOGIC TIMING CHARACTERISTICS3, 6 Data Setup Time Data Hold Clock Pulse Width High Clock Pulse Width Low Select Time Deselect Delay Load Disable Time Load Delay Load Pulse Width Clear Pulse Width SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation Symbol INL INL DNL ZSE FSE TCZSE TCFSE Test Conditions/Comments Min Monotonic over temperature RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ 3 RL = 2 kΩ3 VVREFHI VVREFLO IVREFHI IVREFLO Code 0x000, Code 0x555 Code 0x000, Code 0x555 IOUT tS SR To 0.01% 5 10% to 90%5 3 dB, VVREFHI = 5 V + 10 V p-p, VVREFLO = −10 V3 Code Transition = 0x7FF to 0x8003 VVREFLO + 2.5 −10 −2.0 −3.5 Typ Max Unit ±¼ ±½ ±¼ ±½ ±1 ±1 ±2 ±2 ±4 ±4 LSB LSB LSB LSB LSB ppm/°C ppm/°C ±1 LSB VDD − 2.5 VVREFHI − 2.5 +2.0 V V mA mA +5 13 2 mA μs V/μs >64 >72 90 6 dB dB kHz μV-s ±1.0 −2.0 −5 VINH VINL IIN CIN 2.4 tDS tDH tCH tCL tCSS tCSH tLD1 tLD2 tLDW tCLRW 25 20 30 50 55 15 40 15 45 70 0.8 10 13 PSRR IDD ISS PDISS −8 ns ns ns ns ns ns ns ns ns ns 0.002 6 −5 0.01 9 255 Typical values indicate performance measured at 25°C. All supplies can be varied ±5% and operation is guaranteed. 3 Guaranteed, but not tested. 4 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 5 VOUT swing between +10 V and −10 V. 6 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 1 2 Rev. C | Page 5 of 23 V V μA pF %/% mA mA mW DAC8420 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VSS to GND VSS to VDD VSS to VVREFLO VVREFHI to VVREFLO VVREFHI to VDD IVREFHI, IVREFLO Digital Input Voltage to GND Output Short-Circuit Duration Operating Temperature Range EP, FP, ES, FS, EQ, FQ Dice Junction Temperature Storage Temperature Range Power Dissipation Lead Temperature Soldering Table 4. Rating −0.3 V, +18.0 V +0.3 V, −18.0 V −0.3 V, +36.0 V −0.3 V, VSS − 2.0 V +2.0 V, VDD − VSS +2.0 V, +33.0 V 10 mA −0.3 V, VDD + 0.3 V Indefinite Package Type 16-Lead PDIP (N) 16-Lead CERDIP (Q) 16-Lead SOIC (RW) 1 2 θJA 701 821 862 θJC 27 9 22 Unit °C/W °C/W °C/W θJA is specified for worst case mounting conditions, that is, θJA is specified for device in socket. θJA is specified for device on board. ESD CAUTION –40°C to +85°C 150°C –65°C to +150°C 1000 mW JEDEC Industry Standard J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 6 of 23 Data Sheet DAC8420 DATA LOAD SEQUENCE tCSH CS tCSS A1 SDI A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0 CLK tLD1 tLD2 LD tDS DATA LOAD TIMING tDH CLEAR TIMING SDI CLSEL CLK CLR tCLRW tCL tCH tS tCSH CS VOUT tLD2 tLDW ±1LSB LD VOUTx 00275-002 tS ±1LSB Figure 2. Timing Diagram –10V 1N4001 5kΩ 10kΩ + 10µF 10µF –15V 1N4001 NC 2 15 NC 3 14 4 0.1µF 5kΩ +10V 1N4001 16 0.1µF 10kΩ + 1 DUT 13 NC 5 12 NC 6 11 NC 7 10 8 9 10kΩ + 10µF 0.1µF 10kΩ 10kΩ + 10µF 0.1µF NC = NO CONNECT Figure 3. Burn-In Diagram Rev. C | Page 7 of 23 00275-003 +15V 1N4001 DAC8420 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 16 CLSEL VDD 1 16 CLSEL VOUTD 2 15 CLR VOUTD 2 15 CLR 14 LD VOUTC 3 14 LD TOP VIEW 13 NC (Not to Scale) 12 CS VREFLO 4 VREFHI 5 TOP VIEW 13 NC VREFHI 5 (Not to Scale) 12 CS VOUTB 6 11 CLK VOUTA 7 10 SDI VSS 8 9 GND NC = NO CONNECT DAC8420 VOUTB 6 11 CLK VOUTA 7 10 SDI VSS 8 9 GND NC = NO CONNECT Figure 4. PDIP and CERDIP 00275-005 VREFLO 4 DAC8420 00275-004 VOUTC 3 Figure 5. SOIC Table 5. Pin Function Descriptions Pin No. 1 4 Mnemonic VDD VREFLO 5 VREFHI 7, 6, 3, 2 8 9 10 VOUTA through VOUTD VSS GND SDI 11 CLK 12 CS 13 14 NC LD 15 CLR 16 CLSEL Description Positive Power Supply, 5 V to 15 V. Reference Input. Lower DAC ladder reference voltage input, equal to zero-scale output. Allowable range is VSS to (VVREFHI − 2.5 V). Reference Input. Upper DAC ladder reference voltage input. Allowable range is (VDD − 2.5 V) to (VVREFLO + 2.5 V). Buffered DAC Analog Voltage Outputs. Negative Power Supply, 0 V to −15 V. Power Supply, Digital Ground. Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which shifts data in, beginning with DAC Address Bit A1. This input is ignored when CS is high. SDI is CMOS/TTL compatible. The format of the 16-bit serial word is shown in Table 8. System Serial Data Clock Input, TTL/CMOS Levels. Data presented to the input SDI is shifted into the internal serial-parallel input register on the rising edge of clock. This input is logically OR’ed with CS. Control Input, Device Chip Select, Active Low. This input is logically OR’ed with the clock and disables the serial data register input when high. When low, data input clocking is enabled (see Table 6). CS is CMOS/TTL compatible. No Connect = Don’t Care. Control Input, Asynchronous DAC Register Load Control, Active Low. The data currently contained in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data must remain stable while LD is low. LD is CMOS/TTL compatible. Control Input, Asynchronous Clear, Active Low. Sets internal data Register A through Register D to zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is unaffected by this control. CLR is CMOS/TTL compatible. Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A through Register D to midscale (0x800). If low, the registers are set to zero (0x000). CLSEL is CMOS/ TTL compatible. Table 6. Control Function Logic Table CLK1 2 NC NC2 NC2 ↑ Low High High NC2 CS1 LD CLR CLSEL Serial Input Shift Register DAC Register A to DAC Register D High High High Low ↑ NC (↑)2 NC2 High High High High High High ↓ Low High Low Low ↑ High High High High High High Low High /Low NC2 NC2 NC2 NC2 NC2 No change No change No change Shifts register one bit Shifts register one bit No change No change No change Loads midscale value (0x800) Loads zero-scale value (0x000) Latches value No change No change Loads the serial data-word3 Transparent4 No change CLK and CS are interchangeable. NC = Don’t Care. 3 Returning CS high while CLK is high avoids an additional false clock of serial input data. CLK and CS are interchangeable. 4 Do not clock in serial data while LD is low. 1 2 Rev. C | Page 8 of 23 Data Sheet DAC8420 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.3 TA = +25°C VDD = +15V VSS = –15V VVREFLO = –10V 0.2 0.2 0.1 0.1 INL (LSB) DNL (LSB) TA = +25°C VDD = +5V VSS = 0V VVREFLO = 0V 0.3 0 0 –0.1 –0.1 –0.2 –0.2 –4 –2 0 2 4 6 VVREFHI (V) 8 10 12 14 –0.4 1.5 2.0 Figure 6. DNL vs. VVREFHI (±15 V) 2.5 VVREFHI (V) 00275-010 –0.3 –6 00275-007 –0.3 3.5 3.0 Figure 9. INL vs. VVREFHI (+5 V) 0.7 TA = +25°C VDD = +5V VSS = 0V VVREFLO = 0V 0.05 0 DNL (LSB) FULL-SCALE ERROR WITH RL = 2kΩ (LSB) 0.10 –0.05 –0.10 –0.15 –0.20 –0.25 x + 3σ 0.5 VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 0.3 x 0.1 –0.1 –0.3 x – 3σ 2.0 2.5 3.0 0 00275-008 1.5 3.5 VVREFHI (V) 200 400 600 800 1000 t = HOURS OF OPERATION AT 125°C CURVES NOT NORMALIZED Figure 7. DNL vs. VVREFHI (+5 V) 00275-011 –0.5 –0.30 Figure 10. Full-Scale Error vs. Time Accelerated by Burn-In 1.2 FULL-SCALE ERROR WITH RL = 2kΩ (LSB) 0.3 0.2 0 –0.1 TA = +25°C VDD = +15V VSS = –15V VVREFLO = –10V –0.2 VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 0.8 x 0.6 0.4 0.2 x – 3σ –4 –2 0 2 4 6 8 VVREFHI (V) 10 12 14 0 200 400 600 800 1000 t = HOURS OF OPERATION AT 125°C CURVES NOT NORMALIZED Figure 8. INL vs. VREFHI (±15 V) Figure 11. Zero-Scale Error vs. Time Accelerated by Burn-In Rev. C | Page 9 of 23 00275-012 0 –0.3 –6 00275-009 INL (LSB) 0.1 x + 3σ 1.0 DAC8420 Data Sheet 1.5 0.2 VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 0 0.5 –0.1 DAC C DAC D –0.2 DAC A –0.3 0 –0.5 –1.0 DAC B –0.4 –25 0 25 50 TEMPERATURE (°C) 75 125 100 00275-013 –50 0 Figure 12. Full-Scale Error vs. Temperature 11 4000 4500 10 IDD (mA) DAC C 0.4 DAC A 0.2 9 8 7 DAC D 0 6 –0.2 5 –50 –25 0 25 50 TEMPERATURE (°C) 75 125 100 4 –7 –5 –3 –1 0 1 3 5 VVREFHI (V) 7 9 13 11 00275-017 0.6 Figure 13. Zero-Scale Error vs. Temperature Figure 16. IDD vs. VVREFHI, All DACs High 0.9 0.8 TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 0.7 0.5 TA = +25°C, –55°C, 125°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 0.7 0.6 0.5 0.4 INL (LSB) 0.3 0.1 –0.1 0.3 0.2 0.1 0 –0.3 –0.1 –0.2 –0.5 –0.3 –0.7 0 500 1000 1500 2000 2500 3000 DIGITAL INPUT CODE 3500 4000 4500 Figure 14. Channel-to-Channel Matching 0 500 1000 1500 2000 2500 3000 DIGITAL INPUT CODE Figure 17. INL vs. Code Rev. C | Page 10 of 23 3500 4000 4500 00275-018 –0.4 –0.9 00275-015 ERROR (±LSB) 3500 TA = +25°C VDD = +15V VSS = –15V VVREFLO = –10V 12 DAC B –0.4 –75 1500 2000 2500 3000 DIGITAL INPUT CODE 13 VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 00275-014 ZERO-SCALE ERROR (LSB) 0.8 1000 Figure 15. Channel-to-Channel Matching 1.2 1.0 500 00275-016 –1.5 –0.5 –0.6 –75 TA = +25°C VDD = +5V VSS = 0V VVREFHI = +2.5V VVREFLO = 0V 1.0 ERROR (LSB) FULL-SCALE ERROR (LSB) 0.1 Data Sheet DAC8420 1.5 31.25mV LD TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 0.5 0 TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 4.88mV 1 LSB 0mV –1.0 0 500 1000 1500 2000 2500 3000 DIGITAL INPUT CODE 3500 4000 4500 –18.75mV –9.8µs 90.2µs 10µs/DIV tSETT Figure 18. IVREFHI vs. Code 00275-022 –0.5 00275-019 IVREFHI (mA) 1.0 13µs Figure 21. Positive Settling Time (±15 V) –2.50µV 43.75mV CLR LD TA = +25°C VDD = +5V VSS = –5V VVREFHI = +2.5V VVREFLO = –2.5V 1.22mV 1 LSB 0mV TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 45.1µs 5µs/DIV tSETT 8µs –6.25mV –9.8µs Figure 19. Positive Settling Time (±5 V) 90.2µs 10µs/DIV tSETT 13µs Figure 22. Negative Settling Time (±15 V) 6.5mV CLR 5V TA = +25°C VDD = +5V VSS = –5V VVREFHI = +2.5V VVREFLO = –2.5V TA = +25°C VDD = +5V VSS = –5V VVREFHI = +2.5V VVREFLO = –2.5V +1V/DIV 0 5µs/DIV tSETT 8µs 45.1µs Figure 20. Negative Settling Time (±5 V) –5V –47.6µs SRRISE = 1.65 V µs 20µs/DIV SRFALL = 1.17 Figure 23. Slew Rate (±5 V) Rev. C | Page 11 of 23 V µs 152.4µs 00275-024 3.5mV –4.9µs 00275-021 0mV 1 LSB 1.22mV 00275-023 –10.25mV –4.9µs 00275-020 0mV 1 LSB –4.88mV DAC8420 Data Sheet 6 25V LD POWER SUPPLY CURRENT (mA) IDD CLR +5V/DIV 0 TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 4 2 0 VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V ALL DACS HIGH (FULL SCALE) –2 –4 V µs SRFALL = 2.02 V µs –6 –75 00275-025 SRRISE = 1.9 20µs/DIV 166.4µs 10 0 10mA/DIV –10 –20 –30 VOUTA THROUGH VOUTD TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V DATA = 0x800 1k 1M 10k 100k FREQUENCY (Hz) 10M 00275-029 100 00275-026 TA = +25°C VDD = +15V VSS = –15V VVREFHI = 0 ±100mV VVREFLO = –10V ALL BITS HIGH 200mV p-p 10 150 Figure 27. Power Supply Current vs. Temperature Figure 24. Slew Rate (±15 V) GAIN (dB) 75 0 TEMPERATURE (°C) 00275-028 ISS –25V –33.6µs 5V/DIV Figure 25. Small-Signal Response Figure 28. DAC Output Current vs. VOUTx 100 10 90 80 8 50 40 30 20 10 0 10 TA = +25°C DATA = 0x000 VDD = +15V ±1V VSS = –15V VVREFHI = +10V VVREFLO = –10V 100 6 4 2 1k 10k FREQUENCY (Hz) 100k 1M 0 10 Figure 26. PSRR vs. Frequency TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V DATA = 0xFFF OR 0x000 100 1k LOAD RESISTANCE (Ω) Figure 29. Output Swing vs. Load Resistance Rev. C | Page 12 of 23 10k 00275-030 |VOUT PEAK| (V) 60 00275-027 PSRR (dB) 70 Data Sheet DAC8420 THEORY OF OPERATION INTRODUCTION USING CLR AND CLSEL The DAC8420 is a quad, voltage-output 12-bit DAC with a serial digital input capable of operating from a single 5 V supply. The straightforward serial interface can be connected directly to most popular microprocessors and microcontrollers, and can accept data at a 10 MHz clock rate when operating from ±15 V supplies. A unique voltage reference structure ensures maximum utilization of the DAC output resolution by allowing the user to set the zero-scale and full-scale output levels within the supply rails. The analog voltage outputs are fully buffered, and are capable of driving a 2 kΩ load. Output glitch impulse during major code transitions is a very low 64 nV-s (typ). The clear (CLR) control allows the user to perform an asynchronous reset function. Asserting CLR loads all four DAC data-word registers, forcing the DAC outputs to either zero scale (0x000) or midscale (0x800), depending on the state of CLSEL as shown in Table 6. The clear function is asynchronous and totally independent of CS. When CLR returns high, the DAC outputs remain latched at the reset value until LD is strobed, reloading the individual DAC data-word registers with either the data held in the serial input register prior to the reset or with new data loaded through the serial interface. DIGITAL INTERFACE OPERATION Table 7. DAC Address Word Decode Table The serial input of the DAC8420, consisting of CS, SDI, and LD, is easily interfaced to a wide variety of microprocessor serial ports. While CS is low, the data presented to the input SDI is shifted into the internal serial-to-parallel shift register on the rising edge of the clock, with the address MSB first, data LSB last, as shown in Table 6 and in the timing diagram (Figure 2). The data format, shown in Table 8, is two bits of DAC address and two don’t care fill bits, followed by the 12-bit DAC data-word. Once all 16 bits of the serial data-word have been input, the load control LD is strobed and the word is parallel-shifted out onto the internal data bus. The two address bits are decoded and used to route the 12-bit data-word to the appropriate DAC data register (see the Applications section). CORRECT OPERATION OF CS AND CLK In Table 6, the control pins CLK and CS require some attention during a data load cycle. Since these two inputs are fed to the same logical OR gate, the operation is in fact identical. The user must take care to operate them accordingly to avoid clocking in false data bits. In the timing diagram, CLK must be halted high or CS must be brought high during the last high portion of the CLK following the rising edge that latched in the last data bit. Otherwise, an additional rising edge is generated by CS rising while CLK is low, causing CS to act as the clock and allowing a false data bit into the serial input register. The same issue must also be considered in the beginning of the data load sequence. A1 0 0 1 1 A0 0 1 0 1 DAC Addressed DAC A DAC B DAC C DAC D PROGRAMMING THE ANALOG OUTPUTS The unique differential reference structure of the DAC8420 allows the user to tailor the output voltage range precisely to the needs of the application. Instead of spending DAC resolution on an unused region near the positive or negative rail, the DAC8420 allows the user to determine both the upper and lower limits of the analog output voltage range. Thus, as shown in Table 9 and Figure 30, the outputs of DAC A through DAC D range between VREFHI and VREFLO, within the limits specified in the Specifications section. Note also that VREFHI must be greater than VREFLO. VDD 2.5V MIN VVREFHI 0xFFF 1 LSB 2.5V MIN 0x000 –10V MIN VVREFLO 00275-006 0V MIN VSS Figure 30. Output Voltage Range Programming Table 8. (FIRST) B0 B1 B2 A1 A0 NC —Address Word— B3 NC B4 D11 (MSB) B5 D10 B6 B7 B8 D9 D8 D7 —DAC Data-Word— B9 D6 Rev. C | Page 13 of 23 B10 D5 B11 D4 B12 D3 B13 D2 B14 D1 (LAST) B15 D0 (LSB) DAC8420 Data Sheet Table 9. Analog Output Code DAC Data-Word (Hex) 0xFFF 0x801 0x800 0x7FF 0x000 VOUT (VREFHI − VREFLO) VREFLO + × 4095 4096 (VREFHI − VREFLO) VREFLO + × 2049 4096 (VREFHI − VREFLO) VREFLO + × 2048 4096 (VREFHI − VREFLO) VREFLO + × 2047 4096 (VREFHI − VREFLO) VREFLO + ×0 4096 Rev. C | Page 14 of 23 Note Full-scale output Midscale + 1 Midscale Midscale − 1 Zero scale Data Sheet DAC8420 VREFHI INPUT REQUIREMENTS POWER-UP SEQUENCE The DAC8420 utilizes a unique, patented DAC switch driver circuit that compensates for different supply, reference voltage, and digital code inputs. This ensures that all DAC ladder switches are always biased equally, ensuring excellent linearity under all conditions. Thus, as shown in Table 1, the VREFHI input of the DAC8420 requires both sourcing and sinking current capabilities from the reference voltage source. Many positive voltage references are intended as current sources only and offer little sinking capability. The user must consider references such as the AD584, AD586, AD587, AD588, AD780, and REF43 for such an application. To prevent a CMOS latch-up condition, power up VDD, VSS, and GND prior to any reference voltages. The ideal power-up sequence is GND, VSS, VDD, VREFHI, VREFLO, and digital inputs. Noncompliance with the power-up sequence over an extended period can elevate the reference currents and eventually damage the device. On the other hand, if the noncompliant power-up sequence condition is as short as a few milliseconds, the device can resume normal operation without being damaged once VDD/VSS is powered. Rev. C | Page 15 of 23 DAC8420 Data Sheet APPLICATIONS In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The DAC8420 has a single ground pin that is internally connected to the digital section as the logic reference level. The first thought may be to connect this pin to digital ground; however, in large systems digital ground is often noisy because of the switching currents of other digital circuitry. Any noise that is introduced at the ground pin can couple into the analog output. Thus, to avoid error-causing digital noise in the sensitive analog circuitry, the ground pin must be connected to the system analog ground. The ground path (circuit board trace) must be as wide as possible to reduce any effects of parasitic inductance and ohmic drops. A ground plane is recommended if possible. The noise immunity of the on-board digital circuitry, typically in the hundreds of millivolts, is well able to reject the common-mode noise typically seen between system analog and digital grounds. Finally, the analog and digital ground must be connected to each other at a single point in the system to provide a common reference. This is preferably done at the power supply. Good grounding practice is also essential to maintaining analog performance in the surrounding analog support circuitry. With two reference inputs and four analog outputs capable of moderate bandwidth and output current, there is a significant potential for ground loops. Again, a ground plane is recommended as the most effective solution to minimizing errors due to noise and ground offsets. 1 V DD +VS 0.1µF 8 –VS 10µF VSS GND 9 0.1µF 10µF = TANTALUM 0.1µF = CERAMIC 00275-031 10µF Figure 31. Recommended Supply Bypassing Scheme The DAC8420 must have ample supply bypassing, located as close to the package as possible. Figure 31 shows the recommended capacitor values of 10 μF in parallel with 0.1 μF. The 0.1 μF capacitor must have low effective series resistance (ESR) and effective series inductance (ESI) (such as any common ceramic type capacitor), which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. To preserve the specified analog performance of the device, the supply must be as noise free as possible. In the case of 5 V only systems, it is desirable to use the same 5 V supply for both the analog circuitry and the digital portion of the circuit. Unfortunately, the typical 5 V supply is extremely noisy due to the fast edge rates of the popular CMOS logic families, which induce large inductive voltage spikes, and busy microcontroller or microprocessor buses, and therefore commonly have large current spikes during bus activity. However, by properly filtering the supply as shown in Figure 32, the digital 5 V supply can be used. The inductors and capacitors generate a filter that not only rejects noise due to the digital circuitry, but also filters out the lower frequency noise of switch mode power supplies. The analog supply must be connected as close as possible to the origin of the digital supply to minimize noise pickup from the digital section. FERRITE BEADS: 2 TURNS, FAIR-RITE #2677006301 TTL/CMOS LOGIC CIRCUITS +5V + 100µF + 10µF TO 22µF ELECT. TANT. 0.1µF CER. +5V RETURN +5V POWER SUPPLY 00275-032 POWER SUPPLY BYPASSING AND GROUNDING Figure 32. Single-Supply Analog Supply Filter ANALOG OUTPUTS The DAC8420 features buffered analog voltage outputs capable of sourcing and sinking up to 5 mA when operating from ±15 V supplies, eliminating the need for external buffer amplifiers in most applications while maintaining specified accuracy over the rated operating conditions. The buffered outputs are simply an operational amplifier connected as a voltage follower, and thus have output characteristics very similar to the typical operational amplifier. These amplifiers are short-circuit protected. The user must verify that the output load meets the capabilities of the device, in terms of both output current and load capacitance. The DAC8420 is stable with capacitive loads up to 2 nF typically. However, any capacitive load increases the settling time, and must be minimized if speed is a concern. The output stage includes a P-channel MOSFET to pull the output voltage down to the negative supply. This is very important in single-supply systems where VREFLO usually has the same potential as the negative supply. With no load, the zero-scale output voltage in these applications is less than 500 μV typically, or less than 1 LSB when VVREFHI = 2.5 V. However, when sinking current, this voltage does increase because of the finite impedance of the output stage. The effective value of the pull-down resistor in the output stage is typically 320 Ω. With a 100 kΩ resistor connected to 5 V, the resulting zero-scale output voltage is 16 mV. Thus, the best single-supply operation is obtained with the output load connected to ground, so the output stage does not have to sink current. Rev. C | Page 16 of 23 Data Sheet DAC8420 The AD588 provides both voltages and needs no external components. Additionally, the device is trimmed in production for 12-bit accuracy over the full temperature range without user calibration. Performing a clear with the reset select CLSEL high allows the user to easily reset the DAC outputs to midscale, or 0 V in these applications. Like all amplifiers, the DAC8420 output buffers do generate voltage noise, 52 nV/√Hz typically. This is easily reduced by adding a simple RC low-pass filter on each output. REFERENCE CONFIGURATION The two reference inputs of the DAC8420 allow a great deal of flexibility in circuit design. The user must take care, however, to observe the minimum voltage input levels on VREFHI and VREFLO to maintain the accuracy shown in the data sheet. These input voltages can be set anywhere across a wide range within the supplies, but must be a minimum of 2.5 V apart in any case (see Figure 30). A wide output voltage range can be obtained with ±5 V references, which can be provided by the AD588 as shown in Figure 33. Many applications utilize the DACs to synthesize symmetric bipolar waveforms, which require an accurate, low drift bipolar reference. When driving the reference inputs VREFHI and VREFLO, it is important to note that VREFHI both sinks and sources current, and that the input currents of both are code dependent. Many voltage reference products have a limited current sinking capability and must be buffered with an amplifier to drive VREFHI in order to maintain overall system accuracy. The input VREFLO, however, has no such requirement. +15V SUPPLY 1µF 7 6 4 3 5 AD588 RB A3 DAC8420 +5V 1 VREFHI +5V 0.1µF 1 DAC A 7 VOUTA DAC B 6 VOUTB DAC C 3 VOUTC DAC D 2 VOUTD A1 A4 R5 –5V 15 +15V SUPPLY +VS 2 R3 R6 A2 5 9 0.1µF SYSTEM GROUND –VS 16 10 8 12 DIGITAL CONTROLS 11 13 0.1µF –15V SUPPLY 10 11 12 14 15 16 4 9 GND DIGITAL INPUTS 8 VREFLO –5V –15V SUPPLY Figure 33. ±10 V Bipolar Reference Configuration Using the AD588 Rev. C | Page 17 of 23 0.1µF 00275-033 R2 14 R4 R1 DAC8420 Data Sheet For a single 5 V supply, VVREFHI is limited to at most 2.5 V, and must always be at least 2.5 V less than the positive supply to ensure linearity of the device. For these applications, the REF43 is an excellent low drift 2.5 V reference that consumes only 450 μA (max). It works well with the DAC8420 in a single 5 V system as shown in Figure 34. +5V SUPPLY REF43 2 VIN One opto-isolated line (LD) can be eliminated from this circuit by adding an inexpensive 4-bit TTL counter to generate the load pulse for the DAC8420 after 16 clock cycles. The counter is used to count the number of clock cycles loading serial data to the DAC8420. After all 16 bits have been clocked into the converter, the counter resets, and a load pulse is generated on Clock 17. In either circuit, the serial interface of the DAC8420 provides a simple, low cost method of isolating the digital control. +5V SUPPLY 0.1µF 4 GND VOUT 6 HIGH VOLTAGE ISOLATION 2.5V VREFHI 5V REG 0.1µF 1 5 5V POWER DAC8420 DAC A 7 VOUTA 5V DAC B 6 10kΩ VOUTB 3 VOUTD 10kΩ 14 15 16 9 8 4 GND VREFLO DIGITAL INPUTS GND 5V 10kΩ 0.1µF 5 1 VREFHI VDD 15 CLR 16 CLSEL 14 LD 0.1µF 7 VOUTA 6 VOUTB 3 VOUTC 2 VOUTD DAC8420 5V Figure 34. 5 V Single-Supply Operation Using REF43 10kΩ ISOLATED DIGITAL INTERFACE SDI Because the DAC8420 is ideal for generating accurate voltages in process control and industrial applications, due to noise, from the central controller; it can be necessary to isolate it from the central controller. This can be easily achieved by using optoisolators, which are commonly used to provide electrical isolation in excess of 3 kV. Figure 35 shows a simple 3-wire interface scheme for controlling the clock, data, and load pulse. For normal operation, CS is tied permanently low so that the DAC8420 is always selected. The resistor and capacitor on the CLR pin provide a power-on reset with 10 ms time constant. The three optoisolators are used for the SDI, CLK, and LD lines. Rev. C | Page 18 of 23 12 CS 11 CLK 10 SDI VREFLO VSS GND 4 8 9 00275-035 11 12 00275-034 SCLK 10 4 5V 5V 2 VIN 2.5V VOUTC DIGITAL CONTROLS DAC D REF43 2 VOUT 6 LD DAC C +5V Figure 35. Opto-lsolated 3-Wire Interface Data Sheet DAC8420 5V SUPPLY REF43 VINA 2 VIN 5V 5V SUPPLY 0.1µF 4 GND VOUT 6 2.5V 0.1µF 5 DAC8420 VREFHI 0.1µF 5V 3 1 604Ω CMP04 DAC A 7 VOUTA 5 C1 RED LED 2 OUT A 4 DAC B 6 DAC C 3 DIGITAL CONTROLS DAC D 2 5V VOUTB 7 C2 1 C3 14 C4 13 604Ω 6 VOUTC 9 RED LED OUT B 8 VOUTD 11 11 12 14 15 16 9 4 GND 10 8 VREFLO VSS 12 DIGITAL INPUTS 00275-036 10 VINB Figure 36. Dual Programmable Window Comparator Often a comparator is needed to signal an out-of-range warning. Combining the DAC8420 with a quad comparator such as the CMP04 provides a simple dual window comparator with adjustable trip points as shown in Figure 36. This circuit can be operated with either a dual supply or a single supply. For the A input channel, DAC B sets the low trip point, and DAC A sets the upper trip point. The CMP04 has open-collector outputs that are connected together in a wire-OR’ed configuration to generate an out-ofrange signal. For example, when VINA goes below the trip point set by DAC B, Comparator C2 pulls the output down, turning on the red LED. The output can also be used as a logic signal for further processing. MC68HC11 MICROCONTROLLER INTERFACING Figure 37 shows a serial interface between the DAC8420 and the MC68HC11 8-bit microcontroller. The SCK output of the port outputs the serial data to load into the SDI input of the DAC. The port lines (PD5, PC0, PC1, and PC2) provide the controls to the DAC as shown. PC2 CLSEL PC1 CLR PC0 CS DAC8420* MC68HC11* (PD5) SS LD SCK CLK MOSI SDI 00275-037 DUAL WINDOW COMPARATOR *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 37. MC68HC11 Microcontroller Interface For correct operation, the MC68HC11 must be configured such that the CPOL bit and CPHA bit are both set to 1. In this configuration, serial data on MOSI of the MC68HC11 is valid on the rising edge of the clock, which is the required timing for the DAC8420. Data is transmitted in 8-bit bytes (MSB first), with only eight rising clock edges occurring in the transmit cycle. To load data to the input register of the DAC8420, PC0 is taken low and held low during the entire loading cycle. The first eight bits are shifted in address first, immediately followed by another eight bits in the second least-significant byte to load the complete 16bit word. At the end of the second byte load, PC0 is then taken high. To prevent an additional advancing of the internal shift register, SCK must already be asserted before PC0 is taken high. To transfer the contents of the input shift register to the DAC register, PD5 is then taken low, asserting the LD input of the DAC and completing the loading process. PD5 must return high before the next load cycle begins. The CLR input of the DAC8420 (controlled by the output PC1) provides an asynchronous clear function. Rev. C | Page 19 of 23 DAC8420 Data Sheet DAC8420 TO M68HC11 INTERFACE ASSEMBLY PROGRAM * M68HC11 Register Definitions PORTC EQU $1003 Port C control register * “0,0,0,0;0,CLSEL,CLR,CS” DDRC EQU $1007 Port C data direction PORTD EQU $1008 Port D data register * “0,0,LD,SCLK;SDI,0,0,0” DDRD EQU $1009 Port D data direction SPCR EQU $1028 SPI control register * “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0” SPSR EQU $1029 SPI status register * “SPIF,WCOL,0,MODF;0,0,0,0” SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex) * To select: DAC A – Set SDI1 to $0X DAC B – Set SDI1 to $4X DAC C – Set SDI1 to $8X DAC D – Set SDI1 to $CX SDI2 is encoded from 00 (Hex) to FF (Hex) * DAC requires two 8-bit loads – Address + 12 bits SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8” SDI2 EQU $01 SDI packed byte 2 “DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0” * Main Program ORG $C000 Start of user’s RAM in EVB INIT LDS #$CFFF Top of C page RAM * Initialize Port C Outputs LDAA #$07 0,0,0,0;0,1,1,1 * CLSEL-Hi, CLR-Hi, CS-Hi * To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03) * To reset DAC to MID-SCALE, set CLSEL-Hi ($07) STAA PORTC Initialize Port C Outputs LDAA #$07 0,0,0,0;0,1,1,1 STAA DDRC CLSEL, CLR, and CS are now enabled as outputs * Initialize Port D Outputs LDAA #$30 0,0,1,1;0,0,0,0 * LD-Hi,SCLK-Hi,SDI-Lo STAA PORTD Initialize Port D Outputs LDAA #$38 0,0,1,1;1,0,0,0 STAA DDRD LD,SCLK, and SDI are now enabled as outputs * Initialize SPI Interface LDAA #$5F STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32 * Call update subroutine BSR UPDATE Xfer 2 8-bit words to DAC-8420 JMP $E000 Restart BUFFALO * Subroutine UPDATE UPDATE PSHX Save registers X, Y, and A PSHY PSHA * Enter Contents of SDI1 Data Register (DAC# and 4 MSBs) LDAA #$80 1,0,0,0;0,0,0,0 STAA SDI1 SDI1 is set to 80 (Hex) * Enter Contents of SDI2 Data Register LDAA #$00 0,0,0,0;0,0,0,0 STAA SDI2 SDI2 is set to 00 (Hex) LDX #SDI1 Stack pointer at 1st byte to send via SDI LDY #$1000 Stack pointer at on-chip registers * Clear DAC output to zero BCLR PORTC,Y $02 Assert CLR BSET PORTC,Y $02 Deassert CLR * Get DAC ready for data input BCLR PORTC,Y $01 Assert CS TFRLP LDAA 0,X Get a byte to transfer via SPI STAA SPDR Write SDI data reg to start xfer WAIT LDAA SPSR Loop to wait for SPIF BPL WAIT SPIF is the MSB of SPSR * (when SPIF is set, SPSR is negated) INX Increment counter to next byte for xfer CPX #SDI2+ 1 Are we done yet ? BNE TFRLP If not, xfer the second byte * Update DAC output with contents of DAC register BCLR PORTD,Y 520 Assert LD BSET PORTD,Y $20 Latch DAC register BSET PORTC,Y $01 De-assert CS PULA When done, restore registers X, Y & A PULY PULX RTS ** Return to Main Program ** Rev. C | Page 20 of 23 Data Sheet DAC8420 OUTLINE DIMENSIONS 0.775 0.755 0.735 9 PIN 1 INDICATOR 0.280 0.250 0.240 1 8 TOP VIEW 0.100 BSC 0.210 MAX 0.325 0.310 0.300 0.195 0.130 0.115 SIDE VIEW 0.015 MIN 0.150 0.130 0.115 0.022 0.018 0.015 0.015 GAUGE PLANE END VIEW SEATING PLANE 0.021 0.016 0.011 0.070 0.045 0.060 0.039 0.055 0.030 0.430 MAX 0.012 0.010 0.008 03-07-2014-D 16 COMPLIANT TO JEDEC STANDARDS MS-001-BB Figure 38. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-16) Dimensions shown in inches 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45° 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 39. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. C | Page 21 of 23 1.27 (0.0500) 0.40 (0.0157) 032707-B 1 DAC8420 Data Sheet 0.005 (0.13) MIN 0.098 (2.49) MAX 16 9 1 PIN 1 0.310 (7.87) 0.220 (5.59) 8 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 40. 16-Lead Ceramic Dual In-Line Package [CERDIP] (Q-16) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model 1 DAC8420EPZ DAC8420ES DAC8420ESZ DAC8420ESZ-REEL DAC8420FPZ DAC8420FQ DAC8420FS DAC8420FSZ DAC8420FSZ-REEL 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] Z = RoHS Compliant Part. INL measured at VDD = +15 V and VSS = −15 V. Rev. C | Page 22 of 23 Package Option N-16 RW-16 RW-16 RW-16 N-16 Q-16 RW-16 RW-16 RW-16 INL 2 (±LSB) 0.5 0.5 0.5 0.5 1.0 1.0 1.0 1.0 1.0 Data Sheet DAC8420 NOTES ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00275-0-9/16(C) Rev. C | Page 23 of 23