DAC8562EP

a +5 Volt, Parallel Input Complete 12-Bit DAC DAC8562 FEATURES Complete 12-Bit DAC No External Components Single +5 Volt Operation 1 mV/Bit with 4.095 V Full Scale True Voltage Output, 65 mA Drive Very Low Power –3 mW FUNCTIONAL BLOCK DIAGRAM DAC-8562 Included on the chip, in addition to the DAC, is a rail-to-rail amplifier, latch and reference. The reference (REFOUT) is trimmed to 2.5 volts, and the on-chip amplifier gains up the DAC output to 4.095 volts full scale. The user needs only supply a +5 volt supply. The DAC8562 is coded straight binary. The op amp output swings from 0 to +4.095 volts for a one millivolt per bit resolution, and is capable of driving ± 5 mA. Built using low temperature-coefficient silicon-chrome thin-film resistors, excellent linearity error over temperature has been achieved as shown below in the linearity error versus digital input code plot. Digital interface is parallel and high speed to interface to the fastest processors without wait states. The interface is very simple requiring only a single CE signal. An asynchronous CLR input sets the output to zero scale. VOUT 12 AGND DAC REGISTER 12 DGND CE DATA CLR The DAC8562 is available in two different 20-pin packages, plastic DIP and SOL-20. Each part is fully specified for operation over –40°C to +85°C, and the full +5 V ± 5% power supply range. For MIL-STD-883 applications, contact your local ADI sales office for the DAC8562/883 data sheet which specifies operation over the –55°C to +125°C temperature range. 1 VDD = +5V 0.75 LINEARITY ERROR — LSB The DAC8562 is a complete, parallel input, 12-bit, voltage output DAC designed to operate from a single +5 volt supply. Built using a CBCMOS process, these monolithic DACs offer the user low cost, and ease-of-use in +5 volt only systems. 12-BIT DAC REF APPLICATIONS Digitally Controlled Calibration Servo Controls Process Control Equipment PC Peripherals GENERAL DESCRIPTION VDD REFOUT TA = –55°C, +25°C, +125°C 0.5 –55°C 0.25 0 –0.25 –0.5 +25°C & +125°C –0.75 –1 0 1024 2048 3072 DIGITAL INPUT CODE — Decimal 4096 Figure 1. Linearity Error vs. Digital Input Code Plot REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 DAC8562* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Design Resources View a parametric search of comparable parts • • • • Documentation Data Sheet • DAC8562: 5 Volt, Parallel Input Complete 12-Bit DAC Data Sheet Reference Materials Solutions Bulletins & Brochures • Digital to Analog Converters ICs Solutions Bulletin DAC8562 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all DAC8562 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. DAC8562–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ VDD = +5.0 6 5%, RS = No Load, –408C ≤ TA ≤ +858C, unless otherwise noted) Parameter Symbol Condition Min STATIC PERFORMANCE Resolution Relative Accuracy N INL Differential Nonlinearity Zero-Scale Error Full-Scale Voltage DNL VZSE VFS 12 –1/2 –1 –1 TCVFS Note 2 E Grade F Grade No Missing Codes Data = 000H Data - FFFH3 E Grade F Grade Notes 3, 4 ANALOG OUTPUT Output Current Load Regulation at Half Scale Capacitive Load IOUT LDREG CL Data = 800H RL = 402 Ω to ∞, Data = 800H No Oscillation4 REFERENCE OUTPUT Output Voltage Output Source Current Line Rejection Load Regulation VREF IREF LNREJ LDREG LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance VIL VIH IIL CIL INTERFACE TIMING SPECIFICATIONS1, 4 Chip Enable Pulse Width Data Setup Data Hold Clear Pulse Width tCEW tDS tDH tCLRW Full-Scale Tempco AC CHARACTERISTICS4 Voltage Output Settling Time6 Digital Feedthrough SUPPLY CHARACTERISTICS Positive Supply Current Note 5 Typ Max Units ± 1/4 ± 3/4 ± 3/4 +1/2 +1/2 +1 +1 +3 Bits LSB LSB LSB LSB 4.087 4.079 4.095 4.095 ± 16 4.103 4.111 ±5 ±7 1 500 2.484 5 2.500 7 0.8 2.4 10 10 Note 4 30 30 10 20 16 35 IDD VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5 V VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5V ∆VDD = ± 5% 3 0.6 15 3 0.002 Power Supply Sensitivity PSS mA LSB pF V mA %/V %/mA V V µA pF ns ns ns ns To ± 1 LSB of Final Value PDISS 2.516 0.08 0.1 IREF = 0 to 5 mA tS Power Dissipation 3 V V ppm/°C µs nV sec 6 1 30 5 0.004 mA mA mW mW %/% NOTES 1 All input control signals are specified with t r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 1 LSB = 1 mV for 0 to +4.095 V output range. 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground. 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice. –2– REV. A DAC8562 (@ VDD = +5.0 V 6 5%, RL = No Load, TA = +258C, applies to part number DAC8562GBC only, WAFER TEST LIMITS unless otherwise noted) Parameter Symbol Condition STATIC PERFORMANCE Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Voltage Reference Output Voltage INL DNL VZSE VFS VREF No Missing Codes Data = 000H Data = FFFH LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current VIL VIH IIL SUPPLY CHARACTERISTICS Positive Supply Current IDD Power Dissipation PDISS Power Supply Sensitivity PSS Min Typ Max Units –1 –1 ± 3/4 ± 3/4 +1/2 4.095 2.500 +1 +1 +3 4.105 2.510 LSB LSB LSB V V 0.8 10 V V µA 6 1 30 5 0.004 mA mA mW mW %/% 4.085 2.490 2.4 VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5 V VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5 V ∆VDD = ± 5% 3 0.6 15 3 0.002 NOTE 1 Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. ABSOLUTE MAXIMUM RATINGS* tCEW 1 VDD to DGND and AGND . . . . . . . . . . . . . . . . –0.3 V, +10 V Logic Inputs to DGND . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VREFOUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . . (TJ max – TA)/uJA Thermal Resistance uJA 20-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 74°C/W 20-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 89°C/W Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C CE 0 tDS tDH 1 DB11–0 DATA VALID 0 tCLRW 1 CLR 0 FS ±1 LSB ERROR BAND VOUT ZS tS tS Figure 2. Timing Diagram Table I. Control Logic Truth Table *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CE CLR DAC Register Function H L ↑+ X H H H H L ↑+ Latched Transparent Latched with New Data Loaded with All Zeros Latched All Zeros ↑ + Positive Logic Transition; X Don't Care. CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted. REV. A –3– WARNING! ESD SENSITIVE DEVICE DAC8562 Table II. Nominal Output Voltage vs. Input Code PIN CONFIGURATIONS 20-Pin P-DIP (N-20) SOL-20 (R-20) 1 DB3 1 20 VDD DB4 2 19 DB5 3 18 DB1 DAC-8562 DB6 4 17 DB0 TOP VIEW (Not to Scale) DB7 5 DAC-8562 16 CE DB8 6 TOP VIEW (Not to Scale) 15 CLR DB9 7 14 REFOUT DB2 DB10 8 13 VOUT DB11 9 12 AGND DGND 10 11 NC Binary Hex Decimal Output (V) 0000 0000 0000 0000 0000 0001 0000 0000 0010 0000 0000 1111 0000 0001 0000 0000 1111 1111 0001 0000 0000 0001 1111 1111 0010 0000 0000 0011 1111 1111 0100 0000 0000 0111 1111 1111 1000 0000 0000 1100 0000 0000 1111 1111 1111 000 001 002 00F 010 0FF 100 1FF 200 3FF 400 7FF 800 C00 FFF 0 1 2 15 16 255 256 511 512 1023 1024 2047 2048 3072 4095 0.000 Zero Scale 0.001 0.002 0.015 0.016 0.255 0.256 0.511 0.512 1.023 1.024 2.047 2.048 Half Scale 3.072 4.095 Full Scale NC = NO CONNECT PIN DESCRIPTIONS ORDERING GUIDE Model INL (LSB) Temperature Range Package Option DAC8562EP DAC8562FP DAC8562FS DAC8562GBC ± 1/2 ±1 ±1 ±1 –40°C to +85°C –40°C to +85°C –40°C to +85°C +25°C N-20 N-20 R-20 Dice Pin Name Description 20 VDD 1-9 17-19 16 15 DB0-DB11 8 12 DGND AGND 13 VOUT 14 REFOUT 11 NC Positive supply. Nominal value +5 volts, ± 5%. Twelve Binary Data Bit inputs. DB11 is the MSB and DB0 is the LSB. Chip Enable. Active low input. Active low digital input that clears the DAC register to zero, setting the DAC to minimum scale. Digital ground for input logic. Analog Ground. Ground reference for the internal bandgap reference voltage, the DAC, and the output buffer. Voltage output from the DAC. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature and power supply variations. Nominal 2.5 V reference output voltage. This node must be buffered if required to drive external loads. No Connection. Leave pin floating. CE CLR DICE CHARACTERISTICS VOUT REFOUT DGND DB11 12 10 9 8 13 DB10 14 CLR 15 CE 16 DB0 17 DB1 AGND 7 DB9 6 DB8 5 DB7 4 DB6 3 18 19 20 1 2 DB2 VDD DB3 DB4 DB5 SUBSTRATE IS COMMON WITH VDD. TRANSISTOR COUNT: 524 DIE SIZE: 0.70 X 0.105 INCH; 7350 SQ MILS –4– REV. A DAC8562 current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the –5% supply tolerance value of 4.75 volts. OPERATION The DAC8562 is a complete ready to use 12-bit digital-toanalog converter. Only one +5 V power supply is necessary for operation. It contains a voltage-switched, 12-bit, laser-trimmed digital-to-analog converter, a curvature-corrected bandgap reference, a rail-to-rail output op amp, and a DAC register. The parallel data interface consists of 12 data bits, DB0–DB11, and a active low CE strobe. In addition, an asynchronous CLR pin will set all DAC register bits to zero causing the VOUT to become zero volts. This function is useful for power on reset or system failure recovery to a known state. VDD P-CH VOUT N-CH D/A CONVERTER SECTION The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 volt internal bandgap voltage. It uses a laser trimmed R-2R ladder which is switched by N channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input code. The DAC output (not available to the user) is internally connected to the rail-to-rail output op amp. AGND Figure 4. Equivalent Analog Output Circuit Figures 5 and 6 in the typical performance characteristics section provide information on output swing performance near ground and full scale as a function of load. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability. AMPLIFIER SECTION The internal DAC’s output is buffered by a low power consumption precision amplifier. This low power amplifier contains a differential PNP pair input stage which provides low offset voltage and low noise, as well as the ability to amplify the zeroscale DAC output voltages. The rail-to-rail amplifier is configured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an equivalent circuit schematic of the analog section. REFOUT 2.5V VOLTAGE SWITCHED 12-BIT R-2R D/A CONVERTER BANDGAP REFERENCE REFERENCE SECTION The internal 2.5 V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is available at the REFOUT pin. Since REFOUT is not intended to drive external loads, it must be buffered–refer to the applications section for more information. The equivalent emitter follower output circuit of the REFOUT pin is shown in Figure 3. Bypassing the REFOUT pin is not required for proper operation. Figure 7 shows broadband noise performance. RAIL-TO-RAIL OUTPUT AMPLIFIER 2R POWER SUPPLY R The very low power consumption of the DAC8562 is a direct result of a circuit design optimizing use of the CBCMOS process. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors, good analog accuracy is achieved. VOUT BUFFER R2 2R R1 R 2R SPDT N ch FET SWITCHES AV = 4.096/2.5 = 1.636V/V For power-consumption sensitive applications it is important to note that the internal power consumption of the DAC8562 is strongly dependent on the actual logic-input voltage-levels present on the DB0–DB11, CE and CLR pins. Since these inputs are standard CMOS logic structures, they contribute static power dissipation dependent on the actual driving logic VOH and VOL voltage levels. The graph in Figure 9 shows the effect on total DAC8562 supply current as a function of the actual value of input logic voltage. Consequently for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A VINL = 0 V on the DB0–DB11 pins provides the lowest standby dissipation of 600 µA with a +5 V power supply. 2R 2R Figure 3. Equivalent DAC8562 Schematic of Analog Portion The op amp has a 16 µs typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals versus positive. See the oscilloscope photos in the Typical Performances section of this data sheet. OUTPUT SECTION The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 4 shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull down FETs that will pull an output load directly to GND. The output sourcing REV. A –5– DAC8562 As with any analog system, it is recommended that the DAC8562 power supply be bypassed on the same PC card that contains the chip. Figure 10 shows the power supply rejection versus frequency performance. This should be taken into account when using higher frequency switched-mode power supplies with ripple frequencies of 100 kHz and higher. TIMING AND CONTROL The DAC8562 has a 12-bit DAC register that simplifies interface to a 12-bit (or wider) data bus. The latch is controlled by the Chip Enable (CE) input. If the application does not involve a data bus, wiring CE low allows direct operation of the DAC. The data latch is level triggered and acquires data from the data bus during the time period when CE is low. When CE goes high, the data is latched into the register and held until CE returns low. The minimum time required for the data to be present on the bus before CE returns high is called the data setup time (tDS) as seen in Figure 2. The data hold time (tDH) is the amount of time that the data has to remain on the bus after CE goes high. The high speed timing offered by the DAC8562 provides for direct interface with no wait states in all but the fastest microprocessors. One advantage of the rail-to-rail output amplifier used in the DAC8562 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from +4.75 V to +5.25 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the DAC8562 is possible down to +4.3 volts. The minimum operating supply voltage versus load current plot, in Figure 11, provides information for operation below VDD = +4.75 V. Typical Performance Characteristics 5 100 RL R TIED TO TO AGND AGND L TIED DATA D = FFFH = FFFH 3 2 1 RL TIED TO +5V DATA = 000H 0 10 100 1k 10k LOAD RESISTANCE – Ω 100k TA = +85°C TA = +25°C 0.1 0.01 1 10 100 OUTPUT SINK CURRENT – µA 10 0% TA = 25°C NBW = 630kHz DATA = 800H RL TIED TO +2V 0 –20 –40 –60 –100 1000 Figure 6. Pull-Down Voltage vs. Output Sink Current Capability NEG CURRENT LIMIT 1 2 3 OUTPUT VOLTAGE – Volts Figure 7. IOUT vs. VOUT 5 100 90 20 –80 100 1ms 50mV 40 TA = –40°C POWER SUPPLY REJECTION – dB OUTPUT NOISE VOLTAGE – 500µV/DIV Figure 5. Output Swing vs. Load 10 1 POS0 CURRENT0 LIMIT0 60 OUTPUT CURRENT – mA OUTPUT PULLDOWN VOLTAGE – mV 4 80 VDD = +5V DATA = 000H SUPPLY CURRENT – mA OUTPUT VOLTAGE – Volts VDD = +5V TA = +25°C VDD = +5V 4 TA = +25°C 3 2 1 VDD = +5V ±200mV AC TA = +25°C DATA = FFFH 80 60 40 20 TIME = 1ms/DIV 0 Figure 8. Broadband Noise 0 1 2 3 4 LOGIC VOLTAGE VALUE – Volts 5 Figure 9. Supply Current vs. Logic Input Voltage –6– 0 10 100 1k 10k FREQUENCY – Hz 100k Figure 10. Power Supply Rejection vs. Frequency REV. A DAC8562 5.0 0 5 100 0 OUTPUT DATA = 204810 TO 204710 2.048 PROPER OPERATION WHEN VDD SUPPLY VOLTAGE ABOVE CURVE 4.4 90 VDD = +5V 4 4.6 VOUT – Volts VDD MIN – Volts CE ∆VFS ≤ 1 LSB DATA = FFFH TA = +25°C 4.8 5V INPUT 5 4.2 2.038 TA = +25°C 3 2 1 10 0% 2.028 0 20µs 1V 2.018 TIME = 20µs/DIV 4.0 0.01 0.04 0.1 1.0 0.4 4.0 OUTPUT LOAD CURRENT – mA TIME – 200ns/DIV 10 Figure 11. Minimum Supply Voltage vs. Load Figure 12. Midscale Transition Performance Figure 13. Large Signal Settling Time 16µs 5 0 OUTPUT VOLTAGE 1mV/DIV 0 VDD = +5V TA = +25°C VDD = +5V 1.5 LINEARITY ERROR – LSB DATA 5 OUTPUT VOLTAGE 1mV/DIV DATA 2.0 VDD = +5V TA = +25°C 16µs TA = –40°C, 25°C, +85°C 1.0 –40°C 0.5 0.0 –0.5 +25°C & +85°C –1.0 –1.5 –2.0 TIME – 10µs/DIV TIME – 10µs/DIV 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL INPUT CODE – Decimal Figure 14. Output Voltage Rise Time Detail 30 20 10 0 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 TOTAL UNADJUSTED ERROR – LSB Figure 17. Total Unadjusted Error Histogram REV. A 4.115 3 VDD = +5V NO LOAD SS = 300 PCS DATA = 000H NO LOAD VDD = +5.0V 2 ZERO-SCALE – mV NUMBER OF UNITS 40 4.125 TUE = Σ INL+ZS+FS SS = 300 UNITS TA = +25°C FULL-SCALE OUTPUT –Volts 50 Figure 16. Linearity Error vs. Digital Code Figure 15. Output Voltage Fall Time Detail AVG +1σ 4.105 AVG 4.095 AVG –1σ 1 0 4.085 4.075 –50 –25 0 25 50 75 100 TEMPERATURE – °C Figure 18. Full-Scale Voltage vs. Temperature –7– 125 –1 –50 –25 0 25 50 75 TEMPERATURE – °C 100 125 Figure 19. Zero-Scale Voltage vs. Temperature DAC8562 DAC8562–Typical Performance Characteristics 8 5 VDD = +5V TA = 25°C DATA = FFFH 1 0.1 VDD = +5V DATA = FFF 4 READINGS NORMALIZED TO ZERO HOUR TIME POINT 2 1 0 RANGE –1 AVG –2 –3 1k 10k 100 FREQUENCY – Hz VDD = +5.0V 4 VDD = +5.25V 3 2 135 UNITS TESTED 200 400 600 800 1000 HOURS OF OPERATION AT +125°C 0 Figure 20. Output Voltage Noise Density vs. Frequency 5 VDD = +4.75V 0 –50 –5 100k 6 1 –4 0.01 10 VDATA = +2.4V NO LOAD 7 H 3 SUPPLY CURRENT – mA OUTPUT VOLTAGE CHANGE – mV OUTPUT NOISE DENSITY – µV/ Hz 10 1200 Figure 21. Long-Term Drift Accelerated by Burn-In –25 0 25 50 75 TEMPERATURE – °C 100 125 Figure 22. Supply Current vs. Temperature 10 A4 0.040 V 100 90 13.82 µs 1 8 AVG +1σ CE = HIGH 100 0 6 90 TA = +25°C RL = ∞ VDD VOUT 5mV/DIV 0V VREF 0V DLY VREF OUT ERROR –mV DATA 2V 10 10 0% 0% 5mV 5V 1µs 2V Bw L X 2 0 AVG –1σ –2 –4 –6 5µs –8 TIME = 20µs/DIV TIME = 1µs/DIV 4 VDD = +5V SAMPLE SIZE = 300 –10 –50 –25 0 25 50 75 100 125 TEMPERATURE – °C Figure 23. Reference Startup vs. Time Figure 24. Digital Feedthrough vs. Time 0.004 0.003 0.10 REF LINE REGULATION – %/Volt REF LOAD REGULATION – %/mA 0.005 AVG + 3 σ AVG AVG – 3σ 0.002 0.001 0.000 –50 Figure 25. Reference Error vs. Temperature VDD = +5V ∆ IL = 5mA SAMPLE SIZE = 302 PCS –25 25 50 75 0 TEMPERATURE – °C 100 0.06 AVG + 3 σ AVG 0.04 AVG – 3 σ 0.02 0.00 –50 125 VDD = +4.75 TO +5.25V SAMPLE SIZE = 302 PCS 0.08 –25 0 25 50 75 100 125 TEMPERATURE – °C Figure 26. Reference Load Regulation vs. Temperature Figure 27. Reference Line Regulation vs. Temperature –8– REV. A DAC8562 APPLICATIONS SECTION Power Supplies, Bypassing, and Grounding The DAC8562 includes two ground connections in order to minimize system accuracy degradation arising from grounding errors. The two ground pins are designated DGND (Pin 10) and AGND (Pin 12). The DGND pin is the return for the digital circuit sections of the DAC and serves as their input threshold reference point. Thus DGND should be connected to the same ground as the circuitry that drives the digital inputs. All precision converter products require careful application of good grounding practices to maintain full-rated performance. Because the DAC8562 has been designed for +5 V applications, it is ideal for those applications under microprocessor or microcomputer control. In these applications, digital noise is prevalent; therefore, special care must be taken to assure that its inherent precision is maintained. This means that particularly good engineering judgment should be exercised when addressing the power supply, grounding, and bypassing issues using the DAC8562. Pin 12, AGND, serves as the supply rail for the internal voltage reference and the output amplifier. This pin should also serve as the reference point for all analog circuitry associated with the DAC8562. Therefore, to minimize any errors, it is recommended that the AGND connection of the DAC8562 be connected to a high quality analog ground. If the system contains any analog signal path carrying a significant amount of current, then that path should have its own return connection to Pin 12. The power supply used for the DAC8562 should be well filtered and regulated. The device has been completely characterized for a +5 V supply with a tolerance of ± 5%. Since a +5 V logic supply is almost universally available, it is not recommended to connect the DAC directly to an unfiltered logic supply without careful filtering. Because it is convenient, a designer might be inclined to tap a logic circuit s supply for the DAC’s supply. Unfortunately, this is not wise because fast logic with nanosecond transition edges induces high current pulses. The high transient current pulses can generate glitches hundreds of millivolts in amplitude due to wiring resistances and inductances. This high frequency noise will corrupt the analog circuits internal to the DAC and cause errors. Even though their spike noise is lower in amplitude, directly tapping the output of a +5 V system supplies can cause errors because these supplies are of the switching regulator type that can and do generate a great deal of high frequency noise. Therefore, the DAC and any associated analog circuitry should be powered directly from the system power supply outputs using appropriate filtering. Figure 28 illustrates how a clean, analog-grade supply can be generated from a +5 V logic supply using a differential LC filter with separate power supply and return lines. With the values shown, this filter can easily handle 100 mA of load current without saturating the ferrite cores. Higher current capacity can be achieved with larger ferrite cores. For lowest noise, all electrolytic capacitors should be low ESR (Equivalent Series Resistance) type. FERRITE BEADS: 2 TURNS, FAIR-RITE #2677006301 TTL/CMOS LOGIC CIRCUITS 100µF ELECT. It is often advisable to maintain separate analog and digital grounds throughout a complete system, tying them common to one place only. If the common tie point is remote and an accidental disconnection of that one common tie point were to occur due to card removal with power on, a large differential voltage between the two commons could develop. To protect devices that interface to both digital and analog parts of the system, such as the DAC8562, it is recommended that the common ground tie points be provided at each such device. If only one system ground can be connected directly to the DAC8562, it recommended that the analog common be used. If the system’s AGND has suitably low impedance, then the digital signal currents flowing in it should not seriously affect the ground noise. The amount of digital noise introduced by connecting the two grounds together at the device will not adversely affect system performance due to loss of digital noise immunity. Generous bypassing of the DAC’s supply goes a long way in reducing supply line-induced errors. Local supply bypassing consisting of a 10 µF tantalum electrolytic in parallel with a 0.1 µF ceramic is recommended. The decoupling capacitors should be connected between the DAC’s supply pin (Pin 20) and the analog ground (Pin 12). Figure 29 shows how the DGND, AGND, and bypass connections should be made to the DAC8562. +5V +5V 10-22µF TANT. 20 VDD 0.1µF CER. 10µF DATA DAC-8562 +5V RETURN +5V POWER SUPPLY CE 16 CLR 15 13 AGND 12 0.1µF VOUT TO OTHER ANALOG CIRCUITS DGND 10 Figure 28. Properly Filtering a +5 V Logic Supply Can Yield a High Quality Analog Supply TO POWER GROUND Figure 29. Recommended Grounding and Bypassing Scheme for the DAC-8562 REV. A –9– DAC8562 +12V OR +15V 0.1µF Unipolar Output Operation This is the basic mode of operation for the DAC8562. As shown in Figure 30, the DAC8562 has been designed to drive loads as low as 820 Ω in parallel with 500 pF. The code table for this operation is shown in Table III. 2 REF-02 6 0.1µF 4 +5V 10µF 1 0.1µF DATA DAC-8562 20 VDD DATA 16 CLR 15 16 CLR 15 13 DGND 10 0V ≤ VOUT ≤ 4.095V DAC-8562 CE CE VOUT AGND 12 13 820 Ω DGND 10 500pF AGND 12 Figure 31. Operating the DAC8562 on +12 V or +15 V Supplies Using a REF02 Voltage Reference Measuring Offset Error One of the most commonly specified endpoint errors associated with real-world nonideal DACs is offset error. Figure 30. Unipolar Output Operation In most DAC testing, the offset error is measured by applying the zero-scale code and measuring the output deviation from 0 volt. There are some DACs where offset errors may be present but not observable at the zero scale because of other circuit limitations (for example, zero coinciding with single supply ground). In these DACs, nonzero output at zero code cannot be read as the offset error. In the DAC8562, for example, the zero-scale error is specified to be +3 LSBs. Since zero scale coincides with zero volt, it is not possible to measure negative offset error. Table III. Unipolar Code Table Hexadecimal Number in DAC Register Decimal Number in DAC Register Analog Output Voltage (V) FFF 801 800 7FF 000 4095 2049 2048 2047 0 +4.095 +2.049 +2.048 +2.047 0 Operating the DAC8562 on +12 V or +15 V Supplies Only Although the DAC8562 has been specified to operate on a single, +5 V supply, a single +5 V supply may not be available in many applications. Since the DAC8562 consumes no more than 6 mA, maximum, then an integrated voltage reference, such as the REF02, can be used as the DAC8562 +5 V supply. The configuration of the circuit is shown in Figure 31. Notice that the reference’s output voltage requires no trimming because of the REF02’s excellent load regulation and tight initial output voltage tolerance. Although the maximum supply current of the DAC8562 is 6 mA, local bypassing of the REF02’s output with at least 0. 1 µF at the DAC’s voltage supply pin is recommended to prevent the DAC’s internal digital circuits from affecting the DAC’s internal voltage reference. By adding a pull-down resistor from the output of the DAC8562 to a negative supply as shown in Figure 32, offset errors can now be read at zero code. This configuration forces the output P-channel MOSFET to source current to the negative supply thereby allowing the designer to determine in which direction the offset error appears. The value of the resistor should be such that, at zero code, current through the resistor is 200 µA maximum. +5V 0.1µF 20 VDD DATA DAC-8562 CE VOUT 13 16 200µA MAX CLR 15 DGND 10 AGND 12 V– Figure 32. Measuring Zero-Scale or Offset Error –10– REV. A DAC8562 +5V 0.1µF 20 +5V P2 500 Ω R1 10kΩ VDD DATA VOUT 13 8 2 16 A1 R3 247k Ω R2 12.7k DAC-8562 CE FULL SCALE ADJUST R4 23.7k Ω 10µF 3 1 –5V ≤ VO ≤ +5V 4 REFOUT 14 CLR 15 DGND 10 AGND 12 R6 10k Ω –2.5V –5V P1 10k Ω ZERO SCALE ADJUST R5 10k Ω 6 A2 A1, A2 = 1/2 OP-295 7 5 Figure 33. Bipolar Output Operation  R4   R2  VO = 1 mV × Digital Code ×   × 1 +   R3 + R4   R1  Bipolar Output Operation Although the DAC8562 has been designed for single supply operation, bipolar operation is achievable using the circuit illustrated in Figure 33. The circuit uses a single supply, rail-to-rail OP295 op amp and the DAC’s internal +2.5 V reference to generate the –2.5 V reference required to level-shift the DAC output voltage. The circuit has been configured to provide an output voltage in the range –5 V ≤ VOUT ≤ +5 V and is coded in complementary offset binary. Although each DAC LSB corresponds to 1 mV, each output LSB has been scaled to 2.44 mV. Table IV provides the relationship between the digital codes and output voltage. The transfer function of the circuit is given by:  R4   R4  VO = −1 mV × Digital Code ×   + 2.5 ×   R1   R2    R2  – REFOUT ×    R1  For the ± 2 5 V output range and the circuit values shown in the table, the transfer equation becomes: VO = 1.22 mV × Digital Code – 2.5 V Similarly, for the ± 5 V output range, the transfer equation becomes: VO = 2.44 mV × Digital Code – 5 V Note that, for ± 5 V output voltage operation, R5 is required as a pull-down for REFOUT. Or, REFOUT can be buffered by an op amp configured as a follower that can source and sink current. and, for the circuit values shown, becomes: VO = –2.44 mV × Digital Code + 5 V Table IV. Bipolar Code Table +5V 0.1µF Hexadecimal Number in DAC Register Decimal Number in DAC Register Analog Output Voltage (V) FFF 801 800 7FF 000 4095 2049 2048 2047 0 –4 9976 –2.44E–3 0 +2.44E–3 +5 R2 20 VDD For applications that do not require high accuracy, the circuit illustrated in Figure 34 can also be used to generate a bipolar output voltage. In this circuit, only one op amp is used and no potentiometers are used for offset and gain trim The output voltage is coded in offset binary and is given by: –11– CE 16 CLR 15 +5V R5 4.99k Ω DAC-8562 To maintain monotonicity and accuracy, R1, R2, R4, R5, and R6 should be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient matching. Mismatching between R1 and R2 causes offset and gain errors while an R4 to R1 and R2 mismatch yields gain errors. REV. A R1 REFOUT 14 DATA 8 2 A1 3 R3 1 VO 4 VOUT 13 DGND 10 AGND R4 12 –5V A1 = 1/2 OP-295 VOUT RANGE ±2.5V ±5V R1 10k 10k R2 10k 20k R3 10k 10k R4 15.4k + 274 43.2k + 499 Figure 34. Bipolar Output Operation Without Trim Version 1 DAC8562 Alternatively, the output voltage can be coded in complementary offset binary using the circuit in Figure 35. This configuration eliminates the need for a pull-down resistor or an op amp for REFOUT The transfer equation of the circuit is given by:  R2  VO = –1 mV × Digital Code ×   + REFOUT  R1  audio mixing consoles, music synthesizers, and other audio processors, VCAs, such as the SSM2018, adjust audio channel gain and attenuation from front panel potentiometers. The VCA provides a clean gain transition control of the audio level when the slew rate of the analog input control voltage, VC, is properly chosen. The circuit in Figure 37 illustrates a volume control application using the DAC8562 to control the attenuation of the SSM2018.  R4   R2  ×  × 1 +   R3 + R4   R1  +15V 10M Ω P1 100kΩ OFFSET TRIM and, for the values shown, becomes: P2 500kΩ SYMMETRY TRIM 470k Ω 10pF –15V VO = −2.44 mV × Digital Code + 5 V 18kΩ VOUT R2 R1 +15V VOUT 0.1µF DAC-8562 VO VIN REFOUT R1 = R3 = 10kΩ R4 +15V 16 2 15 3 14 4 13 SSM-2018 5 18kΩ R3 1 0.1µF 30k Ω 12 6 11 7 10 8 9 +15V –15V 0.1µF 47pF VO RANGE ±5V R2 23.7k + 715 2 R4 13.7k + 169 Ω REF-02 Figure 35 Bipolar Output Operation Without Trim Version 2 4 Generating a Negative Supply Voltage Some applications may require bipolar output configuration, but only have a single power supply rail available. This is very common in data acquisition systems using microprocessor-based systems. In these systems, only +12 V, +15 V, and/or +5 V are available. Shown in Figure 36 is a method of generating a negative supply voltage using one CD4049, a CMOS hex inverter, operating on +12 V or +15 V. The circuit is essentially a charge pump where two of the six are used as an oscillator. For the values shown, the frequency of oscillation is approximately 3.5 kHz and is fairly insensitive to supply voltage because R1 > 2 3 R2. The remaining four inverters are wired in parallel for higher output current. The square-wave output is level translated by C2 to a negative-going signal, rectified using a pair of 1N4001s, and then filtered by C3. With the values shown, the charge pump will provide an output voltage of –5 V for current loading in the range 0.5 mA ≤ IOUT ≤ 10 mA with a +15 V supply and 0.5 mA ≤ IOUT ≤ 7 mA with a +12 V supply. 7 6 9 10 11 12 14 15 INVERTERS = CD4049 3 2 R1 510k Ω 5 4 C2 47µF D2 1N4001 D1 1N4001 1N5231 5.1V ZENER C1 0.02µF Figure 36. Generating a –5 V Supply When Only +12 V or +15 V Are Available Audio Volume Control The DAC8562 is well suited to control digitally the gain or attenuation of a voltage controlled amplifiers. In professional 20 CE 16 CLR 15 DATA R6 825 Ω DAC-8562 DGND 10 0V ≤ VC ≤ +2.24V R7 1kΩ* AGND 12 CCON 1µF * – PRECISION RESISTOR PT146 1kΩ COMPENSATOR Figure 37. Audio Volume Control Since the supply voltage available in these systems is typically ± 15 V or ± 18 V, a REF02 is used to supply the +5 V required to power the DAC. No trimming of the reference is required because of the reference’s tight initial tolerance and low supply current consumption of the DAC8562. The SSM2018 is configured as a unity-gain buffer when its control voltage equals 0 volt. This corresponds to a 000H code from the DAC8562. Since the SSM2018 exhibits a gain constant of –28 mV/dB (typical), the DAC’s full-scale output voltage has to be scaled down by R6 and R7 to provide 80 dB of attenuation when the digital code equals FFFH. Therefore, every DAC LSB corresponds to 0.02 dB of attenuation. Table V illustrates the attenuation versus digital code of the volume control circuit. R3 470 Ω C3 47µF 0.1µF 13 Table V. SSM2018 VCA Attenuation vs. DAC8562 Input Code –5V R2 5.1k Ω +5V 6 Hexadecimal Number in DAC Register Control Voltage (V) VCA Attenuation (dB) 000 400 800 C00 FFF 0 +0.56 +1.12 +1.68 +2.24 0 20 40 60 80 –12– REV. A DAC8562 To compensate for the SSM2018’s gain constant temperature coefficient of –3300 ppm/°C, a 1 kΩ, temperature-sensitive resistor (R7) manufactured by the Precision Resistor Company with a temperature coefficient of +3500 ppm/°C is used. A CCON of 1 µF provides a control transition time of 1 ms which yields a click-free change in the audio channel attenuation. Symmetry and offset trimming details of the VCA can be found in the SSM2018 data sheet. lower limits for the test are loaded into each DAC individually by controlling HDAC/LDAC. If a signal at the test input is not within the programmed limits, the output will indicate a logic zero which will turn the red LED on. R2 5kΩ 7 17 Information regarding the PT146 1 kΩ “Compensator” can be obtained by contacting: 0.1µF 6 18 Precision Resistor Company, Incorporated 10601 75th Street North Largo, FL 34647 (813) 541-5771 RCS 100Ω 12 R1 100k AMP-05 10 0mA ≤ IOUT ≤ 10mA 2.4µA/ LSB 8 9 1 11 5 2 A High-Compliance, Digitally Controlled Precision Current Source 4 The circuit in Figure 38 shows the DAC8562 controlling a high-compliance, precision current source using an AMP05 instrumentation amplifier. The AMP05’s reference pin becomes the input, and the “old” inputs now monitor the voltage across a precision current sense resistor, RCS. Voltage gain is set to unity, so the transfer function is given by the following equation: IOUT = +15V P1 100kΩ 0.1µF –15V +15V VIN RCS 0.1µF 2 REF-02 If RCS equals 100 Ω, the output current is limited to +10 mA with a 1 V input. Therefore, each DAC LSB corresponds to 2.4 µA. If a bipolar output current is required, then the circuit in Figure 33 can be modified to drive the AMP05’s reference pin with a ± 1 V input signal. 0.1µF 6 4 20 CE 16 CLR 15 R3 3k DAC-8562 13 Potentiometer P1 trims the output current to zero with the input at 0 V. Fine gain adjustment can be accomplished by adjusting R1 or R2. DATA DGND AGND 10 12 R4 1k A Digitally Programmable Window Detector A digitally programmable, upper/lower limit detector using two DAC8562s is shown in Figure 39. The required upper and +5V +5V 1k Ω 0.1µF Figure 38. A High-Compliance, Digitally Controlled Precision Current Source VIN +5V 20 +5V 16 15 R1 604Ω R2 604Ω RED LED T1 GREEN LED T1 0.1µF DAC-8562 13 3 DGND AGND 12 10 2 +5V 5 1/6 74HC05 C1 2 C2 1 PASS/FAIL 4 1 +5V 0.1µF 7 6 20 HDAC/LDAC 16 CLR 15 DATA 12 DAC-8562 3 4 1/6 74HC05 13 DGND AGND 10 C1, C2 = 1/4 CMP-404 12 Figure 39. A Digitally Programmable Window Detector REV. A –13– DAC8562 Decoding Multiple DAC8562s when PC1 is cleared. The DAC’s CLR input, controlled by the M68HC11’s PC2 output line, provides an asynchronous clear function that sets the DAC’s output to zero. Included in this section is the source code for operating the DAC-8562–M68HC11 interface. The CE function of the DAC8562 can be used in applications to decode a number of DACs. In this application, all DACs receive the same input data; however, only one of the DACs’ CE input is asserted to transfer its parallel input register contents into the DAC. In this circuit, shown in Figure 40, the CE timing is generated by a 74HC139 decoder and should follow the DAC8562’s standard timing requirements. To prevent timing errors, the 74HC139 should not be activated by its ENABLE input while the coded address inputs are changing. A simple timing circuit, R1 and C1, connected to the DACs’ CLR pins resets all DAC outputs to zero during power-up. +5V C1 0.1µF R1 1k Ω VOUT1 15 13 16 MICROPROCESSOR INTERFACING DAC-8562–MC68HC11 INTERFACE DATA The circuit illustrated in Figure 41 shows a parallel interface between the DAC8562 and a popular 8-bit microcontroller, the M68HC11, which is configured in a single-chip operating mode. The interface circuit consists of a pair of 74ACT11373 transparent latches and an inverter. The data is loaded into the latches in two 8-bit bytes; the first byte contains the four most significant bits, and the lower 8 bits are in the second byte. Data is taken from the microcontroller’s port B output lines, and three interface control lines, CLR, CE, and MSB/LSB, are controlled by the M68HC11's PC2, PC1, and PC0 output lines, respectively. To transfer data into the DAC, PC0 is set, enabling U1’s outputs. The first data byte is loaded into U1 where the four least significant bits of the byte are connected to MSB–DB8. PC0 is then cleared; this latches U1’s inputs and enables U2’s outputs. U2s outputs now become DB7–DB0. The DAC output is updated with the contents of U1 and U2 DAC-8562 #1 +5V VOUT2 15 13 74HC139 0.1µF ENABLE 16 1 2 CODED ADDRESS 3 15 +5V 1Y0 VCC 1G 1Y1 1A 1Y2 1B 1Y3 2G 2Y0 1k Ω 14 2Y1 2A 13 8 2B 2Y2 GND 2Y3 16 4 5 DAC-8562 #2 6 12 11 10 9 VOUT3 15 7 13 16 NC DAC-8562 #3 NC NC VOUT4 15 13 NC 16 DAC-8562 #4 Figure 40. Decoding Multiple DAC8562s Using the CE Pin 74ACT11373 *M6BHC11 PC2 13 23 CLR 22 PC1 PC0 CE 74HC04 MSB/ LSB 1 2 21 20 1 16 C 1D 1Q 2D 2Q 3D 3Q 4D 4Q 5D U1 NC 2 3 4 9 10 6D 6Q 7D 7Q 8D 8Q 15 14 5Q 1 24 PB6 PB5 PB4 PB3 PB2 PB1 PB0 22 21 20 1 16 15 14 24 *DAC-8562 NC PC2 15 16 PC1 9 12 8 7 OC 6 74ACT11373 5 CLR CE MSB DB10 DB9 DB8 DB7 4 C 23 NC 11 13 PB7 NC 1D 1Q 2D 2Q 3D 3Q 4D 5D 4Q U2 5Q 6D 6Q 7D 7Q 8D 8Q 1 3 2 2 3 1 4 19 9 18 10 17 DB6 U3 VOUT 13 DB5 DB4 DB3 DB2 DB1 LSB 11 12 OC *ADDITIONAL PINS OMITTED FOR CLARITY Figure 41. DAC8562 to MC68HC11 Interface –14– REV. A DAC8562 DAC8562 – M68HC11 Interface Program Source Code DAC8562–M68HC11 Interface Program Source Code (Continued) * * DAC8562 to M68HC11 Interface Assembly Program * Adolfo A. Garcia * September 14, 1992 * * M68HC11 Register definitions * PORTB EQU $1004 PORTC EQU $1003 Port C control register * “0,0,0,0;0,CLR/,CE/,MSB-LSB/” DDRC EQU $1007 Port C data direction * * RAM variables: MSBS are encoded from 0 (Hex) to F (Hex) * LSBS are encoded from 00 (Hex) to F (Hex) * DAC requires two 8-bit loads * MSBS EQU $00 Hi-byte: “0,0,0,0;MSB,DB10,DB9,DB8” LSBS EQU $01 Lo-byte: “DB7,DB6,DB5,DB4;DB3,DB2, DB1,DB0” * * Main Program * ORG $C000 Start of user’s RAM in EVB INIT LDS #$CFFF Top of C page RAM * * Initialize Port C Outputs * LDAA #$07 0,0,0,0;0,1,1,1 STAA DDRC CLR/,CE/, and MSB-LSB/ are now enabled as outputs LDAA #$06 0,0.0,0;0,1,1,0 * CLR/-Hi, CE/-Hi, MSB-LSB/-Lo STAA PORTC Initialize Port C Outputs * * Call update subroutine * BSR UPDATE Xfer 2 8-bit words to DAC8562 JMP $E000 Restart BUFFALO * * Subroutine UPDATE * UPDATE PSHX Save registers X, Y, and A PSHY PSHA * * Enter contents of the Hi-byte input register * LDAA #$0A 0,0,0,0;1,0,1,0 STAA MSBS MSBS are set to 0A (Hex) * * Enter Contents of’ Lo-byte input register * LDAA #$AA 1,0,1,0;1,0,1,0 STAA LSBS LSBS are set to AA (Hex) * LDX #MSBS Stack pointer at 1st byte to send via Port B LDY #$1000 Stack pointer at on-chip registers * * Clear DAC output to zero * BCLR PORTC,Y $04 Assert CLR/ BSET PORTC,Y $04 De-assert CLR/ * * Loading input buffer latches * BSET PORTC,Y $01 Set hi-byte register load TFRLP LDAA 0,X Get a byte to transfer via Port B STAA PORTB Write data to input register INX Increment counter to next byte for transfer CPX #LSBS+1 Are we done yet ? BEQ DUMP If yes, update DAC output BCLR PORTC,Y $01 Latch hi-byte register and set lo-byte register load BRA TFRLP * * Update DAC output with contents of input registers * DUMP BCLR PORTC,Y $02 Assert CE/ BSET PORTC,Y $02 Latch DAC register * PULA When done, restore registers X, Y & A PULY PULX RTS ** Return to Main Program ** REV. A –15– DAC8562 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20 20-Pin Cerdip (R-Suffix) 20 11 0.255 (6.477) 0.245 (6.223) PIN 1 0.28 (7.11) 0.24 (6.1) 10 1 1.07 (27.18) MAX 0.065 (1.66) 0.045 (1.15) 0.18 (4.57) 0.125 (3.18) 0.20 (5.0) 0.14 (3.56) 0.125 (3.175) MIN 0.11 (2.79) 0.09 (2.28) 0.32 (8.128) 0.29 (7.366) 0.97 (24.64) 0.935 (23.75) 0.135 (3.429) 0.125 (3.17) 0.021 (0.533) 0.015 (0.381) 10 1 0.32 (8.128) 0.30 (7.62) 0.145 (3.683) MIN 11 PIN 1 15° 0 SEATING PLANE 0.011 (0.28) 0.009 (0.23) 0.15 (3.8) 0.125 (3.18) 0.011 (0.28) 0.009 (0.23) C1713–24–10/92 20-Pin Plastic DIP (P-Suffix) 15° 0.02 (0.5) 0.016 (0.14) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42. 0.11 (2.79) 0.09 (2.28) 0.07 (1.78) 0.05 (1.27) SEATING PLANE 0° LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42. 20-Lead SOIC (S-Suffix) 11 20 0.299 (7.60) 0.291 (7.40) 0.419 (10.65) 0.404 (10.00) PIN 1 1 10 0.512 (13.00) 0.496 (12.60) 0.107 (2.72) 0.089 (2.26) 0.050 (1.27) BSC 0.022 (0.56) 0.014 (0.36) 0.015 (0.38) 0.007 (0.18) 0.034 (0.86) 0.018 (0.46) PRINTED IN U.S.A. 0.011 (0.275) 0.005 (0.125) –16– REV. A