DAC8841FS

8-Bit Octal, 2-Quadrant ANALOG DEVICES Multiplying, CMOS TrimDAC DAC-8841 FUNCTIONAL BLOCK DIAGRAM FEATURES Replaces 8 Potentiometers Operates From Single +5 V Supply 1 MHz 2-Quadrant Muitipiying Bandwidth No Signal Inversion Eight Individual Channels 3-Wire Serial Input 500 kHz Update Data Loading Rate +3 Volt Output Swing LOAD i TE Midscale Preset Low 95 mW Power Dissipation APPLICATIONS GENERAL DESCRIPTION QND SDO PRESET V^gpL The DAC-8841 consumes only 95 mW froir a -1-5 V power sup ply. For dual polarity applications see the DAC-8840 which pro vides full 4-quadrant-multiplying ±3 V signal capability while operating from ±5 V power supplies. LE Trimmer Replacement Dynamic Level Adjustment Special Waveform Generation and Modulation Programmable Gain Amplifiers The DAC-8841 provides eight general purpose digitally controDed voltage adjustment devices. The TrimDAC™ capability replaces the mechanical trimmer function in new designs. It is ideal for ac or dc gain control of up to 1 MHz bandwidth signals. SO Internally the DAC-8841 contains eight voltage output CMOS digital-to-analog converters, each wi± separate reference inputs. Each DAC has its own DAC register which holds its output state. These DAC registers are updated from an internal serialto-parallel shift register which is loaded from a standard 3-wire serial input digital interface. Twelve data bits make up the data word clocked into the serial input register. This data word is The DAC-8841 is available in 24-pin plastic DIP, cerdip, and SOIC-24 packages. For MIL-STD/883 applications, contact ADI sales for the DAC-8841BW/883 data sheet which specifies operation over -55®C to 4-125°C. decoded where the first 4 bits determine the address of the DAC B register to be loaded with the last 8 bits of data. A serial data output pin at the opposite end of the serial register allows sim ple daisy-chaining in multiple DAC applications without addi tional external decoding logic. O TrimDAC is a trademark of Analog Devices, Inc. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Telex: 924491 Fax: 617/326-8703 Twx: 710/394-6577 Cable: ANALOG NORWOODMASS DAC-8841 -SPECIFICATIONS ELECTRICAL CHARACTERISTICS: VoD = +5 V, All V,nX = +1.5 V, VrefL = OV, = -AO^C to +85®C apply for DAC- 8841 F, unless otherwise noted. Symbol Parameter Min Conditions Typ Max Units ±1/2 ±1.5 1.500 ±1 1.525 Bits LSB LSB 20 100 All Specifications Apply for DACs A, B, C, STATIC ACCURACY D, E, F, G, H Resolution N Integral Nonlinearity Differential Nonlinearity Half-Scale Output Voltage Zero-Scale Output Voltage Output Voltage Drift INL Note 1 DNL All Devices Monotonic, Note 1 Vhs Vzs TCVhs PR = 0 V, Sets D = 80h Digital Code = OOh PR = 0 V, Sets D = SOh 1.475 V mV iivrc 10 Appliesto All Inputs Vn^X or V^EpL SIGNAL INPUTS Input Voltage Range Input Resistance Input Capacitance REF Low Capacitance Rin On RrefL CrefL D = 55h; Code Dependent Code Dependent D = ABh; Code Dependent Code Dependent OVR Applies to All Outputs VqutX Rl = 10 kft DAC OUTPUTS Voltage Range Output Current Capadtive Load Iqut AVout < 25mV, Vn^X = I.375V, PR = 0 V GBW Applies to All DACs VinX = 100mV p-p +1.0 V dc LE Multiplying Gain Bandwidth 19 0.3 30 0.75 190 250 3 0 V kn 10 ±5 200 No Oscillation DYNAMIC PERFORMANCE 4 TE REF Low Resistance 1.5 0 IVR pF kn pF V mA pF 1 2.5 MHz 1.3 4.0 2.5 V/p,s V/|jis 0.01 % Measured 10% to 90% Slew Rate +SR -SR THD Total Harmonic Distortion AVoutX = +3 V AVoutX = -3 V 1.3 VinX = 1 V p-p + 1.0 V dc, D = FFh, f = 1 kHz, fu = 80 kHz Channel to Channel Crosstalk Digital Feedthrough POWER SUPPLIES f = IkHz 0.17 ±1 LSB Error Band, Sjq to 255io Measured Between Adjacent Channels, f = 100 kHz 3.5 SO Spot Noise Voltage Output Settling Time Ct Q VrefL = +1.5 V, D = 0 to FFh Idd Pdiss PR = OV DC Power Supply Rejection Ratio PSRR PR = OV Power Supply Range PSR Vdd B Positive Supply Current Power Dissipation 60 4.75 p,V/VHz 6 dB 6 nVs 19 26 mA 95 130 mW 5.00 0.01 5.25 V DIGITAL INPUTS Logic High O Logic Low Input Current Input Capacitance Input Coding Vn, II Ql %/% V 2.4 VlH |XS 70 0.8 V ±10 pA pF 8 Binary DIGITAL OUTPUT Logic High Logic Low Vqh Vol. loH = -0-4 mA 3.5 0.4 Uj = 1.6 mA TIMING SPECIFICATIONS Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width Preset Pulse Width Clock Edge to Load Time Load-Edge to Next Clock Edge kw, kx tos ^DH tpD ^LD tpR tcKLD ^LDCK 80 ns 40 ns 20 ns 120 ns 70 ns 50 ns 30 ns 60 ns ^[NL^d DNL tests do not include operation at codes 0thru 7due to zero-scale output voltage. For bias voltages above 100 mV on VrhfL, INL and DNL are maintained over all codes. Specifications subjectto changewithout notice. -2- WAFER TEST LIMITS: Vuo = +5 V, All V|hX = +1.5 V, VrefL =0V, =25''C, unless otherwise noted. DAC-8841GBC Parameter Symbol Integral Nonlinearity INL Note 1 ±1.5 LSB max Differential Nonlinearity DNL All Devices Monotonic, Note 1 ±1 LSB max Half-Scale Output Voltage Vhs Input Resistance (Vu^jX) REF Low Resistance ^REpL DAC Output Voltage Range OVR DAC Output Current lorrr Limits Conditions Units PR = 0 V, Sets D = 80h 1.475/1.525 V min/max D = 55h; Code Dependent 4 kn min D = ABh; Code Dependent Ri, = 10 kft kQ min AVqut < 25 mV mA min V min LE TE Measured 10% to 90% Slew Rate AVoutX= +3V Positive Negative Positive Supply Current DC Power Supply Rejection Ratio Logic Input High Logic Input Low Logic Input Current Logic Output High Logic Output Low ^outX = -3 V V/jLS min V/|AS min PR = OV mA max ^ %/% max = 0 V, AVdo = +5% V min V max fiA max loH = -0.4 mA V min Ir,T = 1.6 mA V max D3 X B SO Electrical tests areperformed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lotqualifications through sample lotassembly andtesting. qETAIL SERIAL DATA INPUT TIMING (PR = "1,'V,N = 1.5V,VREFL = t)V) SOI 1 0 O (DATA IN) SDO 1 — (DATA OUT) 0 — Vout(FPh) VqutIOSh) PRESET TIMING rs1 LSB ERROR BAND Figure 1. Timing Diagram 02 X 01 X 00 DAC REGISTER LOAD. PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS (T^ = +25°C, unless otherwise noted) Vdd to GND VinX to GND VrefL to GND VourXtoGND Short Circuit IqutX to GND Digital Input & Output Voltage to GND utC VoujC -0.3 V, +7 V Vdd Vdd VpD Continuous Vdd [I E utA [I § VqutA E f,N B [I V|nB E DAC-8841 2i| Vd '.nAIT top view iSsD V|nA E L_ (Not to Scale) Vref'- E Operating Temperature Range Extended Industrial: DAC-8841F ^O'C to +85°C Maximum Junction Temperature (Tj max) StorageTemperature Lead Temperature (Soldering, 10 sec) Package Power Dissipation +150°C 1 DAC C Output 5 VoutC VoutB VqujA V,nB V,nA 6 VnEpl- DAC B Output DAC A Output DAC B Reference Input VoutG DICE CHARACTERISTICS DIE SIZE 0.117 X 0.185 inch, 21,645 sq. mils (2.9718 X 4.699 mm, 13.964 sq. mm) The die backside is electrically common to LE Description E! TE VoutF 57'C/W Mnemonic DAC A Reference Input DAC Input Reference Low Preset Input, Active Low, All DAC Registers = 80h DAC E Reference Input DAC F Reference Input 9 V,nF 10 11 VoutE VqutE DAC E Output 2 3 14 15 VoutG VoutH V.nG V,nH DAC G Output DAC H Output 16 LD i f-i mmm SO 4 VqutE 70''C/W Pin 3 V erc/w DAC-8841 PIN DESCRIPTION LI V|nB (Tj Max - Ta)/6ja P-DIP SOIC-24 2 PR -65®C to +150°C -i-SOCC Thermal Resistance 0ja Ccrdip L. VoutB .UtB DAC F Output DAC G Reference Input man DAC H Reference Input Load DAC Register Strobe, Active High Input B that Transfers the Data Bits from the Serial input Register into the Decoded DAC Register. See Table I Serial Clock Input, Positive Edge Triggered Serial Data Output, Active Totem Pole Output Ground Ground 2. Vqut® '• *oUT^ 13. VqujH 14. V,„C 15. V,r,H 17 CLK 18 19 SDO GND 20 SDi Serial Data input 4. V,nB 16. LD 21 VoD Positive 5VPower 5 V Power Supply Supply Positive 5_ Vj^A 17. CLK 22 V,nD Reference Input Input DAC D Reference 23 V,nC DAC CReference C Reference Input Input DAC ^EpL 18. SDO 24 VoutD D Output DAC DOutput PR V,„E V,„F VoutE 19. GND . O * 7. 8. 9. 10. °'-'T 11. VqutE 12. VqutG CAUTION 20. SDI 21. Vdd 22. V,„D 23. V,mC 24. VoutD ^^ ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected, however, permanent damage may occur on unconnected devices subject to high energy electro static fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices areinserted. WARNING! ESD SENSITIVE DEVICE LSBDO D1 1 D2 D3 D4 D6 D5 MSBD7 LSBAO AI 1MSB A3 A2 LSB MSB A3 D5 D4 D3 I D2 I D1 0 0 0 No Operation 0 0 1 1 DAC A DACB DACC 1 DACE 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 DACD DACF 1 0 DACG DACH 0 1 No Operation 1 * 1 1 1/128 {YIN - YREFL) + VREFL LE 127/128 (YIN - YREFL) + YREFL YIN (Preset Value) 129/128 (YIN - YREFL) + YREFL 254/128 (YIN - YREFL) + VREFL 255/128 (YIN - YREFL) + YREFL SO Table I. Serial Input Decode Table SDI CLK LD PR Input Shift Register Operation XL X ^ L L H H XX XL L H L H No Operation Shift One Bit In from SDI (Pin 20), Shift One Bit* Out from SDO (Pin 18) All DAC Registers = 80^ Load Serial Register Data into B DAC(X) Register *Datashifted into the SDI pin appears twelve clocks later at the SDO pin. O Table II: Logic Control Input Truth Table No Operation DAC Output Voltage VOUT = D/I28 (YIN - VREFL) + VREFL VREFL 0 DAC Updated TE D6 AO 0 1 D7 Al 0 1 MSB A2 DAC-8841 —Typical Performance Characteristics +0.5 1 1 +1/2 Kn PF = 0V 2 1.498 0 > IL 1 1.497 ^ 1.496 +1/2 12 DACs E,F, G.H 3UPE RIMP 3SEt 0 2 tM* "WT 1.495 -0.25 -1/2 1.484 1.493 -50 -0.5 64 128 256 192 64 DIGITAL INPUT CODE - Decimal 128 256 192 Code vs. Temperature 1 1.6 1 _i Ul E V IN = z 10 o E O 1st CO as 0.6 / 0.4 la 0.1 E ^ 2 1 0.01 1 0.001 0 32 64 96 128 160 192 224 100 10 256 Ik 10k 100k 100 125 I—I 1 1 _Vbd =sv Ta =25*C I II Voo = +5V Tft b25*C _ Vn, = 1.5V VbefI- = oV ^EpLsOV D/ \TA ALL ZEROS PRbOV I X I4 f ✓ 75 I 8 ✓ av/ 50 Temperature ✓ r "t 25 Figure 7. Vqut S/ew Rate vs. ✓ ✓ ' 0 TEMPERATURE-'C -VtN =+1.51 r -25 vs. Frequency 10 f -50 Figure 6. Total Harmonic Distortion O B Figure 5. If^^pL Input Current vs. Digital Code / 0 -75 FREQUENCY-Hz DIGITAL INPUT CODE - Decimal / SR- & 4 Z 0 SR+ 5 i: u z 0.2 1. 1 6 ' 0 £ ' /A " »1 VfjEpLaaOV > 1.0 5 1^ 1.0 100 Vbd = 5V 7 ~ R|. = 2kQ p 1.4 75 8 - Vbb=+5V Vni = ivpp + iv J>V SO Figure 4. Half Scale vs. Temperature 1 IIII 1 i — SO E 100 1 _Vdb=5V Vref •- = 2.51 25 LE TE Figure 3. Linearity Error vs. Digital 2.0 0 TEMPERATURE-*C Figure 2. Linearity Error vs. Digital 1.8 -25 DIGITAL INPUT CODE - Decimal Input Code < V.uXb1.SV 1.499 Vr,£pLsalOCmV £o -1/2 - Ta = 25''C VpoaaSV a E - V,nX = 1.5V VREFL = 100rnV I 1 Vref L b ov V,uXa1.SV +0.25 1 Vpp =5V 1.500 • VppnSV DACs A,B, C,D 5UPE RIMP DSEC 0 c 1.501 1r~ 1 Ta = -S5,25,+85*C ✓ )/ Vdd 'load ~5mA __ VrefLbOV Ta = 25*C — 1 2 1 1 3 ViN - Volts Figure 8. Full-Scale Output to 0 100 200 300 400 Ik 500 VouxX-mV Figure 9. Zero-Scale Output Detail Positive Saturation -6- 10k 100k FREQUENCY-Hz Figure 10. Voltage Noise Density vs. Frequency sum ll I.i DAC-884t U 1 0.5V/DIV) O 1 1 IV 5h 1J in DIGITAL CODE = 255 -»8 -• 255 B Figure 12. Settling Time Figure 11. Pulse Response SO VrefI. = 2.5V VinX = 1.5V LO U 1 1 A 1 LE VouT (50mV/DIV) 5 ImU U 50 Vod=5V J L . Voo = 4V ms DIGITAL CODE = 128-»127 TE Figure 13. Worst Case 1 LSB Digital Step Change IlllllllliSIIIII IlllllllllliSlI -60 -25 0 25 SO 75 100 TEMPERATURE-'C Figure 14. Supply Current vs. Temperature SHORT CIRCUIT CURRENT llllllllllllllfil LIMITING llllllllllllllll •BBSBi SHORT CIRCUIT CURRENT LIMITING lllllllllllllllll 500 VoutX-Volts FREQUENCY-Hz Figure 15. PSRR vs. Frequency 600 T = HOURS OF OPERATION AT ISO'C Figure 17. Output Drift Delta Accelerated by Burn-In Figure 16. DAC Output Current vs. Vnu-rX DAC-8841 The DAC-8841 is a general purpose multiple-channel ac or do signal level adjustment device designed to replace potentiometers used in the three-terminal connection mode. Eight independent channels of programmable signal level control are available in this 24-pin package device. The outputs are completely buffered providing up to 5 mA of drive current to drive external loads. The DAG and amplifier combination shown in Figure 18 pro During system power up a logic low on the preset PR pin forces all DAC registers to 80^ which in turn forces all the buffer am plifier outputs to equal half-scale. The transfer equation (1) shows that in the preset condition (80h) that Vqut will equal ViN. The asynchronous PR input pin can be activated at any time to force the DAC registers to the half-scale code 80h. This is generally the most convenient place to start for general pur pose adjustment applications. duces two-quadrant multiplication of the signal inputs applied to ViN times the digital input control word. In addition the DAC8841 provides a 1 MHz gain-bandwidth product in the twoquadnmt multiplying channel. Operating from a 5 V power supply, analog inputs to +1.5 V which generate outputs to ADJUSTING AC OR DC SIGNAL LEVELS The two-quadrant multiplication operation of the DAC-8841 is shown in Figiure 18. For dc operation the equation describing the relationship between Vjn, digital inputs and Vqut is: CIRCUIT OPERATION +3 V are easily accommodated. VouiiD) = (D/128) X (V/jv - VrefL) + Vref^ (1) where D is a decimal number between 0 and 255. LE TE The acmal output voltages generated with a fixed 1.5 V dc input on VjN and VrefL = 0 V are summarized in this table. Comments Decimal Input (D) Vqut = 2 XVdac when Vrepl =ov :r2(D/256)xV,M = (D/128)xV,n GENERALCASE WHENVrep L x OV: VouT= (D/128)x (V|n- Vref L) + Vrhf L DAC8841 INPUT-OUTPUT VOLTAGE RANGE n - (I~ — O D=40h 1 O B DsOOh 0 0.000 V* Zero Scale 1 0.012* 2 0.024* 127 1.488 128 1.500 129 1.512 254 2.976 255 2.988 Half Scale = Vin Full Scale (FS) « 2 X ViN *See "Operation Near Ground." X CO a 0 FF.. 7/ .DsCOh 1 ^ (ViN = 1.5 V, VrefL = 0 V) SO VpD = tSV Vref' .=ov Vout(®) 2 4 V,N-Volts Vqut= 2 XV,n (D/256). where D=0 TO255 Notice that the output polarity is the same as the input polarity when the DAC register is loaded with 255 (in binary = all ones). Also note that the output does not exactly equal two times the input voltage. This is a result of the R-2R ladder DAC chosen. When the DAC register is loaded with 0, the output is VrefL. The acmal voltage measured when setting up a DAC in this example will vary within the ± 1 LSB linearity error specifi cation of the DAC-8841. The actual voltage error would be ±0.012 V. Figure 18. DAC Plus Amplifier Combine to Produce Two- Operation Near ground - The input stage of the internal buffer Quadrant Multiplication In order to be easy to use with a controlling microprocessor, a simplelayout-efficient three-wire serial data interface was cho sen. This interface can be easily adapted to almost all microcom puter and microprocessor systems. A clock (CLK), serial data input (SDI) and a load(LD) strobe pin make up the three-wire interface. The 12-bitinput data word used to change the value of the internal DAC registerscontains a 4-bit address and 8-bits of data. Using this combination, any DAC registercan be changed without disturbing the other devices. A serialdata out put (SDO) pin simplifies cascading multiple DAC-8841s without adding address decoder chips to the system. amplifier functions down to groimd, but the output stage cannot pull lower than the internal ground voltage. When a DAC out put tries to output a voltage at or below the internal ground po tential, it saturates and appears like a 50 fl resistor to ground. The typical saturation voltage appearing at the output is 20 mV, see Figure 9. The 100 mV worst case zero-scale voltage specifi cation reflects this saturation effect, including the worst case anticipated variationof the internal ground resistances, quies cent currents and buffer sinking current. Linearity is measured betweencode 8io and code 255^0 to avoid this samration effect. In summary, the transfer function of each DAC will be a straight line from code 8 to code 255 when VrefL = 0 V. For input codes 0 to 7, some DAC outputs will be satiurated in the zero-scale output voltage region; therefore, changing digjtal code 0 to 1 may not change the output voltage when VrefL - 0 V. -8- SIGNAL INPUTS (V,nA, B, C, D, E, F, G, H) The eight independent inputs have a code dependent input resistance whose worst case minimum value is specified in the electrical characteristics table. Use a suitable amplifier capable of driving this input resistance in parallel with the specified input capacitance. These reference inputs are designed to receive not only dc, but ac input voltages. This results from the incorpora tion of a true bilateral analog switch in the DAC design, see Figure 19. The DAC switch operation has been designed to op X< erate in the break-before-make format to minimize transient loading of the inputs. The reference input voltage range can op erate from ground (GND) to 1.5 V. That is, the operating input voltage range, when VnEpL —0 V, is: 0V< Vjj^X < 1.5 V —^ kV 5 ~ Vod-2V (2) 12 3 TE 0 4 VrepL-Volts P-CH Figure 20. DAC-8841 Input Voltage Operating Boundaries For example, biasing V^EpL equal to one volt would accept a 1 V p-p ac input signal on This input signal could then be attenuated or given a gain-of-two depending on the DAC data 2R MSB DAC setting. LE REGSTEH DAC OUTPUTS (VoutA, B, C, D, E, F, G, H) The eight D/A converter outputs are fiilly buffered by the DAC8841s internal amplifier. This amplifier is designed to drive up to 1 kfl loads in parallel with 200 pF. However in order to min imize internal device power consumption, it is recommended whenever possible to use larger values of load resistance. The amplifier output stage can handle shorts to GND; however, care should be taken to avoid continuous short circuit operation. See Figure 16 "DAC output current versus VqutX" graph. SO GND The amplifier output is guaranteed to operate to within 2 V of Vdd under all load conditions and temperature. Figure 8 shows typical operation to positive output saturation with a 5 mA load. Figure 19. DAC-8841 TrimDAC Equivalent Circuit (One Channel) The reference inputs can withstand input voltages up to V^d; however due to the internal amplifier's gain of two configura tion, the output voltage of the circuit reaches its maximum spec ified value of 3 V when the input voltage equals 1.5 V and VrefL = 0 V; see Figure 18. B The low output impedance of the buffers minimizes crosstalk between analog input channels. At 100 kHz 70 dB of channelto-channel isoladon exists. It is recommended to use good cir cuit layout practice such as guard traces between analog channels and power supply bypass capacitors. A 0.01 jaF ce ramic in parallel with a 1-10 |xF tantulum capacitor provides a good power supply bypass for most frequencies encountered. O The reference low input VrepL is the bottom end of the DAC (see Figture 18). This input is normally tied to ground; however it can be biased above ground. When VpppL is biased above ground, its value and that of Vip,X should be chosen in agree ment with Equation 3. DIGITAL INTERFACING VouT ^Voo-2V (3) Also for the general case the headroom restriction to Vpo for VjnX and VrefL is given by Equation 4. V^pL < - 2y (4) According to the above equations, the DAC-8841 can only be operated under certain combinations of Vj^X and VrefL. The shaded area in Figure 20 defines the theoretical allowable ranges of operation. Note that VrefL can be biased higher than Vj^jX. Linearity will vary with the reference voltages and supply condi tions. If a symmetrical output ac signal is desired, then the sym metrical ac input on VinX should be offset to VpEpL. The output signal will then be with respect to VrefL. The four digital input pins (CLK, SDI, LD, PR) of the DAC8841 were designed for TTL and 5 V CMOS logic compatibil ity. The SDO output pin offers good fanout in CMOS logic applications and can easily drive several DAC-8841s. The Logic Control Input Truth Table II describes how to shift data into the internal 12-bit serial input register. Note that the CLK is a positive edge-sensitive input. If mechanical switches are used for breadboard, product evaluation they should be debounced by a flipflop or other suitable means. The required address plus data input format is defined in the Serial Input Decode Table I. Note there are 8 address states that result in no operation (NOP) or activity in the DAC-8841 when the active high load strobe LD is activated. This NOP can be used in cascaded applications where only one DAC out of several packages needs updating. It takes 12 clocks on the CLK -9- DAC-8841 pin to fully load the serial input shift register. Data on the SDI input pin is subject to the timing diagram (Figure 1) data setup and data hold time requirements. After the twelfth clock pulse, the processor needs to activate the LD strobe to have the DAC8841 decode the serial register contents and update the target DAG register with the 8-bit data word. This needs to be done before the thirteenth positive clock edge. The timing require fC PAO PA1 PA2 SDI * CLK DAC-8a41 #1 ments are in the electrical characteristic table and in the Figure 1 timing diagram. After twelve clock edges data initially loaded into the shift register at SDI appears at the shift register output SDI OACA^ SDO. CLK There is some digital feedthrough from the digital input pins. Operating the clock only when the DAG registers require updat ing minimizes the effect of the digital feedthrough on the analog DAC-8841 S2 LD SDO OACH] signal channels. SDI DACA^ CLK that easily cascades for multiple packages. DAC-8841 #3 LE TE Figure 21 shows a three-wire interface for a single DAG-8841 Figure 21. Three-Wire Interface S DAC-8841 ORDERING INFORMATION Temperature Range Model Package 1 DAG8841FP DAG8841FW DAG8841FS DAG8841GBG -40°G to +85''G -40''G to +85°G +85''G Plastic DIP -40''G to +85''G Dice Gerdip SOIG SO For devices processed in total compliance to MIL-STD 883, contact your localsalesofiSce for the DAC8841BW/883 data sheet. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pm Epoxy Dip 0.3" Wide O B C'Skinny DIP") nnnnnnnnnnnn 0.280(7.11) 0.240 (6.10) uuuuuuuuuuuu 0.325 (8.25) 1.275(32.3) 0.300 (7.62) 1.125(28.6) 0.015 (0.38) ^ MIN 0.210 (5.33) MAX 0.160(4.06) " 0.115(2.92) V 0.130 (3.30) MIN 0.022 (0.558) 0.100 (2.54) BOS 0.070 (1.77) 0.045 (1.15) 0.014(0.356) -10- V •V k 0*-15* -4r0.015 (0.381) 0.008 (0.203) iiiliiS®®iffiiMii 24-Pin Wide-Body SOIC Package nnnnnnRRRRnn 0,2992 (7.60) 02914 (7.40) O'-S* 0.4193 (10.65) 02937 (10.00) yyyyyyyyyyyy O.OSCO (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.6141 (15.60) 0.0096 (025) T TE 02985 (1520) 0.1043 (^65) I 0.0926 (2.35) K H % SEATING. 0.0500 BSC 0.0192 (0.49) (127) BSC 0.0138(025) 0.0118 (0.30) 0.0040 (0.10) PLANE 0.0125 (0.32) 0.0091 (0.23) ^ SEE DETAIL - ABOVE LE H fp 24-Pin Narrow-Body Cerdip Package —H 0.005 (0.13) MIN ncuiL r 24 0.098(2.49) h~ nnnnnnnnnj MAX ISA SO LiUUUUiil'UUUULJ' 0.310 (7.87) n 99n m 1.280 (3221) !;m MAX 0.060 (122) 0.015 (028) n 0200 (5.08) MAX 0.150 0200 (S.08) I I O B 0.125 (3.18) 0.023 (0.58) 0.014(0.36) 0.100 (2.54) BSC 0.290 (7.37) MIN 0*-15 0.070 (1.78) SEATING 0.030 (0.76) PLANE -11- 0.320 (8.13) (3.81)