LTM4650
Dual 25A or Single 50A
DC/DC µModule Regulator
DESCRIPTION
FEATURES
Dual 25A or Single 50A Output
nn Input Voltage Range: 4.5V to 15V
nn Output Voltage Range: 0.6V to 1.8V
nn ±1.5% Maximum Total DC Output Error Over Line,
Load and Temperature
nn Differential Remote Sense Amplifier
nn Current Mode Control/Fast Transient Response
nn Adjustable Switching Frequency
nn Frequency Synchronization
nn Overcurrent Foldback Protection
nn Multiphase Parallel Current Sharing with Multiple
LTM4650s Up to 300A
nn Internal Temperature Monitor
nn Pin Compatible with the LTM4620 (Dual 13A, Single
26A) and LTM4630 (Dual 18A, Single 36A)
nn Selectable Burst Mode® Operation
nn Soft-Start/Voltage Tracking
nn Output Overvoltage Protection
nn 16mm × 16mm × 5.01mm BGA Package
The LTM®4650 is a dual 25A or single 50A output switching mode step-down DC/DC µModule® (power module)
regulator. Included in the package are the switching controllers, power FETs, inductors, and all supporting components. Operating from an input voltage range of 4.5V
to 15V, the LTM4650 supports two outputs each with an
output voltage range of 0.6V to 1.8V, each set by a single
external resistor. Its high efficiency design delivers up to
25A continuous current for each output. Only a few input
and output capacitors are needed. The LTM4650 is pin
compatible with the LTM4620 (dual 13A, single 26A) and
the LTM4630 (dual 18A, single 36A).
nn
The device supports frequency synchronization, multiphase operation, Burst Mode operation and output voltage
tracking for supply rail sequencing and has an onboard
temperature diode for device temperature monitoring.
High switching frequency and a current mode architecture enable a very fast transient response to line and load
changes without sacrificing stability.
Fault protection features include overvoltage and
overcurrent protection. The LTM4650 is offered in a
16mm × 16mm × 5.01mm BGA package.
APPLICATIONS
Processor, ASIC and FPGA Core Power
Telecom and Networking Equipment
nn Storage and ATCA Cards
nn Industrial Equipment
nn
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066
and 6580258. Other patents pending.
nn
TYPICAL APPLICATION
50A, 1.2V Output DC/DC µModule Regulator
220µF
CERAMIC
4V
×8
120k
TEMP
DIFFOUT
RUN1
VOUTS2
RUN2
TRACK1
4.7µF
LTM4650
VFB1
INTVCC
10k
PGOOD1
121k
fSW = 500KHz
90
470pF
VFB2
TRACK2
0.1µF
PINS NOT USED
IN THIS CIRCUIT:
CLKOUT
EXTVCC
SW1
SW2
VOUTS1
VOUT1
VIN
22µF
* 25V
×4
1.2VOUT Efficiency vs IOUT
95
EFFICIENCY (%)
VIN
4.5V TO
15V
60.4k
COMP1
85
80
75
COMP2
PGOOD2
DIFFP
fSET
VOUT2
VOUT2
1.2V
50A
PHASMD SGND GND MODE_PLLIN DIFFN
4650 TA01a
70
65
VIN = 12V
VIN = 5V
0
10
20
30
LOAD CURRENT (A)
40
50
4650 TA01b
Rev. C
Document Feedback
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1
LTM4650
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VIN...............................................................–0.3V to 16V
VSW1, VSW2.....................................................–1V to 16V
PGOOD1, PGOOD2, RUN1, RUN2,
INTVCC , EXTVCC........................................... –0.3V to 6V
MODE_PLLIN, fSET, TRACK1, TRACK2,
DIFFOUT, PHASMD................................ –0.3V to INTVCC
VOUT1, VOUT2, VOUTS1, VOUTS2...................... –0.3V to 6V
DIFFP, DIFFN.......................................... –0.3V to INTVCC
COMP1, COMP2, VFB1, VFB2 (Note 5)......... –0.3V to 2.7V
INTVCC Peak Output Current.................................100mA
Internal Operating Temperature Range (Note 2)
LTM4650E, LTM4650I........................ –40°C to 125°C
LTM4650MP....................................... –55°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature........................... 245°C
TOP VIEW
TEMP
EXTVCC
M
L
K
J
CLKOUT
SW1
PHASMD
MODE_PLLIN
TRACK1
VFB1
VOUTS1
INTVCC
SW2
PGOOD1
PGOOD2
RUN2
DIFFOUT
DIFFP
DIFFN
H
G
RUN1
SGND
F
GND
COMP1 COMP2
E
SGND VFB2 TRACK2
D
GND
fSET SGND VOUTS2
C
B
VOUT2
GND
A
1
2
3
4
5
6
7
8
9
10
11
12
BGA PACKAGE 144-LEAD (16mm × 16mm × 5.01mm)
TJMAX = 125°C, θJA = 7°C/W, θJCbottom = 1.5°C/W, θJCtop = 3.7°C/W, θJB + θJBA ≅ 7°C/W
θ VALUES DEFINED PER JESD 51-12
WEIGHT = 3.2g
ORDER INFORMATION
PART MARKING*
PART NUMBER
PAD OR BALL FINISH
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)
LTM4650EY#PBF
SAC305 (RoHS)
LTM4650Y
e1
BGA
3
–40°C to 125°C
LTM4650IY#PBF
SAC305 (RoHS)
LTM4650Y
e1
BGA
3
–40°C to 125°C
LTM4650IY
SnPb (63/37)
LTM4650Y
e0
BGA
3
–40°C to 125°C
LTM4650MPY#PBF
SAC305 (RoHS)
LTM4650Y
e1
BGA
3
–55°C to 125°C
LTM4650MPY
SnPb (63/37)
LTM4650Y
e0
BGA
3
–55°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container.
Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
• LGA and BGA Package and Tray Drawings
2
Rev. C
For more information www.analog.com
LTM4650
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 22.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VIN
Input DC Voltage
l
VOUT
Output DC Voltage
l
0.6
VOUT1(DC),
VOUT2(DC)
Output Voltage, Total Variation with
Line and Load (Note 7)
CIN = 22µF × 3, COUT = 100µF × 2 Ceramic,
470µF POSCAP
VOUT = 1.2V, IOUT = 0A to 25A
l
1.182
1.2
RUN Pin On/Off Threshold
RUN Rising
1.1
1.25
1.40
V
4.5
MAX
UNITS
15
V
1.8
V
1.218
V
Input Specifications
VRUN1, VRUN2
VRUN1HYS , VRUN2HYS RUN Pin On Hysteresis
150
mV
IINRUSH(VIN)
Input Inrush Current at Start-Up
IOUT = 0A, CIN = 22µF × 3, CSS = 0.01µF,
COUT = 100µF × 3, VOUT1 = 1.5V, VOUT2 = 1.5V
1
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 1.2V, Burst Mode Operation
VIN = 12V, VOUT = 1.2V, Pulse-Skipping Mode
VIN = 12V, VOUT= 1.2V, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
4.5
25
240
35
mA
mA
mA
µA
IS(VIN)
Input Supply Current
VIN = 4.5V, VOUT = 1.2V, IOUT = 25A
VIN = 12V, VOUT = 1.2V, IOUT = 25A
8.4
3.2
A
A
IOUT1(DC), IOUT2(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 1.2V (Note 6)
25
A
ΔVOUT1(LINE) /VOUT1
ΔVOUT2(LINE) /VOUT2
Line Regulation Accuracy
VOUT = 1.2V, VIN from 4.5V to 15V
IOUT = 0A for Each Output,
l
0.01
0.1
%/V
ΔVOUT1/VOUT1
ΔVOUT2 /VOUT2
Load Regulation Accuracy
For Each Output, VOUT = 1.2V, 0A to 25A
VIN = 12V (Note 6)
l
0.5
0.75
%
A
Output Specifications
0
VOUT1(AC), VOUT2(AC) Output Ripple Voltage
For Each Output, IOUT = 0A, COUT = 100µF × 3
Ceramic, 470µF POSCAP, VIN = 12V,
VOUT = 1.2V, Frequency = 500kHz
15
mVP-P
fS (Each Channel)
Output Ripple Voltage Frequency
VIN = 12V, VOUT = 1.2V, fSET = 1.25V (Note 4)
500
kHz
fSYNC
(Each Channel)
SYNC Capture Range
∆VOUTSTART
(Each Channel)
Turn-On Overshoot
COUT = 100µF Ceramic, 470µF POSCAP, VOUT =
1.2V, IOUT = 0A VIN = 12V
10
mV
tSTART
(Each Channel)
Turn-On Time
COUT = 100µF Ceramic, 470µF POSCAP,
No Load, TRACK/SS with 0.01µF to GND,
VIN = 12V
5
ms
∆VOUT(LS)
(Each Channel)
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
COUT = 22µF × 3 Ceramic, 470µF POSCAP
VIN = 12V, VOUT = 1.5V
30
mV
tSETTLE
(Each Channel)
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load,
VIN = 12V, COUT = 100µF, 470µF POSCAP
20
µs
IOUT(PK)
(Each Channel)
Output Current Limit
VIN = 12V, VOUT = 1.2V
35
A
400
780
kHz
Rev. C
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3
LTM4650
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 22.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.594
0.600
0.606
V
–5
–20
nA
0.64
0.66
0.68
V
1
1.25
1.5
µA
Control Section
VFB1, VFB2
Voltage at VFB Pins
IOUT = 0A, VOUT = 1.2V
l
(Note 5)
IFB
VOVL
Feedback Overvoltage Lockout
TRACK1 (I),
TRACK2 (I)
Track Pin Soft-Start Pull-Up Current
UVLO
Undervoltage Lockout (Falling)
l
TRACK1 (I),TRACK2 (I) Start at 0V
UVLO Hysteresis
tON(MIN)
Minimum On-Time
RFBHI1, RFBHI2
Resistor Between VOUTS1, VOUTS2
and VFB1, VFB2 Pins for Each Output
(Note 5)
VPGOOD1, VPGOOD2
Low
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPGOOD
PGOOD Trip Level
VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
3.3
V
0.6
V
90
60.05
ns
60.4
60.75
0.1
0.3
V
±5
µA
–10
10
kΩ
%
%
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
6V < VIN < 15V
VINTVCC
Load Regulation
INTVCC Load Regulation
ICC = 0mA to 50mA
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VEXTVCC(DROP)
EXTVCC Dropout
ICC = 20mA, VEXTVCC = 5V
VEXTVCC(HYST)
EXTVCC Hysteresis
4.8
4.5
5
5.2
V
0.75
2
%
4.7
50
V
100
220
mV
mV
Oscillator and Phase-Locked Loop
Frequency Nominal
Nominal Frequency
fSET = 1.2V
Frequency Low
Lowest Frequency
fSET = 0.93V
400
kHz
Frequency High
Highest Frequency
fSET > 2.4V, Up to INTVCC
780
kHz
fSET
Frequency Set Current
RMODE_PLLIN
MODE_PLLIN Input Resistance
CLKOUT
Phase (Relative to VOUT1)
CLK High
CLK Low
Clock High Output Voltage
Clock Low Output Voltage
4
450
9
PHASMD = GND
PHASMD = Float
PHASMD = INTVCC
2
500
10
550
11
kHz
µA
250
kΩ
60
90
120
Deg
Deg
Deg
0.2
V
V
Rev. C
For more information www.analog.com
LTM4650
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 22.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Amplifier
AV Differential
Amplifier
Gain
1
RIN
Input Resistance
Measured at DIFFP Input
VOS
Input Offset Voltage
VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA
PSRR Differential
Amplifier
Power Supply Rejection Ratio
5V < VIN < 15V
ICL
Maximum Output Current
VOUT(MAX)
Maximum Output Voltage
GBW
Gain Bandwidth Product
VTEMP
Diode Connected PNP
TC
Temperature Coefficient
80
kΩ
3
IDIFFOUT = 300µA
dB
3
mA
INTVCC – 1.4
I = 100µA
l
mV
90
V
3
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4650 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4650E is guaranteed to meet specifications from
0°C to 125°C internal temperature. Specifications over the –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4650I is guaranteed over the full –40°C to 125°C internal operating
temperature range. The LTM4650MP is tested and guaranteed over
the –55°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with
board layout, the rated package thermal impedance and other
environmental factors.
V/V
MHz
0.6
V
–2.2
mV/C
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: LTM4650 device is designed to operate from 400kHz to 750kHz.
Note 5: These parameters are tested at wafer sort.
Note 6: See output current derating curves for different VIN, VOUT and TA.
Note 7: Total DC output voltage error includes all errors over temperature:
line and load regulation as well as the tolerance of the integrated top
feedback resistor.
Rev. C
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5
LTM4650
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current,
VIN = 12V
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Current,
VIN = 5V
80
75
0.8VOUT, 400kHz
1.0VOUT, 500kHz
1.2VOUT, 500kHz
1.5VOUT, 600kHz
1.8VOUT, 600kHz
70
65
0
5
10
15
LOAD CURRENT (A)
20
80
75
0.8VOUT, 400kHz
1.0VOUT, 500kHz
1.2VOUT, 500kHz
1.5VOUT, 600kHz
1.8VOUT, 600kHz
70
65
25
0
5
10
15
LOAD CURRENT (A)
4650 G01
Burst Mode and Pulse-Skip Mode
Efficiency VIN=12V, VOUT = 1.2V,
fS = 500kHz
100
CCM
Burst Mode OPERATION
PULSE-SKIP MODE
90
80
EFFICIENCY (%)
EFFICIENCY (%)
90
85
80
75
0.8VOUT, 400kHz
1.0VOUT, 500kHz
1.2VOUT, 500kHz
1.5VOUT, 600kHz
1.8VOUT, 600kHz
70
65
0
10
20
30
LOAD CURRENT (A)
40
70
60
50
40
30
20
10
50
0
0.01
0.1
1
LOAD CURRENT (A)
10
4650 G04
4650 G03
1V Dual Phase Single Output
Load Transient Response
1.2V Dual Phase Single Output
Load Transient Response
VOUT(AC)
20mV/DIV
VOUT(AC)
20mV/DIV
LOAD
STEP
10A/DIV
LOAD
STEP
10A/DIV
50µs/DIV
12VIN, 1VOUT, 500kHz, 12.5A LOAD STEP,
10A/µs STEP-UP AND STEP-DOWN
COUT = 8× 220µF CERAMIC
CFF = 470pF
6
25
4650 G02
Dual Phase Single Output Efficiency
vs Output Current, VIN = 12V,
fS = 500kHz
95
20
4650 G05
50µs/DIV
12VIN, 1.2VOUT, 500kHz, 12.5A LOAD STEP,
10A/µs STEP-UP AND STEP-DOWN
COUT = 8× 220µF CERAMIC
CFF = 470pF
4650 G06
Rev. C
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LTM4650
TYPICAL PERFORMANCE CHARACTERISTICS
1.5V Dual Phase Single Output
Load Transient Response
1.8V Dual Phase Single Output
Load Transient Response
VOUT(AC)
20mV/DIV
VOUT(AC)
20mV/DIV
LOAD
STEP
10A/DIV
LOAD
STEP
10A/DIV
50µs/DIV
12VIN, 1.5VOUT, 600kHz, 12.5A LOAD STEP,
10A/µs STEP-UP AND STEP-DOWN
COUT = 8× 220µF CERAMIC
CFF = 470pF
4650 G07
50µs/DIV
12VIN, 1.8VOUT, 600kHz, 12.5A LOAD STEP,
10A/µs STEP-UP AND STEP-DOWN
COUT = 8× 220µF CERAMIC
CFF = 470pF
4650 G08
Single Phase Start-up with 25A
Single Phase Start-Up with No load
VSW
10V/Div
VSW
10V/Div
VOUT
0.5V/Div
VOUT
0.5V/Div
IIN
1A/Div
IIN
0.2A/Div
20ms/DIV
12VIN, 1.2VOUT, 500kHz
COUT = 1× 470µF POSCAP + 2× 100µF
CERAMIC, CSS = 0.1µF
50μs/DIV
12VIN, 1.2VOUT, 500kHz
COUT = 1× 470µF POSCAP + 2× 100µF
CERAMIC, CSS = 0.1µF
4650 G09
4650 G10
Single Phase Short Circuit
Protection with 25A
Single Phase Short Circuit
Protection with No load
VSW
10V/Div
VSW
10V/Div
VOUT
0.5V/Div
VOUT
0.5V/Div
IIN
1A/Div
IIN
2A/Div
20ms/DIV
12VIN, 1.2VOUT, 500kHz
COUT = 1× 470µF POSCAP + 2× 100µF
CERAMIC, CSS = 0.1μF
4650 G11
50µs/DIV
12VIN, 1.2VOUT, 500kHz
COUT = 1× 470µF POSCAP + 2× 100µF
CERAMIC
4650 G12
Rev. C
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7
LTM4650
PIN FUNCTIONS
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins.
Apply output load between these pins and GND pins.
Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 4.
GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12,
F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1,
J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power
Ground Pins for Both Input and Output Returns.
VOUT2 (A8-A12, B8-B12, C9-C12): Power Output Pins.
Apply output load between these pins and GND pins.
Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 4.
VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top
of the internal top feedback resistor for each output. The
pin can be directly connected to its specific output, or
connected to DIFFOUT when the remote sense amplifier is
used. In paralleling modules, one of the VOUTS pins is connected to the DIFFOUT pin in remote sensing or directly
to VOUT with no remote sensing. It is very important to
connect these pins to either the DIFFOUT or VOUT since
this is the feedback path, and cannot be left open. See the
Applications Information section.
fSET (C6): Frequency Set Pin. A 10µA current is sourced
from this pin. A resistor from this pin to ground sets a
voltage that in turn programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage
that can set the operating frequency. See the Applications
Information section.
SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return
ground path for all analog and low power circuitry. Tie
a single connection to the output capacitor GND in the
application. See layout guidelines in Figure 11.
8
VFB1, VFB2 (D5, D7): The Negative Input of the Error
Amplifier for Each Channel. Internally, this pin is connected to VOUTS1 or VOUTS2 with a 60.4kΩ precision
resistor. Different output voltages can be programmed
with an additional resistor between VFB and GND pins. In
PolyPhase® operation, tying the VFB pins together allows
for parallel operation. See the Applications Information
section for details.
TRACK1, TRACK2 (E5, D8): Output Voltage Tracking Pin
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
current source. When one channel is configured to be
master of the two channels, then a capacitor from this pin
to ground will set a soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See
the Applications Information section.
COMP1, COMP2 (E6, E7): Current control threshold and
error amplifier compensation point for each channel. The
current comparator threshold increases with this control
voltage. Tie the COMP pins together for parallel operation.
The device is internal compensated.
DIFFP (E8): Positive input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output voltage. See the Applications Information section.
DIFFN (E9): Negative input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output GND. See the Applications Information section.
MODE_PLLIN (F4): Force Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to SGND to force both channels into
force continuous mode of operation. Connect to INTVCC
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force both channels into continuous mode of
operation and synchronized to the external clock applied
to this pin.
Rev. C
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LTM4650
PIN FUNCTIONS
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above
1.25V will turn on each channel in the module. A voltage
below 1.25V on the RUN pin will turn off the related channel. Each RUN pin has a 1µA pull-up current, once the
RUN pin reaches 1.2V an additional 4.5µA pull-up current
is added to this pin.
DIFFOUT (F8): Internal Remote Sense Amplifier Output.
Connect this pin to VOUTS1 or VOUTS2 depending on which
output is using remote sense. In parallel operation connect one of the VOUTS pin to DIFFOUT for remote sensing.
SW1, SW2 (G2, G11): Switching node of each channel
that is used for testing purposes. Also an R-C snubber
network can be applied to reduce or eliminate switch node
ringing, or otherwise leave floating. See the Applications
Information section.
PHASMD (G4): Connect this pin to SGND, INTVCC, or
floating this pin to select the phase of CLKOUT to 60
degrees, 120 degrees, and 90 degrees respectively.
CLKOUT (G5): Clock output with phase control using the
PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
PGOOD1, PGOOD2 (G9, G8): Output Voltage Power Good
Indicator. Open drain logic output that is pulled to ground
when the output voltage is not within ±10% of the regulation point.
INTVCC (H8): Internal 5V Regulator Output. The control
circuits and internal gate drivers are powered from this
voltage. Decouple this pin to PGND with a 4.7µF low ESR
tantalum or ceramic. INTVCC is activated when either
RUN1 or RUN2 is activated.
TEMP (J6): Temperature Monitor. An internal diode connected NPN transistor between this pin and SGND with
10nF filtering capacitor. See the Applications Information
section.
EXTVCC (J7): External power input that is enabled through
a switch to INTVCC whenever EXTVCC is greater than 4.7V.
Do not exceed 6V on this input, and connect this pin to
VIN when operating VIN on 5V. An efficiency increase will
occur that is a function of the (VIN – INTVCC) multiplied
by power MOSFET driver current. Typical current requirement is 30mA. VIN must be applied before EXTVCC , and
EXTVCC must be removed before VIN.
VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11):
Power Input Pins. Apply input voltage between these pins
and GND pins. Recommend placing input decoupling
capacitance directly between VIN pins and GND pins.
Heat Sink (Top Exposed Metal): The top exposed metal
is electrically unconnected.
Rev. C
For more information www.analog.com
9
LTM4650
SIMPLIFIED BLOCK DIAGRAM
PGOOD1
TRACK1
SS CAP
VIN
= 100µA VIN
RT
OR TEMP
MONITORS
VIN
4.5V TO 15V
VIN
CIN1
22µF
25V
×3
1μF
GND
RT
TEMP
MTOP1
SW1
CLKOUT
0.12µH
RUN1
MODE_PLLIN
0.22µF
MBOT1
PHASEMD
VOUT1
1.5V
25A
VOUT1
+
GND
COUT1
VOUTS1
COMP1
60.4k
VFB1
INTERNAL
COMP
SGND
RFB1
40.2k
POWER
CONTROL
PGOOD2
TRACK2
VIN
INTVCC
SS CAP
4.7µF
CIN2
22µF
25V
×3
1μF
0.22µF
GND
EXTVCC
MTOP2
SW2
0.12µH
RUN2
VOUT2
0.22µF
MBOT2
GND
+
VOUT2
1.2V
25A
COUT2
VOUTS2
60.4k
COMP2
fSET
RFSET
SGND
+ –
VFB2
RFB2
60.4k
INTERNAL
COMP
INTERNAL
FILTER
DIFFOUT
DIFFN
DIFFP
4650 F01
Figure 1. Simplified LTM4650 Block Diagram
DECOUPLING REQUIREMENTS
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
CIN1, CIN2
External Input Capacitor Requirement
(VIN1 = 4.5V to 15V, VOUT1 = 1.5V)
(VIN2 = 4.5V to 15V, VOUT2 = 1.0V)
IOUT1 = 25A
IOUT2 = 25A
44
44
66
66
µF
µF
External Output Capacitor Requirement
(VIN1 = 4.5V to 15V, VOUT1 = 1.5V)
(VIN2 = 4.5V to 15V, VOUT2 = 1.0V)
IOUT1 = 25A
IOUT2 = 25A
600
600
800
800
µF
µF
COUT1
COUT2
10
MAX
UNITS
Rev. C
For more information www.analog.com
LTM4650
OPERATION
Power Module Description
The LTM4650 is a dual-output standalone nonisolated
switching mode DC/DC power supply. It can provide two
25A outputs with few external input and output capacitors
and setup components. This module provides precisely
regulated output voltages programmable via external
resistors from 0.6VDC to 1.8VDC over 4.5V to 15V input
voltages. The typical application schematic is shown in
Figure 22.
The LTM4650 has dual integrated constant-frequency
current mode regulators and built-in power MOSFET
devices with fast switching speed. The typical switching
frequency is from 400kHz to 600kHz depending on output voltage. For switching-noise sensitive applications, it
can be externally synchronized from 400kHz to 780kHz. A
resistor can be used to program a free run frequency on
the FSET pin. See the Applications Information section.
With current mode control and internal feedback loop
compensation, the LTM4650 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Current mode control provides cycle-by-cycle fast current
limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators
pull the open-drain PGOOD outputs low if the output
feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above
regulation, the bottom MOSFET will turn on to clamp the
output voltage. The top MOSFET will be turned off. This
overvoltage protect is feedback voltage referred.
Pulling the RUN pins below 1.1V forces the regulators
into a shutdown state, by turning off both MOSFETs.
The TRACK pins are used for programming the output
voltage ramp and voltage tracking during start-up or
used for soft-starting the regulator. See the Applications
Information section.
The LTM4650 is internally compensated to be stable over
all operating conditions. Table 4 provides a guide line for
input and output capacitances for several operating conditions. The Linear Technology µModule Power Design
Tool will be provided for transient and stability analysis.
The VFB pin is used to program the output voltage with a
single external resistor to ground. A differential remote
sense amplifier is available for sensing the output voltage
accurately on one of the outputs at the load point, or in
parallel operation sensing the output voltage at the load
point.
Multiphase operation can be easily employed with the
MODE_PLLIN, PHASMD, and CLKOUT pins. Up to
12 phases can be cascaded to run simultaneously with
respect to each other by programming the PHASMD pin to
different levels. See the Applications Information section.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation or pulse-skipping operation using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency
graphs are provided for light load operation in the Typical
Performance Characteristics section. See the Applications
Information section for details.
A general purpose temperature diode is included inside
the module to monitor the temperature of the module. See
the Applications Information section for details.
The switch pins are available for functional operation
monitoring and a resistor-capacitor snubber circuit can
be careful placed on the switch pin to ground to dampen
any high frequency ringing on the transition edges. See
the Applications Information section for details.
Rev. C
For more information www.analog.com
11
LTM4650
APPLICATIONS INFORMATION
The typical LTM4650 application circuit is shown in
Figure 22. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 4 for specific external capacitor
requirements for particular applications.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage.
Each output of the LTM4650 is capable of 98% duty cycle,
but the VIN to VOUT minimum dropout is still shown as a
function of its load current and will limit output current
capability related to high duty cycle on the top side switch.
Minimum on-time tON(MIN) is another consideration in
operating at a specified duty cycle while operating at a
certain frequency due to the fact that tON(MIN) < D/fSW,
where D is duty cycle and fSW is the switching frequency.
tON(MIN) is specified in the electrical parameters as 90ns.
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 60.4kΩ internal
feedback resistor connects between the VOUTS1 to VFB1
and VOUTS2 to VFB2. It is very important that these pins
be connected to their respective outputs for proper feedback regulation. Overvoltage can occur if these VOUTS1
and VOUTS2 pins are left floating when used as individual
regulators, or at least one of them is used in paralleled
regulators. The output voltage will default to 0.6V with no
feedback resistor on either VFB1 or VFB2. Adding a resistor
RFB from VFB pin to GND programs the output voltage:
VOUT = 0.6V •
In parallel operation, the VFB pins have an IFB current
of 20nA maximum each channel. To reduce output voltage error due to this current, an additional VOUTS pin
can be tied to VOUT, and an additional RFB resistor can
be used to lower the total Thevenin equivalent resistance seen by this current. For example in Figure 2,
the total Thevenin equivalent resistance of the VFB pin
is (60.4k//RFB), which is 30.2k where RFB is equal to
60.4k for a 1.2V output. Four phases connected in
parallel equates to a worse case feedback current of
4 • IFB = 80nA maximum. The voltage error is 80nA • 30.2k
= 2.4mV. If VOUTS2 is connected, as shown in Figure 2, to
VOUT, and another 60.4k resistor is connected from VFB2
to ground, then the voltage error is reduced to 1.2mV. If
the voltage error is acceptable then no additional connections are necessary. The onboard 60.4k resistor is 0.5%
accurate and the VFB resistor can be chosen by the user to
be as accurate as needed. All COMP pins are tied together
for current sharing between the phases. The TRACK/SS
pins can be tied together and a single soft-start capacitor can be used to soft-start the regulator. The soft-start
equation will need to have the soft-start current parameter increased by the number of paralleled channels. See
Output Voltage Tracking section.
COMP1
60.4k
TRACK1
60.4k
VFB2
TRACK2
COMP1
LTM4650
0.9V
1.0V
1.2V
1.5V
1.8V
RFB
Open
182k
121k
90.9k
60.4k
40.2k
30.2k
For parallel operation of multiple channels the same feedback setting resistor can be used for the parallel design.
This is done by connecting the VOUTS1 to the output as
shown in Figure 2, thus tying one of the internal 60.4k
resistors to the output. All of the VFB pins tie together with
one programming resistor as shown in Figure 2.
OPTIONAL
RFB
60.4k
VOUT1
VOUT2
COMP2
0.8V
OPTIONAL CONNECTION
VFB1
RFB
0.6V
VOUTS1
VOUTS2
60.4k + RFB
VOUT
4 PARALLELED OUTPUTS
FOR 1.2V AT 100A
VOUT1
VOUT2
COMP2
Table 1. VFB Resistor Table vs Various Output Voltages
12
LTM4650
60.4k
USE TO LOWER
TOTAL EQUIVALENT
RESISTANCE TO LOWER
IFB VOLTAGE ERROR
VOUTS1
VOUTS2
VFB1
TRACK1
0.1µF
TRACK2
60.4k
VFB2
4650 F02
RFB
60.4k
Figure 2. 4-Phase Parallel Configurations
Rev. C
For more information www.analog.com
LTM4650
APPLICATIONS INFORMATION
Input Capacitors
The LTM4650 module should be connected to a low
AC-impedance DC source. For the regulator input two
22µF input ceramic capacitors are required for each channel for RMS ripple current. A 47µF to 100µF surface
mount aluminum electrolytic bulk capacitor can be used
for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough
source capacitance. If low impedance power planes are
used, then this bulk capacitor is not needed.
For a buck converter, the switching duty cycle can be estimated as:
V
D = OUT
VIN
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN(RMS) =
IOUT(MAX)
η%
• D • (1− D )
In the above equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcherrated electrolytic aluminum capacitor, Polymer capacitor.
Output Capacitors
The LTM4650 is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as COUT are chosen with low enough
effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low
ESR tantalum capacitor, the low ESR polymer capacitor
or ceramic capacitor. The typical output capacitance range
for each output is from 400µF to 600µF. Additional output
filtering may be required by the system designer, if further
reduction of output ripples or dynamic transient spikes is
required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop
and overshoot during a 12.5A (25%) load step transient. The table optimizes total equivalent ESR and total
bulk capacitance to optimize the transient performance.
Stability criteria are considered in the Table 4 matrix, and
the Linear Technology LTpowerCAD Design Tool will be
provided for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
a function of stability and transient response. The Linear
Technology µModule Power Design Tool can calculate the
output ripple reduction as the number of implemented
phases increases by N times. A small value 10Ω to 50Ω
resistor can be place in series from VOUT to the VOUTS pin
to allow for a bode plot analyzer to inject a signal into the
control loop and validate the regulator stability. The same
resistor could be place in series from VOUT to DIFFP and
a bode plot analyzer could inject a signal into the control
loop and validate the regulator stability.
Burst Mode Operation
The LTM4650 is capable of Burst Mode operation on each
regulator in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at
very light loads is a high priority, Burst Mode operation
should be applied. Burst Mode operation is enabled with
the MODE_PLLIN pin floating. During this operation, the
peak current of the inductor is set to approximately one
third of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates
a lower value. The voltage at the COMP pin drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.5V, the
BURST comparator trips, causing the internal sleep line
to go high and turn off both power MOSFETs.
In sleep mode, the internal circuitry is partially turned off,
reducing the quiescent current to about 450µA for each
output. The load current is now being supplied from the
output capacitors. When the output voltage drops, causing COMP to rise above 0.5V, the internal sleep line goes
low, and the LTM4650 resumes normal operation. The
next oscillator cycle will turn on the top power MOSFET
and the switching cycle repeats. Either regulator can be
configured for Burst Mode operation.
Rev. C
For more information www.analog.com
13
LTM4650
APPLICATIONS INFORMATION
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency
at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4650 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. At light loads the internal current comparator
may remain tripped for several cycles and force the top
MOSFET to stay off for several cycles, thus skipping cycles.
The inductor current does not reverse in this mode. This
mode will maintain higher effective frequencies thus lower
output ripple and lower noise than Burst Mode operation.
Either regulator can be configured for pulse-skipping mode.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to GND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During startup, forced continuous mode is disabled and inductor
current is prevented from reversing until the LTM4650’s
output voltage is in regulation. Either regulator can be
configured for force continuous mode.
Multiphase Operation
For output loads that demand more than 25A of current,
two outputs in LTM4650 or even multiple LTM4650s can
be paralleled to run out of phase to provide more output current without increasing input and output voltage
ripples. The MODE_PLLIN pin allows the LTM4650 to
synchronize to an external clock (between 400kHz and
780kHz) and the internal phase-locked-loop allows the
LTM4650 to lock onto incoming clock phase as well. The
CLKOUT signal can be connected to the MODE_PLLIN pin
of the following stage to line up both the frequency and
the phase of the entire system. Tying the PHASMD pin to
INTVCC, SGND, or (floating) generates a phase difference
14
(between MODE_PLLIN and CLKOUT) of 120 degrees, 60
degrees, or 90 degrees respectively. A total of 12 phases
can be cascaded to run simultaneously with respect to
each other by programming the PHASMD pin of each
LTM4650 channel to different levels. Figure 3 shows a
2-phase design, 4-phase design and a 6-phase design
example for clock phasing with the PHASMD table.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by the number of phases used when all of the
outputs are tied together to achieve a single high output
current design.
The LTM4650 device is an inherently current mode controlled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Figure 26 shows an example of parallel operation
and pin connection.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and
a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved
phases. Figure 4 shows this graph.
Frequency Selection and Phase-Lock Loop
(MODE_PLLIN and fSET Pins)
The LTM4650 device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the module at 400kHz for output
voltage below 1.0V, 500kHz for output voltage between
1.0V to 1.5V and 600kHz for output voltage above 1.5V,
for the best efficiency and inductor current ripple.
The LTM4650 switching frequency can be set with an
external resistor from the fSET pin to SGND. An accurate
10µA current source into the resistor will set a voltage
Rev. C
For more information www.analog.com
LTM4650
APPLICATIONS INFORMATION
2-PHASE DESIGN
PHASMD
FLOAT
CLKOUT
0 PHASE
MODE_PLLIN
VOUT1
VOUT2
SGND
FLOAT
CONTROLLER1
0
0
0
CONTROLLER2
180
180
240
CLKOUT
60
90
120
180 PHASE
INTVCC
PHASMD
4-PHASE DESIGN
90 DEGREE
CLKOUT
0 PHASE
FLOAT
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
180 PHASE
90 PHASE
FLOAT
PHASMD
MODE_PLLIN
VOUT1
VOUT2
270 PHASE
PHASMD
6-PHASE DESIGN
60 DEGREE
60 DEGREE
CLKOUT
SGND
MODE_PLLIN
VOUT1
VOUT2
180 PHASE
60 PHASE
SGND
PHASMD
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
240 PHASE
PHASMD
120 PHASE
FLOAT
MODE_PLLIN
VOUT1
VOUT2
300 PHASE
PHASMD
4650 F03
Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
0.45
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0 PHASE
CLKOUT
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (VOUT/VIN)
4650 F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
Rev. C
For more information www.analog.com
15
LTM4650
APPLICATIONS INFORMATION
that programs the frequency or a DC voltage can be
applied. Figure 5 shows a graph of frequency setting
verses programming voltage. An external clock can be
applied to the MODE_PLLIN pin from 0V to INTVCC over
a frequency range of 400kHz to 780kHz. The clock input
high threshold is 1.6V and the clock input low threshold
is 1V. The LTM4650 has the PLL loop filter components
on board. The frequency setting resistor should always
be present to set the initial switching frequency before
locking to an external clock. Both regulators will operate
in continuous mode while being externally clock.
The output of the PLL phase detector has a pair of complementary current sources that charge and discharge
the internal filter network. When the external clock is
applied then the fSET frequency resistor is disconnected
with an internal switch, and the current sources control
the frequency adjustment to lock to the incoming external
clock. When no external clock is applied, then the internal
switch is on, thus connecting the external fSET frequency
set resistor for free run operation.
900
800
FREQUENCY (kHz)
700
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
VOUT
VIN • FREQ
> tON(MIN)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple and current will increase. The on-time
can be increased by lowering the switching frequency. A
good rule of thumb is to keep on-time longer than 110ns.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK pins. The output can be tracked up and
down with another regulator. The master regulator’s output is divided down with an external resistor divider that
is the same as the slave regulator’s feedback divider to
implement coincident tracking. The LTM4650 uses an
accurate 60.4k resistor internally for the top feedback
resistor for each channel. Figure 6 shows an example of
coincident tracking. Equations:
⎛ 60.4k ⎞
SLAVE = ⎜ 1+
⎟ • VTRACK
R TA ⎠
⎝
600
500
Minimum On-Time
VTRACK is the track ramp applied to the slave’s track pin.
VTRACK has a control range of 0V to 0.6V, or the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
tracking is disabled when VTRACK is more than 0.6V. RTA
in Figure 6 will be equal to the RFB for coincident tracking.
Figure 7 shows the coincident tracking waveforms.
Minimum on-time tON is the smallest time duration that
the LTM4650 is capable of turning on the top MOSFET on
either channel. It is determined by internal timing delays,
and the gate charge required turning on the top MOSFET.
The TRACK pin of the master can be controlled by a
capacitor placed on the master regulator TRACK pin to
ground. A 1.3µA current source will charge the TRACK
pin up to the reference voltage and then proceed up
400
300
200
100
0
0
0.5
1
1.5
fSET PIN VOLTAGE (V)
2
2.5
4650 F05
Figure 5. Operating Frequency vs fSET Pin Voltage
16
Rev. C
For more information www.analog.com
LTM4650
APPLICATIONS INFORMATION
INTVCC
INTVCC
C10
4.7µF
R2
10k
PGOOD1
C1
22µF
25V
×4
CLKOUT INTVCC EXTVCC
MODE_PLLIN
4.5V TO 15V INTERMEDIATE BUS
VIN
R6
100k
TEMP
VOUTS1
RUN1
SW1
RUN2
VFB1
TRACK1
CSS
0.1µF
RTA
60.4k
VOUT1
1.5V
C6
100µF
6.3V
VFB2
LTM4650
TRACK2
RTB
60.4k
PGOOD1
VOUT1
VIN
RFB
60.4k
COMP1
f SET
COMP2
PHASMD
VOUTS2
VOUT2
R4
121k
SW2 PGOOD2
PGOOD2
SGND
GND
DIFFP
DIFFN
DIFFOUT
C8
470µF
6.3V
VOUT1
(MASTER)
1.5V AT 25A
40.2k
C5
100µF
6.3V
C7
470µF
6.3V
VOUT2
(SLAVE)
1.2V AT 25A
INTVCC
R9
10k
RAMP TIME
tSOFTSTART = (CSS /1.3µA) • 0.6
4650 F06
Figure 6. Example of Output Tracking Application Circuit
Regardless of the mode selected by the MODE_PLLIN
pin, the regulator channels will always start in pulseskipping mode up to TRACK = 0.5V. Between TRACK =
0.5V and 0.54V, it will operate in forced continuous mode
and revert to the selected mode once TRACK > 0.54V. In
order to track with another channel once in steady state
operation, the LTM4650 is forced into continuous mode
operation as soon as VFB is below 0.54V regardless of the
setting on the MODE_PLLIN pin.
OUTPUT VOLTAGE
MASTER OUTPUT
SLAVE OUTPUT
TIME
4650 F07
Figure 7. Output Coincident Tracking Waveform
to INTVCC. After the 0.6V ramp, the TRACK pin will no
longer be in control, and the internal voltage reference
will control output regulation from the feedback divider.
Foldback current limit is disabled during this sequence
of turn-on during tracking or soft-starting. The TRACK
pins are pulled low when the RUN pin is below 1.2V. The
total soft-start time can be calculated as:
Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s
TRACK pin. As mentioned above, the TRACK pin has a
control range from 0 to 0.6V. The master’s TRACK pin
slew rate is directly equal to the master’s output slew rate
in Volts/Time. The equation:
MR
SR
• 60.4k = R TB
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
⎛ C
⎞
tSOFT-START = ⎜ SS ⎟ • 0.6
⎝ 1.3µA ⎠
Rev. C
For more information www.analog.com
17
LTM4650
APPLICATIONS INFORMATION
tracking is desired, then MR and SR are equal, thus RTB
is equal the 60.4k. RTA is derived from equation:
R TA =
0.6V
VFB
V
V
+ FB − TRACK
60.4k RFB
R TB
where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since RTB is equal to the 60.4k
top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then RTA is equal to RFB with
VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in
Figure 6.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. RTB can be solved for when SR is
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then
RTB = 76.8k. Solve for RTA to equal to 49.9k.
Each of the TRACK pins will have the 1.3µA current source
on when a resistive divider is used to implement tracking
on that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. A resistor can
be pulled up to a particular supply voltage no greater than
6V maximum for monitoring.
Stability Compensation
The module has already been internally compensated for
all output voltages. Table 4 is provided for most application requirements. The Linear Technology µModule
Power Design Tool will be provided for other control loop
optimization.
18
Run Enable
The RUN pins have an enable threshold of 1.4V maximum,
typically 1.25V with 150mV of hysteresis. They control the
turn on each of the channels and INTVCC. These pins can be
pulled up to VIN for 5V operation, or a 5V Zener diode can be
placed on the pins and a 10k to 100k resistor can be placed
up to higher than 5V input for enabling the channels. The
RUN pins can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tie together
and controlled from a single control. See the Typical
Application circuits in Figure 22.
INTVCC and EXTVCC
The LTM4650 module has an internal 5V low dropout
regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power
MOSFET drivers. This regulator can source up to 70mA,
and typically uses ~30mA for powering the device at the
maximum frequency. This internal 5V supply is enabled
by either RUN1 or RUN2.
EXTVCC allows an external 5V supply to power the
LTM4650 and reduce power dissipation from the internal
low dropout 5V regulator. The power loss savings can be
calculated by:
(VIN – 5V) • 30mA = PLOSS
EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this
5V input to EXTVCC also to maintain a 5V gate drive level.
EXTVCC must sequence on after VIN, and EXTVCC must
sequence off before VIN.
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is provided
to sense low output voltages accurately at the remote
load points. This is especially true for high current loads.
The amplifier can be used on one of the two channels, or
on a single parallel output. It is very important that the
DIFFP and DIFFN are connected properly at the output,
and DIFFOUT is connected to either VOUTS1 or VOUTS2.
In parallel operation, the DIFFP and DIFFN are connected
properly at the output, and DIFFOUT is connected to
one of the VOUTS pins. Review the parallel schematics in
Figure 23 and review Figure 2.
Rev. C
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LTM4650
APPLICATIONS INFORMATION
SW Pins
The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combination
is used called a snubber circuit. The resistor will dampen
the resonance and the capacitor is chosen to only affect
the high frequency ringing across the resistor. If the stray
inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used
to select the snubber values. The inductance is usually
easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond
wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z
can be calculated:
where ID is the diode current, VD is the diode voltage, η
is the ideality factor (typically close to 1.0) and IS (saturation current) is a process dependent parameter. VT can
be broken out to:
Temperature Monitoring
Measuring the absolute temperature of a diode is possible
due to the relationship between current, voltage and temperature described by the classic diode equation:
⎛ V ⎞
ID = IS • e ⎜ D ⎟
⎝ η • VT ⎠
or
I
VD = η • VT •In D
IS
k•T
q
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. VT is
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable temperature sensors. The IS term in the previous equation is
the extrapolated current through a diode junction when
the diode has zero volts across the terminals. The IS term
varies from process to process, varies with temperature,
and by definition must always be less than ID. Combining
all of the constants into one term:
ZL = 2πfL,
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: ZC = 1/(2πfC). These values are a good
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss.
VT =
KD =
η•k
q
where KD = 8.62 • 10−5, and knowing ln(ID/IS) is always
positive because ID is always greater than IS, leaves us
with the equation that:
I
VD = T (KELVIN ) • K D •In D
IS
where VD appears to increase with temperature. It is common knowledge that a silicon diode biased with a current
source has an approximate –2mV/°C temperature relationship (Figure 8), which is at odds with the equation. In
fact, the IS term increases with temperature, reducing the
ln(ID/IS) absolute value yielding an approximate –2mV/°C
composite diode voltage slope.
To obtain a linear voltage proportional to temperature we
cancel the IS variable in the natural logarithm term to
remove the IS dependency from the equation 1. This is
accomplished by measuring the diode voltage at two currents I1, and I2, where I1 = 10 • I2) and subtracting we get:
I
I
ΔVD = T(KELVIN) • K D •IN 1 – T(KELVIN) • K D •IN 2
IS
IS
Rev. C
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19
LTM4650
APPLICATIONS INFORMATION
Thermal Considerations and Output Current Derating
0.8
DIODE VOLTAGE (V)
0.7
0.6
0.5
0.4
0.3
–50
50
25
0
75
TEMPERATURE (°C)
–25
100
125
4650 F08
Figure 8. Diode Voltage VD vs Temperature T(°C)
Combining like terms, then simplifying the natural log
terms yields:
∆VD = T(KELVIN) • KD • lN(10)
and redefining constant
K'D = K D •IN(10) =
198µV
K
yields
∆VD = K'D • T(KELVIN)
Solving for temperature:
T(KELVIN) =
ΔVD
K'D
(°CELSIUS) = T(KELVIN) – 273.15
where
300°K = 27°C
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198μV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
The diode connected PNP transistor at the TEMP pin
can be used to monitor the internal temperature of the
LTM4650. See Figure 23 for an example.
20
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board—
also defined by JESD51-9 (“Test Boards for Area Array
Surface Mount Package Thermal Measurements”). The
motivation for providing these thermal coefficients is
found in JESD 51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet can
be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to
correlate thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD 51-9 defined test board, which
does not reflect an actual application or viable operating condition.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package. In the typical µModule, the bulk of the heat flows
Rev. C
For more information www.analog.com
LTM4650
APPLICATIONS INFORMATION
out the bottom of the package, but there is always
heat flow out into the ambient environment. As a
result, this thermal resistance value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
3. θJCTOP, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most
of the heat flows from the junction to the top of the
part. As in the case of θJCBOTTOM, this value may be
useful for comparing packages but the test conditions
don’t generally match the user’s application.
4. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD 51-9.
A graphical representation of the aforementioned thermal resistances is given in Figure 9; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule. For example, in normal board-mounted applications, never does 100% of
the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
of the µModule—as the standard defines for θJCtop and
θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow,
a majority of the heat flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are
not exactly linear with respect to total package power
loss. To reconcile this complication without sacrificing
modeling simplicity—but also, not ignoring practical
realities—an approach has been taken using FEA software
modeling along with laboratory testing in a controlledenvironment chamber to reasonably define and correlate
the thermal resistance values supplied in this data sheet:
(1) Initially, FEA software is used to accurately build the
mechanical geometry of the µModule and the specified
PCB with all of the correct material coefficients along with
accurate power loss source definitions; (2) this model
simulates a software-defined JEDEC environment consistent with JSED51-9 to predict power loss heat flow and
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4650 F09
µMODULE DEVICE
Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients
Rev. C
For more information www.analog.com
21
LTM4650
APPLICATIONS INFORMATION
temperature readings at different interfaces that enable
the calculation of the JEDEC-defined thermal resistance
values; (3) the model and FEA software is used to evaluate
the µModule with heat sink and airflow; (4) having solved
for and analyzed these thermal resistance values and
simulated various operating conditions in the software
model, a thorough laboratory evaluation replicates the
simulated conditions with thermocouples within a controlled-environment chamber while operating the device
at the same power loss as that which was simulated. An
outcome of this process and due-diligence yields a set
of derating curves provided in other sections of this data
sheet. After these laboratory test have been performed
and correlated to the µModule model, then the θJB and
θBA are summed together to correlate quite well with the
µModule model with no airflow or heat sinking in a properly define chamber. This θJB + θBA value is shown in the
Pin Configuration section and should accurately equal the
θJA value because approximately 100% of power loss
flows from the junction through the board into ambient
with no airflow or top mounted heat sink. Each system has
its own thermal characteristics, therefore thermal analysis
must be performed by the user in a particular system.
The LTM4650 module has been designed to effectively
remove heat from both the top and bottom of the package. The bottom substrate material has very low thermal
resistance to the printed circuit board. An external heat
sink can be applied to the top of the device for excellent
heat sinking with airflow.
Figure 10 shows a temperature plot of the LTM4650 with
12V input, 1.0V output at 50A without heat sink and a no
airflow condition.
Safety Considerations
The LTM4650 modules do not provide isolation from VIN
to VOUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure. The device does support over current protection. A
temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal
shutdown that can be done by controlling the RUN pin.
Figure 10. Thermal Image 12V to 1V, 50A with No Air Flow and No Heat Sink (Based on 4-Layer
101mm × 114mm PCB Board Containing 2oz Copper on the Top, Bottom and All Internal Layers)
22
Rev. C
For more information www.analog.com
LTM4650
APPLICATIONS INFORMATION
Power Derating
The 0.9V and 1.5V power loss curves in Figure 12 and
Figure 13 can be used in coordination with the load current
derating curves in Figure 14 to Figure 21 for calculating
an approximate θJA thermal resistance for the LTM4650
with various heat sinking and airflow conditions. The
power loss curves are taken at room temperature, and
are increased with a 1.2 multiplicative factor at 120°C.
The derating curves are plotted with CH1 and CH2 in
parallel single output operation starting at 50A of load
with low ambient temperature. The output voltages are
0.9V and 1.5V. These are chosen to include the lower
and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several
temperature measurements in a controlled temperature
chamber along with thermal modeling analysis.
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus the
ambient operating temperature specifies how much module temperature rise can be allowed. As an example in
Figure 15, the load current is derated to ~35A at ~90°C
with 200LFM air but not heat sink and the power loss for
the 12V to 0.9V at 35A output is a ~5.6W loss. The 5.6W
loss is calculated with the ~4.7W room temperature loss
from the 12V to 0.9V power loss curve at 35A, and the 1.20
multiplying factor at 120°C junction temperature. If the
90°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 30°C divided
5.5W equals a 5.4°C/W θJA thermal resistance. Table 2
specifies a 5.5°C/W value which is pretty close. Table 2 and
Table 3 provide equivalent thermal resistances for 0.9V and
1.5V outputs with and without airflow and heat sinking.
The derived thermal resistances in Table 2 and Table 3 for
the various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be
derived from the efficiency curves and adjusted with the
above ambient temperature multiplicative factors. The
printed circuit board is a 1.6mm thick 4-layer board with
2oz copper on each layer. The PCB dimensions are 101mm
× 114mm. The BGA heat sinks are listed in Table 3.
Layout Checklist/Example
The high integration of LTM4650 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
Figure 11 gives a good example of the recommended layout. LGA and BGA PCB layouts are identical with the exception of circle pads for BGA (see Package Description).
Rev. C
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23
LTM4650
APPLICATIONS INFORMATION
CIN1
CIN2
VIN
M
L
K
GND
GND
J
H
G
COUT1
SGND
F
COUT2
E
D
C
B
A
1
2
3
4
5
VOUT1
6
7
8
9
10
11
GND
12
VOUT2
4650 F11
CNTRL
CNTRL
Figure 11. Recommended PCB Layout
Table 2. 0.9V Output
DERATING CURVE
Figure 14, Figure 15
Figure 14, Figure 15
Figure 14, Figure 15
Figure 16, Figure 17
Figure 16, Figure 17
Figure 16, Figure 17
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
AIRFLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
7.5
5.5
5
7
4.5
4
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
AIRFLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
7.5
5.5
5
7
4.5
4
Table 3. 1.5V Output
DERATING CURVE
Figure 18, Figure 19
Figure 18, Figure 19
Figure 18, Figure 19
Figure 19, Figure 20
Figure 19, Figure 20
Figure 19, Figure 20
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Wakefield
LTN20069-T5
wakefield-vette.com
24
Rev. C
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LTM4650
APPLICATIONS INFORMATION
Table 4. Two-Phase Single Output (see Figure 24)
CIN (CERAMIC)
VENDORS
BULK
PART NUMBER
Sun Electronics
CERAMIC
COUT (CERAMIC)
VALUE
25CE150AX
VENDORS
150μF, 25V
PART NUMBER
VALUE
Panasonic
ETPF470M5H
470μF, 2.5V, 5mΩ
220μF, 4V, 1206, X5R
Murata
GRM21BR61E106KA73L
10μF, 25V, 0805, X5R
Murata
GRM32ER60J227M
Taiyo Yuden
TMK212BBJ106KG-T
10μF, 25V, 0805, X5R
Taiyo Yuden
AMK325ABJ227MM-T 220uF, 4V, 1210, X5R
Murata
GRM31CR61E226KE15L
22μF, 25V, 1206, X5R
Taiyo Yuden
TMK316BBJ226ML-T
22μF, 25V, 1206, X5R
25% Load Step (0 to 12.5A), Ceramic Output Cap Only Solutions
CIN
(CERAMIC)
COUT
(BULK)
COUT
(CERAMIC)
CFF (FEEDFORWARD
CAP)
PK–PK
DEVIATION
(VPK–PK)
SETTLING
TIME
(tSETTLE)
LOAD
STEP
LOAD STEP
SLEW RATE
RFB
FREQ
VIN
VOUT
CIN*
(BULK)
12V
1.0V
150μF
22μF ×2
None
220μF ×8
470pF
47mV
30μs
12.5A
10A/μs
90.9kΩ
500kHz
12V
1.2V
150μF
22μF ×2
None
220μF ×8
470pF
49mV
30μs
12.5A
10A/μs
60.4kΩ
500kHz
12V
1.5V
150μF
22μF ×2
None
220μF ×8
470pF
50mV
30μs
12.5A
10A/μs
40.2kΩ
600kHz
12V
1.8V
150μF
22μF ×2
None
220μF ×8
470pF
53mV
30μs
12.5A
10A/μs
30.2kΩ
600kHz
25% Load Step (0 to 12.5A), Bulk + Ceramic Output Cap Solutions
CIN
(CERAMIC)
COUT
(BULK)
COUT
(CERAMIC)
CFF (FEEDFORWARD
CAP)
PK–PK
DEVIATION
(VPK–PK)
SETTLING
TIME
(tSETTLE)
LOAD
STEP
LOAD STEP
SLEW RATE
RFB
FREQ
VIN
VOUT
CIN*
(BULK)
12V
1.0V
150μF
22μF ×2
470μF ×2
220μF ×3
None
58mV
20μs
12.5A
10A/μs
90.9kΩ
500kHz
12V
1.2V
150μF
22μF ×2
470μF ×2
220μF ×3
None
58mV
20μs
12.5A
10A/μs
60.4kΩ
500kHz
12V
1.5V
150μF
22μF ×2
470μF ×2
220μF ×3
None
61mV
30μs
12.5A
10A/μs
40.2kΩ
600kHz
12V
1.8V
150μF
22μF ×2
470μF ×2
220μF ×3
None
64mV
50μs
12.5A
10A/μs
30.2kΩ
600kHz
8
8
7
7
6
5
4
3
5
4
3
2
1
1
0
10
30
20
LOAD CURRENT (A)
40
50
50
6
2
0
60
VIN = 12V
VIN = 5V
9
POWE LOSS (W)
POWE LOSS (W)
10
VIN = 12V
VIN = 5V
9
OUTPUT CURRENT (A)
10
0
30
20
0LFM
200LFM
400LFM
10
0
10
30
20
LOAD CURRENT (A)
40
4650 F12
Figure 12. 0.9V Output Power
Loss Curve
40
50
4650 F13
Figure 13. 1.5V Output Power
Loss Curve
0
25
35
45 55 65 75 85 95 105 115
AMBIENT TEMPERATURE (°C)
4650 F14
Figure 14. 5V to 0.9V
Derating Curve, No Heat Sink
Rev. C
For more information www.analog.com
25
LTM4650
60
60
50
50
50
40
30
20
0LFM
200LFM
400LFM
10
0
25
35
OUTPUT CURRENT (A)
60
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
APPLICATIONS INFORMATION
40
30
20
0LFM
200LFM
400LFM
10
45 55 65 75 85 95 105 115
AMBIENT TEMPERATURE (°C)
0
25
35
45 55 65 75 85 95 105 115
AMBIENT TEMPERATURE (°C)
60
50
50
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 16. 5V to 0.9V Derating
Curve, BGA Heat Sink
60
40
30
20
0LFM
200LFM
400LFM
25
35
0
45 55 65 75 85 95 105 115
AMBIENT TEMPERATURE (°C)
25
35
Figure 19. 12V to 1.5V
Derating Curve, No Heat Sink
50
50
40
30
20
0LFM
200LFM
400LFM
40
30
20
0LFM
200LFM
400LFM
10
45 55 65 75 85 95 105 115
AMBIENT TEMPERATURE (°C)
Figure 20. 5V to 1.5V Derating
Curve, BGA Heat Sink
4650 F17
Figure 17. 12V to 0.9V Derating
Curve, BGA Heat Sink
4650 F19
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
45 55 65 75 85 95 105 115
AMBIENT TEMPERATURE (°C)
45 55 65 75 85 95 105 115
AMBIENT TEMPERATURE (°C)
0
25
35
45 55 65 75 85 95 105 115
AMBIENT TEMPERATURE (°C)
4650 F20
26
35
0LFM
200LFM
400LFM
10
60
35
25
20
60
25
0
30
Figure 18. 5V to 1.5V Derating
Curve, No Heat Sink
0
0LFM
200LFM
400LFM
40
4650 F18
10
20
4650 F16
Figure 15. 12V to 0.9V
Derating Curve, No Heat Sink
0
30
10
4650 F15
10
40
4650 F21
Figure 21. 12V to 1.5V
Derating Curve, BGA Heat Sink
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Rev. C
LTM4650
APPLICATIONS INFORMATION
INTVCC
INTVCC
C10
4.7µF
R2
10k
PGOOD1
VIN
4.5V TO 15V
MODE_PLLIN CLKOUT INTVCC
+
CIN
(OPT)
C1
22µF
25V
×4
R7
100k
VOUT1
VOUTS1
TEMP
RUN1
TRACK1
VFB2
LTM4650
TRACK2
TRACK2
COMP1
fSET
C9
0.1µF
COUT1
100µF
6.3V
SW1
VFB1
RUN2
TRACK1
C5
0.1µF
EXTVCC PGOOD1
VIN
COMP2
PHASMD
VOUT2
SW2
R4
121k
PGOOD2
VOUTS2
SGND
GND
DIFFN
DIFFP
RFB2
60.4k
INTVCC
R3
10k
VOUT1
1.5V AT 25A
+
COUT2
470µF
6.3V
RFB1
40.2k
PGOOD2
COUT3
100µF
6.3V
VOUT2
1.2V AT 25A
+
COUT4
470µF
6.3V
DIFFOUT
4650 F22
Figure 22. Typical 4.5VIN to 15VIN, 1.5V and 1.2V at 25A Outputs
Rev. C
For more information www.analog.com
27
LTM4650
TYPICAL APPLICATIONS
INTVCC
INTVCC
C10
4.7µF
R2
10k
PGOOD
MODE_PLLIN
VIN
4.5V TO 15V
CIN
22µF
25V
×4
CLKOUT INTVCC
EXTVCC PGOOD1
VOUT1
VIN
RUN1
RUN
SW1
RUN2
VFB2
LTM4650
TRACK2
C9
0.1µF
TEMP
MONITOR
COMP1
R5
90.9k
470pF
COMP2
TEMP
VOUT2
VOUTS2
fSET
R4
121k
VOUT
1V
50A
VFB1
TRACK1
TRACK
COUT1
220µF
4V
×8
VOUT2
VOUTS1
SW2
PHASMD
SGND
PGOOD2
GND
DIFFN
DIFFP
PGOOD
DIFFOUT
4650 F23
*SEE TABLE 4
Figure 23. LTM4650 2-Phase, 1V at 50A Design
VOUT(AC)
20mV/DIV
54mV
LOAD STEP
10A/DIV
50µs/DIV
4650 F24
Figure 24. 25%, 12.5A Load Step Transient Waveform Of Figure 23 Circuit
28
Rev. C
For more information www.analog.com
LTM4650
TYPICAL APPLICATIONS
INTVCC
INTVCC
C10
4.7µF
R2
10k
PGOOD1
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
VIN
4.5V TO 15V
CIN
22µF
25V
×4
R6
100k
VOUT1
VIN
TEMP
VOUTS1
RUN1
SW1
RUN2
VFB1
TRACK1
C5
0.1µF
R9
60.4k
VOUT1
1.2V
R7
90.9k
VFB2
LTM4650
TRACK2
fSET
COMP2
VOUTS2
VOUT2
R4
121k
SW2
PGOOD2
GND
DIFFP
R8
90.9k
COMP1
PHASMD
SGND
COUT1
100µF
6.3V
×2
DIFFN
INTVCC
R3
10k
PGOOD2
+
VOUT1
1.2V
COUT2 25A
470µF
6.3V
R5
60.4k
COUT1
100µF
6.3V
×2
+
VOUT2
1V AT 25A
COUT2
470µF
6.3V
DIFFOUT
4650 F25
Figure 25. LTM4650 1.2V and 1V Output Tracking
Rev. C
For more information www.analog.com
29
LTM4650
TYPICAL APPLICATIONS
INTVCC
CLK1
VIN
4.5V TO 15V
R2
5k
PGOOD
MODE_PLLIN CLKOUT INTVCC
CIN1
22µF
25V
×3
INTVCC
C10
4.7µF
EXTVCC PGOOD1
VOUT1
VIN
R6
100k
TEMP
VOUTS1
RUN1
SW1
VFB1
RUN2
VFB2
RUN
LTM4650
TRACK1
TRACK
COMP1
TRACK2
COMP2
fSET
SGND
GND
DIFFP
DIFFN
COUT1
100µF
6.3V
+
COUT2
470µF
6.3V
COMP
VOUTS2
PGOOD2
COUT2
470µF
6.3V
R5
60.4k
SW2
R4
121k
+
VFB
VOUT2
PHASMD
COUT1
100µF
6.3V
PGOOD
DIFFOUT
VOUT
1.2V
100A
C16
4.7µF
CLK1
MODE_PLLIN CLKOUT INTVCC
CIN2
22µF
25V
×3
PGOOD
EXTVCC PGOOD1
VOUT1
VIN
R9
100k
RUN
TRACK
TEMP
VOUTS1
RUN1
SW1
RUN2
VFB1
TRACK1
VFB2
LTM4650
TRACK2
C19
0.22µF
COMP1
fSET
COMP2
PHASMD
VOUTS2
PGOOD2
GND
DIFFP
DIFFN
COUT2
470µF
6.3V
COUT1
100µF
6.3V
+
COUT2
470µF
6.3V
COMP
SW2
SGND
+
VFB
VOUT2
R10
121k
COUT1
100µF
6.3V
PGOOD
DIFFOUT
4650 F26
INTVCC
Figure 26. LTM4650 4-Phase, 1.2V at 100A
30
Rev. C
For more information www.analog.com
LTM4650
PACKAGE DESCRIPTION
LTM4650 Component BGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VOUT1
B1
VOUT1
C1
VOUT1
D1
GND
E1
GND
F1
GND
A2
VOUT1
B2
VOUT1
C2
VOUT1
D2
GND
E2
GND
F2
GND
A3
VOUT1
B3
VOUT1
C3
VOUT1
D3
GND
E3
GND
F3
GND
A4
VOUT1
B4
VOUT1
C4
VOUT1
D4
GND
E4
GND
F4
MODE_PLLIN
A5
VOUT1
B5
VOUT1
C5
VOUT1S
D5
VFB1
E5
TRACK1
F5
RUN1
A6
GND
B6
GND
C6
fSET
D6
SGND
E6
COMP1
F6
SGND
A7
GND
B7
GND
C7
SGND
D7
VFB2
E7
COMP2
F7
SGND
A8
VOUT2
B8
VOUT2
C8
VOUT2S
D8
TRACK2
E8
DIFFP
F8
DIFFOUT
A9
VOUT2
B9
VOUT2
C9
VOUT2
D9
GND
E9
DIFFN
F9
RUN2
A10
VOUT2
B10
VOUT2
C10
VOUT2
D10
GND
E10
GND
F10
GND
A11
VOUT2
B11
VOUT2
C11
VOUT2
D11
GND
E11
GND
F11
GND
A12
VOUT2
B12
VOUT2
C12
VOUT2
D12
GND
E12
GND
F12
GND
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
GND
H1
GND
J1
GND
K1
GND
L1
GND
M1
GND
G2
SW1
H2
GND
J2
VIN
K2
VIN
L2
VIN
M2
VIN
G3
GND
H3
GND
J3
VIN
K3
VIN
L3
VIN
M3
VIN
G4
PHASEMD
H4
GND
J4
VIN
K4
VIN
L4
VIN
M4
VIN
G5
CLKOUT
H5
GND
J5
GND
K5
GND
L5
VIN
M5
VIN
G6
SGND
H6
GND
J6
TEMP
K6
GND
L6
VIN
M6
VIN
G7
SGND
H7
GND
J7
EXTVCC
K7
GND
L7
VIN
M7
VIN
G8
PGOOD2
H8
INTVCC
J8
GND
K8
GND
L8
VIN
M8
VIN
G9
PGOOD1
H9
GND
J9
VIN
K9
VIN
L9
VIN
M9
VIN
G10
GND
H10
GND
J10
VIN
K10
VIN
L10
VIN
M10
VIN
G11
SW2
H11
GND
J11
VIN
K11
VIN
L11
VIN
M11
VIN
G12
GND
H12
GND
J12
GND
K12
GND
L12
GND
M12
GND
Rev. C
For more information www.analog.com
31
For more information www.analog.com
aaa Z
0.630 ±0.025 Ø 144x
4
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PACKAGE TOP VIEW
E
0.6350
0.0000
0.6350
PIN “A1”
CORNER
1.9050
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
Y
X
D
b1
DETAIL B
H2
MOLD
CAP
ccc Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
SUBSTRATE
A1
NOM
5.01
0.60
4.41
0.75
0.63
16.00
16.00
1.27
13.97
13.97
0.41
4.00
MAX
5.21
0.70
4.51
0.90
0.66
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
SUBSTRATE THK
0.46
MOLD CAP HT
4.05
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 144
0.36
3.95
MIN
4.81
0.50
4.31
0.60
0.60
A
A2
DETAIL B
PACKAGE SIDE VIEW
DIMENSIONS
ddd M Z X Y
eee M Z
DETAIL A
Øb (144 PLACES)
aaa Z
// bbb Z
(Reference LTC DWG # 05-08-1523 Rev A)
Z
32
Z
BGA Package
144-Lead (16mm × 16mm × 5.01mm)
e
L
b
K
J
G
G
F
E
e
PACKAGE BOTTOM VIEW
H
D
C
B
A
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
6
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
12
11
10
9
8
7
6
5
4
3
2
1
3
SEE NOTES
PIN 1
6
SEE NOTES
BGA 144 0517 REV A
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
F
b
M
DETAIL A
LTM4650
PACKAGE DESCRIPTION
Rev. C
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
LTM4650
REVISION HISTORY
REV
DATE
DESCRIPTION
A
05/16
Updated package drawing
B
12/16
C
08/18
Changed VOUT specs and condition from VOUT = 1.5V to 1.2V
PAGE NUMBER
32
3
Added Note 7
3, 5
Added MP Grade
2, 5
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
33
LTM4650
PACKAGE PHOTO
BGA
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4630
Lower Current than LTM4650; Dual 18A or Single 36A
Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V,
15mm × 15mm × 4.41mm LGA and 15mm × 15mm × 5.01mm BGA Packages
LTM4630A
Lower Current and Higher VOUT than LTM4650; Up to
5.3VOUT, Dual 18A or Single 26A
Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V,
15mm × 15mm × 4.41mm LGA Package
LTM4630-1
Lower Current than LTM4650 with External Compensation Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V,
15mm × 15mm × 5.01mm BGA Package
and ±0.8% (-1A) or ±1.5% (-1B) VOUT Accuracy
LTM4620
Lower Current than LTM4650; Dual 13A or Single 26A.
Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V,
15mm 15mm × 4.41mm LGA and 15mm × 15mm × 5.01mm BGA Packages
LTM4620A
Lower Current and Higher VOUT than LTM4650; Up to
5.3VOUT, Dual 13A or Single 26A.
Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 2.5V,
15mm 15mm × 4.41mm LGA and 15mm × 15mm × 5.01mm BGA Packages
LTM4628
Lower Current, Higher VIN and VOUT than LTM4650; Dual
8A or Single 16A
Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 26.5V, 0.6V ≤ VOUT ≤ 5.5V,
15mm 15mm × 4.32mm LGA and 15mm × 15mm × 4.92mm BGA Packages
LTM4677
Dual 18A or Single 36A with PSM
4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V. 16mm × 16mm × 5.01mm BGA Package
LTM4644
Quad 4A
4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V. 9mm × 15mm × 5.01mm BGA Package
LTM4639
Lower VIN (2.375V ≤ VIN ≤ 7V), 20A
0.6V ≤ VOUT ≤ 5.5V. 15mm × 15mm × 4.92mm BGA Package
34
Rev. C
08/18
www.analog.com
For more information www.analog.com
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