DS1007S-2+T&R

DS1007 7-1 Silicon Delay Line www.dalsemi.com FEATURES













PIN ASSIGNMENT All-silicon time delay IN1 1 16 IN3 7 independent buffered delays OUT1 2 15 OUT3 Delay tolerance ±2 ns Four delays can be custom set between 3 ns IN4 IN2 3 14 IN3 IN1 1 16 and 10 ns OUT2 4 13 OUT4 OUT3 OUT1 15 2 Three delays can be custom set between 9 ns 14 3 IN4 IN2 VCC GND 5 12 and 40 ns OUT4 4 OUT2 13 OUT7 11 IN5 6 5 GND VCC 12 Delays are stable and precise OUT7 6 11 IN5 OUT5 7 10 Economical IN7 7 IN7 10 OUT5 Auto-insertable, low profile 9 IN6 8 OUT6 IN6 8 OUT6 9 Surface mount 16-pin SOIC DS1007 16-Pin DIP (300-mil) DS1007S 16-Pin SOIC Low-power CMOS See Mech. Drawings Section (300-mil) TTL/CMOS-compatible See Mech. Drawings Section Vapor phase, IR and wave solderable Custom specifications available PIN DESCRIPTION Quick turn prototypes IN1 - IN7 - Inputs Out1 – Out7 - Outputs GND - Ground VCC - +5 Volts DESCRIPTION The DS1007 7-in-1 Silicon Delay Line provides seven independent delay times which are set by Dallas Semiconductor to the customer’s specification. The delay times can be set from 3 ns to 40 ns with an accuracy of ±2 ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC. Since the DS1007 is an all-silicon solution, better economy and reliability are achieved when compared to older methods using hybrid technology. The DS1007 reproduces the input logic state at the output after the fixed delay. Dallas Semiconductor can customize standard products to meet special needs. For special requests and rapid delivery, call (972) 371–4348. 1 of 6 111799 DS1007 LOGIC DIAGRAM Figure 1 PART NUMBER DELAY TABLE (tPLH) Table 1 PART # OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 DS1007-1 3ns 4ns 5ns 6ns 9ns 13ns 18ns DS1007-2 4 6 8 10 12 14 16 DS1007-3 3 3 3 3 10 10 10 DS1007-4 4 4 4 4 12 12 12 DS1007-5 5 5 5 5 15 15 15 DS1007-6 6 6 6 6 20 20 20 DS1007-7 7 7 7 7 25 25 25 DS1007-8 8 8 8 8 30 30 30 DS1007-9 9 9 9 9 35 35 35 DS1007-10 10 10 10 10 40 40 40 DS1007-11 3 4 6 8 10 12 14 DS1007-12 3 4 6 8 10 15 20 DS1007-13 3 4 6 8 12 15 20 DS1007-14 7 7 7 7 9 9 9 Custom delays available. Out 1 through Out 4 can be custom set from 3 to 10 ns (leading edge only accuracy). Out 5 through Out 7 can be set from 9 to 40 ns (both leading and trailing edge accuracy). 2 of 6 DS1007 TIMING DIAGRAM: SILICON DELAY LINE Figure 2 TEST CIRCUIT Figure 3 3 of 6 DS1007 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +7.0V 0°C to 70°C -55°C to +125°C 260°C for 10 seconds 50 mA for 1 second * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER SYM Supply Voltage High Level Input Voltage Low Level Input Voltage Input Leakage Current Active Current High Level Output Current Low Level Output Current IOH TEST CONDITION (0°C to 70°C; VCC = 5.0V ± 5%) MIN TYP MAX UNITS NOTES VCC VIH 4.75 2.2 5.00 5.25 VCC + 0.5 V V 1 1 VIL -0.5 0.8 V 1 -1.0 1.0 uA 70.0 mA -1.0 mA II 0.0V ≤ VI ≤ VCC ICC VCC=Max; Period=Min. VCC=Min. VOH=2.4V VCC=Min. VOL=0.5V IOL 40.0 12.0 AC ELECTRICAL CHARACTERISTICS PARAMETER Input Pulse Width Input to Output (leading edge) Power-up Time SYMBOL tWI tPLH tPU Period MIN 100% of tPLH mA (TA = 25°C; VCC = 5V ± 5%) TYP MAX Table 1 100 3 (tWI) CAPACITANCE PARAMETER Input Capacitance 2 UNITS ns ns NOTES ms ns 7 6 3, 4, 5 (TA = 25°C) SYMBOL CIN MIN 4 of 6 TYP 5 MAX 10 UNITS pF NOTES DS1007 NOTES: 1. All voltages are referenced to ground. 2. Measured with outputs open. 3. VCC = 5V @25°C. Delays accurate on rising edges within ±2 ns. 4. See Test Conditions below. 5. All output delays in the same speed output tend to vary unidirectionally with temperature or voltage range (i.e., if Out 2 slows down, all other outputs also slow down). 6. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling, layout, etc.). 7. tPU = 0 ms for Out 1 through Out 4. TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of the corresponding output pulse. TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1007. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected between the input and each output. Each output is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus. 5 of 6 DS1007 TEST CONDITIONS INPUT: Ambient Temperature: Supply Voltage (VCC): Input Pulse: Source Impedance: Rise and Fall Time: Pulse Width: Period: 25°C ± 3°C 5.0V ± 0.1V High = 3.0V ± 0.1V Low = 0.0V ± 0.1V 50 ohm max. 3.0 ns max. 500 ns 1 µs OUTPUT: Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on the rising edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. 6 of 6