DS1010S-50+T&R

DS1010 10-Tap Silicon Delay Line www.dalsemi.com FEATURES












All-silicon time delay 10 taps equally spaced Delays are stable and precise Leading and trailing edge accuracy Delay tolerance ±5% or ±2 ns, whichever is greater Economical Auto-insertable, low profile Standard 14-pin DIP or 16-pin SOIC Low-power CMOS TTL/CMOS-compatible Vapor phase, IR and wave solderable Custom delays available Fast turn prototypes PIN ASSIGNMENT IN1 1 14 VCC NC 2 13 TAP 1 TAP 2 3 12 TAP 3 TAP 4 4 11 TAP 5 NC NC TAP 2 TAP 4 IN1 TAP 6 5 10 TAP 7 TAP 8 6 9 TAP 9 GND 7 8 TAP 10 DS1010 14-Pin DIP (300-mil) See Mech. Drawings Section TAP 6 TAP 8 GND 1 2 3 4 5 6 7 16 15 14 VCC NC 13 12 11 10 TAP 3 TAP 5 8 9 TAP 1 TAP 7 TAP 9 TAP 10 DS1010S 16-Pin SOIC (300-mil) See Mech. Drawings Section PIN DESCRIPTION TAP 1 - TAP 10 VCC GND NC IN - TAP Output Number - 5 Volts - Ground - No Connection - Input DESCRIPTION The DS1010 series delay line has ten equally spaced taps providing delays from 5 ns to 500 ns. The devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines. Alternatively, a 16-pin SOIC is available for surface mount technology which reduces PC board area. Since the DS1010 is an all-silicon solution, better economy is achieved when compared to older methods using hybrid techniques. The DS1010 series delay lines provide a nominal accuracy of ±5% or ±2 ns, whichever is greater. The DS1010 reproduces the input logic state at the TAP 10 output after a fixed delay as specified by the dash number extension of the part number. The DS1010 is designed to produce both leading and trailing edge with equal precision. Each tap is capable of driving up to 10 74LS type loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests and rapid delivery, call (972) 371-4348. 1 of 6 111799 DS1010 LOGIC DIAGRAM Figure 1 PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1 CATALOG P/N DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010-100 DS1010-125 DS1010-150 DS1010-175 DS1010-200 DS1010-250 DS1010-300 DS1010-350 DS1010-400 DS1010-450 DS1010-500 Custom delays available. TOTAL DELAY 50 60 75 80 100 125 150 175 200 250 300 350 400 450 500 2 of 6 DELAY/TAP (ns) 5 6 7.5 8 10 12.5 15 17.5 20 25 30 35 40 45 50 DS1010 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +7.0V 0°C to 70°C -55°C to +125°C 260°C for 10 seconds 50 mA for 1 second * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER SYM Supply Voltage High Level Input Voltage Low Level Input Voltage Input Leakage Current Active Current High Level Output Current Low Level Output Current IOH TEST CONDITION (0°C to 70°C; VCC = 5.0V ± 5%) MIN TYP MAX UNITS NOTES VCC VIH 4.75 2.2 5.00 5.25 VCC + 0.5 V V 1 1 VIL -0.5 0.8 V 1 -1.0 1.0 µA 150 mA -1.0 mA II 0.0V ≤ VI ≤ VCC ICC VCC=Max; Period=Min. VCC=Min. VOH=4 VCC=Min. VOL=0.5 IOL 40 12 AC ELECTRICAL CHARACTERISTICS PARAMETER Input Pulse Width Input to Tap Delay (leading edge) Input to Tap Delay (trailing edge) Power-up Time SYMBOL tWI tPLH MIN tPU Period mA (TA = 25°C; VCC = 5V ± 5%) TYP MAX Table 1 UNITS ns ns Table 1 ns 40% of TAP 10 tPLH tPHL 100 4 (tWI) CAPACITANCE PARAMETER Input Capacitance 2 ms ns NOTES 8 3, 4, 5, 6, 7, 9 3, 4, 5, 6, 7, 9 8 (TA = 25°C) SYMBOL CIN MIN 3 of 6 TYP 5 MAX 10 UNITS pF NOTES DS1010 NOTES: 1. All voltages are referenced to ground. 2. Measured with outputs open. 3. VCC = 5V @ 25°C. Input-to-tap delays accurate on both rising and falling edges within ±2 ns or ±5% whichever is greater. 4. See “Test Conditions” section. 5. For DS1010 delay lines with a TAP 10 delay of 100 ns or greater, temperature variations from 25°C to 0°C or 70°C may produce an additional input-to-tap delay shift of ±2ns or ±3%, whichever is greater. 6. For DS1010 delay lines with a TAP 10 delay less than 100 ns, temperature variations from 25°C to 0°C or 70°C may produce an additional input-to-tap delay shift of ±1 ns or ±9%, whichever is greater. 7. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP 1 slows down, all other taps will also slow down; TAP 3 can never be faster than TAP 2. 8. Pulse width and period specifications may be exceeded; however, accuracy will be applicationsensitive (decoupling, layout, etc.). 9. Certain high-frequency applications not recommended for -50 in 16-pin package. Consult factory. TIMING DIAGRAM: SILICON DELAY LINE Figure 2 4 of 6 DS1010 TEST CIRCUIT Figure 3 TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any tap output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any tap output pulse. 5 of 6 DS1010 TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1010. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus. TEST CONDITIONS INPUT: Ambient Temperature: Supply Voltage (VCC): Input Pulse: Source Impedance: Rise and Fall Time: Pulse Width: Period: 25°C ± 3°C 5.0V ± 0.1V High = 3.0V ± 0.1V Low = 0.0V ± 0.1V 50 ohm max. 3.0 ns max. 500 ns (1 µs for -500) 1 µs ( 2 µs for -500) OUTPUT: Each output is loaded with the equivalent of one 74FO4 input gate. Delay is measured at the 1.5V level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. 6 of 6