DS1343/DS1344
Low-Current SPI/3-Wire RTCs
General Description
The DS1343/DS1344 low-current real-time clocks (RTCs)
are timekeeping devices that provide an extremely low
standby current, permitting longer life from a backup
supply source. The devices also support high-ESR
crystals, broadening the pool of usable crystals for the
devices. The clock/calendar provides seconds, minutes,
hours, day, date, month, and year information. The date
at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections
for leap year. The clock operates in either 24-hour or
12-hour format with an AM/PM indicator.
Address and data are transferred serially through an
SPI or 3-wire interface. Two programmable time-of-day
alarms are provided. Each alarm can generate an interrupt on a combination of seconds, minutes, hours, and
day. Don’t-care states can be inserted into one or more
fields if it is desired for them to be ignored for the alarm
condition. The time-of-day alarms can be programmed
to assert two different interrupt outputs, or they can be
combined to assert one common interrupt output. Both
interrupt outputs operate when the device is powered by
either VCC or VBAT.
The devices are available in a lead-free/RoHS-compliant,
20-pin TSSOP or 14-pin TDFN package, and support a
-40°C to +85°C extended industrial temperature range.
Applications
Medical
Features
S Low Timekeeping Current of 250nA (typ)
S Compatible with Crystal ESR Up to 100kI
S Versions Available to Support Either 6pF or
12.5pF Crystals
S RTC Counts Seconds, Minutes, Hours, Day, Date,
Month, and Year with Leap Year Compensation
Valid Through 2099
S Power-Fail and Switch Circuitry
S Three Operating Voltages
1.8V ±5%
3.0V±10%
3.3V ±10%
S Trickle-Charge Capability
S Maintain Time Down to 1.15V (typ)
S Support Motorola SPI Modes 1 and 3, or Standard
3-Wire Interface
S Burst Mode for Reading/Writing Successive
Addresses in Clock/RAM
S 96-Byte Battery-Backed NV RAM for Data Storage
S Two Time-of-Day Alarms with Two Interrupt
Outputs
S Industrial Temperature Range
S 20-Pin TSSOP or 14-Pin TDFN Package
S Underwriters Laboratories (UL) Recognized
Handheld Devices
Typical Operating Circuit
Telematics
Embedded Timestamping
VCC
RPU
INT
RST
μP
Ordering Information appears at end of data sheet.
3-WIRE
PORT
VCC
INT0
PF
INT1
CE
SCLK
SDI
SDO
X1
DS1343
DS1344
X2
VBAT
SERMODE GND
NOTE: SHOWN IN 3-WIRE I/O CONFIGURATION.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-5801; Rev 2; 10/14
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC or VBAT
Relative to Ground.............................................-0.3V to +6.0V
Voltage Range on Any Nonpower Pin
Relative to Ground................................. -0.3V to (VCC + 0.3V)
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature Maximum......................................+150NC
Storage Temperature Range............................. -55NC to +125NC
Lead Temperature (soldering, 10s).................................+260NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (BJA)...........91NC/W
Junction-to-Case Thermal Resistance (BJC)................20NC/W
TDFN
Junction-to-Ambient Thermal Resistance (BJA)...........54NC/W
Junction-to-Case Thermal Resistance (BJC)..................8NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
Operating Voltage Range
Minimum Timekeeping Voltage
Backup Voltage
SYMBOL
VCC
VBATTMIN
CONDITIONS
MIN
TYP
MAX
DS134_-18
1.71
1.8
5.5
DS134_-3
2.7
3.0
5.5
DS134_-33
3.0
3.3
5.5
1.15
1.3
V
TA = +25NC
UNITS
V
VBAT
1.3
5.5
V
Logic 1 Input
VIH
0.7 x
VCC
VCC +
0.3
V
Logic 0 Input
VIL
-0.3
0.3 x
VCC
V
MAX
UNITS
-3 or -33: fSCLK = 4MHz (Note 4)
400
FA
VCC = 3.63V
120
VCC = VCC(MAX)
160
VCC = 3.3V
130
VCC = VCC(MAX)
175
VCC = 1.89V
120
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to +5.5V, VBAT = +1.3V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER
Power-Supply Active Current
SYMBOL
ICCA
CONDITIONS
-33
Power-Supply Standby Current
(Note 5)
ICCS
-3
-18
Backup Leakage Current
Backup Current (Oscillator Off)
Backup Current
(Note 6)
2
IBATLKG
IBAT
DS1343
IBAT1
DS1344
MIN
TYP
VCC = VCC(MAX)
VCC > VPF
TA = +25NC, VCC = 0V, EOSC = 1
VBAT = 3V
200
-100
+25
VBAT = VBAT(MAX)
+100
nA
100
nA
250
VBAT = VBAT(MAX)
VBAT = 3V
FA
500
350
nA
600
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to +5.5V, VBAT = +1.3V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER
Backup Current
(Note 7)
SYMBOL
CONDITIONS
MIN
VBAT = 3V
DS1343
IBAT2
DS1344
TYP
MAX
UNITS
300
VBAT = VBAT(MAX)
600
VBAT = 3V
400
VBAT = VBAT(MAX)
nA
700
Input Leakage (CE, SERMODE,
SCLK, SDI)
II
VIN = 0V to VCC
-0.1
+0.1
FA
Output Leakage
(INT0, INT1, PF, SDO)
IO
CE = VIL, no alarms
-0.1
+0.1
FA
Output Logic 1 (PF, SDO)
IOH
Output Logic 0
(INT0, INT1, PF, SDO)
IOL
Power-Fail Trip Point
VPF
Switchover Voltage
Trickle-Charger Resistors
VSW
-3 or -33: VOH = 2.4V
-1
mA
-18: VOH = 1V
-0.5
-3 or -33: VOL = 0.4V
3.0
-18: VOL = 0.4V
2.0
VBAT R 1.3V R VCC + 0.2V, VOL = 0.2V
(Note 8)
0.25
-18
1.51
1.6
1.71
-3
2.45
2.6
2.70
-33
2.70
2.88
3.0
mA
VBAT > VPF
VPF
VBAT < VPF
VBAT > VCC
R1
1
R2
2
R3
4
V
V
kI
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER
SCLK Frequency
SYMBOL
fSCLK
CONDITIONS
MIN
1
-3 or -33
DC
4
tDC
30
SCLK to Data Hold
tCDH
30
tCDD
SCLK Low Time
tCL
SCLK High Time
tCH
Maxim Integrated
MAX
DC
Data to SCLK Setup
SCLK to Data Delay
TYP
-18
ns
240
-3 or -33
80
-18
400
110
-18
400
-3 or -33
110
MHz
ns
-18
-3 or -33
UNITS
ns
ns
ns
3
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 3)
SCLK Rise and Fall
tR, tF
CE to SCLK Setup
tCC
400
ns
SCLK to CE Hold
tCCH
100
ns
CE Inactive Time
tCWH
CE to Output High-Z
tCDZ
Oscillator Stop Flag (OSF) Delay
tOSF
200
-18
500
-3 or -33
400
(Note 9)
ns
ns
80
ns
25
100
ms
TYP
MAX
UNITS
20
40
ms
POWER-UP/DOWN CHARACTERISTICS
(TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
Recovery at Power-Up
CONDITIONS
MIN
tREC
VCC Fall Time (VPF to 0V)
tVCCF
150
Fs
VCC Rise Time (0V to VPF)
tVCCR
0
Fs
CAPACITANCE
(TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
CI
(Note 10)
10
pF
Output Capacitance
CO
(Note 10)
15
pF
CRYSTAL PARAMETERS
PARAMETER
Nominal Frequency
SYMBOL
Series Resistance
ESR
Load Capacitance
CL
Note
Note
Note
Note
Note
Note
Note
Note
Note
4
CONDITIONS
fO
MIN
TYP
MAX
32.768
kHz
100
DS1343
6
DS1344
12.5
UNITS
kI
pF
2: Voltage referenced to ground.
3: Limits at TA = -40°C are guaranteed by design and not production tested.
4: CE = VCC, VSCLK = VCC to GND, IOUT = 0mA, trickle charger disabled.
5: CE = GND, IOUT = 0mA, EOSC = EGFIL = DOSF = 0, trickle charger disabled.
6: VCC = 0V, EGFIL = 0, DOSF = 1.
7: VCC = 0V, EGFIL = 1, DOSF = 0.
8: Applies to INT0 and INT1.
9: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set.
10: Guaranteed by design; not 100% production tested.
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
SPI Write Timing
tCWH
CE
tCCH
tF
tCC
tCL
tCH
tR
SCLK*
tDC
SDI
tCDH
tCDH
A6
R/W = 1
A0
D7
WRITE ADDRESS BYTE
D0
WRITE DATA BYTE
*SCLK CAN BE EITHER POLARITY. TIMING SHOWN FOR CPOL = 1.
SERMODE = VCC.
SPI Read Timing
tCWH
CE
tCC
tCL
tCH
SCLK*
tCDH
tCDD
tDC
SDI
R/W = 0
A6
SDO
tCDZ
A0
D7
WRITE ADDRESS BYTE
D0
READ DATA BYTE
*SCLK CAN BE EITHER POLARITY. TIMING SHOWN FOR CPOL = 1.
SERMODE = VCC.
Maxim Integrated
5
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
3-Wire Write Timing
tCWH
CE
tCCH
tCC
tR
tCL
tF
SCLK
tCH
tCDH
tDC
A0
I/O*
A1
R/W = 1
D0
WRITE ADDRESS BYTE
D7
WRITE DATA BYTE
*I/O IS SDI AND SDO CONNECTED TOGETHER.
SERMODE = GND.
3-Wire Read Timing
tCWH
CE
tCC
tCL
tCDZ
tCDD
SCLK
I/O*
tCH
tCDH
tDC
A0
A1
WRITE ADDRESS BYTE
R/W = 0
D0
D7
READ DATA BYTE
*I/O IS SDI AND SDO CONNECTED TOGETHER.
SERMODE = GND.
6
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
fSCLK = 4MHz
300
200
fSCLK = 1MHz
100
4.0
4.5
5.0
320
TA = +85°C
TA = +25°C
TA = -40°C
300
EGFIL = 1
DOSF = 0
IOUT = 0mA
TA = +85°C
280
260
5.5
TA = +25°C
240
TA = -40°C
220
200
180
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
BATTERY VOLTAGE (V)
BATTERY VOLTAGE (V)
DS1344 BATTERY CURRENT1
vs. BATTERY VOLTAGE
DS1344 BATTERY CURRENT2
vs. BATTERY VOLTAGE
440
DS1343/4 toc05
EGFIL = 0, DOSF = 1, IOUT = 0mA
TA = +85°C
TA = +25°C
260
TA = -40°C
BATTERY CURRENT (nA)
BATTERY CURRENT (nA)
5.0
DS1343/4 toc04
340
DS1343/4 toc03
EGFIL = 0
DOSF = 1
IOUT = 0mA
300
240
4.5
DS1343 BATTERY CURRENT2
vs. BATTERY VOLTAGE
340
280
4.0
DS1343 BATTERY CURRENT1
vs. BATTERY VOLTAGE
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
320
3.5
SUPPLY VOLTAGE (V)
140
360
TA = -40°C
3.0
160
380
80
SUPPLY VOLTAGE (V)
220
180
90
5.5
BATTERY CURRENT (nA)
BATTERY CURRENT (nA)
3.5
240
200
TA = +25°C
100
60
3.0
260
TA = +85°C
110
70
0
280
120
DS1343/4 toc06
SUPPLY CURRENT (µA)
400
CE = VIL
IOUT = 0mA
130
SUPPLY CURRENT (µA)
TA = +25°C
CE = VIH
IOUT = 0mA
500
140
DS1343/4 toc01
600
POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE
DS1343/4 toc02
POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE
EGFIL = 1, DOSF = 0, IOUT = 0mA
390
TA = +85°C
TA = +25°C
340
290
TA = -40°C
220
240
200
Maxim Integrated
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
BATTERY VOLTAGE (V)
BATTERY VOLTAGE (V)
7
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Pin Configurations
VCC
SERMODE
PF
SDO
SDI
SCLK
CE
TOP VIEW
14
13
12
11
10
9
8
TOP VIEW
N.C.
17
N.C.
16
SDO
6
15
SDI
INT0
7
14
SCLK
N.C.
8
13
N.C.
INT1
9
12
CE
GND
10
11
SERMODE
TSSOP
DS1343
DS1344
EP
+
1
2
3
4
5
6
7
GND
5
PF
INT1
4
X2
18
N.C.
N.C.
DS1343
DS1344
N.C.
INT0
3
VCC
19
X2
X1
20
X1
2
VBAT
1
N.C.
+
VBAT
TDFN
(3mm × 3mm)
Pin Descriptions
PIN
NAME
FUNCTION
TSSOP
TDFN-EP
1
1
VBAT
Battery Input for Standard +3V Lithium Cell or Other Energy Source. UL recognized
to ensure against reverse charging current when used in conjunction with a primary
lithium battery.
2, 4, 6, 8,
13, 17, 19
5
N.C.
No Connection. N.C. pins can be connected to GND to reduce noise around the
crystal inputs.
3
2
X1
5
3
X2
7
9
8
4
6
Connections for Standard 32.768kHz Quartz Crystal (see the Crystal Characteristics
table). The devices can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator and the X2 pin is left
unconnected.
INT0
Active-Low Interrupt 0 Output. INT0 is an active-low output that can be used as
an interrupt output to a processor. INT0 can be programmed to be asserted by
only Alarm 0, or can be programmed to be asserted by either Alarm 0 or Alarm 1.
INT0 remains low as long as the status bit causing the interrupt is present and the
corresponding interrupt enable bit is set. INT0 operates when the component is
powered by VCC or VBAT. INT0 is an open-drain output and requires an external
pullup resistor.
INT1
Active-Low Interrupt 1 Output. INT1 is an active-low output that can be used either
as an interrupt output to a processor or a 32kHz square-wave output. INT1 can be
programmed to be asserted by Alarm 1 only. INT1 remains low as long as the status
bit causing the interrupt is present and the corresponding interrupt enable bit is set.
INT1 operates when the component is powered by VCC or VBAT. INT1 is an opendrain output and requires an external pullup resistor.
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Pin Descriptions (continued)
PIN
NAME
FUNCTION
TSSOP
TDFN-EP
10
7
GND
11
13
SERMODE
12
8
CE
14
9
SCLK
15
10
SDI
Serial-Data Input. When SPI communication is selected, SDI is the serial-data input
for the SPI bus. When 3-wire communication is selected, this pin must be connected
to SDO (SDI and SDO function as a single I/O pin when connected together).
Ground
Serial-Interface Mode Input. When connected to GND, standard 3-wire
communication is selected. When connected to VCC, SPI communication is selected.
Chip Enable. The chip-enable signal must be asserted high during a read or a write
for either 3-wire or SPI communications.
Serial-Clock Input. SCLK is used to synchronize data movement on the serial
interface for either 3-wire or SPI communications.
16
11
SDO
Serial-Data Output. When SPI communication is selected, SDO is the serial-data
output for the SPI bus. When 3-wire communication is selected, this pin must be
connected to SDI (SDI and SDO function as a single I/O pin when connected
together).
18
12
PF
Active-Low Power-Fail Output. The PF pin is used to indicate loss of the primary
power supply (VCC). When VCC is less than VPF, the PF pin is driven low.
20
14
VCC
—
—
EP
Power-Supply Input
Exposed Pad (TDFN Only). Connect to GND or leave unconnected.
Functional Diagram
32.768kHz
X1
VCC
PF
VBAT
GND
POWER CONTROL
AND
TRICKLE CHARGER
ON_VCC
X2
OSCILLATOR AND
COUNTDOWN CHAIN
1Hz
INT0
CLOCK, CALENDAR, AND
ALARM REGISTERS
DS1343
DS1344
CONTROL
REGISTERS
CE
SCLK
SDI
SDO
N
INT1
N
SERIAL
INTERFACE
INPUT
SHIFT
REGISTER
USER RAM
SERMODE
Maxim Integrated
9
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Detailed Description
The DS1343/DS1344 low-current real-time clocks (RTCs)
are timekeeping devices that consume an extremely low
timekeeping current and also support high-ESR crystals,
broadening the pool of usable crystals for the device.
The devices provide a full binary-coded decimal (BCD)
clock calendar that is accessed by a simple serial interface. The clock/calendar provides seconds, minutes,
hours, day, date, month, and year information. The date
at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections
for leap year through 2099. The clock operates in either
a 24-hour or 12-hour format with an AM/PM indicator. In
addition, 96 bytes of NV RAM are provided for data storage. The devices maintain the time and date, provided
that the oscillator is enabled, as long as at least one supply is at a valid level.
Both devices provide two programmable time-of-day
alarms. Each alarm can generate an interrupt on a programmable combination of seconds, minutes, hours, and
day. Don’t-care states can be inserted into one or more
fields if it is desired for them to be ignored for the alarm
condition. The time-of day alarms can be programmed
to assert two different interrupt outputs or to assert one
common interrupt output. Both interrupt outputs operate
when the device is powered by VCC or VBAT.
The devices support a direct interface to SPI serial-data
ports or standard 3-wire interface. A straight-forward
address and data format is implemented in which data
transfers can occur one byte at a time or in multiple-byte
burst mode.
The devices have a built-in temperature-compensated
power-sense circuit that detects power failures and
automatically switches to the backup supply. The VBAT
pin can be configured to provide trickle charging of a
rechargeable voltage source, with selectable charging
resistance and diode-voltage drops.
I/O and Power-Switching Operation
The devices operate as slave devices on a 3-wire or SPI
serial bus. Access is obtained by selecting the part by
the CE pin and clocking data into/out of the part using
the SCLK and SDI/SDO pins. Multiple byte transfers
are supported within one CE high period; see the Serial
Peripheral Interface (SPI) section for more information.
The devices are fully accessible and data can be written and read when VCC is greater than VPF. However,
10
when VCC falls below VPF, the internal clock registers
are blocked from any access, and the device power is
switched from VCC to VBAT.
If VPF is less than the voltage on the backup supply, the
device power is switched from VCC to the backup supply when VCC drops below VPF. If VPF is greater than the
backup supply, the device power is switched from VCC
to the backup supply when VCC drops below the backup
supply. The registers are maintained from the backup
supply source until VCC is returned to nominal levels.
The Functional Diagram illustrates the main elements.
Freshness Seal Mode
When a battery is first attached to the device, the device
does not immediately provide battery-backup power to
the RTC or internal circuitry. After VCC exceeds VPF,
the devices leave the freshness seal mode and provide
battery-backup power whenever VCC subsequently falls
below VBAT. This mode allows attachment of the battery
during product manufacturing, but no battery capacity is
consumed until after the system has been activated for
the first time. As a result, minimum battery energy is used
during storage and shipping.
Oscillator Circuit
The devices use an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors or
capacitors to operate. The DS1343 includes integrated
capacitive loading for a 6pF CL crystal, and the DS1344
includes integrated capacitive loading for a 12.5pF CL
crystal. See the Crystal Parameters table for the external
crystal parameters. The Functional Diagram shows a
simplified schematic of the oscillator circuit. The startup
time is usually less than one second when using a crystal
with the specified characteristics.
Clock Accuracy
When running from the internal oscillator, the accuracy of
the clock is dependent upon the accuracy of the crystal
and the accuracy of the match between the capacitive
load of the oscillator circuit and the capacitive load for
which the crystal was trimmed. Additional error is added
by crystal frequency drift caused by temperature shifts.
External circuit noise coupled into the oscillator circuit
can result in the clock running fast. Figure 1 shows a
typical PCB layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal
Considerations with Dallas Real-Time Clocks for detailed
information.
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
GND
Figure 1. Layout Example
Register Map
Table 1 shows the devices’ register map. During a multibyte RTC access, if the address pointer reaches the
end of the register space (1Fh), it wraps around to location 00h. During a multibyte RAM access, if the address
pointer reaches the end of the register space (7Fh), it
wraps around to location 20h. On either the rising edge
of CE or an RTC address pointer wrap around, the current time is transferred to a secondary set of registers.
The time information is read from these secondary registers, while the clock continues to run. This eliminates the
need to reread the registers in case the main registers
update during a read.
Clock and Calendar (00h–06h)
The time and calendar information is obtained by reading
the appropriate register bytes. Table 1 shows the RTC
registers. The time and calendar are set or initialized by
writing the appropriate register bytes. The contents of
the time and calendar registers are in the BCD format.
The Day register increments at midnight and rolls over
from 7 to 1. Values that correspond to the day-of-week
are user defined, but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical time
and date entries result in undefined operation.
The devices can be run in either 12-hour or 24-hour
mode. Bit 6 of the Hours register is defined as the 12- or
24-hour mode-select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit,
with a content of 1 being PM. In the 24-hour mode, bit 5
is the 20-hour field. Changing the 12/24 mode-select bit
requires that the Hours data subsequently be reentered,
including the Alarm register (if used). The Century bit (bit
Maxim Integrated
7 of Month) is toggled when the Years register rolls over
from 99 to 00. On a power-on reset (POR), the time and
date are set to 00:00:00 01/01/00 (hh:mm:ss DD/MM/YY),
and the Day register is set to 01.
Alarms (07h–0Eh)
The devices contains two time-of-day/date alarms. Alarm
0 can be set by writing to registers 07h–0Ah. Alarm 1 can
be set by writing to registers 0Bh–0Eh. The alarms can
be programmed to activate the INT0 or INT1 outputs on
an alarm match condition (see Table 2). Bit 7 of each
of the time of day/date alarm registers are mask bits.
When all the mask bits for each alarm are 0, an alarm
only occurs when the values in the timekeeping registers
00h–06h match the values stored in the alarm registers.
The alarms can also be programmed to repeat every
second, minute, hour, or day. Configurations not listed
in the table result in illogical operation. POR values are
undefined.
When the RTC register values match alarm register
settings, the corresponding alarm flag bit (IRQF0 or
IRQF1) is set to 1 in the Status register. If the corresponding alarm interrupt enable bit (A0IE or A1IE) is
also set to 1 in the Control register, the alarm condition
activates the output(s) defined by the INTCN bit. Upon
an active alarm, clearing the associated IRQF[1:0] bit
deasserts the selected interrupt output while leaving
the alarm enabled for the next occurrence of a match.
Alternatively, clearing the A_IE bit deasserts the output
and inhibits further output activations.
The alarm flags are always active, fully independent of
the A_IE bit states. All alarm registers should be written
to logic zero to disable the alarm matching.
11
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Table 1. Register Map
ADDRESS
BIT 7
MSB
00h
0
10 Seconds
01h
0
10 Minutes
02h
0
12/24
AM/PM
20
Hours
10
Hours
03h
0
0
0
0
04h
0
0
05h
Century
BIT 6
BIT 5
BIT 3
BIT 2
RANGE
Seconds
Seconds
00–59
Minutes
Minutes
00–59
Hours
1–12 +
AM/PM
00–23
Day
1–7
Hour
0
10
Month
0
BIT 1
BIT 0
LSB
FUNCTION
Day
10 Date
0
06h
BIT 4
Date
Date
01–31
Month
Month/
Century
01–12 +
Century
Year
Year
00–99
00–59
10 Year
07h
A0M1
10 Seconds
Seconds
Alarm 0
Seconds
08h
A0M2
10 Minutes
Minutes
Alarm 0
Minutes
00–59
09h
A0M3
12/24
AM/PM
20
Hours
10
Hours
Hour
Alarm 0 Hours
1–12 +
AM/PM
00–23
0Ah
A0M4
0
0
0
Day
Alarm 0 Day
1–7
00–59
0Bh
A1M1
10 Seconds
Seconds
Alarm 1
Seconds
0Ch
A1M2
10 Minutes
Minutes
Alarm 1
Minutes
00–59
0Dh
A1M3
Hour
Alarm 1 Hours
1–12 +
AM/PM
00–23
AM/PM
20
Hours
12/24
10
Hours
0Eh
A1M4
0
0
0
Alarm 1 Day
1–7
0Fh
X
DOSF
EGFIL
SQW
INTCN
A1IE
A0IE
Control
—
10h
EOSC
OSF
Day
0
0
0
0
0
IRQF1
IRQF0
Status
—
11h
TCS3
TCS2
TCS1
TCS0
DS1
DS0
RS1
RS0
Trickle
Charger
—
12h–1Fh
Reserved
Reserved
—
20h–7Fh
User RAM
User RAM
00h–FFh
Note: Bits listed as 0 always read back as 0 and cannot be written to 1.
Table 2. Alarm Mask Bits
ALARM REGISTER MASK BITS (BIT 7)
ALARM RATE
A_M4
A_M3
A_M2
A_M1
1
1
1
1
Alarm once a second
1
1
1
0
Alarm when seconds match
1
1
0
0
Alarm when minutes and seconds match
1
0
0
0
Alarm when hours, minutes, and seconds match
0
0
0
0
Alarm when day, hours, minutes, and seconds match
12
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Control Register (0Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
1
X
DOSF
EGFIL
SQW
INTCN
A1IE
A0IE
0
0
0
0
0
0
0
BIT 7
EOSC: Enable oscillator. During battery backup, when EOSC is set to 0, the oscillator is enabled during backup operation. When set to 1, the oscillator is stopped when the device is powered by the backup supply. This
bit is set to logic 1 on the initial application of power.
BIT 6
Not used.
BIT 5
DOSF: Disable oscillator stop flag. When the DOSF bit is set to 1, sensing of the oscillator conditions that
would set the OSF bit are disabled. OSF remains at 0 regardless of what happens to the oscillator. This bit is
cleared (0) on the initial application of power.
BIT 4
EGFIL: Enable glitch filter. When the EGFIL bit is 1, the 5Fs glitch filter at the output of crystal oscillator is
enabled. The glitch filter is disabled when this bit is 0. This bit is cleared (0) on the initial application of power.
BIT 3
SQW: Enable square wave. When the SQW bit is set to 1, a 32kHz square wave is output on the INT1 output.
This bit is cleared (0) on the initial application of power.
BIT 2
INTCN: Interrupt control. This bit controls the relationship between the two time-of-day alarms and the two
interrupt output pins. When the INTCN bit is 1, a match between the timekeeping registers and the Alarm
0 registers activates the INT0 output (provided A0IE = 1), and a match between the timekeeping registers
and the Alarm 1 registers activates the INT1 output (provided A1IE = 1). When the INTCN bit is 0, a match
between the timekeeping registers and either the Alarm 0 registers or Alarm 1 registers activates the INT0 output (provided A0IE = A1IE = 1). The INT1 output has no function when INTCN = 0. The INTCN bit is cleared
(0) on the initial application of power.
BIT 1
A1IE: Alarm 1 interrupt enable. When A1IE is set to 0, the Alarm 1 interrupt function is disabled. When A1IE
is 1, the Alarm 1 interrupt function is enabled and is routed to either INT0 (if INTCN = 0) or INT1 (if INTCN
= 1). Regardless of the state of A1IE, a match between the timekeeping registers and the Alarm 1 registers
(0Bh–0Eh) sets the interrupt request 1 flag bit (IRQF1). The A1IE bit is cleared (0) when power is first applied.
BIT 0
A0IE: Alarm 0 interrupt enable. When A0IE is set to 0, the Alarm 0 interrupt function is disabled. When A0IE
is 1, the Alarm 0 interrupt function is enabled and is routed to INT0. Regardless of the state of A0IE, a match
between the timekeeping registers and the Alarm 0 registers (07h–0Ah) sets the interrupt register 0 flag bit
(IRQF0). The A0IE bit is cleared (0) when power is first applied.
Maxim Integrated
13
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Status Register (10h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OSF
0
0
0
0
0
IRQF1
IRQF0
1
0
0
0
0
0
0
0
OSF: Oscillator stop flag. If the OSF bit is 1, the oscillator either has stopped or was stopped for some period
and could be used to judge the validity of the clock and calendar data. This bit is edge triggered and is set to
1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a stop condition.
This bit remains at logic 1 until written to logic 0. Attempting to write OSF to 1 leaves the value unchanged.
BIT 7
The following are examples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The EOSC bit is a logic one during battery backup.
4) External influences on the crystal (i.e., noise, leakage, etc.).
BIT 1
IRQF1: Interrupt request 1 flag. A logic 1 in the IRQF1 bit indicates that the time matched the Alarm 1 registers. This flag can be used to generate an interrupt on either INT0 or INT1 depending on the status of the
INTCN bit in the Control register. If the INTCN bit is 0 and IRQF1 is 1 (and the A1IE bit is also 1), INT0 goes
low. If the INTCN bit is 1 and IRQF1 is 1 (and the A1IE bit is also 1), INT1 goes low. IRQF1 is cleared when
the address pointer is set to any of the Alarm 1 registers during an I/O transaction. The IRQF1 bit can also
be cleared by writing it to 0. This bit can only be written to 0. Attempting to write the IRQF1 bit to 1 leaves the
value unchanged.
BIT 0
IRQF0: Interrupt request 0 flag. A logic 1 in the IRQF0 bit indicates that the time matched the Alarm 0 registers. If the A0IE bit is also 1, INT0 goes low. IRQF0 is cleared when the address pointer is set to any of the
Alarm 0 registers during an I/O transaction. The IRQF0 bit can also be cleared by writing it to 0. This bit can
only be written to 0. Attempting to write the IRQF0 bit to 1 leaves the value unchanged.
Trickle Charger Register (11h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TCS3
TCS2
TCS1
TCS0
DS1
DS0
RS1
RS0
0
0
0
0
0
0
0
0
Register 11h controls the devices’ trickle-charge characteristics. The simplified schematic of Figure 2 shows
the basic components of the trickle charger. The tricklecharge select (TCS[3:0]) bits (bits 7:4) control the
selection of the trickle charger. To prevent accidental
enabling, only a pattern of 1010 enables the trickle
charger; all other patterns disable the trickle charger.
On the initial application of power, the devices power
up with the trickle charger disabled. The diode-select
14
(DS[1:0]) bits (bits 3:2) select whether or not a diode is
connected between VCC and VBAT. The resistor-select
(RS[1:0]) bits (bits 1:0) select the resistor that is connected between VCC and VBAT. The RS and DS bits
select the resistor and diodes, as shown in Table 3. The
user determines diode and resistor selection according
to the maximum current desired for secondary battery or
super cap charging. The maximum charging current can
be calculated using the equation that follows.
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
R1
1kΩ
R2
2kΩ
VCC
VBAT
R3
4kΩ
1 0F 18 SELECT
NOTE: ONLY 1010 CODE ENABLES CHARGER
TRICKLE
CHARGER
REGISTER
1 OF 2
SELECT
1 OF 3
SELECT
TCS = TRICKLE-CHARGER SELECT
DS = DIODE SELECT
RS = RESISTOR SELECT
TCS
TCS
TCS
TCS
DS
DS
RS
RS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Figure 2. Trickle Charger Block Diagram
Table 3. Trickle-Charger Resistor and Diode Select
TCS3
TCS2
TCS1
TCS0
DS1
DS0
RS1
RS0
FUNCTION
X
X
X
X
X
X
X
X
X
X
0
0
0
0
Disabled
X
X
X
X
X
X
1
1
X
X
Disabled
Disabled
1
0
1
0
0
1
0
1
No diode, 1kI
1
0
1
0
0
1
1
0
No diode, 2kI
1
0
1
0
0
1
1
1
No diode, 4kI
1
0
1
0
1
0
0
1
One diode, 1kI
1
0
1
0
1
0
1
0
One diode, 2kI
1
0
1
0
1
0
1
1
One diode, 4kI
0
0
0
0
0
0
0
0
Initial power-on state—disabled
X = Don’t care.
Assume, for the purposes of the example, that a system
power supply of 5V is applied to VCC and a super cap is
connected to VBAT. Also assume that the trickle charger
has been enabled with one diode and resistor R1. The
maximum current IMAX would be calculated as follows:
IMAX = (5.0V - diode drop)/R1 ≈ (5.0V - 0.6V)/2kΩ ≈
2.2mA
As the super cap charges, the voltage drop between
VCC and VBAT decreases, and therefore, the charge
current decreases.
Maxim Integrated
Serial Port Operation
The devices offer the flexibility to choose between two
serial-interface modes. The component can communicate with the SPI interface or with a standard 3-wire
interface. The interface method used is determined by
SERMODE. When SERMODE is connected to VCC, SPI
communication is selected. When SERMODE is connected to ground, standard 3-wire communication is
selected.
15
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a synchronous
bus for address and data transfer, and is used when
interfacing with the SPI bus on specific Motorola microcontrollers, such as the 68HC05C4 and the 68HC11A8.
The SPI mode of serial communication is selected by
connecting SERMODE to VCC. Four pins are used for the
SPI. The four pins are SDO (serial-data out), SDI (serialdata in), CE (chip enable), and SCLK (serial clock). The
IC is the slave device in an SPI application, with the
microcontroller being the master.
SDI and SDO are the serial-data input and output pins,
respectively, for the device. The CE input is used to
initiate and terminate a data transfer. SCLK is used to
synchronize data movement between the master (microcontroller) and the slave (IC) devices.
The input clock (SCLK), which is generated by the microcontroller, is active only during address and data transfer
to any device on the SPI bus. The inactive clock polarity
is programmable in some microcontrollers. The device
determines the clock polarity by sampling SCLK when
CE becomes active. Therefore, either SCLK polarity can
be accommodated. Input data (SDI) is latched on the
internal strobe edge and output data (SDO) is shifted out
on the shift edge (Figure 3). There is one clock for each
bit transferred. Address and data bits are transferred in
groups of eight, MSB first.
Address and Data Bytes
Address and data bytes are shifted MSB first into the
serial-data input (SDI) and out of the serial-data output
(SDO). Any transfer requires the address of the byte to
specify a write or read to either a RTC or RAM location,
followed by one or more bytes of data. Data is transferred out of the SDO for a read operation and into the
SDI for a write operation (Figure 4 and Figure 5).
The address byte is always the first byte entered after CE
is driven high. The most significant bit (R/W) of this byte
determines if a read or write takes place. If R/W is 0, one
or more read cycles occur. If R/W is 1, one or more write
cycles occur.
Data transfers can occur 1 byte at a time or in multiplebyte burst mode. After CE is driven high an address is
written to the device. After the address, one or more data
bytes can be written or read. For a single-byte transfer,
1 byte is read or written and then CE is driven low. For
a multiple-byte transfer, however, multiple bytes can
be read or written to the device after the address has
been written. Each read or write cycle causes the RTC
register or RAM address to automatically increment.
Incrementing continues until the device is disabled.
When the RTC address space is selected, the address
wraps to 00h after incrementing from 1Fh. When the
RAM address space is selected, the address wraps to
20h after incrementing from 7Fh.
CE
CPOL = 1
CPOL = 0
SCLK
SHIFT DATA OUT (READ)
DATA LATCH (WRITE)
SCLK
SHIFT DATA OUT (READ)
DATA LATCH (WRITE)
NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY.
NOTE 2: CPOL IS A BIT THAT IS SET IN THE MICROCONTROLLER’S CONTROL REGISTER.
NOTE 3: SDO REMAINS AT HIGH-Z UNTIL 8 BITS OF DATA ARE READY TO BE SHIFTED OUT DURING A READ.
Figure 3. Serial Clock as a Function of Microcontroller Clock Polarity (CPOL)
16
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
CE
SCLK*
1
SDI
A6
A5
A4
R/W
A3
A2
A1
A0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
SDO
*SCLK CAN BE EITHER POLARITY.
SERMODE = VCC.
Figure 4. SPI Single-Byte Write
CE
SCLK*
0
SDI
A6
R/W
SDO
A5
A4
HIGH-Z
D0
*SCLK CAN BE EITHER POLARITY.
SERMODE = VCC.
Figure 5. SPI Single-Byte Read
CE
SCLK
WRITE
SDI
ADDRESS
BYTE
SDI
ADDRESS
BYTE
READ
SDO
DATA
BYTE 0
DATA
BYTE 1
DATA
BYTE 0
DATA
BYTE 1
DATA
BYTE N
DATA
BYTE N
Figure 6. SPI Multibyte Burst Transfer
Maxim Integrated
17
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Reading and Writing in Burst Mode
Applications Information
3-Wire Interface
To achieve the best results when using the devices,
decouple the VCC power supply with a 0.01µF and/or
0.1µF capacitor. Use a high-quality, ceramic, surfacemount capacitor if possible. Surface-mount components
minimize lead inductance, which improves performance,
and ceramic capacitors tend to have adequate highfrequency response for decoupling applications.
Burst mode is similar to a single-byte read or write,
except that CE is kept high and additional SCLK cycles
are sent until the end of the burst. The clock registers
and the user RAM can be read or written in burst mode.
The address pointer wraps around to 00h after reaching
1Fh (RTC), and the address pointer wraps around to 20h
after reaching 7Fh (RAM). See Figure 6.
Power-Supply Decoupling
The 3-wire interface mode operates similarly to the SPI
mode. However, in 3-wire mode there is one I/O instead
of separate data-in and data-out signals. The 3-wire
interface consists of the I/O (SDI and SDO pins connected together), CE, and SCLK pins. In 3-wire mode,
each byte is shifted in LSB first, unlike SPI mode, where
each byte is shifted in MSB first.
Using Open-Drain Outputs
The INT0 and INT1 outputs are open drain and therefore
require external pullup resistors to realize a logic-high
output level.
Battery Charge Protection
The devices contain Maxim’s redundant battery-charge
protection circuit to prevent any charging of an external
battery. The DS1343 and DS1344 are recognized by
Underwriters Laboratories (UL) under file E141114.
As is the case with the SPI mode, an address byte is
written to the device followed by a single data byte or
multiple data bytes. Figure 7 illustrates a write cycle, and
Figure 8 illustrates a read cycle. In 3-wire mode, data is
input on the rising edge of SCLK and output on the falling
edge of SCLK.
CE
SCLK
I/O*
HIGH-Z
A0
A1
A2
A3
A4
A5
A6
1
D0
D1
D2
D3
D4
D5
D6
D7
R/W
*I/O IS SDI AND SDO CONNECTED TOGETHER.
SERMODE = GND.
Figure 7. 3-Wire Single-Byte Write
CE
SCLK
I/O*
HIGH-Z
A0
A1
A2
*I/O IS SDI AND SDO CONNECTED TOGETHER.
SERMODE = GND
A3
A4
A5
A6
0
D0
D1
D2
D3
D4
D5
D6
D7
R/W
Figure 8. 3-Wire Single-Byte Read
18
Maxim Integrated
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Ordering Information
PART
TEMP RANGE
TYP OPERATING
VOLTAGE (V)
OSC CL
(pF)
DS1343E-18+
-40NC to +85NC
1.8
6
20 TSSOP
DS1343E-3+
-40NC to +85NC
3.0
6
20 TSSOP
DS1343E-33+
-40NC to +85NC
3.3
6
20 TSSOP
DS1343D-18+
-40NC to +85NC
1.8
6
14 TDFN-EP*
DS1343D-3+
-40NC to +85NC
3.0
6
14 TDFN-EP*
DS1343D-33+
-40NC to +85NC
3.3
6
14 TDFN-EP*
DS1344E-18+
-40NC to +85NC
1.8
12.5
20 TSSOP
DS1344E-3+
-40NC to +85NC
3.0
12.5
20 TSSOP
DS1344E-33+
-40NC to +85NC
3.3
12.5
20 TSSOP
DS1344D-18+
-40NC to +85NC
1.8
12.5
14 TDFN-EP*
DS1344D-3+
-40NC to +85NC
3.0
12.5
14 TDFN-EP*
DS1344D-33+
-40NC to +85NC
3.3
12.5
14 TDFN-EP*
PIN-PACKAGE
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
SUBSTRATE CONNECTED TO GROUND
Maxim Integrated
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 TSSOP
U20+1
21-0066
90-0116
14 TDFN-EP
T1433+2
21-0137
90-0063
19
DS1343/DS1344
Low-Current SPI/3-Wire RTCs
Revision History
REVISION
NUMBER
REVISION
DATE
0
3/11
Initial release
1
12/11
Removed future status from several DS1344 parts in the Ordering Information table;
added UL recognized to the Features and Battery Charge Protection sections;
added IBATLKG and DS1344 IBAT1, IBAT2 specs to the DC Electrical Characteristics
section; added DS1344 Typical Operating Characteristics graphs
1, 2, 7, 18, 19
2
10/14
Added standby current and IOH and IOL for 3V and 1.8V versions, decreased active
current, increased SCLK to data delay and CE OT output high impedance, and
removed future product references
2, 3, 19
DESCRIPTION
PAGES
CHANGED
—
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
20
© 2014
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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