DS18S20-PAR+T&R

DS18S20-PAR 1-Wire Parasite-Power Digital Thermometer www.maxim-ic.com FEATURES · · · · · · · · · · PIN ASSIGNMENT Unique 1-Wire interface requires only one port pin for communication Derives power from data line (“parasite power”)—does not need a local power supply Multi-drop capability simplifies distributed temperature sensing applications Requires no external components ±0.5°C accuracy from –10°C to +85°C Measures temperatures from –55°C to +100°C (–67°F to +212°F) 9-bit thermometer resolution Converts temperature in 750 ms (max.) User–definable non-volatile temperature alarm settings Alarm search command identifies and addresses devices whose temperature is outside of programmed limits (temperature alarm condition) Ideal for use in remote sensing applications (e.g., temperature probes) that do not have a local power source DALLAS 18S20P 1 2 3 GND DQ NC · ® 1 2 3 (BOTTOM VIEW) TO-92 (DS18S20-PAR) PIN DESCRIPTION GND - Ground DQ - Data In/Out NC - No Connect DESCRIPTION The DS18S20-PAR digital thermometer provides 9–bit centigrade temperature measurements and has an alarm function with nonvolatile user-programmable upper and lower trigger points. The DS18S20-PAR does not need an external power supply because it derives power directly from the data line (“parasite power”). The DS18S20-PAR communicates over a 1-Wire bus, which by definition requires only one data line (and ground) for communication with a central microprocessor. It has an operating temperature range of –55°C to +100°C and is accurate to ±0.5°C over a range of –10°C to +85°C. Each DS18S20-PAR has a unique 64-bit identification code, which allows multiple DS18S20-PARs to function on the same 1–wire bus; thus, it is simple to use one microprocessor to control many DS18S20-PARs distributed over a large area. Applications that can benefit from this feature include HVAC environmental controls, temperature monitoring systems inside buildings, equipment or machinery, and process monitoring and control systems. 1-Wire is a registered trademark of Dallas Semiconductor. 1 of 20 111803 DS18S20-PAR DETAILED PIN DESCRIPTIONS Table 1 PIN 1 2 SYMBOL GND DQ 3 NC DESCRIPTION Ground. Data Input/Output pin. Open-drain 1-Wire interface pin. Also provides power to the device when used in parasite power mode (see “Parasite Power” section.) No Connect. Doesn’t connect to internal circuit. OVERVIEW The DS18S20-PAR uses Dallas’ exclusive 1-Wire bus protocol that implements bus communication using one control signal. The control line requires a weak pullup resistor since all devices are linked to the bus via a 3-state or open-drain port (the DQ pin in the case of the DS18S20-PAR). In this bus system, the microprocessor (the master device) identifies and addresses devices on the bus using each device’s unique 64-bit code. Because each device has a unique code, the number of devices that can be addressed on one bus is virtually unlimited. The 1-Wire bus protocol, including detailed explanations of the commands and “time slots,” is covered in the 1-WIRE BUS SYSTEM section of this datasheet. An important feature of the DS18S20-PAR is its ability to operate without an external power supply. Power is instead supplied through the 1-Wire pullup resistor via the DQ pin when the bus is high. The high bus signal also charges an internal capacitor (CPP), which then supplies power to the device when the bus is low. This method of deriving power from the 1-Wire bus is referred to as “parasite power.” Figure 1 shows a block diagram of the DS18S20-PAR, and pin descriptions are given in Table 1. The 64-bit ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte temperature register that stores the digital output from the temperature sensor. In addition, the scratchpad provides access to the 1-byte upper and lower alarm trigger registers (TH and TL). The TH and TL registers are nonvolatile (EEPROM), so they will retain their data when the device is powered down. DS18S20-PAR BLOCK DIAGRAM Figure 1 VPU PARASITE POWER CIRCUIT 4.7K MEMORY CONTROL LOGIC DS18S20-PAR DQ TEMPERATURE SENSOR INTERNAL VDD 64-BIT ROM AND 1-wire PORT CPP SCRATCHPAD ALARM HIGH TRIGGER (TH) REGISTER (EEPROM) ALARM LOW TRIGGER (TL) REGISTER (EEPROM) GND 8-BIT CRC GENERATOR 2 of 20 DS18S20-PAR PARASITE POWER The DS18S20-PAR’s parasite power circuit allows the DS18S20-PAR to operate without a local external power supply. This ability is especially useful for applications that require remote temperature sensing or that are very space constrained. Figure 1 shows the DS18S20-PAR’s parasite-power control circuitry, which “steals” power from the 1-Wire bus via the DQ pin when the bus is high. The stolen charge powers the DS18S20-PAR while the bus is high, and some of the charge is stored on the parasite power capacitor (CPP) to provide power when the bus is low. The 1-Wire bus and CPP can provide sufficient parasite power to the DS18S20-PAR for most operations as long as the specified timing and voltage requirements are met (refer to the DC ELECTRICAL CHARACTERISTICS and the AC ELECTRICAL CHARACTERISTICS sections of this data sheet). However, when the DS18S20-PAR is performing temperature conversions or copying data from the scratchpad memory to EEPROM, the operating current can be as high as 1.5 mA. This current can cause an unacceptable voltage drop across the weak 1-Wire pullup resistor and is more current than can be supplied by CPP. To assure that the DS18S20-PAR has sufficient supply current, it is necessary to provide a strong pullup on the 1-Wire bus whenever temperature conversions are taking place or data is being copied from the scratchpad to EEPROM. This can be accomplished by using a MOSFET to pull the bus directly to the rail as shown in Figure 2. The 1-Wire bus must be switched to the strong pullup within 10 ms (max) after a Convert T [44h] or Copy Scratchpad [48h] command is issued, and the bus must be held high by the pullup for the duration of the conversion (tconv) or data transfer (twr = 10 ms). No other activity can take place on the 1-Wire bus while the pullup is enabled. SUPPLYING THE DS18S20-PAR DURING TEMPERATURE CONVERSIONS Figure 2 VPU DS18S20-PAR Microprocessor GND VPU DQ 4.7K 1-Wire Bus To Other 1-Wire Devices OPERATION – MEASURING TEMPERATURE The core functionality of the DS18S20-PAR is its direct-to-digital temperature sensor. The temperature sensor output has 9-bit resolution, which corresponds to 0.5°C steps. The DS18S20-PAR powers-up in a low-power idle state; to initiate a temperature measurement and A-to-D conversion, the master must issue a Convert T [44h] command. Following the conversion, the resulting thermal data is stored in the 2-byte temperature register in the scratchpad memory and the DS18S20-PAR returns to its idle state. The DS18S20-PAR output data is calibrated in degrees centigrade; for Fahrenheit applications, a lookup table or conversion routine must be used. The temperature data is stored as a 16-bit sign-extended two’s complement number in the temperature register (see Figure 3). The sign bits (S) indicate if the temperature is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. Table 2 gives examples of digital output data and the corresponding temperature reading. Resolutions greater than 9 bits can be calculated using the data from the temperature, COUNT REMAIN and COUNT PER °C registers in the scratchpad. Note that the COUNT PER °C register is hard-wired to 3 of 20 DS18S20-PAR 16 (10h). After reading the scratchpad, the TEMP_READ value is obtained by truncating the 0.5°C bit (bit 0) from the temperature data (see Figure 3). The extended resolution temperature can then be calculated using the following equation: TEMPERATURE = TEMP _ READ - 0.25 + COUNT _ PER _ C - COUNT _ REMAIN COUNT _ PER _ C TEMPERATURE REGISTER FORMAT Figure 3 bit 7 LS Byte MS Byte bit 6 6 bit 5 5 bit 4 4 bit 3 3 bit 2 2 bit 1 1 bit 0 0 2 2 2 2 2 2 2 2-1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 S S S S S S S S TEMPERATURE/DATA RELATIONSHIP Table 2 TEMPERATURE +85.0°C* +25.0°C +0.5°C 0°C -0.5°C -25.0°C -55.0°C DIGITAL OUTPUT DIGITAL OUTPUT (Binary) (Hex) 0000 0000 1010 1010 0000 0000 0011 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1100 1110 1111 1111 1001 0010 00AAh 0032h 0001h 0000h FFFFh FFCEh FF92h *The power-on reset value of the temperature register is +85°C OPERATION – ALARM SIGNALING After the DS18S20-PAR performs a temperature conversion, the temperature value is compared to the user-defined two’s complement alarm trigger values stored in the 1-byte TH and TL registers (see Figure 4). The sign bit (S) indicates if the value is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. The TH and TL registers are nonvolatile (EEPROM) so they will retain data when the device is powered down. TH and TL can be accessed through bytes 2 and 3 of the scratchpad as explained in the MEMORY section of this datasheet. TH AND TL REGISTER FORMAT Figure 4 bit 7 S bit 6 2 6 bit 5 2 5 bit 4 bit 3 5 5 2 2 bit 2 2 2 bit 1 2 1 bit 0 20 Only bits 8 through 1 of the temperature register are used in the TH and TL comparison since TH and TL are 8-bit registers. If the result of a temperature measurement is higher than TH or lower than TL, an alarm condition exists and an alarm flag is set inside the DS18S20-PAR. This flag is updated after every temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next temperature conversion. The master device can check the alarm flag status of all DS DS18S20-PARs on the bus by issuing an Alarm Search [ECh] command. Any DS18S20-PARs with a set alarm flag will respond to the command, 4 of 20 DS18S20-PAR so the master can determine exactly which DS18S20-PARs have experienced an alarm condition. If an alarm condition exists and the TH or TL settings have changed, another temperature conversion should be done to validate the alarm condition. 64-BIT LASERED ROM CODE Each DS18S20-PAR contains a unique 64–bit code (see Figure 5) stored in ROM. The least significant 8 bits of the ROM code contain the DS18S20-PAR’s 1–wire family code: 10h. The next 48 bits contain a unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is calculated from the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in the CRC GENERATION section. The 64–bit ROM code and associated ROM function control logic allow the DS18S20-PAR to operate as a 1–wire device using the protocol detailed in the 1-WIRE BUS SYSTEM section of this datasheet. 64-BIT LASERED ROM CODE Figure 5 8-BIT CRC MSB 48-BIT SERIAL NUMBER LSB MSB LSB 8-BIT FAMILY CODE (10h) MSB LSB MEMORY The DS18S20-PAR’s memory is organized as shown in Figure 6. The memory consists of an SRAM scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL). Note that if the DS18S20-PAR alarm function is not used, the TH and TL registers can serve as generalpurpose memory. All memory commands are described in detail in the DS18S20-PAR FUNCTION COMMANDS section. Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register, respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Bytes 4 and 5 are reserved for internal use by the device and cannot be overwritten; these bytes will return all 1s when read. Bytes 6 and 7 contain the COUNT REMAIN and COUNT PER ºC registers, which can be used to calculate extended resolution results as explained in the OPERATION – MEASURING TEMPERATURE section. Byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (CRC) code for bytes 0 through 7 of the scratchpad. The DS18S20-PAR generates this CRC using the method described in the CRC GENERATION section. Data is written to bytes 2 and 3 of the scratchpad using the Write Scratchpad [4Eh] command; the data must be transmitted to the DS18S20-PAR starting with the least significant bit of byte 2. To verify data integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the least significant bit of byte 0. To transfer the TH and TL data from the scratchpad to EEPROM, the master must issue the Copy Scratchpad [48h] command. Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM 2 to the scratchpad at any time using the Recall E [B8h] command. The master can issue “read time slots” (see the 1-WIRE BUS SYSTEM section) following the Recall E2 command and the DS18S20-PAR will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. 5 of 20 DS18S20-PAR DS18S20-PAR MEMORY MAP Figure 6 SCRATCHPAD (Power-up State) byte 0 Temperature LSB (AAh) (85°C) byte 1 Temperature MSB (00h) byte 2 TH Register or User Byte 1* EEPROM TH Register or User Byte 1 byte 3 TL Register or User Byte 2* TL Register or User Byte 2 byte 4 Reserved (FFh) byte 5 Reserved (FFh) byte 6 COUNT REMAIN (0Ch) byte 7 COUNT PER °C (10h) byte 8 CRC* *Power-up state depends on value(s) stored in EEPROM CRC GENERATION CRC bytes are provided as part of the DS18S20-PAR’s 64-bit ROM code and in the 9th byte of the scratchpad memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is contained in the most significant byte of the ROM. The scratchpad CRC is calculated from the data stored in the scratchpad, and therefore it changes when the data in the scratchpad changes. The CRCs provide the bus master with a method of data validation when data is read from the DS18S20-PAR. To verify that data has been read correctly, the bus master must re-calculate the CRC from the received data and then compare this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for scratchpad reads). If the calculated CRC matches the read CRC, the data has been received error free. The comparison of CRC values and the decision to continue with an operation are determined entirely by the bus master. There is no circuitry inside the DS18S20-PAR that prevents a command sequence from proceeding if the DS18S20-PAR CRC (ROM or scratchpad) does not match the value generated by the bus master. The equivalent polynomial function of the CRC (ROM or scratchpad) is: CRC = X8 + X5 + X4 + 1 The bus master can re-calculate the CRC and compare it to the CRC values from the DS18S20-PAR using the polynomial generator shown in Figure 7. This circuit consists of a shift register and XOR gates, and the shift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the least significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. After shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, the polynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC from the DS18S20-PAR must be shifted into the circuit. At this point, if the re-calculated CRC was correct, the shift register will contain all 0s. Additional information about the Dallas 1-Wire cyclic redundancy check is available in Application Note 27 entitled “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch Memory Products.” INPUT CRC GENERATOR Figure 7 XOR XOR XOR (MSB) (LSB) 6 of 20 DS18S20-PAR 1-WIRE BUS SYSTEM The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18S20PAR is always a slave. When there is only one slave on the bus, the system is referred to as a “singledrop” system; the system is “multi-drop” if there are multiple slaves on the bus. All data and commands are transmitted least significant bit first over the 1-Wire bus. The following discussion of the 1-Wire bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). HARDWARE CONFIGURATION The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the data line via an open drain or 3–state port. This allows each device to “release” the data line when the device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the DS18S20-PAR (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 8. The 1-Wire bus requires an external pullup resistor of approximately 5 kW; thus, the idle state for the 1Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480 ms, all components on the bus will be reset. In addition, to assure that the DS18S20-PAR has sufficient supply current during temperature conversions, it is necessary to provide a strong pullup (such as a MOSFET) on the 1-Wire bus whenever temperature conversions or EEPROM writes are taking place (as described in the PARASITE POWER section). HARDWARE CONFIGURATION Figure 8 VPU Microprocessor VPU Strong Pullup DS18S20-PAR 1-WIRE PORT 4.7K 1-wire bus RX DQ Pin RX 5 µA Typ. TX RX = RECEIVE TX = TRANSMIT TX 100 W MOSFET TRANSACTION SEQUENCE The transaction sequence for accessing the DS18S20-PAR is as follows: Step 1. Initialization Step 2. ROM Command (followed by any required data exchange) Step 3. DS18S20-PAR Function Command (followed by any required data exchange) 7 of 20 DS18S20-PAR It is very important to follow the transaction sequence every time the DS18S20-PAR is accessed, as the DS18S20-PAR will not respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM commands, the master must return to Step 1 in the sequence. INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that slave devices (such as the DS18S20-PAR) are on the bus and are ready to operate. Timing for the reset and presence pulses is detailed in the 1-WIRE SIGNALING section. ROM COMMANDS After the bus master has detected a presence pulse, it can issue a ROM command. These commands operate on the unique 64–bit ROM codes of each slave device and allow the master to single out a specific device if many are present on the 1-Wire bus. These commands also allow the master to determine how many and what types of devices are present on the bus or if any device has experienced an alarm condition. There are five ROM commands, and each command is 8 bits long. The master device must issue an appropriate ROM command before issuing a DS18S20-PAR function command. A flowchart for operation of the ROM commands is shown in Figure 9. SEARCH ROM [F0h] When a system is initially powered up, the master must identify the ROM codes of all slave devices on the bus, which allows the master to determine the number of slaves and their device types. The master learns the ROM codes through a process of elimination that requires the master to perform a Search ROM cycle (i.e., Search ROM command followed by data exchange) as many times as necessary to identify all of the slave devices. If there is only one slave on the bus, the simpler Read ROM command (see below) can be used in place of the Search ROM process. For a detailed explanation of the Search ROM procedure, refer to the iButton® Book of Standards at www.ibutton.com/ibuttons/standard.pdf. After every Search ROM cycle, the bus master must return to Step 1 (Initialization) in the transaction sequence. READ ROM [33h] This command can only be used when there is one slave on the bus. It allows the bus master to read the slave’s 64-bit ROM code without using the Search ROM procedure. If this command is used when there is more than one slave present on the bus, a data collision will occur when all the slaves attempt to respond at the same time. MATCH ROM [55h] The match ROM command followed by a 64–bit ROM code sequence allows the bus master to address a specific slave device on a multi-drop or single-drop bus. Only the slave that exactly matches the 64–bit ROM code sequence will respond to the function command issued by the master; all other slaves on the bus will wait for a reset pulse. SKIP ROM [CCh] The master can use this command to address all devices on the bus simultaneously without sending out any ROM code information. For example, the master can make all DS18S20-PARs on the bus perform simultaneous temperature conversions by issuing a Skip ROM command followed by a Convert T [44h] command. Note, however, that the Skip ROM command can only be followed by the Read Scratchpad [BEh] command when there is one slave on the bus. This sequence saves time by allowing the master to iButton is a registered trademark of Dallas Semiconductor. 8 of 20 DS18S20-PAR read from the device without sending its 64–bit ROM code. This sequence will cause a data collision on the bus if there is more than one slave since multiple devices will attempt to transmit data simultaneously. ALARM SEARCH [ECh] The operation of this command is identical to the operation of the Search ROM command except that only slaves with a set alarm flag will respond. This command allows the master device to determine if any DS18S20-PARs experienced an alarm condition during the most recent temperature conversion. After every Alarm Search cycle (i.e., Alarm Search command followed by data exchange), the bus master must return to Step 1 (Initialization) in the transaction sequence. Refer to the OPERATION – ALARM SIGNALING section for an explanation of alarm flag operation. DS18S20-PAR FUNCTION COMMANDS After the bus master has used a ROM command to address the DS18S20-PAR with which it wishes to communicate, the master can issue one of the DS18S20-PAR function commands. These commands allow the master to write to and read from the DS18S20-PAR’s scratchpad memory, initiate temperature conversions and determine the power supply mode. The DS18S20-PAR function commands, which are described below, are summarized in Table 4 and illustrated by the flowchart in Figure 10. CONVERT T [44h] This command initiates a single temperature conversion. Following the conversion, the resulting thermal data is stored in the temperature register, COUNT REMAIN register and COUNT PER °C register in the scratchpad memory, and the DS18S20-PAR returns to its low-power idle state. Within 10 ms (max) after this command is issued the master must enable a strong pullup on the 1-Wire bus for the duration of the conversion (tconv) as described in the PARASITE POWER section. WRITE SCRATCHPAD [4Eh] This command allows the master to write 2 bytes of data to the DS18S20-PAR’s scratchpad. The first byte is written into the TH register (byte 2 of the scratchpad), and the second byte is written into the TL register (byte 3 of the scratchpad). Data must be transmitted least significant bit first. Both bytes MUST be written before the master issues a reset, or the data may be corrupted. READ SCRATCHPAD [BEh] This command allows the master to read the contents of the scratchpad. The data transfer starts with the least significant bit of byte 0 and continues through the scratchpad until the 9th byte (byte 8 – CRC) is read. If only part of the scratchpad contents is required, the master may issue a reset to terminate reading at any time. COPY SCRATCHPAD [48h] This command copies the contents of the scratchpad TH and TL registers (bytes 2 and 3) to EEPROM. Within 10 ms (max) after this command is issued the master must enable a strong pullup on the 1-Wire bus for at least 10 ms as described in the PARASITE POWER section. RECALL E2 [B8h] This command recalls the alarm trigger values (TH and TL) from EEPROM and places the data in bytes 2 and 3, respectively, in the scratchpad memory. The master device can issue “read time slots” (see the 1WIRE BUS SYSTEM section) following the Recall E2 command and the DS18S20-PAR will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. The recall operation happens automatically at power-up, so valid data is available in the scratchpad as soon as power is applied to the device. 9 of 20 DS18S20-PAR DS18S20-PAR FUNCTION COMMAND SET Table 4 Command Convert T Read Scratchpad Write Scratchpad Copy Scratchpad 2 Recall E 1-Wire Bus Activity Description Protocol After Command is Issued TEMPERATURE CONVERSION COMMANDS Initiates temperature 44h None conversion. MEMORY COMMANDS Reads the entire scratchpad BEh DS18S20-PAR transmits up including the CRC byte. to 9 data bytes to master. Writes data into scratchpad 4Eh Master transmits 2 data bytes 2 and 3 (TH and TL). bytes to DS18S20-PAR. Copies TH and TL data from the 48h None scratchpad to EEPROM. Recalls TH and TL data from B8h DS18S20-PAR transmits EEPROM to the scratchpad. recall status to master. Notes 1 2 3 1 NOTES: 1. The master must enable a strong pullup on the 1-Wire bus during temperature conversions and copies from the scratchpad to EEPROM. No other bus activity may take place during this time. 2. The master can interrupt the transmission of data at any time by issuing a reset. 3. Both bytes must be written before a reset is issued. 10 of 20 DS18S20-PAR ROM COMMANDS FLOW CHART Figure 9 Initialization Sequence MASTER TX RESET PULSE DS18S20-PAR TX PRESENCE PULSE MASTER TX ROM COMMAND 33h READ ROM COMMAND Y N 55h MATCH ROM COMMAND F0h SEARCH ROM COMMAND N Y N Y ECh ALARM SEARCH COMMAND N Y Y MASTER TX BIT 0 DS18S20-PAR TX BIT 0 DS18S20-PAR TX BIT 0 DS18S20-PAR TX BIT 0 DS18S20-PAR TX BIT 0 MASTER TX BIT 0 MASTER TX BIT 0 DS18S20-PAR TX FAMILY CODE 1 BYTE N BIT 0 MATCH? DS18S20-PAR TX SERIAL NUMBER 6 BYTES N BIT 0 MATCH? Y Y Y DS18S20-PAR TX BIT 1 DS18S20-PAR TX CRC BYTE MASTER TX BIT 1 DS18S20-PAR TX BIT 1 MASTER TX BIT 1 BIT 1 MATCH? N N BIT 1 MATCH? Y Y DS18S20-PAR TX BIT 63 MASTER TX BIT 63 DS18S20-PAR TX BIT 63 MASTER TX BIT 63 N BIT 63 MATCH? Y DEVICE(S) WITH ALARM FLAG SET? N BIT 63 MATCH? Y MASTER TX FUNCTION COMMAND (FIGURE 10) 11 of 20 CCh SKIP ROM COMMAND N N DS18S20-PAR DS18S20-PAR FUNCTION COMMANDS FLOW CHART Figure 10 44h CONVERT TEMPERATURE ? MASTER TX FUNCTION COMMAND 48h COPY SCRATCHPAD ? N Y Y MASTER ENABLES STRONG PULL-UP ON DQ MASTER ENABLES STRONG PULLUP ON DQ DATA COPIED FROM SCRATCHPAD TO EEPROM DS18S20-PAR CONVERTS TEMPERATURE MASTER DISABLES STRONG PULLUP MASTER DISABLES STRONG PULLUP N B8h RECALL E2 ? BEh READ SCRATCHPAD ? N Y N Y 4Eh WRITE SCRATCHPAD ? Y MASTER TX TH BYTE TO SCRATCHPAD MASTER RX DATA BYTE FROM SCRATCHPAD MASTER BEGINS DATA RECALL FROM E2 PROM N MASTER TX TL BYTE TO SCRATCHPAD MASTER TX RESET ? DEVICE BUSY RECALLING DATA ? N N N Y MASTER RX “0s” Y HAVE 8 BYTES BEEN READ ? MASTER RX “1s” Y MASTER RX SCRATCHPAD CRC BYTE RETURN TO INITIALIZATION SEQUENCE (FIGURE 9) FOR NEXT TRANSACTION 12 of 20 DS18S20-PAR 1-WIRE SIGNALING The DS18S20-PAR uses a strict 1-Wire communication protocol to insure data integrity. Several signal types are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of these signals, with the exception of the presence pulse, are initiated by the bus master. INITIALIZATION PROCEDURE: RESET AND PRESENCE PULSES All communication with the DS18S20-PAR begins with an initialization sequence that consists of a reset pulse from the master followed by a presence pulse from the DS18S20-PAR. This is illustrated in Figure 11. When the DS18S20-PAR sends the presence pulse in response to the reset, it is indicating to the master that it is on the bus and ready to operate. During the initialization sequence the bus master transmits (TX) the reset pulse by pulling the 1-Wire bus low for a minimum of 480 ms. The bus master then releases the bus and goes into receive mode (RX). When the bus is released, the 5k pullup resistor pulls the 1-Wire bus high. When the DS18S20-PAR detects this rising edge, it waits 15–60 ms and then transmits a presence pulse by pulling the 1-Wire bus low for 60–240 ms. INITIALIZATION TIMING Figure 11 MASTER TX RESET PULSE MASTER RX 480 ms minimum DS18S20-PAR TX presence pulse 60-240 ms 480 ms minimum VPU DS18S20-PAR waits 15-60 ms 1-WIRE BUS GND LINE TYPE LEGEND Bus master pulling low DS18S20-PAR pulling low Resistor pullup READ/WRITE TIME SLOTS The bus master writes data to the DS18S20-PAR during write time slots and reads data from the DS18S20-PAR during read time slots. One bit of data is transmitted over the 1-Wire bus per time slot. WRITE TIME SLOTS There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master uses a Write 1 time slot to write a logic 1 to the DS18S20-PAR and a Write 0 time slot to write a logic 0 to the DS18S20-PAR. All write time slots must be a minimum of 60 ms in duration with a minimum of a 1 ms recovery time between individual write slots. Both types of write time slots are initiated by the master pulling the 1-Wire bus low (see Figure 12). To generate a Write 1 time slot, after pulling the 1-Wire bus low, the bus master must release the 1-Wire bus within 15 ms. When the bus is released, the 5k pullup resistor will pull the bus high. To generate a Write 0 time slot, after pulling the 1-Wire bus low, the bus master must continue to hold the bus low for the duration of the time slot (at least 60 ms). 13 of 20 DS18S20-PAR The DS18S20-PAR samples the 1-Wire bus during a window that lasts from 15 ms to 60 ms after the master initiates the write time slot. If the bus is high during the sampling window, a 1 is written to the DS18S20-PAR. If the line is low, a 0 is written to the DS18S20-PAR. READ/WRITE TIME SLOT TIMING DIAGRAM Figure 12 START OF SLOT START OF SLOT MASTER WRITE “0” SLOT MASTER WRITE “1” SLOT 1 ms < TREC < ¥ 60 ms < TX “0” < 120 > 1 ms VPU 1-WIRE BUS GND DS18S20-PAR samples MIN 15 ms TYP 15 ms DS18S20-PAR samples MAX 30 ms MIN 15 ms MASTER READ “0” SLOT TYP 15 ms MAX 30 ms MASTER READ “1” SLOT 1 ms < TREC < ¥ VPU 1-WIRE BUS GND Master samples > 1 ms Master samples > 1 ms 15 ms 45 ms 15 ms LINE TYPE LEGEND Bus master pulling low DS18S20-PAR pulling low Resistor pullup READ TIME SLOTS The DS18S20-PAR can only transmit data to the master when the master issues read time slots. Therefore, the master must generate read time slots immediately after issuing a Read Scratchpad [BEh] command, so that the DS18S20-PAR can provide the requested data. In addition, the master can generate read time slots after issuing a Recall E2 [B8h] command to find out the recall status as explained in the DS18S20-PAR FUNCTION COMMAND section. All read time slots must be a minimum of 60 ms in duration with a minimum of a 1 ms recovery time between slots. A read time slot is initiated by the master device pulling the 1-Wire bus low for a minimum of 1 ms and then releasing the bus (see Figure 12). After the master initiates the read time slot, the DS18S20-PAR will begin transmitting a 1 or 0 on bus. The DS18S20-PAR transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. When transmitting a 0, the DS18S20-PAR will 14 of 20 DS18S20-PAR release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output data from the DS18S20-PAR is valid for 15 ms after the falling edge that initiated the read time slot. Therefore, the master must release the bus and then sample the bus state within 15 ms from the start of the slot. Figure 13 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15 ms for a read time slot. Figure 14 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible and by locating the master sample time during read time slots towards the end of the 15 ms period. DETAILED MASTER READ 1 TIMING Figure 13 VPU VIH of Master 1-WIRE BUS GND TINT > 1 ms TRC Master samples 15 ms RECOMMENDED MASTER READ 1 TIMING Figure 14 VPU VIH of Master 1-WIRE BUS GND Master samples TINT = TRC = small small 15 ms LINE TYPE LEGEND Bus master pulling low Resistor pullup 15 of 20 DS18S20-PAR DS18S20-PAR OPERATION EXAMPLE 1 In this example there is only one DS18S20-PAR on the bus. The master writes to the TH and TL registers in the DS18S20-PAR scratchpad and then reads the scratchpad and recalculates the CRC to verify the data. The master then copies the scratchpad contents to EEPROM. MASTER MODE TX RX TX TX TX TX RX TX TX RX DATA (LSB FIRST) Reset Presence CCh 4Eh 2 data bytes Reset Presence CCh BEh 9 data bytes TX RX TX TX TX Reset Presence CCh 48h DQ line held high by strong pullup COMMENTS Master issues reset pulse. DS18S20-PAR responds with presence pulse. Master issues Skip ROM command. Master issues Write Scratchpad command. Master sends two data bytes to scratchpad (TH and TL). Master issues reset pulse. DS18S20-PAR responds with presence pulse. Master issues Skip ROM command. Master issues Read Scratchpad command. Master reads entire scratchpad including CRC. The master then recalculates the CRC of the first eight data bytes from the scratchpad and compares the calculated CRC with the read CRC (byte 9). If they match, the master continues; if not, the read operation is repeated. Master issues reset pulse. DS18S20-PAR responds with presence pulse. Master issues Skip ROM command. Master issues Copy Scratchpad command. Master applies strong pullup to DQ for at least 10 ms while copy operation is in progress. 16 of 20 DS18S20-PAR DS18S20-PAR OPERATION EXAMPLE 2 In this example there are multiple DS18S20-PARs on the bus. The bus master initiates a temperature conversion in a specific DS18S20-PAR and then reads its scratchpad and recalculates the CRC to verify the data. MASTER MODE TX RX TX TX TX TX TX RX TX TX TX RX DATA (LSB FIRST) Reset Presence 55h 64-bit ROM code 44h DQ line held high by strong pullup Reset Presence 55h 64-bit ROM code BEh 9 data bytes COMMENTS Master issues reset pulse. DS18S20-PARs respond with presence pulse. Master issues Match ROM command. Master sends DS18S20-PAR ROM code. Master issues Convert T command. Master applies strong pullup to DQ for the duration of the conversion (tconv). Master issues reset pulse. DS18S20-PARs respond with presence pulse. Master issues Match ROM command. Master sends DS18S20-PAR ROM code. Master issues Read Scratchpad command. Master reads entire scratchpad including CRC. The master then recalculates the CRC of the first eight data bytes from the scratchpad and compares the calculated CRC with the read CRC (byte 9). If they match, the master continues; if not, the read operation is repeated. DS18S20-PAR OPERATION EXAMPLE 3 In this example there is only one DS18S20-PAR on the bus. The bus master initiates a temperature conversion then reads the DS18S20-PAR scratchpad and calculates a higher resolution result using the data from the temperature, COUNT REMAIN and COUNT PER °C registers. MASTER MODE TX TR TX TX TX TX RX TX TX RX DATA (LSB FIRST) Reset Presence CCh 44h DQ line held high by strong pullup Reset Presence CCh BEh 9 data bytes TX RX - Reset Presence - COMMENTS Master issues reset pulse. DS18S20-PAR responds with presence pulse. Master issues Skip ROM command. Master issues Convert T command. Master applies strong pullup to DQ for the duration of the conversion (tconv). Master issues reset pulse. DS18S20-PAR responds with presence pulse. Master issues Skip ROM command. Master issues Read Scratchpad command. Master reads entire scratchpad including CRC. The master then recalculates the CRC of the first eight data bytes from the scratchpad and compares the calculated CRC with the read CRC (byte 9). If they match, the master continues; if not, the read operation is repeated. The master also calculates the TEMP_READ value and stores the contents of the COUNT REMAIN and COUNT PER °C registers. Master issues reset pulse. DS18S20-PAR responds with presence pulse. CPU calculates extended resolution temperature using the equation in the OPERATION - MEASURING TEMPERATURE section of this datasheet. 17 of 20 DS18S20-PAR ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to ground Operating temperature Storage temperature Soldering temperature –0.5V to +6.0V –55°C to +100°C –55°C to +125°C See J-STD-020A Specification *These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER Pullup Supply Voltage Thermometer Error SYMBOL VPU tERR CONDITION (-55°C to +100°C; VPU=3.0V to 5.5V) MIN 3.0 TYP MAX 5.5 ±½ -10°C to +85°C -55°C to +100°C Input Logic Low Input Logic High Sink Current Active Current DQ Input Current Drift VIL VIH IL IDQA IDQ VI/O=0.4V UNITS NOTES V 1,2 °C 3 ±2 +0.8 5.5 -0.3 3.0 4.0 1 5 ±0.2 V V mA mA µA °C 1.5 1,4,5 1,6 1 7 8 9 NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. All voltages are referenced to ground. The Pullup Supply Voltage specification assumes that the pullup device (resistor or transistor) is ideal, and therefore the high level of the pullup is equal to VPU. In order to meet the VIH spec of the DS18S20-PAR, the actual supply rail for the strong pullup transistor must include margin for the voltage drop across the transistor when it is turned on; thus: VPU_ACTUAL = VPU_IDEAL + VTRANSISTOR. See typical performance curve in Figure 15. Logic low voltages are specified at a sink current of 4 mA. To always guarantee a presence pulse under low voltage parasite power conditions, VILMAX may have to be reduced to as low as 0.5V. Logic high voltages are specified at a source current of 1 mA. Active current refers to supply current during active temperature conversions or EEPROM writes. DQ line is high (“hi-Z” state). Drift data is based on a 1000 hour stress test at 125°C. AC ELECTRICAL CHARACTERISTICS: NV MEMORY (-55°C to +100°C; VPU=3.0V to 5.5V) PARAMETER NV Write Cycle Time EEPROM Writes EEPROM Data Retention SYMB OL twr NEEWR tEEDR CONDITION -55°C to +55°C -55°C to +55°C 18 of 20 MIN 50k 10 TYP MAX UNITS 2 10 ms writes years DS18S20-PAR AC ELECTRICAL CHARACTERISTICS (-55°C to +100°C; VPU=3.0V to 5.5V) PARAMETER SYMBOL CONDITION MIN TYP Temperature Conversion tCONV Time Time to Strong Pullup tSPON Start Convert T or On Copy Scratchpad Command Issued Time Slot tSLOT 60 Recovery Time tREC 1 Write 0 Low Time rLOW0 60 Write 1 Low Time tLOW1 1 Read Data Valid tRDV Reset Time High tRSTH 480 Reset Time Low tRSTL 480 Presence Detect High tPDHIGH 15 Presence Detect Low tPDLOW 60 Capacitance CIN/OUT MAX 750 UNITS NOTES ms 1 10 µs 120 µs µs µs µs µs µs µs µs µs pF 120 15 15 960 60 240 25 NOTES: 1. Refer to timing diagrams in Figure 16. 2. If tRSTL > 960 ms, a power on reset may occur. TYPICAL PERFORMANCE CURVE Figure 15 DS18S20-PAR Typical Error Curve 0.5 Thermometer Error (°C) 0.4 +3s Error 0.3 0.2 0.1 0 -0.1 0 10 20 30 40 50 60 -0.2 -0.3 -0.4 Mean Error -3s Error -0.5 Reference Temp (°C) 19 of 20 70 1 1 1 1 1 1 1,2 1 1 DS18S20-PAR TIMING DIAGRAMS Figure 16 20 of 20