DS28C16Q+T

Click here for production status of specific part numbers. DS28C16 I2C Low-Voltage SHA-3 Authenticator General Description Benefits and Features The DS28C16 secure authenticator combines FIPS202-compliant Secure Hash Algorithm (SHA-3) challenge and response authentication with secured EEPROM. ● Robust Countermeasures Protect Against Security Attacks • All Stored Data Cryptographically Protected from Discovery The device provides a core set of cryptographic tools derived from integrated blocks including a SHA-3 engine, 256 bits of secured user EEPROM, a decrement-only counter, and a unique 64-bit ROM identification number (ROM ID). The unique ROM ID is used as a fundamental input parameter for cryptographic operations and serves as an electronic serial number within the application. ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC) Applications ● Medical Tools/Accessories Authentication and Calibration ● Accessory and Peripheral Secure Authentication ● Battery Authentication and Charge Cycle Tracking ● Supplemental Features Enable Easy Integration into End Applications • 17-Bit One-Time Settable, Nonvolatile DecrementOnly Counter with Authenticated Read • Secure Storage for Secrets • 256 Bits of Secure EEPROM for User Data • Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID) • I2C Communications Up to 1MHz • Operating Range: 1.62V–3.63V, -40°C to +85°C • 8-Pin, 2mm x 2mm TDFN-EP Package Ordering Information appears at end of data sheet. Typical Application Circuit VCC VCC µC GND 19-100753; Rev 0; 3/20 I2C PORT VCC SDA SCL DS28C16 GND DS28C16 I2C Low-Voltage SHA-3 Authenticator TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 TDFN-EP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Design Resource Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Decrement Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I 2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Idle or Not Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 START Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STOP Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Repeated START Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 www.maximintegrated.com Maxim Integrated | 2 DS28C16 I2C Low-Voltage SHA-3 Authenticator LIST OF FIGURES Figure 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. I2C Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 www.maximintegrated.com Maxim Integrated | 3 I2C Low-Voltage SHA-3 Authenticator DS28C16 Absolute Maximum Ratings Voltage Range on Any Pin Relative to GND ........... -0.5V to 4.0V Maximum Current into Any Pin ............................ -20mA to 20mA Operating Temperature Range ............................ -40°C to +85°C Junction Temperature ...................................................... +150°C Storage Temperature Range ..............................-40°C to +125°C Lead Temperature (soldering, 10s)................................... +300°C Soldering Temperature (reflow) ........................................ +260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information 8 TDFN-EP Package Code T822+3C Outline Number 21-0168 Land Pattern Number 90-0065 Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) — Junction to Case (θJC) — Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 85.1°C/W Junction to Case (θJC) 20.8°C/W For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (Limits are 100% tested at TA = +25ºC and TA = +85ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.) PARAMETER SYMBOL Supply Voltage VCC Supply Current ICC CONDITIONS (Note 1) MIN TYP MAX UNITS 1.62 3.3 3.63 V Standby 3.5 12 60 Communicating (Note 2) μA I2C SCL AND SDA PINS (Note 3) Low-Level Input Voltage High-Level Input Voltage -0.3 0.3 × VCC VCC > 1.98V 0.7 × VCC VCC + 0.3 VCC ≤ 1.98V 0.8 × VCC VCC + 0.3 VIL VIH Hysteresis of Schmitt Trigger Inputs VHYS (Note 4) Low-Level Output Voltage at 4mA Sink Current VOL (Note 5) www.maximintegrated.com 0.05 × VCC V V V 0.4 V Maxim Integrated | 4 I2C Low-Voltage SHA-3 Authenticator DS28C16 Electrical Characteristics (continued) (Limits are 100% tested at TA = +25ºC and TA = +85ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.) PARAMETER SYMBOL Output Fall Time from VIH(MIN) to VIL(MAX) with a Bus Capacitance from 10pF to 400pF tOF Pulse Width of Spikes that are Suppressed by the Input Filter tSP Input Current with an Input Voltage Between 0.1VCCmax and 0.9VCCmax II Input Capacitance CONDITIONS MIN CI (Note 4) SCL Clock Frequency fSCL (Note 1) Hold Time (Repeated) START Condition tHD:STA Low Period of the SCL Clock tLOW High Period of the SCL Clock MAX 30 (Note 4) (Note 4, Note 6) TYP -1 UNITS ns 50 ns +1 µA 1 MHz 10 pF 0.45 µs 0.65 µs tHIGH 0.35 µs Setup Time for a Repeated START Condition tSU:STA 0.35 µs Data Hold Time tHD:DAT (Note 4, Note 7, Note 8) Data Setup Time tSU:DAT (Note 7, Note 9) Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive Load for Each Bus Line Warm-Up Time (Note 7) 0.35 µs 100 ns tSU:STO 0.35 µs tBUF 0.6 µs CB (Note 1, Note 10) 400 pF tOSCWUP (Note 1, Note 11) 1 ms CRYPTO FUNCTIONS Computation Current ICMP 3 mA Read Memory Time tRM 5 ms Write Memory Time tWM 60 ms Short Write Memory Time tWMS 15 ms Computation Time tCMP 15 ms EEPROM Write/Erase Cycles (Endurance) www.maximintegrated.com NCY (Note 12) 100K Maxim Integrated | 5 I2C Low-Voltage SHA-3 Authenticator DS28C16 Electrical Characteristics (continued) (Limits are 100% tested at TA = +25ºC and TA = +85ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.) PARAMETER Data Retention SYMBOL tDR CONDITIONS MIN TA = +85ºC (Note 13) 10 TYP MAX UNITS years Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: System requirement. Operating current during I2C communication at 1MHz with < 25ns rise and fall times on SDA and SCL. All I2C timing values are referred to VIH(MIN) and VIL(MAX) levels. Guaranteed by design and/or characterization only. Not production tested. The I-V characteristic is linear for voltages less than 1V. I/O pins of the DS28C16 do not obstruct the SDA and SCL lines if VCC is switched off. tLOW min = tHD:DAT max + 200ns for rise or fall time + tSU:DAT min. Values greater than these can be accommodated by extending tLOW accordingly. Note 8: The DS28C16 provides a hold time of at least 100ns for the SDA signal (referenced to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 9: The DS28C16 can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250ns must then be met. Also, the acknowledge timing must meet this setup time (I2C bus specification Rev. 03, 19 June 2007). Note 10: CB = Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application (I2C bus specification Rev. 03, 19 June 2007). Note 11: I2C communication should not take place for at least tOSCWUP after VCC reaches VCC(MIN). Note 12: Write-cycle endurance is tested in compliance with JESD47H. Note 13: Data retention is tested in compliance with JESD47H. Pin Configuration TDFN TOP VIEW VCC SDA SCL DNC 8 7 6 5 DS28C16 EP* + 1 2 3 4 DNC DNC DNC GND TDFN-EP 2mm x 2mm *EP = EXPOSED PAD www.maximintegrated.com Maxim Integrated | 6 I2C Low-Voltage SHA-3 Authenticator DS28C16 Pin Description PIN NAME FUNCTION 1–3, 5 DNC Do Not Connect 4 GND Ground Reference. Connect all contacts to GND. 6 SCL I2C Clock. Connect to VCC with pullup resistor. 7 SDA I2C Data. Connect to VCC with pullup resistor. 8 VCC Supply Voltage — EP www.maximintegrated.com Exposed Pad (TDFN Only). Solder evenly to the board's ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. Maxim Integrated | 7 I2C Low-Voltage SHA-3 Authenticator DS28C16 Detailed Description The DS28C16 integrates the Maxim DeepCover® capability to protect all device stored data from invasive discovery. In addition to the SHA-3 engine for signatures, 256-bit EEPROM for user memory, SHA-3 secret storage, 17-bit decrement counter, and control registers. The device operates from an I2C interface. VCC 64-BIT ROM ID SDA SCL I2C FUNCTION CONTROL AND COMMAND BUFFER SHA3-256 SECRET E2 ARRAY USER MEMORY DECREMENT COUNTER DS28C16 Figure 1. Block Diagram Design Resource Overview Operation of the DS28C16 involves use of device EEPROM and execution of device function commands. The following section provides an overview including the decrement counter. Refer to the DS28C16 Security User Guide for details. Memory A secured EEPROM array provides SHA-3 secret storage, along with a decrement counter, and/or general-purpose, user-programmable memory. Depending on the memory space, there are either default or user-programmable options to set protection modes. Decrement Counter The optional 17-bit decrement counter can be written one time on a page of memory. A dedicated device function command is used to decrement the count value by one with each call. Once the count value reaches a value of 0, no additional decrements are possible. I 2C General Characteristics The I2C bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are high. The output stages of devices connected to the bus must have an open drain or open collector to perform the wired- www.maximintegrated.com Maxim Integrated | 8 I2C Low-Voltage SHA-3 Authenticator DS28C16 AND function. Data on the I2C bus can be transferred at rates up to 100kbps in standard mode and up to 400kbps in fast mode. The DS28C16 works in both modes or up to a clock rate of 1MHz. A device that sends data on the bus is defined as a transmitter, and a device receiving data is defined as a receiver. The device that controls communication is called a master. Devices controlled by the master are slaves. To be individually accessed, each device must have a slave address that does not conflict with other devices on the bus. Data transfers can be initiated only when the bus is not busy. The master generates the serial clock (SCL), controls the bus access, generates the START and STOP conditions, and determines the number of data bytes transferred between START and STOP (Figure 2). Data is transferred in bytes with the most significant bit being transmitted first. An acknowledge bit follows each byte to allow synchronization between master and slave. Slave Address The slave address to which the DS28C16 responds is shown in Figure 3. The slave address is part of the slave address/ control byte. The last bit of the slave address/control byte (R/W) defines the data direction. When set to 0, subsequent data flows from master to slave (write access); when set to 1, data flows from slave to master (read access). IDLE S MSB FIRST LSB MSB P LSB MSB SDA SLAVE ADDRESS SCL R/W ACK 8 9 1-7 DATA 1-7 8 ACK/ NACK DATA ACK 9 1-7 8 9 REPEATED IF MORE BYTES ARE TRANSFERRED Figure 2. I2C Protocol Overview 7-BIT SLAVE ADDRESS A6 A5 A4 A3 A2 A1 A0 0 1 1 0 0 0 1 MSB R/W DETERMINES READ OR WRITE Figure 3. I2C Slave Address I2C Definitions The following terminology is commonly used to describe I2C data transfers. The timing references are defined in Figure 4. Bus Idle or Not Busy Both SDA and SCL are inactive and in their logic-high states. www.maximintegrated.com Maxim Integrated | 9 I2C Low-Voltage SHA-3 Authenticator DS28C16 START Condition To initiate communication with a slave, the master must generate a START condition. A START condition is defined as a change in state of SDA from high to low while SCL remains high. STOP Condition To end communication with a slave, the master must generate a STOP condition. A STOP condition is defined as a change in state of SDA from low to high while SCL remains high. Repeated START Condition Repeated STARTs are commonly used for read accesses after having specified a memory address to read from in a preceding write access. The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data transfer following the current one. A repeated START condition is generated the same way as a normal START condition, but without leaving the bus idle after a STOP condition. Data Valid With the exception of the START and STOP condition, transitions of SDA can occur only during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL; see Figure 4). There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL pulse. When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum tSU:DAT, + tR in Figure 4) before the next rising edge of SCL to start reading. The slave shifts out each data bit on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. The master generates all SCL clock pulses, including those needed to read from a slave. tF IF MASTER DRIVEN OR tOF IF SLAVE DRIVEN tF/tOF Sr S P S SDA tF tR tSU:DAT tSU:STA tLOW tBUF tSP SCL tHD:STA tHD:DAT tHIGH tSU:STO NOTE: TIMING REFERENCED TO VIH(MIN) AND VIL(MAX). Figure 4. I2C Timing Diagram www.maximintegrated.com Maxim Integrated | 10 I2C Low-Voltage SHA-3 Authenticator DS28C16 Ordering Information PART NUMBER DS28C16Q+T TEMP RANGE PIN-PACKAGE -40°C to +85°C 8 TDFN-EP* (2.5k pcs) +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. www.maximintegrated.com Maxim Integrated | 11 I2C Low-Voltage SHA-3 Authenticator DS28C16 Revision History REVISION NUMBER REVISION DATE 0 3/20 DESCRIPTION Initial release PAGES CHANGED — For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2020 Maxim Integrated Products, Inc.