DS28S60Q+

Click here for production status of specific part numbers. DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA General Description Benefits and Features The DS28S60 DeepCover® cryptographic coprocessor easily integrates into embedded systems enabling confidentiality, authentication and integrity of information. With a fixed command set and no device-level firmware development required, the DS28S60 makes it fast and easy to implement full security for IoT devices. Communication with the device is performed using the industry standard SPI slave interface at up to 20Mbps with a simple set of commands that provide a comprehensive security toolbox utilizing HW-based cryptographic blocks. As a coprocessor to an SPI- interfaced host controller, the command functionality includes ECDSA-P256 signature and verification, SHA-256 based digital signature, AES-128 packet encryption/decryption, ECDHE key exchange for session key generation, and access to high-quality random numbers. A NIST SP800-90B compliant true random number generator (TRNG) is integrated for on-chip cryptographic operations as well as providing random data and nonces to the host controller, if required. Nonvolatile storage for secrets, certificates, public/private keys, and applicationspecific sensitive data is supported with 3.6KB of secured flash memory. The DS28S60 integrates Maxim’s patented ChipDNA™ feature, a physically unclonable function (PUF) to provide a cost-effective solution with the ultimate protection against security attacks. Using the random variation of semiconductor device characteristics that naturally occur during wafer fabrication, the ChipDNA circuit generates a unique output value that is repeatable over time, temperature, and operating voltage. Attempts to probe or observe ChipDNA operation modifies the underlying circuit characteristics, preventing discovery of the unique value used by the chip's cryptographic functions. ChipDNA output is utilized as key content to cryptographically secure all device stored data and optionally, under user control, key content for specific cryptographic operations. ● Secure Coprocessor with NIST-Compliant HardwareBased Crypto • FIPS-180 SHA-256 MAC and FIPS-198 HMAC Hash • FIPS-197 AES-128 with GCM • FIPS-186 ECDSA-P256 Elliptic Curve Digital Signature/Verification • SP800-56A ECDHE-P256 Key Exchange • SP800-90B Compliant TRNG Applications ● -40°C to +105°C, 1.62V to 3.63V ● ● ● ● ● Internet of Things (IoT) Device Security Key Management and Exchange End-to-End Encryption End-Point Authentication Prevention of Counterfeit Products ● Robust Countermeasures Protect Against Security Attacks • ChipDNA Produced Key Cryptographically Protects All Stored Data • Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts ● Enables Fast Time-to-Market with Easy End Application Integration • Fixed-Function Command Set, No Device-Level Firmware • C-Source SDK for Host Micro SW Development • 3.6KB Flash Array for Secure Key, Certificate, and Data Storage ● High-Speed Interface for Host Microcontroller Communication • 20MHz SPI with Mode 0 or Mode 3 Operation ● Supplemental Features Enable Easy Integration into End Applications • Unique and Unalterable Factory-Programmed, 64-Bit Identification Number (ROM ID) • Low-Power Operation • 100nA Power-Down Mode • 0.35mA Idle • 12-Pin 3mm x 3mm TDFN Ordering Information appears at end of data sheet. DeepCover is a registered trademark of Maxim Integrated Products, Inc. ChipDNA is a trademark of Maxim Integrated Inc. 19-000793; Rev 0; 3/20 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Simplified Block Diagram DS28S60 CEXT VDD POWER MANAGER SHA-256 ECDSA ECDHE PDWN AES-128 SPIS_SS 3.6KB FLASH MEMORY SPIS_SCK SPIS_MOSI FUNCTION CONTROL AND COMMAND INTERFACE SPI SLAVE USER MEMORY KEYS & SECRETS SPIS_MISO ChipDNA PUF 64-BIT ROM ID TRNG GND www.maximintegrated.com 19-100793 Maxim Integrated | 2 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DS28S60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ChipDNA Physically Unclonable Function (PUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Cryptographic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 64-Bit ROM ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Function Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Simple Application Level Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 www.maximintegrated.com 19-100793 Maxim Integrated | 3 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA LIST OF FIGURES Figure 1. 64-Bit ROM ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. SPI Mode 0 and 3 Data Sampling Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 www.maximintegrated.com 19-100793 Maxim Integrated | 4 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA LIST OF TABLES Table 1. Typical Cryptographic Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 www.maximintegrated.com 19-100793 Maxim Integrated | 5 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Absolute Maximum Ratings VDD to GND........................................................... -0.3V to 3.63V Any Pin to GND except VDD....................... -0.3V to (VDD + 0.3)V Operating Temperature Range .......................... -40°C to +105°C Storage Temperature Range .............................. -40°C to +150°C Junction Temperature ...................................................... +150°C Soldering Temperature (reflow) ........................................ +260°C Continuous Package Power Dissipation 12-Pin TDFN (SingleLayer Board) TA = +70°C, (derate 15.90mW/°C above +70°C) .........................................................................1269.8 mW Continuous Package Power Dissipation 12-Pin TDFN (Multilayer Board) TA = +70°C (derate 24.40mW/°C above +70°C) ..........................................................................1951.2mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information 12 TDFN Package Code TD1233+1C Outline Number 21-0664 Land Pattern Number 90-0397 Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) 63°C/W Junction to Case (θJC) 8.5°C/W Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 41°C/W Junction to Case (θJC) 8.5°C/W For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (Limits are 100% tested at TA = +25ºC and TA = +105ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.3 3.63 V POWER SUPPLY Supply Voltage Power-On Reset VDD Idle Current Power-Down Current www.maximintegrated.com 1.62 1.33 V TA = +25°C, no I/O or cryptographic operation are active 1.28 IECDSA TA = +25°C, performing signature operation 1.62 ISHA TA = +25°C, performing SHA-256 operation 0.95 IIDLE TA = +25°C, PDWN = VDD, CPU/ peripherals inactive, I/O pins in inactive state 0.4 mA IPDWN TA = +25°C, VPDWN = 0V, VDD = 1.8V 100 nA IA Active Current (Note 1) VPOR 19-100793 3 mA Maxim Integrated | 6 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Electrical Characteristics (continued) (Limits are 100% tested at TA = +25ºC and TA = +105ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.) PARAMETER SYMBOL Power-Down Resistance RPDWN CONDITIONS MIN Pulldown to ground TYP MAX 1 UNITS MΩ FUNCTIONAL TIMING Operation Time tOP 1 ms DIGITAL I/O: GENERAL Output Voltage High (SPIS_MISO) VOH ISOURCE = 2mA VDD 0.4 Output Voltage Low (SPIS_MISO) VOL ISINK = 2mA Input Voltage High (SPIS_SCK, SPIS_SS, SPIS_MOSI) VIH Input Voltage Low (SPIS_SCK, SPIS_SS, SPIS_MOSI) VIL Input Leakage Current Low IIL VDD = 3.63V, VIN = 0V -500 +500 nA Input Leakage Current High IIH VDD = 3.63V, VIN = 3.63V -500 +500 nA 20 MHz V 0.4 0.7 x VDD V V 0.3 x VDD SPI SLAVE Operating Frequency fSCK Clock Period tSCK 1/fSCK μs Clock Input High Time tSCH (Note 2) tSCK/2 μs Clock Input Low Time tSCL (Note 2) tSCK/2 μs SS Active Setup Time tSSE 10 ns Data Input Setup Time tSIS 5 ns Data Input Hold Time tSIH 1 ns Clock Edge to Data Output Valid tSOV 5 ns SS Inactive Setup Time tSSD 10 ns SS Inactive Time tSSH 1/fSCK μs Output Disable Time tSLH 10 ns Clock Stable to SS Active tSAD 10 ns 10 ms 8 μs FLASH MEMORY Flash Erase Time tP_ERASE Flash Programming Time per Word tPROG Flash Endurance NEND Data Retention tRET www.maximintegrated.com Page erase TA = +85°C 19-100793 10 kcycles 10 years Maxim Integrated | 7 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Note 1: System requirement. Note 2: tSCH + tSCL ≥ 1/fSCK (MAX) www.maximintegrated.com 19-100793 Maxim Integrated | 8 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Typical Operating Characteristics (TA = TMIN to TMAX unless otherwise noted.) Pin Configuration DS28S60 VDD DNC DNC DNC DNC PDWN TOP VIEW 12 11 10 9 8 7 DS28S60 *EP 2 3 4 5 6 SPIS_MOSI SPIS_MISO SPIS_SS GND CEXT 1 SPIS_SCK + TDFN-EP 3mm x 3mm x 0.75mm www.maximintegrated.com 19-100793 *EP = EXPOSED PAD Maxim Integrated | 9 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Pin Description PIN NAME FUNCTION POWER 1 CEXT External Capacitor. Connect to ground through a 1µF external ceramic chip capacitor. Place the capacitor as close as possible to the CEXT pin. No other components should be connected to the CEXT pin. 6 GND Digital Ground. Connect directly to the ground plane. 7 PDWN 12 VDD — EP Power Down. Controls the power state of the DS28S60. Setting this pin to GND places the DS28S60 into power-down mode. In power-down mode, all volatile/ephemeral registers and data are erased. Set this pin high prior to communicating with the device. This pin should remain in a high state for the duration of any cryptography computations and as long as any ephemeral data/ keys are required by the host application. Supply Voltage. Connect to the external power supply for the DS28S60. Exposed Pad. Solder evenly to the board's ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. SPI Slave 2 SPIS_SCK Slave Clock (SCK). The SPI clock input from an external SPI master controller. 3 SPIS_MOSI Master Out Slave In (MOSI). This is the SPI data input line from the SPI master. 4 SPIS_MISO Master In Slave Out (MISO). This is the SPI data output line for data going from the DS28S60 to an external SPI master. 5 SPIS_SS 8–11 DNC www.maximintegrated.com Slave Select (SS). An input from a SPI master to select the DS28S60 for communication. Do Not Connect. Leave unconnected. 19-100793 Maxim Integrated | 10 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Detailed Description The DS28S60 secure coprocessor provides a comprehensive cryptographic toolbox, command set and nonvolatile memory for securing a broad range of embedded equipment. It includes a 3.6KB flash memory array that provides secure storage for keys, certificates, secrets, and application/user data. As a fixed function device, there is no firmware development involved. A simple to use command set provides functions and capabilities for: ● ● ● ● ● ● Asymmetric key authentication with ECDSA-P256 signature and verification Symmetric key authentication with SHA-256 HMAC ECDHE secure key exchange Encryption/decryption of bulk data with AES-128 Securely store certificates, keys and data Generation of NIST SP800-90B compliant random data ChipDNA Physically Unclonable Function (PUF) ChipDNA PUF security technology provides an exponential increase in protection against the invasive and reverse engineering attacks that hackers apply. Attempts to probe or observe ChipDNA operation modifies the underlying circuit characteristics, preventing the discovery of the unique value used by the chip cryptographic functions. Similarly, more exhaustive reverse-engineering attempts are defeated due to the factory conditioning required to make the ChipDNA PUF circuitry operational. The per-device unique key is generated by the ChipDNA PUF circuitry only when needed for cryptographic operations and is then instantaneously deleted. Most importantly, the ChipDNA secure key never resides statically in registers or memory, nor does it ever leave the electrical boundary of the IC. In addition to the protection benefits, ChipDNA simplifies or eliminates the need for secure IC key management. Cryptographic Functions Designed to meet the security requirements of IoT devices, the DS28S60 includes HW-based cryptographic accelerators. The cryptographic toolbox enables client/server applications to communicate over the Internet in a way that is designed to prevent eavesdropping, tampering, and message forgery. Segregating the cryptographic functions from the main IoT microcontroller simplifies the overall IoT development effort and ensures the application level code does not interfere with the security implementation. Typical cryptographic command times are listed in Table 1. Table 1. Typical Cryptographic Times CRYPTOGRAPHIC TASK TIME ECDSA computation tOP x 100 SHA-256 computation tOP x 50 Memory Memory Resources A secured flash memory array is configured to provide up to 92 pages (32 bytes per page) of programmable user memory. In addition, the flash memory includes reserved pages for keys and secrets. Multiple user-programmable protection modes exist for the user memory space including ECDSA and SHA-256 HMAC R/W authentication protections or optionally left unprotected. With these options, general-purpose memory can be flexibly configured to store end application data ranging from nonsensitive calibration constants to critically sensitive host-system crypto keys. 64-Bit ROM ID Each DS28S60 contains a unique ROM ID that is 64 bits long. The first 8 bits are a family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits. See Figure 1 for details. The CRC is generated using a polynomial generator consisting of a shift register and XOR gates. The polynomial is X8 + X5 + X4 + 1. Additional information about the CRC is available in Application Note 27: Understanding and Using Cyclic www.maximintegrated.com 19-100793 Maxim Integrated | 11 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Redundancy Checks with Maxim 1-Wire and iButton Products. LSB MSB 8-BIT CRC CODE MSB 48-BIT SERIAL NUMBER LSB MSB 8-BIT FAMILY CODE [55h] LSB MSB LSB Figure 1. 64-Bit ROM ID Device Function Commands After configuring the SPI interface for communication with the DS28S60, a device function command can be transmitted. The data transfer is verified when writing and reading by a CRC of 16-bit type (CRC-16). The CRC-16 is computed as described in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim 1-Wire and iButton Products. Refer to the DS28S60 Security User Guide for a list of supported commands. Each command requires a code and one or more parameters. Commands are used to configure, read, write, and perform cryptographic operations. All commands, parameters and data are 8-bit each and require eight serial clock cycles to transmit. The commands, parameters and data are always transferred most significant bit first. All commands are synchronized to the falling edge of the slave select (SS) input signal. Prior to transmitting a command code, the SPIS_SS signal must be driven low and must remain low until the completion of the command including the command code, the parameters and all data bits. Any low-to-high transition of the SPIS_SS input prior to completion of the command terminates the in-process command and results in the DS28S60 entering standby mode. SPI Modes The DS28S60 supports SPI communications running in either of the following two SPI modes: ● Mode 0 (CPOL = 0, CPHA = 0): Data is sampled at the leading rising edge of the clock. ● Mode 3 (CPOL = 1, CPHA =1): Data is sampled on the trailing rising edge of the clock. Details of the timing are described in Figure 2. If enabled, an autodetect feature is available to detect between Mode 0 and Mode 3. The feature works by checking if the SPIS_SCK signal is low (Mode 0) or high (Mode 3) before the falling edge of the SPIS_SS signal during the tSAD time. Mode 1 and Mode 2 are not supported. www.maximintegrated.com 19-100793 Maxim Integrated | 12 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA CPHA = 0: CPHA = 1: SPIS_SS (SHOWN ACTIVE LOW) SAMPLE SHIFT SAMPLE SHIFT SHIFT SAMPLE SHIFT SAMPLE tSSE tSAD tSSH tSCK tSSD tSCH tSCL SPIS_SCK CPOL/CPHA 0/0 OR 1/1 SPIS_MOSI (INPUT) tSIS MSB tSIH MSB-1 LSB tSOV SPIS_MISO (OUTPUT) MSB MSB-1 tSLH LSB Figure 2. SPI Mode 0 and 3 Data Sampling Edges www.maximintegrated.com 19-100793 Maxim Integrated | 13 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Typical Application Circuits Simple Application Level Diagram 1.8V 1.8V MCU VDD VDD DS28S60 PWDN GPIO SPIM_SS SPIS_SS SPIM_SCK SPIS_SCK SPIM_MOSI SPIS_MOSI SPIM_MISO SPIS_MISO GND GND CEXT 1µF Ordering Information PART NUMBER DS28S60Q+ USER FLASH MEMORY (KB) TEMP RANGE PIN-PACKAGE 3.6KB -40°C to +105°C 12 TDFN +Denotes a lead(Pb)-free/RoHS-compliant package. www.maximintegrated.com 19-100793 Maxim Integrated | 14 DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA Revision History REVISION NUMBER REVISION DATE 0 3/20 DESCRIPTION Initial release PAGES CHANGED — For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2020 Maxim Integrated Products, Inc.