DS3902U-530+T&R

Rev 1; 2/06 Dual, NV, Variable Resistors with User EEPROM The DS3902 features a dual, nonvolatile (NV), low temperature-coefficient, variable digital resistor with 256 user-selectable positions. The DS3902 can operate over a wide supply range of 2.4V to 5.5V, and communication with the device is achieved through an I2C compatible serial interface. Internal address settings allow the DS3902 slave address to be programmed to one of 128 possible addresses. The low cost and the small size of the DS3902 make it an ideal replacement for conventional mechanical-trimming resistors. Applications Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Dual 256-Position Linear Digital Resistors Available as 50kΩ/30kΩ or 50kΩ/15kΩ Resistor Settings Stored in NV Memory Low Temperature Coefficient I2C-Compatible Serial Interface Wide Operating Voltage (2.4V to 5.5V) Software Write Protection User-EEPROM Memory Programmable Slave Address Operating Temperature Range: -40°C to +95°C Small 8-Pin µSOP Package Optical Transceivers Ordering Information Optical Transponders Instrumentation and Industrial Controls RESISTOR VALUES (R0, R1) TOP MARK PINPACKAGE DS3902U-530 30kΩ, 50kΩ 3902A 8 µSOP DS3902U-515 15kΩ, 50kΩ 3902B 8 µSOP PART RF Power Amps Audio Power-Amp Biasing Replacement for Mechanical Variable Resistors and DIP Switches Ordering Information continued at end of data sheet. Typical Operating Circuit VCC VCC 0.1μF 4.7kΩ 2-WIRE MASTER IN+ INTX_DISABLE TX_FAULT VCC 4.7kΩ DS3902 SCL H0 SDA H1 ADD_SEL1 GND BIAS SET BIASMAX2 MOD SET APCSET2 MODSET2 PC_MON BS_MON OUT- LASER DRIVER IC OUT+ BIAS+ VCC BIASMD NOTES: 1. WITH ADD_SEL TIED TO GND, THE SLAVE ADDRESS WILL BE A2H. 2. FOR A DETAILED APPLICATION DIAGRAM OF A SPECIFIC LD, CONSULT THE LASER DRIVER DATA SHEET. Pin Configuration appears at end of data sheet. ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS3902 General Description DS3902 Dual, NV, Variable Resistors with User EEPROM ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC, SDA, SCL, H0, and H1 Relative to Ground................................-0.5V to +6.0V Voltage Range on ADD_SEL Relative to Ground ...............-0.5V to (VCC + 0.5V), not to exceed 6.0V Resistor Current ....................................................................3mA Operating Temperature Range ...........................-40°C to +95°C Programming Temperature Range .........................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature ...............................................See IPC/JEDEC J-STD-020A Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +95°C) PARAMETER Supply Voltage SYMBOL TYP MAX UNITS +2.4 +5.5 V VIH VCC + 0.3 V VIL -0.3 +0.3 x VCC V Resistor Inputs H0, H1 -0.3 +5.5 V Resistor Current IRES 3 mA MAX UNITS Input Logic 0 (SDA, SCL, ADD_SEL) (Note 1) MIN 0.7 x VCC Input Logic 1 (SDA, SCL, ADD_SEL) VCC CONDITIONS DC ELECTRICAL CHARACTERISTICS (VCC = +2.4V to +5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Standby Current Input Leakage Low-Level Output Voltage (SDA) SYMBOL ISTBY CONDITIONS` MIN TYP (Note 2) IL 200 µA -1 +1 µA VOL1 3mA sink current 0 0.4 VOL2 6mA sink current 0 0.6 V ANALOG RESISTOR CHARACTERISTICS (VCC = +2.4V to +5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL Resistance Tolerance CONDITIONS` TA = +25°C MIN TYP -20 Position 0 Resistance 160 MAX UNITS +20 % 250 Ω LSB Absolute Linearity (Note 3) -1 +1 Relative Linearity (Note 4) -0.75 +0.75 LSB Temperature Coefficient At position FFh. (Notes 5, 6) -300 +300 ppm/°C -1 +1 µA High-Impedance Resistor Current 2 IRHIZ H0, H1 = VCC _____________________________________________________________________ Dual, NV, Variable Resistors with User EEPROM (VCC = +2.4V to +5.5V, TA = -40°C to +95°C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS TYP 0 MAX UNITS 400 kHz fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 µs tHD:STA 0.6 µs Low Period of SCL tLOW 1.3 µs High Period of SCL tHIGH 0.6 µs Hold Time (Repeated) START Condition (Note 7) MIN SCL Clock Frequency Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 0.9 µs ns Start Setup Time tSU:STA 0.6 µs SDA and SCL Rise Time tR (Note 8) 20 + 0.1 x CB 300 ns SDA and SCL Fall Time tF (Note 8) 20 + 0.1 x CB 300 ns 400 pF 10 ms 2 ms MAX UNITS Stop Setup Time tSU:STO 0.6 SDA and SCL Capacitive Loading CB (Note 8) EEPROM Write Time tWR (Note 9) Input Capacitance CI Startup Time tST µs 5 (Note 6) pF NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.4V to +5.5V, unless otherwise noted.) PARAMETER EEPROM Writes SYMBOL CONDITIONS +70°C (Note 6) MIN TYP 50,000 Note 1: All voltages referenced to ground. Note 2: ISTBY specified for the inactive state measured with SDA = SCL = VCC, ADD_SEL = GND, and with H0 and H1 floating. Note 3: Absolute linearity is the difference of measured value from expected value at resistor position. Expected value is from the measured minimum position to measured maximum position. Note 4: Relative linearity is the deviation of an LSB resistor setting change vs. the expected LSB change. Expected LSB slope of the straight line is the typical operating curves from the measured minimum position to measured maximum position. Note 5: See the Typical Operating Characteristics section. Note 6: Guaranteed by design. Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode. Note 8: CB—total capacitance of one bus line in picofarads. Note 9: EEPROM write begins after a STOP condition occurs. _____________________________________________________________________ 3 DS3902 AC ELECTRICAL CHARACTERISTICS (Figure 1) Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SCL FREQUENCY 120 VCC = +3V 100 80 60 ASEL = GND H0, H1, OPEN SDA = SCL = VCC 0 -20 0 20 40 60 80 25 20 15 40 10 20 5 0 0 100 150 200 250 300 350 400 50 H0 (-530 VERSION) 0 25 50 75 100 125 150 175 200 225 250 RESISTOR SETTING (DEC) TEMPERATURE COEFFICIENT vs. POSITION POSITION FFh RESISTANCE PERCENT CHANGE FROM +25°C vs. TEMPERATURE POSITION 00h RESISTANCE PERCENT CHANGE FROM +25°C vs. TEMPERATURE 1200 1000 TC OF +25°C TO +85°C 800 600 TC OF +25°C TO -40°C 400 200 0 0.6 0.4 0.2 0 12 -0.2 50 100 150 200 -40 250 10 8 6 4 2 0 -2 -4 -6 -8 -10 -20 0 20 40 60 -40 80 -20 0 20 40 60 80 POSITION (DEC) TEMPERATURE (°C) TEMPERATURE (°C) H0, H1 RESISTANCE vs. POWER-UP VOLTAGE H0, H1 RESISTANCE vs. POWER-DOWN VOLTAGE POSITION 7Fh RESISTANCE vs. SUPPLY VOLTAGE RESISTANCE (Ω) 70 H1 60 50 PROGRAMMED RESISTANCE (FFh) 40 80 30 70 H1 60 50 PROGRAMMED RESISTANCE (FFh) 40 30 20 20 H0 (-530 VERSION) 30 28 H0 (-530 VERSION) 24 22 20 18 14 12 0 0 10 2 3 4 5 0 1 2 3 4 5 POWER-DOWN VOLTAGE (V) _____________________________________________________________________ H0 (-530 VERSION) 16 10 POWER-UP VOLTAGE (V) H1 26 10 1 DS3902 toc09 EEPROM RECALL >100k 90 POSITION 7Fh RESISTANCE (Ω) >100k 80 100 DS3902 toc07 100 DS3902 toc08 0 DS3902 toc06 0.8 -200 0 H1 30 SCL FREQUENCY (kHz) 1400 90 35 60 0 DS3902 toc04 TEMPERATURE COEFFICIENT (ppm/°C) 100 80 1600 4 120 TEMPERATURE (°C) RESISTANCE % CHANGE (FROM +25°C) -40 45 RESISTANCE % CHANGE (FROM +25°C) 20 50 40 140 DS3902 toc05 40 160 SUPPLY CURRENT (µA) 140 VCC = SDA = +5V 180 DS3902 toc03 160 200 RESISTANCE (Ω) VCC = +5V DS3902 toc01 STANDBY SUPPLY CURRENT (µA) 180 RESISTANCE vs. RESISTOR SETTING DS3902 toc02 STANDBY SUPPLY CURRENT vs. TEMPERATURE RESISTANCE (Ω) DS3902 Dual, NV, Variable Resistors with User EEPROM 2.4 2.9 3.4 3.9 4.4 SUPPLY VOLTAGE (V) 4.9 5.4 Dual, NV, Variable Resistors with User EEPROM H0 ABSOLUTE LINEARITY vs. POSITION 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.1 DS3902 toc11 H0 ABSOLUTE LINEARITY (LSB) 0.09 H0 RELATIVE LINEARITY (LSB) DS3902 toc10 0.1 H0 RELATIVE LINEARITY vs. POSITION 0.08 0.06 0.04 0.02 0.01 0 0 50 100 150 200 50 100 150 200 POSITION (DEC) POSITION (DEC) H1 ABSOLUTE LINEARITY vs. POSITION H1 RELATIVE LINEARITY vs. POSITION 0.08 0.06 0.04 0.02 0 0.1 250 DS3902 toc13 DS3902 toc12 0.1 H1 ABSOLUTE LINEARITY (LSB) 0 250 H1 RELATIVE LINEARITY (LSB) 0 0.08 0.06 0.04 0.02 0 0 50 100 150 POSITION (DEC) 200 250 0 50 100 150 200 250 POSITION (DEC) _____________________________________________________________________ 5 DS3902 Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) Dual, NV, Variable Resistors with User EEPROM DS3902 Pin Description PIN NAME 1 H0 2 SDA The block diagram of the DS3902 is shown in the Block Diagram section. Detailed descriptions of major components follow. FUNCTION Resistor 0 High Terminal I2C Serial-Data Open-Drain Input/Output 3 SCL I2C Serial-Clock Input 4 GND Ground 5 Detailed Description Memory Map A memory map of the DS3902 is shown in Table 1. Resistors The DS3902 contains two, 256-position (plus High-Z), NV, variable digital resistors. Pins H0 and H1 are the high terminals of Resistor 0 and Resistor 1, respectively. The low terminals of both resistors are tied to ground internally. The resistors are programmed using the I2C serial interface (see the Resistor 0 and Resistor 1 regis- ADD_SEL Address Select 6 H1 7 N.C. Resistor 1 High Terminal No Connection 8 VCC Power-Supply Voltage Block Diagram DS3902 DEVICE MEMORY (EEPROM) SDA I2C INTERFACE SCL 7 MSB 00h HIGH-Z LSB H0 SLAVE ADDRESS RESISTOR 0 256 POSITION 30k OR 15kΩ ADD_SEL 01h X 8 X X X X HI-Z X R1 R0 02h RESISTOR 0 03h RESISTOR 1 8 8 HI-Z VCC VCC H1 04-05h PASSWORD ENTRY (RAM) 06-07h PASSWORD SETTING MSBYTE LSBYTE GND 10-1Fh USER MEMORY (16 BYTES) 6 _____________________________________________________________________ RESISTOR 1 256 POSITION 50kΩ Dual, NV, Variable Resistors with User EEPROM DESCRIPTION ADDR BINARY MSB SLAVE ADDRESS LSB FACTORY DEFAULT Slave Address 00h Configuration 01h X X X X Resistor 0 02h b7 b6 b5 Resistor 1 03h b7 b6 b5 Password Entry 04h PW MSB FFh 05h PW LSB FFh Password Setting 06h PW MSB FFh 07h PW LSB FFh No Memory 08h– 0Fh — User Memory 10h– 1Fh 16 BYTES OF GENERAL PURPOSE EEPROM ACCESS W/O PW W/PW DS3902 Table 1. Memory Map TYPE X A0h R R/W EEPROM X X R1 R0 00h R R/W EEPROM b4 b b2 b1 b0 7Fh R R/W EEPROM b4 b3 b2 b1 b0 7Fh R R/W EEPROM W W RAM — R/W EEPROM — — — — ALL FFh R R/W EEPROM X = Don’t care. ters in the Memory Map). The Configuration register contains a bit (R0 and R1) for each resistor to enable the High-Z state. When one of the High-Z bits is written to a ‘1’, the corresponding resistor goes High-Z. When written back to a ‘0’, the resistor goes back to the programmed resistance. Writing the Resistor 0 or Resistor 1 register to 00h, sets the respective resistor to its minimum position (and minimum resistance). This value can be found in the Analog Resistor Characteristics electrical table. Writing Resistor 0 or Resistor 1 to FFh, sets the resistor to its maximum resistance. The nominal resistance (in ohms) of the resistors can be found in the ordering information table at the beginning of this data sheet. When the DS3902 is powered up, the resistors are both set to High-Z instantaneously while the settings stored in EEPROM are recalled. Slave Address & ADD_SEL Pin The I2C slave address of the DS3902 depends on the state of the ADD_SEL pin. If this pin is low, then the slave address is A2h. If the ADD_SEL pin is high, then the slave address is determined by the value stored in EEPROM at address 00h. Refer to the Memory Map to see the factory default of the slave address. The seven most significant bits are used (the LSB is not used because it is in the bit position of the R/W bit) to allow the slave address to be programmed to one of 128 possible addresses. The I2C interface is described in detail in a later section. Software Write Protection Software write protection is enabled by creating a two byte password and writing it to the Password Setting register (06h to 07h). When write protected, all memory locations can be read, but only the Password Entry register (04h to 05h) can be written. When the correct password is entered, then the memory can be written to. Refer to the Memory Map to see which registers can be read/written with and without the password (PW). When shipped from the factory, the password setting is FFFFh. Likewise, every time the device is powered-up the Password Entry register (which is RAM, not EEPROM) defaults to FFFFh, giving full access to the device. If write protection is not desired, then leave the Password Setting at the factory default and ignore the Password Entry register. I2C Serial Interface Description I2C Definitions The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, START, and STOP conditions. Slave Devices: Slave devices send and receive data at the master’s request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic high states. When the bus is idle it often initiates a low-power mode for slave devices. _____________________________________________________________________ 7 DS3902 Dual, NV, Variable Resistors with User EEPROM SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START tHD:DAT REPEATED START tSU:STO NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN) Figure 1. I2C Timing Diagram START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See the timing diagram for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See the timing diagram for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it immediately initiates a new data transfer following the current one. Repeated STARTS are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 1). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 1) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current 8 SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 1) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8-bits of information transferred from the master to the slave (MSB first) plus a 1-bit acknowledgement from the slave to the master. The 8-bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (MSB first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. _____________________________________________________________________ Dual, NV, Variable Resistors with User EEPROM I2C Communication Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data and generate a STOP condition. Remember the master must read the slave’s acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 2 data bytes and generates a STOP condition. The DS3902 is capable of writing 1 or 2 bytes (1 page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 2-byte page. Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrapping around to the beginning of the present row. Each row begins on even memory addresses. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, and then wait for the bus free or EEPROM write time to elapse. Then the master may generate a new START condition, write the slave address byte (R/W = 0), and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time an EEPROM page is written, the DS3902 requires the EEPROM write time (tW) after the STOP condition to write the contents of the page to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeated addressing the DS3902, which allows the next page to be written as soon as the DS3902 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of tW to elapse before attempting to write again to the device. EEPROM Write Cycles: When EEPROM writes occur, the DS3902 will write the whole EEPROM memory page even if only a single byte on the page was modified. Writes that do not modify all 2-bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page one byte at a time will wear the EEPROM out two times faster than writing the entire page at once. The DS3902’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst case temperature. It is capable of handling approximately 10x that many writes at room temperature. Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. _____________________________________________________________________ 9 DS3902 Slave Address Byte: Each slave on the I 2 C bus responds to a slave addressing byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7-bits and the R/W bit in the least significant bit. The DS3902’s slave address depends on the state of the ADD_SEL pin. If ADD_SEL is low, then the slave address byte is A2h, where the LSB is the R/W bit. If the R/W bit is 0 (such as in A2h), then master indicates it will write data to the slave. If R/W = 1 (A3h in this case), the master will read data from the slave. If an incorrect slave address is written, the DS3902 will assume the master is communicating with another I2C device and ignore the communication until the next START condition is sent. On the other hand, if the ADD_SEL pin is a logic high, then the slave address byte is determined by the Slave Address register saved in EEPROM (address 00h). The LSB of the register is not used since it is in the bit location of the R/W bit. Refer to the Slave Address and ADD_SEL Pin section for more information. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. DS3902 Dual, NV, Variable Resistors with User EEPROM TYPICAL 2-WIRE WRITE TRANSACTION MSB START 1 LSB 0 1 0 SLAVE ADDRESS* 0 0 1 R/W MSB SLAVE ACK b7 LSB b6 READ/ WRITE b5 b4 b3 b2 b1 b0 MSB SLAVE ACK b7 LSB b6 b5 b4 REGISTER ADDRESS b3 b2 b1 b0 SLAVE ACK STOP DATA * THE ADDRESS IS DETERMINED BY THE ADD_SEL PIN. THE EXAMPLES ASSUME ADD_SEL IS TIED TO GND. IF THE ADD_SEL PIN WERE INSTEAD CONNECTED TO VCC. THEN THE ADDRESS WOULD BE DETERMINED BY THE SLAVE ADDRESS REGISTER. EXAMPLE 2-WIRE TRANSACTIONS (WHEN ADD_SEL TIED TO GND) A2h 02h 7Fh A) SINGLE BYTE WRITE -WRITE RESISTOR 0 TO MID POSITION (7FH) START 1 0 1 0 0 0 1 0 SLAVE 0 0 0 0 0 0 1 0 ACK B) SINGLE BYTE READ -READ RESISTOR 1 START 1 0 1 0 0 0 1 0 SLAVE 0 0 0 0 0 0 1 1 SLAVE ACK ACK C) SINGLE BYTE WRITE -SET RESISTOR 1 TO HI-Z START 1 0 1 0 0 0 1 0 D) TWO BYTE WRITE - ENTER THE PASSWORD. SLAVE SLAVE START 1 0 1 0 0 0 1 0 00000 100 ACK ACK D) TWO BYTE READ - READ BOTH RESISTORS IN ONE TRANSACTION. START 1 0 1 0 0 0 1 0 A2h 03h A2h A2h A2h SLAVE 0 1 1 1 1 1 1 1 ACK 00000 001 STOP A3h 01h SLAVE ACK SLAVE ACK REPEATED START DATA 1 0 1 0 0 0 1 1 SLAVE ACK MASTER NACK RES VALUE STOP 02h SLAVE ACK 000 0 0 0 1 0 SLAVE ACK STOP 04h PW MSB 02h SLAVE SLAVE 000 00010 ACK ACK REPEATED START SLAVE ACK SLAVE ACK PW LSB STOP DATA A3h 1 0 1 0 0 0 1 1 SLAVE ACK RES 0 DATA MASTER ACK RES 1 MASTER NACK STOP Figure 2. I2C Communication Examples See Figure 2 for a read example using the repeated START condition to specify the starting memory location. Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it NACKs to indicate the end of the transfer and generates a stop condition. This can be done with or without modifying the address counter’s location before the read cycle. 10 Application Information Using the Resistors as a Switch By taking advantage of the resistor’s high-impedance state, the resistors can be used as a digitally controlled switch. Setting the resistor to position 0 is equivalent to a logic low level. By using an external pull-up resistor, a logic high level can be generated by setting the resistor to the High-Z state. Power Supply Decoupling To achieve best results, it is highly recommended that a decoupling capacitor is used on the IC power supply pins. Typical values of decoupling capacitors are 0.01µF and 0.1µF. Use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the VCC and GND pins of the IC to minimize lead inductance. ____________________________________________________________________ Dual, NV, Variable Resistors with User EEPROM RESISTOR VALUES (R0, R1) TOP MARK PINPACKAGE DS3902U-515+ 15kΩ, 50kΩ 3902B 8 µSOP DS3902U-515+T&R 15kΩ, 50kΩ 3902B 8 µSOP DS3902U-530+ 30kΩ, 50kΩ 3902A 8 µSOP DS3902U-530+T&R 30kΩ, 50kΩ 3902A 8 µSOP DS3902U-530/T&R 30kΩ, 50kΩ 3902A 8 µSOP PART Pin Configuration TOP VIEW H0 1 8 VCC SDA 2 7 N.C. 3 6 H1 GND 4 5 ADD_SEL DS3902 SCL +Denotes lead-free package. T&R denotes tape-and-reel package. µSOP Chip Topology TRANSISTOR COUNT: 11252 SUBSTRATE CONNECTED TO GROUND Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. DS3902 Ordering Information (continued)