Intermediate Frequency Receiver,
800 MHz to 4000 MHz
HMC8100LP6JE
Data Sheet
FEATURES
GENERAL DESCRIPTION
High linearity: supports modulations to 1024 QAM
Rx IF range: 80 MHz to 200 MHz
Rx RF range: 800 MHz to 4000 MHz
Rx power control: 80 dB
SPI programmable bandpass filters
SPI controlled interface
40-lead, 6 mm × 6 mm LFCSP package
The HMC8100LP6JE is a highly integrated intermediate
frequency (IF) receiver chip that converts radio frequency (RF)
input signals ranging from 800 MHz to 4000 MHz down to a
single-ended intermediate frequency (IF) signal of 140 MHz at its
output.
The IF receiver chip is housed in a compact 6 mm × 6 mm
LFCSP package and supports complex modulations up to
1024 QAM. The HMC8100LP6JE device includes two variable
gain amplifiers (VGAs), three power detectors, a programmable
automatic gain control (AGC) block, and selected integrated
band-pass filters with 14 MHz, 28 MHz, 56 MHz, and 112 MHz
bandwidth. The HMC8100LP6JE also supports baseband IQ
interfaces after the mixer so that the chips can be used in the
full outdoor units (ODU) configuration. The HMC8100LP6JE
supports all standard microwave frequency bands from 6 GHz
to 42 GHz.
APPLICATIONS
Point to point communications
Satellite communications
Wireless microwave backhaul systems
DVDD 1
AMP2_P
SPI
2
31 IRM_Q_P
32 IRM_Q_N
33 LOP
34 LON
35 SEN
36 SCLK
37 SDI
38 SDO
HMC8100
39 RST
40 REF_CLK_P
FUNCTIONAL BLOCK DIAGRAM
OTP
AMP2_N 3
FILTER
14MHz
28MHz
56MHz
112MHz
VCC_FILTER 4
FILTER2P 5
VCC_AMP3 6
GND1 7
AGC
30
VDD
29
IRM_I_N
28
IRM_I_P
27
VCC_IRM
26
VCC_VGA1_BALUN
25
VCC_VGA1
24
FILTER1P
PACKAGE
BASE
GND
13867-001
PD3_OUT_RSSI 15
PD3_IN 14
AUX_OUT 13
RX_OUT 11
VCC_VGA3 12
RFIN 20
GND
PD1_OUT 19
21
VCC_PD1 18
AMP1
VGA_EXT_CAP 10
VC_VGA_RF_CAP 17
VCC_AMP1
22
VC_VGA_IF_CAP 16
23
GND2 9
VCC_BB 8
Figure 1.
Rev. B
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Technical Support
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HMC8100LP6JE
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Applications ....................................................................................... 1
External AGC Configuration.......................................................9
General Description ......................................................................... 1
Internal AGC Configuration .................................................... 16
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 18
Revision History ............................................................................... 2
Register Array Assignments and Serial Interface .................. 18
Specifications..................................................................................... 3
Register Descriptions ..................................................................... 20
Electrical Characteristics: 800 MHz to 1800 MHz RF
Frequency Range .......................................................................... 3
Register Array Assignments...................................................... 20
Applications Information .............................................................. 24
Electrical Characteristics: 1800 MHz to 2800 MHz RF
Frequency Range .......................................................................... 4
Schematic/Typical Application Circuit ................................... 24
Electrical Characteristics: 2800 MHz to 4000 MHz RF
Frequency Range .......................................................................... 5
Outline Dimensions ....................................................................... 27
Absolute Maximum Ratings ............................................................ 6
Evaluation Printed Circuit Board (PCB)................................. 25
Ordering Guide .......................................................................... 27
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
REVISION HISTORY
9/2017—Rev. A to Reb. B
Changes to Figure 1 .......................................................................... 1
Changes to Figure 2 and Table 5 ..................................................... 7
Changes to Theory of Operation Section and Register Array
Assignment and Serial Interface Section ..................................... 18
Changes to Figure 50 and Figure 51............................................. 19
Changes to Figure 52 ...................................................................... 25
Changes to Ordering Guide .......................................................... 27
5/2016—v00.0416 to Rev. A
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
Updated Format .................................................................. Universal
Added Pin Configuration Diagram, Renumbered
Sequentially ....................................................................................... 7
Added Ordering Guide .................................................................. 22
04/2016—v00.0416: Initial Version
Rev. B | Page 2 of 27
Data Sheet
HMC8100LP6JE
SPECIFICATIONS
TA = 25°C, IF frequency = 140 MHz, local oscillator (LO) input signal level = 0 dBm, RF input signal level = −80 dBm per tone, filter
bandwidth = 56 MHz, IF gain limit (decimal) = 7, sideband select = lower sideband, AGC select = external AGC, unless otherwise noted,
see the Typical Performance Characteristics section.
ELECTRICAL CHARACTERISTICS: 800 MHz TO 1800 MHz RF FREQUENCY RANGE
Table 1.
Parameter
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
RF INPUT INTERFACE
Input Impedance
Return Loss
IF OUTPUT INTERFACE
Input Impedance
Return Loss
LO INPUT INTERFACE
Input Impedance
Return Loss
DYNAMIC PERFORMANCE
Power Conversion Gain
RF VGA Dynamic Range
IF VGA Dynamic Range
Image Rejection
Noise Figure at PIN (One Tone)
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (OP1dB)
LO Leakage at the IF Input
LO Leakage at the RF Input
RF Leakage at the IF Output
POWER SUPPLY
Supply Voltage
VCCX
VCC − VGA 1
Supply Current
VCCX
VCC − VGA1
1
Min
Typ
600
80
Max
Unit
2000
200
MHz
MHz
50
10
Ω
dB
8
50
13
Ω
dB
2
50
9
Ω
dB
86
52
49
36
5
16
11
−48
−75
−68
dB
dB
dB
dBc
dB
dBm
dBm
dBm
dBm
dBm
81
40
30
11
7
8
−26
−70
−60
3.3
3.3
V
V
600
11
mA
μA
VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
Rev. B | Page 3 of 27
HMC8100LP6JE
Data Sheet
ELECTRICAL CHARACTERISTICS: 1800 MHz TO 2800 MHz RF FREQUENCY RANGE
Table 2.
Parameter
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
RF INPUT INTERFACE
Input Impedance
Return Loss
IF OUTPUT INTERFACE
Input Impedance
Return Loss
LO INPUT INTERFACE
Input Impedance
Return Loss
DYNAMIC PERFORMANCE
Power Conversion Gain
RF VGA Dynamic Range
IF VGA Dynamic Range
Image Rejection
Noise Figure at PIN (One Tone)
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (OP1dB)
LO Leakage at the IF Input
LO Leakage at the RF Input
RF Leakage at the IF Output
POWER SUPPLY
Supply Voltage
VCCX
VCC − VGA 1
Supply Current
VCCX
VCC − VGA1
1
Min
Typ
1600
80
Max
Unit
3000
200
MHz
MHz
50
12
Ω
dB
8
50
13
Ω
dB
7
50
15
Ω
dB
85
47
49
36
5
18
11
−55
−73
−73
dB
dB
dB
dBc
dB
dBm
dBm
dBm
dBm
dBm
77
40
40
30
11
7
7
−45
−66
−65
3.3
3.3
V
V
600
11
mA
μA
VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
Rev. B | Page 4 of 27
Data Sheet
HMC8100LP6JE
ELECTRICAL CHARACTERISTICS: 2800 MHz TO 4000 MHz RF FREQUENCY RANGE
Table 3.
Parameter
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
RF INPUT INTERFACE
Input Impedance
Return Loss
IF OUTPUT INTERFACE
Input Impedance
Return Loss
LO INPUT INTERFACE
Input Impedance
Return Loss
DYNAMIC PERFORMANCE
Power Conversion Gain
RF VGA Dynamic Range
IF VGA Dynamic Range
Image Rejection
Noise Figure at PIN (One Tone)
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (OP1dB)
LO Leakage at the IF Input
LO Leakage at the RF Input
RF Leakage at the IF Output
POWER SUPPLY
Supply Voltage
VCCX
VCC − VGA 1
Supply Current
VCCX
VCC − VGA1
1
Min
Typ
2600
80
Max
Unit
4200
200
MHz
MHz
50
13
Ω
dB
8
50
13
Ω
dB
7
50
14
Ω
dB
82
47
49
38
5
22
12
−65
−66
−72
dB
dB
dB
dBc
dB
dBm
dBm
dBm
dBm
dBm
72
35
30
12
7
8
−48
−62
−65
3.3
3.3
V
V
600
11
mA
μA
VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
Rev. B | Page 5 of 27
HMC8100LP6JE
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
RF Input
LO Input
VCCX
Maximum Junction Temperature to
Maintain 1 Million Hour MTTF
Thermal Resistance (RTH), Junction to
Ground Paddle
Temperature
Operating
Storage
Maximum Peak Reflow Temperature
(MSL3)
ESD Sensitivity (Human Body Model)
Rating
10 dBm
10 dBm
−0.5 V to +5.5 V
−0.3 V to +3.6 V
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
10.5°C/W
−40°C to +85°C
−65°C to +150°C
260°C
2000 V (Class 2)
Rev. B | Page 6 of 27
Data Sheet
HMC8100LP6JE
40
39
38
37
36
35
34
33
32
31
REF_CLK_P
RST
SDO
SDI
SCLK
SEN
LON
LOP
IRM_Q_N
IRM_Q_P
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
HMC8100
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
VDD
IRM_I_N
IRM_I_P
VCC_IRM
VCC_VGA1_BALUN
VCC_VGA1
FILTER1P
VCC_AMP1
AMP1
GND
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW
IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE.
13867-002
RX_OUT
VCC_VGA3
AUX_OUT
PD3_IN
PD3_OUT_RSSI
VC_VGA_IF_CAP
VC_VGA_RF_CAP
VCC_PD1
PD1_OUT
RFIN
11
12
13
14
15
16
17
18
19
20
DVDD
AMP2_P
AMP2_N
VCC_FILTER
FILTER2P
VCC_AMP3
GND1
VCC_BB
GND2
VGA_EXT_CAP
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7, 9, 21
8
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
29
30
31
32
33
Mnemonic
DVDD
AMPT2_P
AMP2_N
VCC_FILTER
FILTER2P
VCC_AMP3
GND1, GND2, GND3
VCC_BB
VGA_EXT_CAP
RX_OUT
VCC_VGA3
AUX_OUT
PD3_IN
PD3_OUT/RSSI
VC_VGA_IF/CAP−
VC_VGA_RF/CAP+
VCC_PD1
PD1_OUT
RFIN
AMP1
VCC_AMP1
FILTER1P
VCC_VGA1
VCC_VGA1_BALUN
VCC_IRM
IRM_I_P
IRM_I_N
VDD
IRM_Q_P
IRM_Q_N
LOP
Description
SPI Digital Power Supply (3.3 V dc). See Figure 52 for the required components.
Second Differential Amplifier Output (Positive).
Second Differential Amplifier Output (Negative).
Power Supply for the Filter (3.3 V dc). See Figure 52 for the required components.
Input of the Third External Filter Amplifier.
Power Supply for the Third External Filter Amplifier (3.3 V dc). See Figure 52 for the required components.
Ground Connect.
Power Supply for the Baseband Blocks (3.3 V dc). See Figure 52 for the required components.
External Capacitor for VGA3. See Figure 52 for the required components.
Receiver Output.
Power Supply for VGA3 (3.3 V dc). See Figure 52 for the required components.
Receiver Auxiliary Output.
Receive AGC Loop Input.
Third Power Detector Output.
Control Voltage of IFVGA/AGC Integrator Capacitor. See Figure 52 for the required components.
Control Voltage of RFVGA/AGC Integrator Capacitor. See Figure 52 for the required components.
Power Supply for the First Power Detector (3.3 V dc). See Figure 52 for the required components.
First Power Detector Output.
Radio Frequency Input. This pin is matched to 50 Ω.
Single-Ended Output of Amplifier 1 (3.3 V dc). See Figure 52 for the required components.
Power Supply for AMP1 (3.3 V dc). See Figure 52 for the required components.
RFVGA Input.
Power Supply for the RFVGA (3.3 V dc). See Figure 52 for the required components.
Power Supply for RFVGA Balun(3.3 V dc). See Figure 52 for the required components.
Power Supply for the Image Reject Mixer (3.3 V dc). See Figure 52 for the required components.
Positive In-Phase IF Output for the Image Reject Mixer.
Negative In-Phase IF Output for the Image Reject Mixer.
Power Supply for Logic Circuitry (3.3 V dc). See Figure 52 for the required components.
Positive Quadrature IF Output for the Image Reject Mixer.
Negative Quadrature IF Output for the Image Reject Mixer.
Local Oscillator Input (Positive). This pin is ac-coupled and matched to 50 Ω.
Rev. B | Page 7 of 27
HMC8100LP6JE
34
35
36
37
38
39
LON
SEN
SCLK
SDI
SDO
RST
40
REF_CLK_P
EPAD
Data Sheet
Local Oscillator Input (Negative). This pin is ac-coupled and matched to 50 Ω.
SPI Serial Enable.
SPI Clock Digital Input.
SPI Serial Data Input.
SPI Serial Data Output.
SPI Reset. RESET must be held low (Logic 0) during power on. This is critical for proper programming and
reliable operation. Refer to the Theory of Operation section.
Filter Calibration Clock.
Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane.
Rev. B | Page 8 of 27
Data Sheet
HMC8100LP6JE
TYPICAL PERFORMANCE CHARACTERISTICS
EXTERNAL AGC CONFIGURATION
90
85
85
80
75
70
14MHz
28MHz
56MHz
112MHz
EXT
60
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Figure 3. Conversion Gain vs. RF Frequency
over Internal and External Filters
85
CONVERSION GAIN (dB)
85
80
75
70
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
1.2
2.0
2.4
2.8
3.2
2.0
2.4
2.8
3.2
3.6
4.0
80
75
70
3.63V
3.30V
2.97V
65
1.6
1.6
Figure 6. Conversion Gain vs. RF Frequency over Temperature, 56 MHz Filter
90
60
0.8
1.2
RF FREQUENCY (GHz)
90
65
+85°C
+25°C
–40°C
60
0.8
3.6
4.0
RF FREQUENCY (GHz)
60
0.8
13867-004
Figure 4. Conversion Gain vs. RF Frequency at Various Local
Oscillator (LO) Powers, 56 MHz Filter
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 7. Conversion Gain vs. RF Frequency at Various VCCx, 56 MHz Filter
45
45
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
35
CONVERSION GAIN (dB)
35
25
15
5
–5
–15
25
15
5
–5
–25
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
VC_VGA_RF (V)
0.9
0.6
0.3
0
13867-005
–15
Figure 5. Conversion Gain vs. VC_VGA_RF at RF = 1 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
–25
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
VC_VGA_RF (V)
0.9
0.6
0.3
0
13867-008
CONVERSION GAIN (dB)
70
65
RF FREQUENCY (GHz)
CONVERSION GAIN (dB)
75
13867-007
65
80
13867-006
CONVERSION GAIN (dB)
90
13867-003
CONVERSION GAIN (dB)
Lower sideband selected, maximum gain.
Figure 8. Conversion Gain vs. VC_VGA_RF at RF = 2 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
Rev. B | Page 9 of 27
HMC8100LP6JE
Data Sheet
Lower sideband selected, maximum gain.
45
90
+85°C
+25°C
–40°C
25
15
5
–5
60
50
40
30
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
VC_VGA_RF (V)
20
13867-009
–25
Figure 9. Conversion Gain vs. VC_VGA_RF at RF = 4 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
VC_VGA_IF (V)
Figure 12. Conversion Gain vs. VC_VGA_IF at RF = 1 GHz, 56 MHz Filter
(VC_VGA_RF = 3.3 V)
90
90
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
80
CONVERSION GAIN (dB)
80
70
60
50
40
60
50
40
30
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0
0.3
VC_VGA_IF (V)
20
13867-010
20
Figure 10. Conversion Gain vs. VC_VGA_IF at RF = 2 GHz, 56 MHz Filter
(VC_VGA_RF = 3.3 V)
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
VC_VGA_IF (V)
13867-013
30
70
Figure 13. Conversion Gain vs. VC_VGA_IF at RF = 4 GHz, 56 MHz Filter,
(VC_VGA_RF = 3.3 V)
10
10
14MHz
28MHz
56MHz
112MHz
9
8
+85°C
+25°C
–40°C
9
8
NOISE FIGURE (dB)
7
6
5
4
3
2
7
6
5
4
3
2
1
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 11. Noise Figure vs. RF Frequency over Internal Filters
13867-011
1
0
0.8
1.2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
13867-014
CONVERSION GAIN (dB)
70
13867-012
–15
NOISE FIGURE (dB)
+85°C
+25°C
–40°C
80
CONVERSION GAIN (dB)
CONVERSION GAIN (dB)
35
Figure 14. Noise Figure vs. RF Frequency over Temperature, 56 MHz Filter
Rev. B | Page 10 of 27
Data Sheet
HMC8100LP6JE
Lower sideband selected, maximum gain.
10
8
5
4
3
4
3
2
1
1
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 15. Noise Figure vs. RF Frequency at Various LO Powers, 56 MHz Filter
0
0.8
45
45
40
40
IMAGE REJECTION (dBc)
50
30
25
20
15
10
0
0.8
1.2
1.6
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 16. Image Rejection vs. RF Frequency over Internal Filters
0
0.8
IMAGE REJECTION (dBc)
40
35
30
25
20
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
35
30
25
20
15
10
3.63V
3.30V
2.97V
5
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
13867-017
1.6
+85°C
+25°C
–40°C
Figure 19. Image Rejection vs. RF Frequency over Temperature, 56 MHz Filter
40
1.2
4.0
RF FREQUENCY (GHz)
45
0
0.8
3.6
15
50
5
3.2
20
45
10
2.8
25
50
15
2.4
30
5
2.0
2.0
35
10
14MHz
28MHz
56MHz
112MHz
5
1.6
Figure 18. Noise Figure vs. RF Frequency at Various VCCx, 56 MHz Filter
50
35
1.2
RF FREQUENCY (GHz)
13867-016
IMAGE REJECTION (dBc)
5
2
0
0.8
IMAGE REJECTION (dBc)
6
13867-019
6
7
13867-018
NOISE FIGURE (dB)
7
13867-015
NOISE FIGURE (dB)
8
3.63V
3.30V
2.97V
9
Figure 17. Image Rejection vs. RF Frequency at Various LO Powers,
56 MHz Filter
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 20. Image vs. RF Frequency at Various VCCx, 56 MHz Filter
Rev. B | Page 11 of 27
13867-020
9
10
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
HMC8100LP6JE
Data Sheet
Lower sideband selected, maximum gain.
32
32
24
20
20
IP3 (dBm)
24
16
12
8
8
4
4
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 21. Output IP3 vs. RF Frequency over Internal Filters
0
0.8
2.4
2.8
3.2
3.6
4.0
3.63V
3.30V
2.97V
28
24
20
16
16
12
12
8
8
4
4
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 22. Output IP3 vs. RF Frequency at Various LO Powers, 56 MHz Filter
13867-025
IP3 (dBm)
20
13867-022
Figure 25. Output IP3 vs. RF Frequency at Various VCCx, 56 MHz Filter
0
0
+85°C
+25°C
–40°C
–5
RETURN LOSS (dB)
–10
–15
–20
–10
–15
–20
–25
–30
–30
1.2
1.6
2.0
2.4
2.8
3.2
RF FREQUENCY (GHz)
3.6
4.0
4.4
4.8
13867-023
–25
0.8
+85°C
+25°C
–40°C
–5
Figure 23. RF Return Loss vs. RF Frequency over Temperature (Optimize RF
Return Loss by Adjusting Capacitor C12, see Figure 52)
Rev. B | Page 12 of 27
–35
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
LO FREQUENCY (GHz)
Figure 26. LO Return Loss vs. LO Frequency over Temperature
13867-026
IP3 (dBm)
2.0
32
24
–35
0.4
1.6
Figure 24. Output IP3 vs. RF Frequency over Temperature, 56 MHz Filter
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
28
0
0.8
1.2
RF FREQUENCY (GHz)
32
RETURN LOSS (dB)
16
12
0
0.8
+85°C
+25°C
–40°C
28
13867-021
IP3 (dBm)
28
13867-024
14MHz
28MHz
56MHz
112MHz
Data Sheet
HMC8100LP6JE
Lower sideband selected, maximum gain.
0
0
+85°C
+25°C
–40°C
LO TO RF LEAKAGE
LO TO IF LEAKAGE
–10
–20
–10
LEAKAGE (dBm)
RETURN LOSS (dB)
–5
–15
–20
–30
–40
–50
–25
–60
–30
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
IF FREQUENCY (GHz)
–80
0.8
2.8
3.2
3.6
4.0
4.4
LO TO (AMP2_P + AMP2_N) LEAKAGE
–10
–20
–30
–40
–50
–30
–40
–50
–60
–60
–70
–70
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
–80
0.8
13867-028
1.2
Figure 28. RF Leakage vs. RF Frequency at IF Port with 56 MHz Filter and at
(AMP2_P + AMP2_N) Pins
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
LO FREQUENCY (GHz)
13867-031
LEAKAGE (dBm)
–20
LEAKAGE (dBm)
2.4
0
RF TO IF LEAKAGE
RF TO (AMP2_P + AMP2_N) LEAKAGE
–10
Figure 31. LO Leakage vs. LO Frequency at (AMP2_P + AMP2_N) Pins
20
20
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
10
CONVERSION GAIN (dB)
10
CONVERSION GAIN (dB)
2.0
LO FREQUENCY (GHz)
0
0
–10
–20
–30
0
–10
–20
–30
–40
–40
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
IF FREQUENCY (GHz)
Figure 29. 14 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
–50
0.05
13867-029
–50
0.05
1.6
Figure 30. LO Leakage vs. LO Frequency at RF and IF Ports with 56 MHz Filter
Figure 27. IF Return Loss vs. IF Frequency over Temperature
–80
0.8
1.2
0.10
0.15
0.20
0.25
0.30
0.35
IF FREQUENCY (GHz)
0.40
0.45
0.50
13867-032
0
13867-027
–35
13867-030
–70
Figure 32. 28 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
Rev. B | Page 13 of 27
HMC8100LP6JE
Data Sheet
Lower sideband selected, maximum gain.
20
20
+85°C
+25°C
–40°C
0
–10
–20
–30
–40
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Figure 33. 56 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Figure 36. 112 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
2.0
+85°C
+25°C
–40°C
1.9
1.8
PD3 OUTPUT VOLTAGE (V)
1.7
1.6
1.5
1.4
1.3
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
–35
–30
–25
–20
–15
–10
–5
0
5
10
IF OUTPUT POWER (dBm)
1.0
–50 –45 –40 –35 –30 –25 –20 –15 –10
–5
0
5
10
IF OUTPUT POWER (dBm)
Figure 34. PD3 Output Voltage vs. IF Power Output at RF = 1 GHz,
56 MHz Filter
13867-037
–40
13867-034
1.1
Figure 37. PD3 Output Voltage vs. IF Power Output at RF = 2 GHz,
56 MHz Filter
2.0
15
+85°C
+25°C
–40°C
14
1.8
13
1.7
12
P1dB (dBm)
1.6
1.5
1.4
11
10
9
8
1.2
7
1.1
6
1.0
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10
–5
0
5
IF OUTPUT POWER (dBm)
Figure 35. PD3 Output Voltage vs. IF Power Output at RF = 4 GHz,
56 MHz Filter
13867-035
1.3
5
0.8
+85°C
+25°C
–40°C
1.2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
13867-038
PD3 OUTPUT VOLTAGE (V)
–30
IF FREQUENCY (GHz)
+85°C
+25°C
–40°C
1.2
PD3 OUTPUT VOLTAGE (V)
–20
–50
0.05
2.0
1.9
1.9
–10
13867-036
0.10
IF FREQUENCY (GHz)
1.0
–45
0
–40
13867-033
–50
0.05
+85°C
+25°C
–40°C
10
CONVERSION GAIN (dB)
CONVERSION GAIN (dB)
10
Figure 38. Output P1dB vs. RF Frequency over Temperature, 56 MHz Filter
Rev. B | Page 14 of 27
Data Sheet
HMC8100LP6JE
Lower sideband selected, maximum gain.
15
14
13
P1dB (dBm)
12
11
10
9
8
7
6
5
0.8
1.2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
13867-039
4
5
6
7
Figure 39. Output P1dB vs. RF Frequency over IF Gain Limit, 56 MHz Filter
Rev. B | Page 15 of 27
HMC8100LP6JE
Data Sheet
INTERNAL AGC CONFIGURATION
80
80
70
70
60
60
50
50
IM3 (dBc)
40
30
30
20
+85°C
+25°C
–40°C
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
INPUT POWER (dBm)
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
Figure 43. IM3 vs. Input Power over Temperature, RF = 2 GHz
80
70
70
60
NOISE FIGURE (dB)
60
50
40
30
+85°C
+25°C
–40°C
50
40
30
20
20
+85°C
+25°C
–40°C
10
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
INPUT POWER (dBm)
0
–90
13867-041
10
Figure 41. IM3 vs. Input Power over Temperature, RF = 4 GHz
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT POWER (dBm)
13867-044
IM3 (dBc)
0
INPUT POWER (dBm)
Figure 40. IM3 vs. Input Power over Temperature, RF = 1 GHz
Figure 44. Noise Figure vs. Input Power over Temperature, RF = 1 GHz
70
70
+85°C
+25°C
–40°C
60
NOISE FIGURE (dB)
40
30
50
40
30
20
20
10
10
–70
–60
–50
–40
–30
INPUT POWER (dBm)
–20
–10
0
0
–90
13867-042
–80
+85°C
+25°C
–40°C
60
50
0
–90
+85°C
+25°C
–40°C
10
13867-040
10
13867-043
20
NOISE FIGURE (dB)
40
Figure 42. Noise Figure vs. Input Power over Temperature, RF = 2 GHz
–80
–70
–60
–50
–40
–30
INPUT POWER (dBm)
–20
–10
0
13867-045
IM3 (dBc)
POUT = −9 dBm per tone, lower sideband, and 56 MHz filter selected.
Figure 45. Noise Figure vs. Input Power over Temperature, RF = 4 GHz
Rev. B | Page 16 of 27
Data Sheet
HMC8100LP6JE
POUT = −9 dBm per tone, lower sideband, and 56 MHz filter selected.
–4
–4
+85°C
+25°C
–40°C
–8
–10
–12
–14
–70
–60
–50
–40
–30
–20
–10
0
–12
–14
–18
–90
13867-046
–80
Figure 46. Output Power vs. Input Power over Temperature, RF = 1 GHz
–8
–10
–12
–14
–70
–60
–50
–40
–30
INPUT POWER (dBm)
–20
–10
0
13867-047
–16
–80
–70
–60
–50
–40
–30
–20
–10
0
Figure 48. Output Power vs. Input Power over Temperature, RF = 2 GHz
+85°C
+25°C
–40°C
–6
–80
INPUT POWER (dBm)
–4
OUTPUT POWER (dBm)
–10
–16
INPUT POWER (dBm)
–18
–90
–8
13867-048
–16
–18
–90
+85°C
+25°C
–40°C
–6
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
–6
Figure 47. Output Power vs. Input Power over Temperature, RF = 4 GHz
Rev. B | Page 17 of 27
HMC8100LP6JE
Data Sheet
THEORY OF OPERATION
The HMC8100LP6JE utilizes an input low noise amplifier
(LNA) cascaded with a variable gain amplifier (VGA), which
can either be controlled by the internal AGC or external
voltages, that feeds the RF signals to an image reject mixer. The
local oscillator port can either be driven single ended through
LON or differentially through the combination of LON and
LOP.
The radio frequency is then converted to intermediate
frequencies, which can either feed off chip via baseband
differential outputs or feed on chip into a programmable bandpass filter. It is recommended during IF mode operation that
the baseband outputs be unconnected. The programmable
band-pass filter on chip has four programmable bandwidths
(14 MHz, 28 MHz, 56MHz, and 112 MHz). The programmable
band-pass filter has the capability to adjust the center frequency.
From the factory, a filter calibration is conducted and the center
frequency of the filter is set to 140 MHz. This calibration can be
recalled via SPI control or the customer can adjust the center
frequency, but the calibration value must be stored off chip (see
the Register Array Assignments section). An external filter
option can be utilized to allow the customer to select other filter
bandwidths/responses that are not available on chip. The
external filter path coming from the image reject mixer feeds
into an amplifier that has differential outputs. The output of the
external filter can be fed back into the chip, which is then
connected to another amplifier.
REGISTER ARRAY ASSIGNMENTS AND SERIAL
INTERFACE
The register arrays for the HMC8100LP6JE are organized into
nine registers of 16 bits. Using the serial interface, the arrays are
written or read one row at a time, as shown in Figure 50 and
Figure 51. Figure 50 shows the sequence of signals on the enable
(SEN), CLK, and data (SDI) lines to write one 16-bit array of data
to a single register. The enable line goes low, the first of 24 data
bits is placed on the data line, and the data is sampled on the
rising edge of the clock. The data line should remain stable for
at least 2 ns after the rising edge of CLK. The device supports a
serial interface running up to 10 MHz, the interface is 3.3 V
CMOS logic.
A write operation requires 24 data bits and 24 clock pulses, as
shown in Figure 50. The 24 data bits contain the 3-bit chip
address, followed by the 5-bit register array number, and finally
the 16-bit register data. After the 24th clock pulses of the write
operation, the enable line returns high to load the register array
on the IC.
A read operation requires 24 data bits and 48 clock pulses, as
shown in Figure 51. For every register read operation you must
first write to Register 7. The data written should contain the
3-bit chip address, followed by the 5-bit register number for
Register 7, and finally the 5-bit number of the register to be
read. The remaining 11 bits should be logic zeroes. When the
read operation is initiated, the data is available on the data
output (SDO) pin. The output data bits are placed on the data
line during the rising edge of the clock.
Read Example
If reading Register 2, the following 24 bits should be written to
initiate the read operation.
A VGA follows immediately after the band-pass filter. Control
the IF VGA either by the AGC or external voltages. The output
of the variable gain amplifier is the output of the device.
The SPI RESET pin on the HMC8100LP6JE must be held low
(Logic 0) during power on. This is critical for proper
programming and reliable operation. Apply a RESET low before
the bias voltage is applied to the device or use a pull-down
resistor on the RESET pin.
Rev. B | Page 18 of 27
00000000000 00010 00111 110
ZERO BITS (11 BITS)
REGISTER 7 ADDRESS (5 BITS)
REGISTER TO BE READ (5 BITS)
CHIP ADDRESS (3 BITS)
Figure 49. Sample Bits to Initiate Read
13867-049
The HMC8100LP6JE is a highly integrated intermediate
frequency (IF) receiver chip that converts radio frequency (RF)
to a single-ended IF signal at its output. The internal active gain
circuit (AGC) of the HMC8100LP6JE is able to actively level the
output power at the IF output via SPI control. The gain control of
the HMC8100LP6JE can be controlled externally as an
alternative option via the VC_VGA_RF and VC_VGA_IF pins
with voltages ranging from 3.3 V (minimum attenuation) to 0 V
(maximum attenuation).
Data Sheet
HMC8100LP6JE
24 CLOCK CYCLES
SEN
24
1
CLK
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
REGISTER
ADDRESS
MSB
MSB
LSB
WRITE DATA
CHIP
ADDRESS
13867-050
3
LSB
2
MSB
1
LSB
0
SDI
Figure 50. Timing Diagram, SPI Register Write
24 CLOCK CYCLES
SEN
24 CLOCK CYCLES
24
1
24
1
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SDO
READ DATA
Figure 51. Timing Diagram, SPI Register Read
Rev. B | Page 19 of 27
LSB
LSB
LSB
MSB
LSB
MSB
CHIP
READ
ADDRESS
REGISTER
REG 7
ADDRESS ADDRESS
LSB
MSB
MSB
ALL ZEROS
13867-051
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSB
SDI
HMC8100LP6JE
Data Sheet
REGISTER DESCRIPTIONS
REGISTER ARRAY ASSIGNMENTS
In the Access columns (Table 6 through Table 14), R means read, W means write, and R/W means read/write.
Enable Bits
Table 6. Enable Register, (Address 0x01)
Bit No.
15
Bit Name
PD2_EN
14
13
Factory diagnostics
PD3_AMP1_EN
12
11
Reserved
AMP1_EN
10
RF_VGA_EN
9
IRM_EN
8
FIL2_EN
7
IF_VGA_EN
6
5
Factory diagnostics
PD1_EN
4
PD3_EN
3
AGC_EN
2
AMP3_PDWN
1
AMP2_PDWN
0
IQ_BUF_EN
Description
Power Detector 2 enable
0 = disable
1 = enable
Logic 0 for normal operation
Auxiliary output (Pin 13) enable
0 = disable
1 = enable
Logic 1 for normal operation
LNA enable
0 = disable
1 = enable
RF VGA enable
0 = disable
1 = enable
Image reject mixer enable
0 = disable
1 = enable
Filter 2 enable
0 = disable
1 = enable
Filter 2 enable
0 = disable
1 = enable
Logic 0 for normal operation
Power Detector 1 enable
0 = disable
1 = enable
Power Detector 3 enable
0 = disable
1 = enable
Available gain control (AGC) enable
0 = enable
1 = disable
Amplifier 3 power-down
0 = enable
1 = disable
Amplifier 2 power-down
0 = enable
1 = disable
IQ buffer enable
0 = disable
1 = enable
Rev. B | Page 20 of 27
Reset
0x1
Access
R/W
0x0
0x1
R/W
R/W
0x1
0x1
R/W
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x0
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x0
R/W
Data Sheet
HMC8100LP6JE
Image Reject and Band-Pass Filter Bits
Table 7. Image Reject and Band-Pass Filter Register, (Address 0x02)
Bit No.
15
Bit Name
IRM_IS
[14:13]
FIL2_SEL
12
SEL_EXT_FIL
11
10
Reserved
FIL2_CAL_OVR
9
FIL2_CAL_EN
8
[7:0]
Reserved
FIL2_FREQ_SET
Description
Image sideband select
0 = lower sideband
1 = upper sideband
Internal band-pass filter select
00 = 14 MHz
01 = 28 MHz
10 = 56 MHz
11 = 112 MHz
Select external filter
0 = internal
1 = external
Not used
Override on-chip calibration and use 8-bit word from SPI
0 = use on-chip calibration word
1 = use FIL2_FREQ_SET word from SPI
Enable filter center frequency calibration
0 = disable
1 = enable (transition from 0 to 1)
Not used
Internal band-pass filter center frequency setting
Reset
0x1
Access
R/W
0x2
R/W
0x0
R/W
0x0
0x1
R/W
R/W
0x0
R/W
0x1
0x85
R/W
R/W
Description
Logic 1000 for normal operation
Override SPI FIL2_FRQ_SET and use 8-bit word from OTP
0 = select OTP setting
1 = select SPI setting
Logic 110 1001 1111 for normal operation
Reset
0x8
0x0
Access
R/W
R/W
0x69F
R/W
Description
Active gain control (AGC) select
0x3 = internal AGC mode
0xC = external AGC mode
Active gain control external capacitor select
0 = no external capacitor
1 = external capacitor
AGC bandwidth
000 = 17 Hz
001 = 22 Hz
010 = 33 Hz
011 = 67 Hz
100 = 83 Hz
101 = 111 Hz (recommended setting)
110 = 167 Hz
111 = 333 Hz
Reset
0x3
Access
R/W
0x0
R/W
0x4
R/W
Band-Pass Filter Bits: OTP and SPI
Table 8. Band-Pass Filter Register, (Address 0x03)
Bit No.
[15:12]
11
Bit Name
Reserved
FIL_OPT_MUX_SEL
[10:0]
Reserved
AGC
Table 9. AGC Register, (Address 0x04)
Bit No.
[15:12]
Bit Name
AGC_SELECT
11
AGC_EXT_CAP_SEL
[10:8]
AGC_BW
Rev. B | Page 21 of 27
HMC8100LP6JE
Bit No.
[7:6]
Bit Name
VGA3_GAIN
[5:0]
POUT_CTRL
Data Sheet
Description
VGA 3 attentuation
00 = 0 dB (recommended setting)
01 = 5 dB
10 = 10 dB
11 = 15 dB
Power output control
0x0 = −54 dBm
0x1 = −53 dBm
0x2 = …
0x3E = +8 dBm
0x3F = +9 dBm
Reset
0x0
Access
R/W
0x30
R/W
Description
Not used
IF gain limit
000 = 0 dB
001 = 6 dB
010 = 12 dB
011 = 18 dB
100 = 24 dB
101 = 30 dB
110 = 36 dB
111 = 42 dB
Logic 1 0000 0100 for normal operation
Reset
0xA
0x4
Access
R/W
R/W
0x104
R/W
Reset
0x0
0x1
0x1
0x85
Access
R
R
R
R
AGC: IF Gain Limit Bits
Table 10. AGC Register, (Address 0x05)
Bit No.
[15:12]
[11:9]
Bit Name
Reserved
IF_GAIN_LIMIT
[8:0]
Reserved
Band-Pass Filter Bits: Calibration and 8-Bit Word Frequency
Table 11. Band-Pass Filter Register, (Address 0x06)
Bit No.
[15:10]
9
8
[7:0]
Bit Name
Reserved
FIL2_CAL_OVFL
FIL2_VCAL_END
FL2_FC_CAL
Description
Not used
FIL2 calibration overflow signal
FIL2 calibration end signal
FIL2 8-bit word frequency setting, read only
Rev. B | Page 22 of 27
Data Sheet
HMC8100LP6JE
AGC: Blocker Power Detector Bits
Table 12. AGC Register, (Address 0x12)
Bit No.
[15:8]
7
6
Bit Name
Reserved
Reserved
AGC_BLOCKER_MODE_EN
[5:3]
AGC_BLOCKER_PD2_REF
[2:0]
AGC_BLOCKER_PD2_LOOP_BW
Description
Not used
Not used
AGC blocker mode enable
0 = off
1 = on
AGC blocker power detector reference level
000 = −4 dBm
001 = −2 dBm
010 = 0 dBm
011 = 2 dBm
100 = 4 dBm
101 = 6 dBm
110 = 8 dBm
111 = 10 dBm
AGC blocker power detector loop bandwidth control
000 = 17 Hz
001 = 22 Hz
010 = 33 Hz
011 = 67 Hz
100 = 83 Hz
101 = 111 Hz
110 = 167 Hz
111 = 333 Hz
Reset
0xF0
0x0
0x01
Access
R/W
R/W
R/W
0x3
R/W
0x4
R/W
Description
Not used
Not used
I phase adjust
Reset
0xF
0x0
0x0
Access
R/W
R/W
R/W
Description
Not used
Not used
Q phase adjust
Reset
0xF
0x0
0x0
Access
R/W
R/W
R/W
Phase I Bits
Table 13. Phase I Register, (Address 0x14)
Bit No.
[15:12]
[11:9]
[8:0]
Bit Name
Reserved
Reserved
I_PHASE_ADJ
Phase Q Bits
Table 14. Phase Q Register, (Address 0x15)
Bit No.
[15:12]
[11:9]
[8:0]
Bit Name
Reserved
Reserved
Q_PHASE_ADJ
Rev. B | Page 23 of 27
HMC8100LP6JE
Data Sheet
APPLICATIONS INFORMATION
During operation at P1dB, the IF gain limit of the
HMC8100LP6JE, as described in the Register Array
Assignments and Serial Interface section, needs to be limited by
the radio frequency (RF), as listed in Table 15. There is a
recommended IF gain limit setting and maximum allowed IF
gain limit setting that is to be used.
SCHEMATIC/TYPICAL APPLICATION CIRCUIT
Table 15. Recommended IF Gain Limit Settings by RF
Frequency
RF Frequency
(GHz)
0.8 to 1.8
1.8 to 2.8
2.8 to 4.0
Rev. B | Page 24 of 27
Maximum
Setting
5
6
7
Recommended
Setting
4
5
6
VCC_OTP
VCC_3P3V
2
J18
J17
J16
J15
J14
J13
3059
140MHz
F1
1
J6
R7
49.9
4
5
T1
3
2
1
IFOUT
2 - 800 MHz
1:4
MABAES0061
10NF
C39
C30
10nF
C54
10uF
10nF
C34
VCC_AMP2
VCC_VGA3
C31
100PF
DVDD
1UF
R8
75
VCC_BB
VCC_AMP3
C56
10uF
C55
10uF
VCC_AMP2
C27
10nF
L2
2.2UH
C57
10uF
C67
10uF
C33
10nF
C28
100PF
R6
160
R5
160
C58
10uF
C36
10nF
C64
10nF
C32
100PF
1UF
C29
C38
10nF
C35
100PF
C63
100PF
C37
100PF
VCC_BB
GND1
VCC_AMP3
FILTER2P
VCC_FILTER
AMP2N
AMP2P
DVDD
R11
4.99
C13
10nF
GND2
10 VGA_ext_cap
9
8
7
6
5
4
3
2
1
REF_CLK_P 40
U1
HMC8100LP6JE
11 RX_OUT
12
Vcc_VGA3
13 Aux_out
130-150HMz
RBP-140+
PD3_in
R15
49.9
14
PD3_out/RSSI
15
PD3_OUT
Vc_VGA_IF/Cap-
16
VC_VGA_EXT23
C24
RST 39
SDO 38
37
SDI
36
SCLK
35
SEN
34
32
VCC_IRM2
IRM2_IN
IRM2_IP
VDD5V
C69
10nF
DEPOP
R16
49.9
GND
AMP1
VCC_AMP1
FILTER1P
VCC_VGA1
VCC_VGA1_BALUN
C70
1NF
2
Rev. B | Page 25 of 27
F3
Figure 52. PCB Schematic/Typical Applications Circuit
6
31
IRM2_QN
IRM2_QP
33
LON
Vc_VGA_RF/Cap+
17
VC_VGA_EXT01
LOP
VCC_PD1
18
RFIN
20
PD1_OUT
19
PD1_OUT
REF_CLK_N
21
22
23
24
25
26
27
28
29
30
LOP
LON
C12
5PF
J8
J7
RFIN
L1
15NH
C15
100PF
5PF
C9
C11
100PF
VCC_AMP1
C7
100PF
C6
100PF
C3
100PF
C2
100PF
C66
100PF
J4
C16
10nF
C8
10nF
C5
10nF
C4
10nF
C1
10nF
C65
10nF
1
C49
10uF
VCC_PD1
DC - 5000 MHz
F2
LFCN-5000
C47
10uF
VCC_AMP1
C46
10uF
VCC_VGA0
C45
10uF
VCC_BALUN
C44
10uF
VCC_IRM
C68
10uF
VCC_OTP
3
VCC_3P3V
T2
5
4
VCC_VGA3
NC
3
1
4
2
7 VCC_VGA0
5 VCC_BALUN
3 VCC_IRM
1 NC
8
6
4
2
87759-1250
9 VCC_AMP1
10
11 VCC_PD1
VCC_BB
5
J19
VCC_AMP3
7
12
DVDD
9
6
11 VCC_AMP2
MABAES0061
1:4
2 - 800 MHz
T3
8
87759-1250
J20
1
2
3
MABAES0061
1:4
2 - 800 MHz
5
10
12
1UF
C43
1
2
3
J3
4
32
31
NC
NC
30
29
SSW-116-22-F-D-VS
1UF
C42
NC
NC
28
27
NC
NC
26
25
NC
24
23
NC
22
NC
21
NC
17
NC
20
NC
16
15
NC
19
NC
14
13
NC
NC
NC
12
11
NC
18
NC
10
9
NC
NC
8
7
NC
NC
4
6
2
3
5
1
NC
NC
BBOUT_I
BBOUT_Q
J10
J9
C52
10uF
3
PD1_OUT
J12
TSM-103-01-L-SV
2
1
TSM-103-01-L-SV
3
2
1
J11
DVDD
C23
10nF
NC
VC_VGA_EXT23
VC_VGA_EXT01
NC
PD3_OUT
C22
100PF
13867-052
J5
Data Sheet
HMC8100LP6JE
EVALUATION PRINTED CIRCUIT BOARD (PCB)
Data Sheet
13867-053
HMC8100LP6JE
Figure 53. Evaluation PCB
Rev. B | Page 26 of 27
Data Sheet
HMC8100LP6JE
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.011
SQ
0.30
0.25
0.20
30
0.50
BSC
0.45
0.40
0.35
TOP VIEW
0.95
0.90
0.85
PKG-000000
SEATING
PLANE
40
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
1
4.60
4.50 SQ
4.40
EXPOSED
PAD
21
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
SIDE VIEW
0.004
BSC
31
BOTTOM VIEW
10
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5.
04-20-2016-A
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 54. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.90 mm Package Height
(CP-40-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
HMC8100LP6JE
Temperature
Range
−40°C to +85°C
MSL
Rating 3
MSL3
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP]
Package
Option
CP-40-22
Package
Marking 4
HMC8100LP6JETR
−40°C to +85°C
MSL3
40-Lead Lead Frame Chip Scale Package [LFCSP]
CP-40-22
H8100
XXXX
EK1HMC8100LP6J
Evaluation Kit
All models are RoHS compliant.
The HMC8100LP6JE and HMC8100LP6JETR lead finishes are NiPdAu.
3
See the Absolute Maximum Ratings section.
4
XXXX is the 4-digit lot number.
1
2
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13867-0-9/17(B)
Rev. B | Page 27 of 27
H8100
XXXX
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