HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLLs with Integrated VCO - SMT
Features
1
• RF Bandwidth:
45 - 1050, 1400 - 2100, 2800 - 4200, 5600
- 8400 MHz
• Maximum Phase Detector Rate
100 MHz
• Ultra Low Phase Noise
-110 dBc/Hz in Band Typ.
• Figure of Merit (FOM) -227 dBc/Hz
• 0.5V/ns
Recommended
Sinusoidal Input
Recommended Swing (Vpp)
Min
Max
Recommended Power Range (dBm)
Recommended
Min
Max
< 10
YES
0.6
2.5
x
x
x
10
YES
0.6
2.5
x
x
x
25
YES
0.6
2.5
ok
8
15
50
YES
0.6
2.5
YES
6
15
100
YES
0.6
2.5
YES
5
15
150
ok
0.9
2.5
YES
4
12
200
ok
1.2
2.5
YES
3
8
Input referred phase noise of the PLL when operating at 50 MHz is between -150 and -156 dBc/Hz at
10 kHz offset depending upon the mode of operation. The input reference signal should be 10 dB better
than this floor to avoid degradation of the PLL noise contribution. It should be noted that such low levels
are only necessary if the PLL is the dominant noise contributor and these levels are required for the system
goals.
27
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
Fax: 978-250-3373
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
1.7
Reference Path ’R’ Divider
Minimum pulse width at the reference buffer input is 2.5 ns. For best spur performance when R = 1, the
pulse width should be (2.5 ns + 8Tps), where Tps is the period of the VCO at the prescaler input. When R
> 1 minimum pulse width is 2.5 ns.
1.8
RF Path ’N’ Divider
The main RF path divider is capable of average divide ratios between 219-5 (524,283) and 20 in fractional
mode, and 219-1 (524,287) to 16 in integer mode. The VCO frequency range divided by the minimum N
divider value will place practical restrictions on the maximum usable PD frequency. For example a VCO
operating at 1.5 GHz in fractional mode with a minimum N divider value of 20 will have a maximum PD
frequency of 75 MHz.
1.9
Charge Pump & Phase Detector
The Phase detector (PD) has two inputs, one from the reference path divider and one from the RF path
divider. When in lock these two inputs are at the same average frequency and are fixed at a constant
average phase offset with respect to each other. We refer to the frequency of operation of the PD as fpd.
Most formulae related to step size, delta-sigma modulation, timers etc., are functions of the operating
frequency of the PD, fpd. fpd is also referred to as the comparison frequency of the PD.
The PD compares the phase of the RF path signal with that of the reference path signal and controls the
charge pump output current as a linear function of the phase difference between the two signals. The
output current varies linearly over a full ±2π radians (±360°) of input phase difference.
1.10
Phase Detector Functions
Phase detector register Reg 0Bh allows manual access to control special phase detector features.
PD_up_en (Reg 0Bh[5]), if 0, masks the PD up output, which prevents the charge pump from pumping up.`
PLLs with Integrated VCO - SMT
The reference path “R” divider is based on a 14-bit counter and can divide input signals by values from 1
to 16,383 and is controlled by rdiv (Reg 02h).
PD_dn_en (Reg 0Bh[6]), if 0, masks the PD down output, which prevents the charge pump from pumping
down.
Clearing both PD_up_en and PD_dn_en effectively tri-states the charge pump while leaving all other
functions operating internally.
PD Force UP Reg 0Bh[9] = 1 and PD Force DN Reg 0Bh[10] = 1 allows the charge pump to be forced up
or down respectively. This will force the VCO to the ends to the tuning range which can be useful in test
of the VCO.
1.11
Phase Detector Window Based Lock Detect
Lock Detect Enable Reg 07h[3]=1 is a global enable for all lock detect functions.
The window based Lock Detect circuit effectively measures the difference between the arrival of the
reference and the divided VCO signals at the PD. The arrival time difference must consistently be less
than the Lock Detect window length, to declare lock. Either signal may arrive first, only the difference in
arrival times is counted.
1.11.1 Analog Window Lock Detect
The lock detect window may be generated by either an analog one shot circuit or a digital one shot based
upon an internal timer. Setting Reg 07h[6]=0 will result in a fixed, analog, nominal 10 ns window, as shown
in Figure 40. The analog window cannot be used if the PD rate is above 50 MHz, or if the offset is too large.
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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28
HMC834LP6GE
v01.0112
PLLs with Integrated VCO - SMT
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
Figure 40. Normal Lock Detect Window - Integer Mode, Zero Offset
For example a 25 MHz PD rate with a 1 mA charge pump setting (Reg 09h[6:0]=Reg 09h[13:7]= 32h) and
400 µA offset down current (Reg 09h[20:14]=50h Reg 09h[22]= 1), would have an offset of about 400/1000
= 40% of the PD period or about 16 ns. In such an extreme case the divided VCO would arrive 16 ns after
the PD reference, and would always arrive outside of the 10 ns lock detect window. In such a case the lock
detect circuit would always read unlocked, even though the VCO might be locked. When using the 10 ns
analog lock detect window, with a 40 ns PD period, the offset must always be less than 25% of the charge
pump setting, 20% to allow for tolerances. Hence a 1 mA charge pump setting can not use more than 200
µA offset with a 25 MHz PD and an analog Lock detect window. Charge pump current, charge pump offset,
phase detector rate and lock detect window are related.
1.11.2 Digital Window Lock Detect
Setting Reg 07h[6]=1 will result in a variable length lock detect window based upon an internal digital timer.
The timer period is set by the number of cycles of the internal LD clock as programmed by Reg 07h[9:7].
The LD clock frequency is adjustable by Reg 07h[11:10]. The LD clock signal can be viewed via the GPO
test pins. Refer 1.16 for details.
1.11.3 Declaration of Lock
wincnt_max in Reg 07h[2:0] defines the number of consecutive counts of the divided VCO that must land
inside the lock detect window to declare lock. If for example we set wincnt_max = 2048, then the VCO
arrival would have to occur inside the window 2048 times in a row to be declared locked, which would
result in a Lock Detect Flag high. A single occurrence outside of the window will result in an out of lock, i.e.
Lock Detect Flag low. Once low, the Lock Detect Flag will stay low until the wincnt_max = 2048 condition
is met again.
The Lock Detect Flag status is always readable in Reg 12h[1], if locked = 1. Lock Detect status is also
output to the LD_SDO pin if Reg 0Fh[4:0]=1. Again, if locked, LD_SDO will be high. Setting Reg 0Fh[6]=0
will display the Lock Detect Flag on LD_SDO except when a serial port read is requested, in which case
the pin reverts temporarily to the Serial Data Out pin, and returns to the Lock Detect Flag after the read is
completed. Refer to 1.11.5 for Timing of the Lock Detect information.
29
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
When operating in fractional mode the linearity of the charge pump and phase detector are much more
critical than in integer mode. The phase detector linearity is degraded when operating with zero phase
offset. Hence in fractional mode it is necessary to offset the phase of the PD reference and the VCO at the
phase detector. In such a case, for example with an offset delay, as shown in Figure 41, the VCO arrival will
always occur after the reference. The lock detect circuit window may need to be adjusted to allow for the
delay being used. for details see section “Digital Lock Detect with Digital Window Example”.
Figure 41. Lock Detect Window - Fractional Mode with Offset
1.11.5 Digital Lock Detect with Digital Window Example
Typical Digital Lock detect window widths are shown in Table 3. Lock Detect windows typically vary ±10%
vs voltage and ±25% over temperature (-40°C to +85°C).
Table 3. Typical Digital Lock Detect Window
LD Timer Speed
Reg07[11:10]
Digital Lock Detect Window
Nominal Value ±25% (ns)
Fastest 00
6.5
8
11
17
29
53
100
195
01
7
8.9
12.8
21
36
68
130
255
10
1.7
9.2
13.3
22
38
72
138
272
Slowest 11
7.6
10.2
15.4
26
47
88
172
338
LD Timer Divide Setting
Reg07[9:7]
0
1
2
3
4
5
6
7
LD Timer
Divide Value
0.5
1
2
4
8
16
32
64
PLLs with Integrated VCO - SMT
1.11.4 Phase Offset & Fractional Linearity
As an example, in fractional mode, with a 50 MHz PD, with a Charge pump gain of 2 mA and a Down
Leakage of -400 µA (Reg 09h[13:7] = 64h, Reg 09h[6:0] = 64h, Reg 09h[20:14] = 50h, Reg 09h[22] = 1),
the average offset at the PD will be -0.400/2 = 0.2 of the PD period, or about 4 ns ±25%. Hence, when in
lock, the divided VCO will arrive at the PD about 4 ns after the divided Reference. The Lock Detect Window
always starts on the arrival of the first signal at the PD, in this case the Reference. The Lock Detect window
must be longer than 4 ns + 25% and shorter than the period of the PD, in this example, 20 ns. A perfect
Lock Detect window would be the geometric mean or 9.8 ns.
A comfortable solution of 12.8 ns with timer speed set at Reg 07h[11:10]=1 and Timer divider Reg
07h[9:7]=2 works well for the example PD frequency and charge pump offset setting.
Tolerance on the window is +25% at +85 °C, -25% at -40 °C. Here 12.8 ns nominal window may extend
by +25% at +85°C to 16 ns, which is fine for a PD period of 20 ns. Also the minimum window may shrink by
25% to 9.6 ns at -40°C, which again works well for the worst case offset of 4.6 ns.
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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30
HMC834LP6GE
v01.0112
PLLs with Integrated VCO - SMT
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
Figure 42. Lock Detect Window Example with 50 MHz PD and 3.9 ns VCO Offset
There is always a good solution for the lock detect window for a given operating point. The user should
understand however that one solution does not fit all operating points. If charge pump offset or PD frequency
are changed significantly then the lock detect window may need to be adjusted.
1.11.6 Cycle Slip Prevention (CSP)
When changing VCO frequency and the VCO is not yet locked to the reference, the instantaneous
frequencies of the two PD inputs are different, and the phase difference of the two inputs at the PD varies
rapidly over a range much greater than ±2π radians. Since the gain of the PD varies linearly with phase
up to ±2π, the gain of a conventional PD will cycle from high gain, when the phase difference approaches
a multiple of 2π, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. The
output current from the charge pump will cycle from maximum to minimum even though the VCO has not
yet reached its final frequency.
The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the
cycle. This can make the VCO frequency actually reverse temporarily during locking. This phenomena is
known as cycle slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically.
Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal
Laplace analysis.
The synthesizer PD features an ability to reduce cycle slipping during acquisition. The Cycle Slip Preven
tion (CSP) feature increases the PD gain during large phase errors. The specific phase error that triggers
the momentary increase in PD gain is set via Reg 0Bh[8:7]
1.11.7 Charge Pump Gain
A simplified diagram of the charge pump is shown in Figure 43. Charge pump Up and Down gains are set
by CP DN Gain and CP UP Gain respectively (Reg 09h[6:0] and Reg 09h [13:7]). The current gain of the
pump in Amps/radian is equal to the gain setting of this register divided by 2π.
For example if both CP DN Gain and CP UP Gain are set to ‘50d’ the output current of each pump will be 1
mA and the phase frequency detector gain kp = 1 mA/2π radians, or 159 µA/rad. See section 1.4 for more
information.
31
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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Order
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
In integer mode, the phase detector operates with zero offset. The divided reference signal and the divided
VCO signal arrive at the phase detector inputs at the same time. In fractional mode of operation, charge
pump linearity and ultimately, phase noise, is much better if the VCO and reference inputs are operated
with a phase offset. A phase offset is implemented by adding a constant DC offset current at the output of
the charge pump.
DC offset may be added to the UP or DN switching pumps using Reg 09h[21] or Reg 09h[22]. The
magnitude of the offset is controlled by Reg 09h[20:14], and can range from 0 to 635 µA in steps of 5 µA.
Down offset is highly recommended in fractional mode of operation. Integer mode of operation works best
with zero offset.
As an example, a PD comparison of fPD = 50 MHz (20 ns period) with the main pump gain set at 2 mA, and
a down (DN) offset of -385 µA would represent a phase offset of about (-385/2000)*360 = -69 degrees.
This is equivalent to the divided VCO arriving 3.8 ns after the reference at the PD input. It is critical that
phase offset be used in fractional mode. Normally, down offsets larger than 3 ns are typical.
If the charge pump gain is changed, for example to compensate for changes in VCO sensitivity, it is
recommended to change the charge pump offset proportionally to maintain a constant phase offset.
PLLs with Integrated VCO - SMT
1.11.8 Charge Pump Phase Offset - Fractional Mode
Figure 43. Charge Pump Gain & Offset Control
1.12
Frequency Tuning
HMC834LP6GE VCO subsystem always operates in fundamental frequency of operation (2800 MHz
to 4200 MHz). The HMC834LP6GE generates frequencies below its fundamental frequency (45 MHz
to 2800 MHz) by tuning to the appropriate fundamental frequency and selecting the appropriate Output
Divider setting (divide by 2/4/6.../60/62) in VCO_Reg 02h[5:0]. Conversely the HMC834LP6GE generates
frequencies greater than its fundamental frequency (5600 MHz to 8400 MHz) by tuning to the appropriate
fundamental frequency and enabling the doubler mode (VCO_Reg 03h[0] = 1).
The HMC834LP6GE automatically controls frequency tuning in the fundamental band of operation, for
more information see “1.2.1 VCO Auto-Calibration (AutoCal)”.
To tune to frequencies below the fundamental frequency range (4200 MHz) it is required to tune the HMC834LP6GE to the appropriate fundamental
frequency, and then enable the doubler mode of operation (VCO_Reg 03h[0] = 1).
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Phone: 978-250-3343
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32
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
1.12.1 Integer Mode
PLLs with Integrated VCO - SMT
The HMC834LP6GE is capable of operating in integer mode. For Integer mode set the following registers
a. Disable the Fractional Modulator, Reg 06h[11]=0
b. Bypass the Modulator circuit, Reg 06h[7]=1
In integer mode the VCO step size is fixed to that of the PD frequency, fpd. Integer mode typically has 3
dB lower phase noise than fractional mode for a given PD operating frequency. Integer mode, however,
often requires a lower PD frequency to meet step size requirements. The fractional mode advantage is that
higher PD frequencies can be used, hence lower phase noise can often be realized in fractional mode.
Charge Pump offset should be disabled in integer mode.
1.12.1.1 Integer Frequency Tuning
In integer mode the digital Δ∑ modulator is shut off and the N (Reg 03h) divider may be programmed to any
integer value in the range 16 to 219-1. To run in integer mode configure Reg 06h as described, then program
the integer portion of the frequency as explained by (EQ 13), ignoring the fractional part.
a. Disable the Fractional Modulator, Reg 06h[11] = 0
b. Bypass the delta-sigma modulator Reg 06h[7] = 1
c. To tune to frequencies (4200 MHz), enable the doubler mode of operation (VCO_Reg 03h [0] = 1).
Writing to VCO subsystem registers (VCO_Reg 02h[5:0] and VCO_Reg 03h [0] in this case) is accomplished
indirectly through PLL register 5 (Reg 05h). More information on communicating with the VCO subsystem
through PLL Reg 05h is available in “1.19 VCO Serial Port Interface (SPI)” section.
1.12.2 Fractional Mode
The HMC834LP6GE is placed in fractional mode by setting the following registers:
a. Enable the Fractional Modulator, Reg 06h[11]=1
b. Connect the delta sigma modulator in circuit, Reg 06h[7]=0
1.12.2.1 Fractional Frequency Tuning
This is a generic example, with the goal of explaining how to program the output frequency. Actual variables
are dependant upon the reference in use.
The HMC834LP6GE in fractional mode can achieve frequencies at fractional multiples of the reference.
The frequency of the HMC834LP6GE, fvco, is given by
fvco =
fxtal
R
(Nint + Nfrac) = fint + ffrac
fout = fvco / k
(EQ 13)
(EQ 14)
Where:
fout
is the output frequency after any potential dividers or doublers.
k
is 0.5 for doubler, 1 for fundamental, or k = 1,2,4,6,…58,60,62 according to the
VCO Subsystem type
Nint
is the integer division ratio, Reg 03h, an integer number between 20 and
524,284
33
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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HMC834LP6GE
v01.0112
Nfrac
is the fractional part, from 0.0 to 0.99999...,Nfrac=Reg 04h/224
R
is the reference path division ratio, Reg 02h
fxtal
is the frequency of the reference oscillator input
fpd
is the PD operating frequency, fxtal /R
As an example:
fout
k 2
fvco
2,805 MHz
fxtal
= 50 MHz
R
=1
fpd
= 50 MHz
Nint
= 56
Nfrac
= 0.1
Reg 04h
= round(0.1 x 224) = round(1677721.6) = 1677722
1402.5 MHz
f VCO =
50e6
1
fout =
1677722
(56 + 24
2
f VCO
2
-
) = 2805 MHz + 1.92 Hz error
= 1402.5 MHz + 0.596 Hz error
(EQ 15)
(EQ 16)
In this example the output frequency of 1402.5 MHz is achieved by programming the 19-bit binary value
of 56d = 38h into intg_reg in Reg 03h, and the 24-bit binary value of 1677722d = 19999Ah into frac_reg in
Reg 04h. The 0.596 Hz quantization error can be eliminated using the exact frequency mode if required. In
this example the output fundamental is divided by 2. Specific control of the output divider is required. See
section 3.0 and description for more details.
PLLs with Integrated VCO - SMT
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
1.12.2.2 Exact Frequency Tuning
Due to quantization effects, the absolute frequency precision of a fractional PLL is normally limited by
the number of bits in the fractional modulator. For example, a 24 bit fractional modulator has frequency
resolution set by the phase detector (PD ) comparison rate divided by 224. The value 224 in the denominator
is sometimes referred to as the modulus. Hittite PLLs use a fixed modulus which is a binary number. In
some types of fractional PLLs the modulus is variable, which allows exact frequency steps to be achieved
with decimal step sizes. Unfortunately small steps using small modulus values results in large spurious
outputs at multiples of the modulus period (channel step size). For this reason Hittite PLLs use a large
fixed modulus. Normally, the step size is set by the size of the fixed modulus. In the case of a 50 MHz PD
rate, a modulus of 224 would result in a 2.98 Hz step resolution, or 0.0596 ppm. In some applications it is
necessary to have exact frequency steps, and even an error of 3 Hz cannot be tolerated.
Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can be
exactly represented in binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some common
frequencies cannot be exactly represented. For example, Nfrac = 0.1 = 1/10 must be approximated as
round((0.1 x 224)/ 224 ) ≈ 0.100000024. At fPD = 50 MHz this translates to 1.2 Hz error. Hittite’s exact frequency
mode addresses this issue, and can eliminate quantization error by programming the channel step size to
FPD/10 in Reg 0Ch to 10 (in this example). More generally, this feature can be used whenever the desired
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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34
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLLs with Integrated VCO - SMT
frequency, f VCO, can be exactly represented on a step plan where there are an integer number of steps
(
61.44 × 106
= 3750
214
Since (EQ 17) is satisfied, the HMC834LP6GE can be configured for exact frequency mode at
f VCO = 2800.2 MHz as follows:
f
1. NINT = Reg 03h = floor
2800.2 × 106
45
=
=
d 2Dh
61.44 × 106
VCO
=
floor
fPD
2. Reg 0Ch =
61.44 × 106
61.44 × 106
=
=
= 512
=
d 200h
6
6
120000
gcd ( fVCO , fPD ) gcd 2800.2 × 10 ,61.44 × 10
fPD
)
(
3. To program Reg 04h, the closest integer-N boundary frequency fN that is less than the
desired VCO frequency f VCO must be calculated. fN = fPD ∙ NINT. Using the current example:
fN =fPD × NINT =45 × 61.44 × 106 =2764.8 MHz.
(
)
24
224 f
2800.2 × 106 − 2764.8 × 106
2
VCO − fN
=
ceil
=
=
d 938000h
9666560
fPD
61.44 × 106
then=
reg04h ceil
1.12.2.5.5
(
)
PLLs with Integrated VCO - SMT
1.12.2.4.4
Hittite Exact Frequency Channel Mode
If it is desirable to have multiple, equally spaced, exact frequency channels that fall within
the same interval (ie. fN ≤ f VCOk < fN+1) where f VCOk is shown in Figure 44 and 1 ≤ k ≤ 214,
it is possible to maintain the same integer-N (Reg 03h) and exact frequency register (Reg 0Ch) settings
and only update the fractional register (Reg 04h) setting. The Exact Frequency Channel Mode is possible
if (EQ 17) is satisfied for at least two equally spaced adjacent frequency channels, i.e. the channel step
size.
To configure the HMC834LP6GE for Exact Frequency Channel Mode, initially and only at the beginning,
integer (Reg 03h) and exact frequency (Reg 0Ch) registers need to be programmed for the smallest fVCO
frequency (f VCO1 in Figure 44), as follows:
1. Calculate and program the integer register setting Reg 03h = NINT = floor(f VCO1/fPD), where f VCO1 is
shown in Figure 44 and corresponds to minimum channel VCO frequency. Then the lower integer
boundary frequency is given by fN = NINT ∙ fPD.
2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd,
where fgcd = gcd((f VCOk+1 - f VCOk),fPD) = greatest common divisor of the desired equidistant channel
spacing and the PD frequency ((fVCOk+1 - f VCOk) and fPD).
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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36
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLLs with Integrated VCO - SMT
Then, to switch between various equally spaced intervals (channels) only the fractional register (Reg 04h)
needs to be programmed to the desired VCO channel frequency f VCOk in the following manner:
(
)
224 f
VCOk − fN
fPD
Reg 04h = NFRAC = ceil
where fN = floor(f VCO1/fPD), and f VCO1, as shown in Figure 44, represents
the smallest channel VCO frequency that is greater than fN.
Example: To configure the HMC834LP6GE for Exact Frequency Mode for equally spaced intervals of 100
kHz where first channel (Channel 1) = f VCO1 = 2800.200 MHz and Phase Detector (PD) rate fPD = 61.44
MHz proceed as follows:
First check
that the exact frequency mode for this f VCO1 = 2800.2 MHz (Channel 1)
and f VCO2 = 2800.2 MHz + 100 kHz = 2800.3 MHz (Channel 2) is possible.
fPD
214
=
fgcd1 gcd(fVCO1, fPD ) and fgcd1 ≥
f
and=
fgcd 2 gcd(fVCO2 , fPD ) and fgcd 2 ≥ PD
214
)
(
=gcd ( 2800.3 × 10 ,61.44 × 10 ) =20 × 10
61.44 × 106
= 3750
214
6
61.44 × 10
>
=3750
214
fgcd1 = gcd 2800.2 × 106 ,61.44 × 106 = 120 × 103 >
fgcd2
6
6
3
If (EQ 17) is satisfied for at least two of the equally spaced interval (channel) frequencies f VCO1,f VCO2 ,f VCO3 ,...
f VCON, as it is above, Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies,
and can be configured as follows:
1. Reg 03h =
2. Reg 0Ch =
6
VCO
1 floor 2800.2 × 10=
45
=
=
d 2Dh
fPD
61.44 × 106
f
floor
61.44 × 106
61.44 × 106
d C00h
=
=
= 3072
=
3
6
20000
gcd 100 × 10 ,61.44 × 10
gcd ( fVCOk +1 − fVCOk ) , fPD
fPD
(
)
)
(
where (f VCOk+1 - f VCOk) is the desired channel spacing (100 kHz in this example).
3. To program Reg 04h the closest integer-N boundary frequency fN that is less than the smallest
channel VCO frequency f VCO1 must be calculated. fN = floor(f VCO1/fPD). Using the current example:
2800.2 × 106
=45 × 61.44 × 106 =2764.8 MHz
61.44 × 106
fN =fPD × floor
Then
224 f
( VCO1 − fN ) for channel 1 where f
Reg 04h ceil
=
=
VCO1 2800.2 MHz
f
PD
24
2800.2 × 106 − 2764.8 × 106
2
d 938000h
= ceil
=
=
9666560
61.44 × 106
)
(
4. To change from channel 1 (f VCO1 = 2800.2 MHz) to channel 2 (f VCO2 = 2800.3 MHz), only
Reg 04h needs to be programmed, as long as all of the desired exact frequencies f VCOk (Figure 44)
fall between the same integer-N boundaries (fN < f VCOk < fN+1). In that case
(
)
24
2800.3 × 106 − 2764.8 × 106
2
=
=
d 93EAABh
9693867
61.44 × 106
Reg 04h = ceil
37
, and so on.
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
The start phase of the fractional modulator digital phase accumulator (DPA) may be set to one of four possible
default values via the seed register Reg 06h[1:0]. If AutoSeed Reg 06h[8] is set, then the HMC834LP6GE
will automatically reload the start phase into the DPA every time a new fractional frequency is selected.
If AutoSeed is not set, then the HMC834LP6GE will start new fractional frequencies with the last value
left in the DPA from the last frequency. Hence the start phase will effectively be random. Certain zero or
binary seed values may cause spurious energy correlation at specific frequencies. Correlated spurs are
advantageous only in very special cases where the spurious are known to be far out of band and are
removed in the loop filter. For most cases a random, or non zero, non-binary start seed is recommended.
Further, since the AutoSeed always starts the accumulators at the same place, performance is repeatable
if AutoSeed is used. Reg 06h[1:0]=2 is recommended.
1.13
Soft Reset & Power-On Reset
The HMC834LP6GE features a hardware Power on Reset (POR). All chip registers will be reset to default
states approximately 250 µs after power up.
The PLL subsystem SPI registers may also be soft reset by an SPI write to register rst_swrst (Reg 00h).
Note that the soft reset does not clear the SPI mode of operation referred to in section 1.17.2. It should be
noted that the VCO subsystem is not affected by the PLL soft reset, the VCO subsystem registers can only
be reset by removing the power supply.
NOTE: if external power supplies or regulators have rise times slower than 250 µs, then it is advised to
write to the SPI reset register (Reg 00h[5]=1) immediately after power up, before any other SPI activity.
This will ensure starting from a known state.
1.14
Power Down Mode
Note that the VCO subsystem is not affected by the CEN or soft reset. Hence device power down is a two
step process. First power down the VCO by writing 0 to VCO register 1 via Reg 05h and then power down
the PLL by pulling CEN pin 17 low (assuming no SPI overrides (Reg 01h[0]=1)). This will result in all analog
functions and internal clocks disabled. Current consumption will typically drop below 10 µA in Power Down
state. The serial port will still respond to normal communication in Power Down mode.
PLLs with Integrated VCO - SMT
1.12.2.6 Seed Register & AutoSeed Mode
It is possible to ignore the CEN pin, by clearing rst_chipen_pin_select (Reg 01h[0]=0). Control of Power
Down Mode then comes from the serial port register rst_chipen_from_spi, Reg 01h[1] .
It is also possible to leave various blocks on when in Power Down (see Reg 01h), including:
a. Internal Bias Reference Sources Reg 01h[2]
b. PD Block
Reg 01h[3]
c. CP Block Reg 01h[4]
d. Reference Path Buffer Reg 01h[5]
e. VCO Path buffer
Reg 01h[6]
f. Digital I/O Test pads
Reg 01h[7]
To turn off the VCO RF buffer but leave the VCO running and the PLL locked write Reg 05h = 2A98(manual
select) then write Reg 05h = 0D88(disable VCO RF buffer) To re-enable the RF buffer write Reg
05h=0F88(Enable VCO RF buffer)
1.15
Chip Identification
PLL subsystem version information may be read by reading the content of read only register, chip_ID in
Reg 00h. It is not possible to read the VCO subsystem version.
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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38
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLLs with Integrated VCO - SMT
1.16
General Purpose Output (GPO) Pin
The PLL shares the LD_SDO (Lock-Detect/Serial Data Out) pin to perform various functions. While the pin
is most commonly used to read back registers from chip via the SPI, it is also capable of exporting a variety
of interesting signals and real time test waveforms (including Lock Detect). It is driven by a tri-state CMOS
driver with ~200 Ω Rout. It has logic associated with it to dynamically select whether the driver is enabled,
and to decide which data to export from the chip.
In its default configuration, after power-on-reset, the output driver is disabled, and only drives during
appropriately addressed SPI reads. This allows it to share the output with other devices on the same bus.
Depending on the SPI mode, the read section of SPI cycle is recognized differently
HMC SPI Mode: The driver is enabled during the last 24 bits of SPI READ cycle (not during write
cycles).
Open SPI Mode: The driver is enabled if the chip is addressed - ie. The last 3 bits of SPI cycle =
‘000’b before the rising edge of SEN (Note A).
To monitor any of the GPO signals, including Lock Detect, set Reg 0Fh[7] = 1 to keep the SDO driver
always on. This stops the LDO driver from tri-stating and means that the SDO line cannot be shared with
other devices.
The chip will naturally switch away from the GPO data and export the SDO during an SPI read (Note B). To
prevent this automatic data selection, and always select the GPO signal, set “Prevent AutoMux of SDO”
(Reg 0Fh[6] = 1). The phase noise performance at this output is poor and uncharacterized. Also, the GPO
output should not be toggling during normal operation. Otherwise the spectral performance may degrade.
Note that there are additional controls available, which may be helpful if sharing the bus with other devices:
•
To allow the driver to be active (subject to the conditions above) even when the chip is disabled - set
Reg 01h[7] = 0.
•
To disable the driver completely, set Reg 08h[5] = 0 (it takes precedence over all else).
•
To disable either the pull-up or pull-down sections of the driver, Reg 0Fh[8] = 1 or Reg 0Fh[9] = 1
respectively.
Note A: If SEN rises before SCK has clocked in an ‘invalid’ (non-zero) chip -address, the HMC834LP6GE
will start to drive the bus.
Note B: In Open Mode, the active portion of the read is defined between the 1st SCK rising edge after
SEN, to the next rising edge of SEN.
Example Scenarios:
•
Drive SDO during reads, tri-state otherwise (to allow bus-sharing)
• No action required.
•
Drive SDO during reads, Lock Detect otherwise
• Set GPO Select Reg 0Fh[4:0] = ‘00001’ (which is default)
• Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1)
•
Always drive Lock Detect
• Set “ Prevent AutoMux of SDO” Reg 0Fh[6] = 1
• Set GPO Select Reg 0Fh[4:0]= 00001 (which is default)
• Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1))
The signals available on the GPO are selected by changing “GPO Select”, Reg 0Fh[4:0].
39
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Phone: 978-250-3343
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
SERIAL PORT
1.17.1 Serial Port Modes of Operation
The HMC834LP6GE serial port interface can operate in two different modes of operation.
a. HMCSPI HMC Mode (HMC Legacy Mode) - Single slave per HMCSPI Bus
b. HMCSPI Open Mode - Up to 8 slaves per HMCSPI Bus.
Both Modes support 5-bits of register address space. HMC Mode can support up to 6 bits of register
address.
Register 0 has a dedicated function in each mode. Open Mode allows wider compatibility with other
manufacturers SPI protocols.
Table 4. Register 0 Comparison - Single vs Multi-User Modes
Single User
HMC Mode
Multi-User
Open Mode
READ
Chip ID
24-bits
Chip ID 24-bits
WRITE
Soft Reset,
General Strobes
Read Address [4:0]
Soft reset [5]
General Strobes [23:6]
1.17.2 HMCSPI Protocol Decision after Power-On Reset
On power up both types of modes are active and listening.
A decision to select the desired SPI protocol is made on the first occurrence of SEN or SCLK following a
hard reset, after which the protocol is fixed and only changeable by cycling the power OFF and ON.
a. If a rising edge on SEN is detected first HMC Mode is selected.
b. If a rising edge on SCLK is detected first Open mode is selected.
1.17.3 Serial Port HMC Mode - Single PLL
PLLs with Integrated VCO - SMT
1.17
HMC Mode (Legacy Mode) serial port operation can only address and talk to a single PLL, and is compatible
with most Hittite PLLs and PLLs with Integrated VCOs.
The HMC Mode protocol, shown in figures Figure 45 and Figure 46, is designed for a 4 wire interface with
a fixed protocol featuring
a. 1 Read/Write bit
b. 6 Address bits
c. 24 data bits
d. 3 wire for Write only, 4 wire for Read/Write capability
1.17.3.1 HMC Mode - Serial Port WRITE Operation
AVDD = DVDD = 3V ±10%, AGND = DGND = 0V
Table 5. SPI HMC Mode - Write Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max
Units
t1
SEN to SCLK setup time
8
t2
SDI to SCLK setup time
3
ns
t3
SCLK to SDI hold time
3
ns
t4
SEN low duration
20
ns
t5
SCK to SEN fall
10
Max Serial port Clock Speed
ns
ns
50
MHz
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for its use,
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of patents orCorporation,
other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Phone: 978-250-3343
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40
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLLs with Integrated VCO - SMT
A typical HMC Mode WRITE cycle is shown in Figure 45.
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE cycle,
followed by a rising edge of SCK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI low indicates a Write
cycle (/WR).
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave shifts the address bits in the next six rising edges of SCK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first.
f. Slave shifts the data bits on the next 24 rising edges of SCK (8-31).
g. The data is registered into the chip on the 32nd rising edge of SCK.
h. SEN is cleared after a minimum delay of t5. This completes the write cycle.
Figure 45. HMC Mode - Serial Port Timing Diagram - WRITE
1.17.3.2 HMC Mode - Serial Port READ Operation
A typical HMC Mode READ cycle is shown in Figure 46.
a. The Master (host) asserts both SEN (Serial Port Enable) and SDI to indicate a READ cycle, followed
by a rising edge SCLK. Note: The Lock Detect (LD) function is usually multiplexed onto the LD_SDO
pin. It is suggested that LD only be considered valid when SEN is low. In fact LD will not toggle until
the first active data bit toggles on LD_SDO, and will be restored immediately after the trailing edge of
the LSB of serial data out as shown in Figure 46.
b. The slave (HMC834LP6GE) reads SDI on the 1st rising edge of SCLK after SEN. SDI high initiates
the READ cycle (RD)
c. Host places the six address bits on the next six falling edges of SCLK, MSB first.
d. Slave registers the address bits on the next six rising edges of SCLK (2-7).
e. Slave switches from Lock Detect and places the requested 24 data bits on SD_LDO on the next 24
rising edges of SCK (8-31), MSB first .
f. Host registers the data bits on the next 24 falling edges of SCK (8-31).
g. Slave restores Lock Detect on the 32nd rising edge of SCK.
h. De-assertion of SEN completes the cycle
41
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
Table 6. SPI HMC Mode - Read Timing Characteristics
Conditions
Min.
Typ.
Max
Units
t1
SEN to SCLK setup time
8
t2
SDI to SCLK setup time
3
ns
t3
SCLK to SDI hold time
3
ns
t4
SEN low duration
20
t5
SCLK to SDO delay
t6
Recovery Time
ns
ns
8.2ns+0.2
ns/pF
10
ns
ns
Figure 46. HMC Mode - Serial Port Timing Diagram - READ
PLLs with Integrated VCO - SMT
Parameter
1.17.4 Serial Port Open Mode
The Serial Port Open Mode, shown in Figure 47 and Figure 48, features:
a. Compatibility with general serial port protocols that use shift and strobe approach to communication
b. Compatible with Hittite PLL with Integrated VCO solutions, useful to address multiple chips of various
types from a single serial port bus.
The Open Mode protocol has the following general features:
a. 3-bit chip address , can address up to 8 devices connected to the serial bus
b. Wide compatibility with multiple protocols from multiple vendors
c. Simultaneous Write/Read during the SPI cycle
d. 5-bit address space
e. 3 wire for Write Only capability, 4 wire for Read/Write capability
Hittite PLLs with integrated VCOs support Open Mode. Some legacy PLL and microwave PLLs with
integrated VCOs only support HMC Mode. Consult the relevant data sheets for details.
Typical serial port operation can be run with SCLK at speeds up to 50 MHz.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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42
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
1.17.4.1 Open Mode - Serial Port WRITE Operation
PLLs with Integrated VCO - SMT
AVDD = DVDD = 3V ±10%, AGND = DGND = 0V
Table 7. SPI Open Mode - WRITE Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max
Units
t1
SDI setup time to SCLK Rising Edge
3
ns
t2
SCLK Rising Edge to SDI hold time
3
ns
t3
SEN low duration
10
ns
t4
SEN high duration
10
ns
t5
SCLK 32 Rising Edge to SEN Rising Edge
10
ns
t6
Recovery Time
20
Max Serial port Clock Speed
ns
50
MHz
A typical WRITE cycle is shown in Figure 47.
a. The Master (host) places 24-bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK.
b. the slave (HMC834LP6GE) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5-bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of SCLK
(25-29)
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32). Hittite
reserves chip address a2:a0 = 000 for all RF PLL with Integrated VCOs.
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
h. Slave registers the SDI data on the rising edge of SEN.
Figure 47. Open Mode - Serial Port Timing Diagram - WRITE
1.17.4.2 Open Mode - Serial Port READ Operation
A typical READ cycle is shown in Figure 48.
In general, in Open Mode the LD_SDO line is always active during the WRITE cycle. During any Open
Mode SPI cycle LD_SDO will contain the data from the current address written in Reg0h[7:3]. If Reg0h[7:3]
is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in
progress. If it is desired to READ from a specific address, it is necessary in the first SPI cycle to write the
desired address to Reg0h[7:3], then in the next SPI cycle the desired data will be available on LD_SDO.
43
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
a. The Master (host), on the first 24 falling edges of SCLK places 24-bit data, d23:d0, MSB first, on SDI
as shown in Figure 48. d23:d5 should be set to zero. d4:d0 = address of the register to be READ on
the next cycle.
b. the slave (HMC834LP6GE) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5-bit register address , r4:r0, (the READ ADDRESS register), MSB first, on the next 5
falling edges of SCLK (25-29). r4:r0=00000.
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32)..Chip
address is always 000 for RF PLL with Integrated VCOs.
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
h. Slave registers the SDI data on the rising edge of SEN.
i. Master clears SEN to complete the the address transfer of the two part READ cycle.
j. If one does not wish to write data to the chip at the same time as we do the second cycle , then it is
recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of
the cycle.
k. Master places the same SDI data as the previous cycle on the next 32 falling edges of SCLK.
l. Slave (HMC834LP6GE) shifts the SDI data on the next 32 rising edges of SCLK.
m. Slave places the desired read data (ie. data from the address specified in Reg 00h[7:3] of the first
cycle) on LD_SDO which automatically switches to SDO mode from LD mode, disabling the LD
output.
m. Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock
Detect on LD_SDO.
PLLs with Integrated VCO - SMT
An example of the Open Mode two cycle procedure to read from any random address is as follows:
Table 8. SPI Open Mode - Read Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max
Units
t1
SDI setup time to SCLK Rising Edge
3
ns
t2
SCLK Rising Edge to SDI hold time
3
ns
t3
SEN low duration
10
ns
t4
SEN high duration
10
t5
SCLK Rising Edge to SDO time
t6
Recovery TIme
10
ns
t7
SCK 32 Rising Edge to SEN Rising Edge
10
ns
ns
8.2ns+0.2ns/pF
ns
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
Fax: 978-250-3373
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44
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLLs with Integrated VCO - SMT
1.17.4.3 HMCSPI Open Mode READ Operation - 2 Cycles
Figure 48. Serial Port Timing Diagram - READ
For more information on using the GPO pin while in SPI Open Mode please see section 1.16.
45
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
1.18
Configuration at Start-Up
1. Configure the reference divider (write to Reg 02h), if required.
2. Configure the delta-sigma modulator (write to Reg 06h).
• Configuration involves selecting the mode of the delta-sigma modulator (Mode A or Mode B),
selection of the delta-sigma modulator seed value, and configuration of the delta-sigma modulator
clock scheme. It is recommended to use the values found in the Hittite PLL evaluation board
control software register files.
3. Configure the charge pump current and charge pump offset current (write to Reg 09h)
4. Configure the VCO Subsystem (write to Reg 05h, for more information see section 1.19, and “3.0
VCO Subsystem Register Map”. Detailed writes to the VCO subsystem via PLL Reg 05h at start-up
are available in the Register Setting Files found in the HIttite PLL Evaluation Software received with a
product evaluation kit or downloaded from www.hittite.com.
5. Program the frequency of operation
• Program the integer part (write to Reg 03h)
• Program the fractional part (write to Reg 04h)
6. Configure the VCO output divider/doubler, if needed in the VCO subsystem via PLL Reg 05h.
Once the HMC834LP6GE is configured after startup, in most cases the user only needs to change
frequencies by writing to Reg 03h integer register, Reg 04h fractional register, and Reg 05h to change the
VCO output divider or doubler setting if needed, and possibly adjust the charge pump settings by writing
to Reg 09h.
For detailed and most up-to-date start-up configuration please refer to the appropriate Register Setting
Files found in the HIttite PLL Evaluation Software received with a product evaluation kit or downloaded
from www.hittite.com.
1.19
VCO Serial Port Interface (SPI)
PLLs with Integrated VCO - SMT
To configure the PLL after power up, follow the instructions below:
The HMC834LP6GE communicates with the internal VCO subsystem via an internal 16 bit VCO Serial
Port, (e.g. see Figure 29). The internal serial port is used to control the step tuned VCO and other VCO
subsystem functions, such as RF output divider / doubler control and RF buffer enable.
Note that the internal VCO subsystem SPI (VSPI) runs at the rate of the AutoCal FSM clock, TFSM, (section
1.2.1) where the FSM clock frequency cannot be greater than 50 MHz. The VSPI clock rate is set by
Reg 0Ah[14:13].
Writes to the VCO’s control registers are handled indirectly, via writes to Reg 05h of the PLL. A write to PLL
Reg 05h causes the PLL subsystem to forward the packet, MSB first, across its internal serial link to the
VCO subsystem, where it is interpreted.
The VCO serial port has the capability to communicate with multiple subsystems inside the IC. For this
reason each subsystem has a subsystem ID, Reg 05h[2:0].
Each subsystem has multiple registers to control the functions internal to the subsystem, which may be
different from one subsystem to the next. Hence each subsystem has internal register addresses bits
(Reg 05h[6:3])
Finally the data required to configure each register within the VCO subsystem is contained in Reg 05h[15:7].
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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46
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLLs with Integrated VCO - SMT
1.19.1 VSPI Use of Reg05h
The packet data written into, Reg 05h is sub-parsed by logic at the VCO subsystem into the following 3
fields:
1. [2:0] - 3 bits - VCO_ID, target subsystem address = 000b.
2. [6:3] - 4 bits - VCO_REGADDR, the internal register address inside the VCO subsystem.
3. [15:7] - 9- bits- VCO_DATA, data field to write into the VCO register.
For example, to write 0_1111_1110 into register 2 of the VCO subsystem (VCO_ID = ‘000’b), and set the
VCO output divider to divide by 62, the following needs to be written to Reg 05h =’0_1111_1110, 0010, 000’
b.
During AutoCal, the AutoCal controller only updates the data field of Reg 05h. The VCO subsystem register
address (Reg 05h[6:3]) must be set to 0000 for the AutoCal data to be sent to the correct address.
VCO subsystem ID and register address are not modified by the AutoCal state machine. Hence, if a
manual access is done to a VCO Subsystem register the user must reset the register address to zero
before a change of frequency which will re-run AutoCal.
Since every write to Reg 05h will result in a transfer of data to the VCO subsystem, if the VCO
subsystem needs to be reset manually, it is important to make sure that the VCO switch settings are
not changed. Hence the switch settings in Reg 10h[7:0] need to be read first, and then rewritten to
Reg 05h[15:8].
In summary, first read Reg 10h, then write to Reg 05h as follows:
Reg 10h[7:0]
= vv x yyyyy
Reg 05h
= vv x yyyyy 0 0000 iii
Reg 05h[2:0]
= iii, subsystem ID, 3 bits (000)
Reg 05h[6:3]
= 0000, subsystem register address
Reg 05h[7]
= 0 , calibration tune voltage off
Reg 05h[12:8]
= yyyyy, VCO caps
Reg 05h[13]
= x, don’t care
Reg 05h[15:14]
47
= vv, VCO Select
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLL Register Map
2.1
Reg 00h ID Register (Read Only)
Bit
Type
[23:0]
RO
2.2
Bit
Name
chip_ID
Width
Default
24
A7975
Description
HMC834LP6GE chip ID
Reg 00h Open Mode Read Address/RST Strobe Register (Write Only)
Type
Name
Width
Default
Description
[4:0]
WO
Read Address
5
-
(WRITE ONLY) Read Address for next cycle - Open Mode
Only
[5]
WO
Soft Reset
1
-
Soft Reset - both SPI modes reset (set to 0 for proper
operation)
[23:6]
WO
Not Defined
18
-
Not Defined (set to 0 for proper operation)
Width
Default
2.3
Reg 01h RST Register
(Default 000002h)
Bit
Type
Name
Description
1 = take PLL enable via CEN pin, see Power Down Mode
description
[0]
R/W
rst_chipen_pin_select
1
0
[1]
R/W
rst_chipen_from_spi
1
1
SPI’s PLL enable bit
[2]
R/W
Keep_bias_on
1
0
when PLL is disabled, keeps internal bias generators on,
ignores chip enable control.
[3]
R/W
Keep_PD_on
1
0
when PLL is disabled, keeps PD circuit on, ignores Chip
enable control
[4]
R/W
Keep_CP_on
1
0
when PLL is disabled, keeps Charge Pump on, ignores
Chip enable control
[5]
R/W
Keep_Ref_buf_on
1
0
when PLL is disabled, keeps Reference buffer block on,
ignores Chip enable control
[6]
R/W
Keep_VCO_on
1
0
when PLL is disabled, keeps VCO divider buffer on,
ignores Chip enable control
[7]
R/W
Keep_GPO_driver_on
1
0
when PLL is disabled, keeps GPO output Driver On,
ignores Chip enable control
[8]
R/W
Reserved
1
0
Reserved
[9]
R/W
Reserved
1
0
Reserved
Width
Default
Description
1
Reference Divider ’R’ Value “(EQ 13)”)
Divider use also requires refBufEn Reg08[3]=1and Divider
min 1d
max 16383d
2.4
0 = take PLL enable via SPI (rst_chipen_from_spi)
Reg01[1]
PLLs with Integrated VCO - SMT
2.0
Reg 02h REFDIV Register
(Default 000001h)
Bit
[13:0]
Type
R/W
Name
rdiv
14
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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48
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
2.5
Reg 03h Frequency Register - Integer Part
PLLs with Integrated VCO - SMT
(Default 000019h)
Bit
Type
Name
Width
Default
Description
VCO Divider Integer part, used in all modes, see (EQ 13)
[18:0]
R/W
intg
19
25d
Fractional Mode
min 20d
max 219 -4 = 7FFFCh = 524,284d
Integer Mode
min 16d
max 219 -1 = 7FFFFh = 524,287d
2.6
Reg 04h Frequency Register - Fractional Part
(Default 000000h)
Bit
Type
Name
Width
Default
Description
VCO Divider Fractional part (24-bit unsigned) see
Fractional Frequency Tuning
[23:0]
2.7
R/W
frac
24
0
Used in Fractional Mode only (Nfrac = Reg 04h/224
min 0d
max 224-1
Reg 05h VCO SPI Register
(Default 000000h)
Bit
Type
Name
Width
Default
[2:0]
R/W
VCO Subsystem_ID,
3
0
Internal VCO Subsystem ID
Description
[6:3]
R/W
VCO Subsystem register address
4
0
For interfacing with the VCO please see section 1.19.
[15:7]
R/W
VCO Subsystem data
9
0
Note: Reg05h is a special register used for indirect addressing of the VCO subsystem. Writes to Reg05h are
automatically forwarded to the VCO subsystem by the VCO SPI state machine controller.
Reg05h is a Read-Write register. However, Reg05h only holds the contents of the last transfer to the VCO subsystem.
Hence it is not possible to read the full contents of the VCO subsystem. Only the content of the last transfer to the
VCO subsystem can be read. Please take note special considerations for AutoCal related to Reg05h
49
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of patents orCorporation,
other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
2.8
Reg 06h SD CFG Register
Bit
[1:0]
Type
R/W
Name
seed
Width
2
Default
Description
2
Selects the Seed in Fractional Mode
00: 0 seed
01: lsb seed
02: B29D08h seed
03: 50F1CDh seed
Note; Writes to this register are stored in the
HMC834LP6GE and are only loaded into the modulator
when a frequency change is executed and if AutoSeed
Reg06h[8] =1
Select the Modulator Type
0: 1st order
1: 2nd order
2: Type 1 Mode B
3: Type 2 Mode A
[3:2]
R/W
order
2
2
[6:4]
R/W
Reserved
3
4
Program to 7d
0: Use Modulator, Required for Fractional Mode,
1: Bypass Modulator, Required for Integer Mode
[7]
R/W
frac_bypass
1
0
[8]
R/W
AutoSeed
1
1
1: loads the seed whenever the frac register is written
0: when frac register write changes frequency, modulator
starts with previous contents
Note: In bypass fractional modulator output is ignored,
but fractional modulator continues to be clocked if frac_
rstb =1, Can be used to test the isolation of the digital
fractional modulator from the VCO output in integer mode
[9]
R/W
clkrq_refdiv_sel
1
1
selects the modulator clock source- for Test Only
1: VCO divider clock (Recommended for normal
operation)
0: Ref divider clock
Ignored if bits [10] or [21] are set
[10]
R/W
SD Modulator Clk Select
1
0
0 - SD auxclk,
1- SD VCO Clock delay (Recommended)
0: disable frac core, use for Integer Mode or Integer Mode
with CSP
1: Enable Frac Core, required for Fractional Mode, or
Integer isolation testing
This register controls whether AutoCal starts on an
Integer or a Fractional write
[11]
R/W
SD Enable
1
1
[12]
R/W
Reserved
1
0
[13]
R/W
Reserved
1
0
[15:14]
R/W
Reserved
2
0
[17:16]
R/W
Reserved
2
0
Program to 3d
[18]
R/W
BIST Enable
1
0
Enable Built in Self Test
PLLs with Integrated VCO - SMT
(Default 200B4Ah)
[20:19]
R/W
RDiv BIST Cycles
2
0
RDiv BIST Cycles
00: 1032
01: 2047
10: 3071
11: 4095
[21]
R/W
auto_clock_config
1
1
Set to 0 for fpd > 50 MHz
[22]
R/W
Reserved
1
0
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50
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
2.9
Reg 07h Lock Detect Register
PLLs with Integrated VCO - SMT
(Default 00014Dh)
51
Bit
[2:0]
Type
R/W
Name
Width
Default
lkd_wincnt_max
3
5d
Description
lock detect window
sets the number of consecutive counts of divided VCO
that must land inside the Lock Detect Window to declare
LOCK
0: 5
1: 32
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65535
[3]
R/W
Enable Internal Lock Detect
1
1
see section 1.16
[5:4]
R/W
Reserved
2
0
Reserved
[6]
R/W
Lock Detect Window type
1
1
Lock Detection Window Timer Selection
1: Digital programmable timer
0: Analog one shot, nominal 10 ns window
[9:7]
R/W
LD Digital Window duration
3
2
0 Lock Detection - Digital Window Duration
0: 1/2 cycle
1: 1 cycle
2: 2 cycles
3: 4 cycles
4: 8 cycles
5: 16 cycles
6: 32 cycles
7: 64 cycles
[11:10]
R/W
LD Digital Timer Freq Control
2
0
Lock Detect Digital Timer Frequency Control
“00” fastest “11” slowest
[12]
R/W
LD Timer Test Mode
1
0
1: force Timer Clock ON Continuously - For Test Only
0: Normal Timer operation - one shot
[13]
R/W
Auto Relock - One Try
1
0
1: Attempts to relock if Lock Detect fails for any reason
Only tries once.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
2.10
Reg 08h Analog EN Register
Bit
Type
Width
Default
[0]
R/W
bias_en
Name
1
1
Enables main chip bias reference
Description
charge pump enable
[1]
R/W
cp_en
1
1
[2]
R/W
PD_en
1
1
PD enable
[3]
R/W
refbuf_en
1
Reference path buffer enable
[4]
R/W
vcobuf_en
1
1
VCO path RF buffer enable
0 - Pin LD_SDO disabled
[5]
R/W
gpo_pad_en
1
1
1 - and RegFh[7]=1 , Pin LD_SDO is always on required
for use of GPO port
1 - and RegFh[7]=0 SPI LDO_SPI is off if unmatched chip
address is seen on the SPI, allowing a shared SPI with
other compatible parts
[6]
R/W
reserved
1
1
[7]
R/W
VCO_Div_Clk_to_dig_en
1
1
VCO Divider Clock to Digital Enable
[8]
R/W
reserved
1
0
reserved
[9]
R/W
Prescaler Clock enable
1
1
Prescaler clock enable
[10]
R/W
VCO Buffer and Prescaler
Bias Enable
1
1
VCO Buffer and Prescaler Bias Enable
[11]
R/W
Charge Pump Internal
Opamp enable
1
1
Should be programmed to 1
reserved
[14:12]
R/W
reserved
3
011
reserved
[17:15]
R/W
reserved
3
011
reserved
[18]
R/W
spare
1
0
[19]
R/W
reserved
1
0
spare
reserved
[20]
R/W
reserved
1
0
reserved program to 0
[21]
R/W
High Frequency Reference
1
0
Program to 1 for XTAL > 200 MHz
[22]
R/W
reserved
1
1
reserved program to 1
[23]
R/W
reserved
1
1
reserved program to 1
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for its use,
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infringements
of patents orCorporation,
other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
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Trademarks and registered trademarks are
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PLLs with Integrated VCO - SMT
(Default C1BEFFh)
52
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
2.11
Reg 09h Charge Pump Register
PLLs with Integrated VCO - SMT
(Default 403264h)
53
Bit
[6:0]
[13:7]
[20:14]
Type
R/W
R/W
R/W
Name
CP DN Gain
CP UP Gain
Offset Magnitude
Width
7
7
7
Default
Description
100d
64h
Charge Pump DN Gain Control 20 µA√step
Affects fractional phase noise and lock detect settings
0d = 0 µA
1d = 20 µA
2d = 40 µA
...
127d = 2.54mA
100d
64h
Charge Pump UP Gain Control 20 µA per step
Affects fractional phase noise and lock detect settings
0d = 0 µA
1d = 20 µA
2d = 40 µA
...
127d = 2.54mA
0
Charge Pump Offset Control 5 µA/step
Affects fractional phase noise and lock detect settings
0d = 0 µA
1d = 5 µA
2d = 10 µA
...
127d = 635 µA
[21]
R/W
Offset UP enable
1
0
recommended setting = 0
[22]
R/W
Offset DN enable
1
1
recommended setting = 1 in Fractional Mode, 0 otherwise
[23]
R/W
HiKcp
1
0
HiKcp High Current Charge Pump
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for its use,
nor for any
infringements
of patents orCorporation,
other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
Fax: 978-250-3373
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Trademarks and registered trademarks are
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Application
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
2.12
Reg 0Ah VCO AutoCal Configuration Register
Bit
[2:0]
[5:3]
Type
R/W
R/W
Name
Vtune Resolution
VCO Curve Adjustment
Width
3
3
Default
Description
5
R Divider Cycles
0-1
1-2
2-4
3-8
4 - 32
5 - 64
6 - 128
7 - 256
0
VCO Curve Adjustment vs Temp for AutoCal
0 - Disabled
1 : + 1 Curve
2: +2 Curves
3: +3 Curves
4: -4 Curves
5: -3 Curves
6: -2 Curves
7: -1 Curve
Wait State Setup 100 TFSM see section 1.2.4
[7:6]
R/W
Wait State Set Up
2
0
Tmmt = 1 measurement cycle of AutoCal
0: Wait Only at Startup
1: Wait on startup and after first Tmmt cycle
2: Wait on startup and after first two Tmmt cycles
3: Wait on startup and after first three Tmmt cycles
[9:8]
R/W
Num of SAR BIts in VCO
2
0
Number of SAR bits in VCO
0: 8 - recommended
1: 7
2: 6
3: 5
[10]
R/W
Force Curve
1
0
Force curve sent during Tuning Tune from Reg5
[11]
R/W
Bypass VCO Tuning
1
0
Bypass VCO Tuning
[12]
R/W
No VSPI Trigger
1
0
Don’t trigger a transfer on writes to Reg 05h
[14:13]
R/W
FSM/VSPI Clock Select
2
1
Set the AutoCal FSM and VSPI Clock (50 MHz maximum)
0: Input Crystal Reference
1: Input Crystal Reference/4
2: Input Crystal Reference/16
3: Input Crystal Reference/32
[15]
R/W
Xtal Falling Edge for FSM
1
0
Use the falling Edge of the Xtal for FSM AutoCal Clock Required for BIST
[16]
R/W
Force RDivider Bypass
1
0
Force the R Divider Bypass
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for its use,
nor for any
infringements
of patents orCorporation,
other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
Fax: 978-250-3373
Order
at www.hittite.com
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Application
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Trademarks and registered trademarks are
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respective owners.
Application
Support:
Phone: 978-250-3343
or apps@hittite.com
PLLs with Integrated VCO - SMT
(Default 002205h)
54
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
2.13
Reg 0Bh PD Register
PLLs with Integrated VCO - SMT
(Default 7C061h)
Bit
Type
Width
Default
[2:0]
R/W
PD_del_sel
Name
3
1
Sets PD reset path delay (Recommended setting 001)
Description
[3]
R/W
Short PD Inputs
1
0
Shorts the inputs ot the Phase frequency detector - Test
Only
Inverts the PD polarity (program to 0)
[4]
R/W
pd_phase_sel
1
0
0- Use with a positive tuning slope VCO and Passive
Loop Filter (default)
1- Use with a Negative Slope VCO or with an inverting
Active Loop Filter with a Positive Slope VCO
[5]
R/W
PD_up_en
1
1
Enables the PD UP output
[6]
R/W
PD_dn_en
1
1
Enables the PD DN output
0
Cycle Slip Prevention Mode
Extra current is driven into the loop filter when the phase
error is larger than:
0: Disabled
1: 5.4ns
2: 14.4ns
3: 24.1ns
This delay varies by +- 10% with temperature, and +- 12%
with process.
[8:7]
R/W
CSP Mode
2
[9]
R/W
Force CP UP
1
0
Forces CP UP output on - Use for Test only
[10]
R/W
Force CP DN
1
0
Forces CP DN output on - Use for Test only
Force CP MId Rail - Use for Test only
[11]
R/W
Force CP MId Rail
1
0
[14:12]
R/W
Reserved
3
4
program to 100
[16:15]
R/W
CP Internal OpAmp Bias
2
3
program to 11
3
MCounter Clock Gating
0: MCounter Off
1: N 62 - invalid, defaults to 62
Note: This register automatically controls the enables to
the, RF output buffer, RF divider, RF divide by 1 path,
and requires Master Enable (VCO_Reg 01h[0] = 1) and
AutoRFO mode (VCO_Reg 03h [2] = 0)
Note: bit[0] is a don’t care in ManualRFO mode.
3
11 - Max Gain
10 - Max Gain - 3 dB
01 - Max Gain - 6 dB
00 - Max Gain - 9 dB
0
1 - Max Gain
0 - Max Gain - 3 dB
Used to flatten the output power level across frequency
• For divide-by 1 or divide-by 2 it is recommended to set
this bit to 1. 0 will reduce output power and degrade
noise floor performance.
• For divide-by 4 or higher, it is recommended to set this
bit to 0 to maintain flat output power across divider
settings. Setting this bit to 1, with divide-by 4 or higher
provides higher output power compared to the divideby 1 or two case.
For example, to write 0_1111_1110 into VCO_Reg02h VCO subsystem (VCO_ID = ‘000’b), and set the VCO output
divider to divide by 62, the following needs to be written to Reg 05h =’0_1111_1110, 0010, 000’ b.
Reg 05h[2:0] = 00; subsystem ID 0
Reg 05h[6:3] = 0010; VCO register address 2d
Reg 05h[16:7] = 0_1111_1110; Divide by 62, max output RF gain, Divider output stage gain = 0
3.4
Bit
59
VCO_Reg 03h Config
Type
Name
Width
Default
Description
0- Enable the frequency doubler mode of operation
1- Enable fundamental mode of operation
- For more information please see “VCO Subsystem”
section.
[0]
WO
Fundamental/Doubler Mode
Selection
1
1
[1]
WO
reserved
1
0
reserved
[2]
WO
Manual RFO Mode
1
0
0 - AutoRFO mode (recommended)
1 - ManualRFO mode
AutoRFO mode controls output buffers and RF divider
enables according to RF divider setting in VCO_Reg
02h[5:0]
ManualRFO mode requires manual enables of individual
blocks via VCO_Reg01h
[4:3]
WO
RF buffer bias
2
2
Program to ‘10’ when fundamental mode enabled
Program to ‘00’ when doubler mode enabled
[8:5]
WO
Spare
4
2
don’t care
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nor for any
infringements
of patents orCorporation,
other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
Fax: 978-250-3373
Order
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license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Application
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Trademarks and registered trademarks are
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respective owners.
Application
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Phone: 978-250-3343
or apps@hittite.com
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
VCO_Reg 04h Cal/Bias
Specified performance is only guaranteed with the required settings in this table. Other settings are not
supported.
Bit
Type
Width
Default
[2:0]
WO
VCO bias
Name
3
1
Program to 5d
Description
Program to 1d
[4:3]
WO
PLL buffer bias
2
1
[6:5]
WO
FndLmtr bias
2
2
Program to 3d
[8:7]
WO
Preset Cal 0
2
1
Program to 2d
Width
Default
2
2
3.6
VCO_Reg05h CF_Cal
Bit
Type
[1:0]
WO
CF L
[3:2]
WO
CF ML
2
2
Program to 3d
[5:4]
WO
CF MH
2
2
Program to 3d
[7:6]
WO
CF H
2
2
Program to 3d
[8]
WO
Spare
1
0
Program to 0d
Width
Default
2
3
3.7
Name
Description
Program to 0d
VCO_Reg06h MSB Cal
Bit
Type
[1:0]
WO
Name
MSB L
Description
Program to 3d
[3:2]
WO
MSB ML
2
3
Program to 3d
[5:4]
WO
MSB MH
2
3
Program to 3d
[7:6]
WO
MSB H
2
3
Program to 3d
[8]
WO
Spare
1
0
don’t care
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for its use,
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of patents orCorporation,
other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
Fax: 978-250-3373
Order
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Trademarks and registered trademarks are
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Application
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PLLs with Integrated VCO - SMT
3.5
60
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
PLLs with Integrated VCO - SMT
NOTES:
61
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other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 978-250-3343
Fax: 978-250-3373
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