EV-ADF4153ASD1Z

Fractional-N Frequency Synthesizer ADF4153A Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump current 3-wire serial interface Analog and digital lock detect Power-down mode Pin-compatible with ADF4106, ADF4110/ADF4111/ ADF4112/ADF4113, and ADF4153 Consistent RF output phase Loop filter design possible with ADIsimPLL The ADF4153A is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. A sigma-delta (Σ-Δ) based fractional interpolator allows programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO). APPLICATIONS A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. CATV equipment Base stations for mobile radio (GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP SDVDD RSET ADF4153A REFERENCE 4-BIT R COUNTER ×2 DOUBLER REFIN + PHASE FREQUENCY DETECTOR – VDD HIGH-Z CHARGE PUMP DGND LOCK DETECT MUXOUT CP OUTPUT MUX CURRENT SETTING VDD RDIV RFCP3 RFCP2 RFCP1 NDIV N-COUNTER RFINA RFINB THIRD ORDER FRACTIONAL INTERPOLATOR LE FRACTION REG 24-BIT DATA REGISTER AGND MODULUS REG DGND INTEGER REG CPGND 11047-001 CLK DATA Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADF4153A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 N Divider Register, R0 ............................................................... 15 Applications ....................................................................................... 1 R Divider Register, R1................................................................ 15 General Description ......................................................................... 1 Control Register, R2 ................................................................... 15 Functional Block Diagram .............................................................. 1 Noise and Spur Register, R3 ...................................................... 16 Revision History ............................................................................... 2 Reserved Bits ............................................................................... 16 Specifications..................................................................................... 3 Initialization Sequence .............................................................. 17 Timing Specifications .................................................................. 4 RF Synthesizer: A Worked Example ........................................ 17 Absolute Maximum Ratings ............................................................ 5 Modulus ....................................................................................... 17 ESD Caution .................................................................................. 5 Reference Doubler and Reference Divider ............................. 17 Pin Configurations and Function Descriptions ........................... 6 12-Bit Programmable Modulus ................................................ 17 Typical Performance Characteristics ............................................. 7 Fastlock with Spurious Optimization ...................................... 18 Circuit Description ........................................................................... 8 Spur Mechanisms ....................................................................... 18 Reference Input Section ............................................................... 8 Spur Consistency ........................................................................ 19 RF Input Stage ............................................................................... 8 Phase Resync ............................................................................... 19 RF INT Divider ............................................................................. 8 Filter Design—ADIsimPLL....................................................... 19 INT, FRAC, MOD, and R Relationship ..................................... 8 Interfacing ................................................................................... 19 RF R Counter ................................................................................ 8 PCB Design Guidelines for Chip Scale Package .................... 20 Phase Frequency Detector (PFD) and Charge Pump .............. 9 Applications Information .............................................................. 21 MUXOUT and Lock Detect ........................................................ 9 Local Oscillator for a GSM Base Station Transmitter ........... 21 Input Shift Registers ..................................................................... 9 Outline Dimensions ....................................................................... 22 Program Modes ............................................................................ 9 Ordering Guide .......................................................................... 22 Register Maps .................................................................................. 10 REVISION HISTORY 1/13—Rev. 0 to Rev. A Added TSSOP Package ...................................................... Universal Added Figure 3, Renumbered Sequentially ................................... 6 Updated Outline Dimensions ........................................................22 Changes to Ordering Guide ...........................................................22 10/12—Revision 0: Initial Version Rev. A | Page 2 of 24 Data Sheet ADF4153A SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1. Parameter RF INPUT CHARACTERISTICS (3 V) RF Input Frequency (RFIN) REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD, SDVDD VP IDD Low Power Sleep Mode NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 2 Normalized 1/f Noise (PN1_f) 3 Phase Noise Performance 4 1750 MHz Output 5 Min Typ Max Unit 0.5 1 4 4 GHz GHz 10 250 MHz 0.7 AVDD 10 ±100 V p-p pF µA 32 MHz 5 312.5 2.5 3.0 10 1 2 2 2 1.4 0.6 ±1 10 V V µA pF 0.4 V V 3.3 V 5.5 24 V mA µA 1.4 2.7 mA µA % kΩ nA % % % Test Conditions/Comments See Figure 12 for an input circuit −8 dBm minimum/0 dBm maximum −10 dBm minimum/0 dBm maximum For lower frequencies, ensure slew rate (SR) > 400 V/µs See Figure 11 for an input circuit For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave; slew rate > 25 V/µs Biased at AVDD/2 1 Programmable; see Figure 19 With RSET = 4.7 kΩ With RSET = 4.7 kΩ With RSET = 4.7 kΩ Sink and source current 0.5 V ≤ VCP ≤ VP − 0.5 V 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2 Open-drain 1 kΩ pull-up to 1.8 V IOL = 500 µA AVDD AVDD 20 1 −223 −121 dBc/Hz dBc/Hz −107 dBc/Hz PLL loop BW = 500 kHz Measured at 10 kHz offset, normalized to 1 GHz @ VCO output @ 5 kHz offset, 25 MHz PFD frequency AC coupling ensures AVDD/2 bias. The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N). 3 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 4 The phase noise is measured with the EV-ADF4153ASD1Z and the Rohde & Schwarz FSUP spectrum analyzer operating in phase noise mode. 5 fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode. 1 2 Rev. A | Page 3 of 24 ADF4153A Data Sheet TIMING SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min t4 Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t5 CLK t3 t2 DATA DB23 (MSB) DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 11047-002 t6 LE Figure 2. Timing Diagram Rev. A | Page 4 of 24 Data Sheet ADF4153A ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD = SDVDD, unless otherwise noted. Table 3. Parameter VDD to GND DVDD to AVDD SDVDD to AVDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +4 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 112°C/W 30.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of