EV-ADUCM322IQSPZ

ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com ADuCM320i/ADuCM322/ADuCM322i Reference Manual SCOPE This manual provides a detailed description of the ADuCM320i/ADuCM322/ADuCM322i functionality and features. FUNCTIONAL BLOCK DIAGRAMS BUF_VREF2V5 2.5V BAND GAP XTALO XTALI ECLKIN 1.8V LDO CLOCK SYSTEM 32.768kHz 16MHz OSC 80MHz PLL AIN0 AIN5 14-BIT SAR ADC MUX AIN6 DGNDx AVDDx AGNDx IOVDDx IOGNDx AIN15 INTERNAL CHANNELS: TEMPERATURE, AVDD, IOVDD MEMORY 2 × 128kB FLASH 32kB SRAM COMPARATOR VDAC0 VDAC VDAC7 VDAC IDAC0 IDAC IDAC3 IDAC ARM CORTEX-M3 PROCESSOR DMA NVIC ADuCM320i GPIO PORTS UART 2 × SPI 2 × I2C EXT IRQs MDIO PLA GENERALPURPOSE I/O PORTS 3 × GENERALPURPOSE TIMER WATCHDOG TIMER WAKE-UP TIMER PWM PWM0 TO PWM6 RESET SYSTEM SERIAL WIRE SWDIO PVDDx PGND 13437-001 SWCLK RESET Figure 1. ADuCM320i Functional Block Diagram BUF_VREF2V5 XTALO XTALI ECLKIN 2.5V BAND GAP 1.8V LDO CLOCK SYSTEM 32.768kHz 16MHz OSC 80MHz PLL AIN0 AIN5 AIN6 MUX SAR ADC DGNDx AVDDx AGNDx IOVDDx IOGNDx AIN15 ARM CORTEX-M3 PROCESSOR INTERNAL CHANNELS: TEMPERATURE, AVDD, IOVDD MEMORY 2 × 128kB FLASH 32kB SRAM COMPARATOR VDAC0 GENERALPURPOSE I/O PORTS 3 × GENERALPURPOSE TIMER WATCHDOG TIMER WAKE-UP TIMER PWM PWM0 TO PWM6 VDAC DMA NVIC VDAC7 GPIO PORTS UART 2 × SPI 2 × I2C EXT IRQs MDIO PLA VDAC ADuCM322/ ADuCM322i RESET SYSTEM SERIAL WIRE SWDIO PVDDx PGND RESET Figure 2. ADuCM322/ADuCM322i Functional Block Diagram PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. D | Page 1 of 195 13437-102 SWCLK UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual TABLE OF CONTENTS Scope .................................................................................................. 1 Register Summary: ADC Circuit ............................................. 27 Functional Block Diagrams............................................................. 1 Register Details: ADC Circuit .................................................. 28 Revision History ............................................................................... 5 Register Summary: Additional Registers ................................ 31 Using the ADuCM320i/ADuCM322/ADuCM322i Reference Manual ............................................................................................... 6 Register Details: Additional Registers ..................................... 32 Analog Comparator ....................................................................... 33 Number Notations ....................................................................... 6 Analog Comparator Features ................................................... 33 Register Access Conventions ...................................................... 6 Analog Comparator Overview ................................................. 33 Introduction to the ADuCM320i/ADuCM322/ADuCM322i ... 7 Analog Comparator Operation ................................................ 33 Main Features of the ADuCM320i/ADuCM322/ADuCM322i ......................................................................................................... 8 Register Summary: Analog Comparator ................................ 33 Memory Organization ................................................................. 8 Clocking Architecture.................................................................... 10 Clocking Architecture Features ............................................... 10 Clocking Architecture Block Diagram .................................... 10 Clocking Architecture Overview.............................................. 11 Register Summary: Clock Architecture................................... 11 Clocking Architecture Operation ............................................ 11 Register Details: Clock Architecture ....................................... 11 Power Management Unit .............................................................. 15 Power Management Unit Features .......................................... 15 Power Management Unit Overview ........................................ 15 Power Management Unit Operation ....................................... 15 Code Examples ........................................................................... 16 Register Summary: Power Management Unit ....................... 17 Register Details: Power Management Unit ............................ 17 ARM Cortex-M3 Processor .......................................................... 18 ARM Cortex-M3 Processor Features ...................................... 18 ARM Cortex-M3 Processor Overview .................................... 18 ARM Cortex-M3 Processor Operation ................................... 18 ARM Cortex-M3 Processor Related Documents .................. 19 ADC Circuit .................................................................................... 20 ADC Circuit Features ................................................................ 20 ADC Circuit Block Diagram..................................................... 20 ADC Circuit Overview .............................................................. 21 ADC Circuit Operation ............................................................. 21 ADC Transfer Function ............................................................ 22 ADC Typical Setup Sequence ................................................... 23 ADC Input Buffer....................................................................... 23 ADC Internal Channels ............................................................. 24 ADC Support Circuits ............................................................... 25 Register Details: Analog Comparator ..................................... 33 IDACs (ADuCM320i Only).......................................................... 34 IDAC Features ............................................................................ 34 IDAC Block Diagram ................................................................ 34 IDAC Overview .......................................................................... 34 Register Summary: IDAC ......................................................... 36 Register Details: IDAC .............................................................. 36 VDACs ............................................................................................. 40 VDAC Features .......................................................................... 40 VDAC Block Diagram ............................................................... 40 VDAC Overview ........................................................................ 40 VDAC Operation ....................................................................... 40 Register Summary: VDAC ........................................................ 42 Register Details: VDAC ............................................................. 42 System Exceptions and Peripheral Interrupts ............................ 48 Cortex-M3 and Fault Management ......................................... 48 External Interrupt Configuration ............................................ 51 Register Summary: External Interrupts .................................. 51 Register Details: External Interrupts ....................................... 51 Low Voltage Analog Die Interrupt Configuration................ 54 Register Summary: Low Voltage Die Interrupts.................... 54 Register Details: Low Voltage Die Interrupts ........................ 55 Reset ................................................................................................. 56 Reset Features ............................................................................. 56 Reset Operation .......................................................................... 56 Register Summary: Reset........................................................... 57 Register Details: Reset................................................................ 57 Direct Memory Access (DMA) Controller ................................. 58 DMA Features ............................................................................ 58 DMA Overview .......................................................................... 58 DMA Operation ......................................................................... 58 Rev. D | Page 2 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DMA Interrupts ..........................................................................59 SPI Transfer Initiation .............................................................123 DMA Priority ..............................................................................59 SPI Interrupts ............................................................................125 Channel Control Data Structure...............................................59 SPI Wire-OR’ed Mode (WOM)..............................................126 Control Data Configuration ......................................................60 SPI CSERR Condition ..............................................................126 DMA Transfer Types (CHNL_CFG[2:0]) ...............................61 SPI DMA ....................................................................................126 Address Calculation....................................................................63 SPI and Power-Down Modes ..................................................127 Aborting DMA Transfers ..........................................................63 Register Summary: SPI0...........................................................128 Register Summary: DMA ...........................................................64 Register Details: SPI0 ...............................................................128 Register Details: DMA................................................................64 Register Summary: SPI1...........................................................132 Flash Controller ...............................................................................70 Register Details: SPI1 ...............................................................132 Flash Controller Features...........................................................70 UART Serial Interface ..................................................................136 Flash Controller Overview.........................................................70 UART Features..........................................................................136 Flash Controller Operation .......................................................70 UART Overview........................................................................136 Flash Memory Operation...........................................................72 UART Operation ......................................................................136 Register Summary: Flash Controller ........................................79 Register Summary: UART .......................................................140 Register Details: Flash Controller .............................................80 Register Details: UART ............................................................140 Silicon Identification ......................................................................88 Programmable Logic Array (PLA) .............................................145 Silicon Identification Memory Mapped Registers .................88 PLA Features .............................................................................145 Digital Die ID Register ...............................................................88 PLA Overview ...........................................................................145 Low Voltage Die ID Register .....................................................88 PLA Operation ..........................................................................146 Digital Inputs/Outputs ...................................................................89 Register Summary: PLA ...........................................................149 Digital Inputs/Outputs Features ...............................................89 Register Details: PLA ................................................................149 Digital Inputs/Outputs Block Diagram ...................................89 General-Purpose Timers ..............................................................153 Digital Inputs/Outputs Overview .............................................89 General-Purpose Timers Features ..........................................153 Digital Inputs/Outputs Operation............................................89 General-Purpose Timers Block Diagram ..............................153 Digital Port Multiplex ................................................................92 General-Purpose Timers Overview ........................................153 Register Summary: Digital Input/Output................................94 General-Purpose Timer Operations ......................................154 Register Details: Digital Input/Output ....................................95 Register Summary: General-Purpose Timer 0......................156 I C Serial Interface ..........................................................................99 Register Details: General-Purpose Timer 0 ..........................156 I2C Features ..................................................................................99 Register Summary: General-Purpose Timer 1......................158 I2C Overview ................................................................................99 Register Details: General-Purpose Timer 1 ..........................158 I2C Operation...............................................................................99 Register Summary: General-Purpose Timer 2......................160 I2C Operating Modes ............................................................... 101 Register Details: General-Purpose Timer 2 ..........................160 Register Summary: I2C0 .......................................................... 104 Watchdog Timer ...........................................................................163 Register Details: I2C0 ............................................................... 104 Watchdog Timer Features .......................................................163 Register Summary: I C1 .......................................................... 113 Watchdog Timer Block Diagram ...........................................163 Register Details: I C1 ............................................................... 113 Watchdog Timer Overview .....................................................163 Serial Peripheral Interfaces ......................................................... 122 Watchdog Timer Operation....................................................163 SPI Features .............................................................................. 122 Register Summary: Watchdog Timer ....................................164 SPI Overview ............................................................................ 122 Register Details: Watchdog Timer .........................................164 SPI Operation ........................................................................... 122 Wake-Up Timer ............................................................................166 2 2 2 Rev. D | Page 3 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Wake-Up Timer Features ....................................................... 166 Management Data Input/Output (MDIO) ............................... 181 Wake-Up Timer Block Diagram ............................................ 166 MDIO Features ......................................................................... 181 Wake-Up Timer Overview ..................................................... 166 MDIO Overview ....................................................................... 181 Wake-Up Timer Operation .................................................... 166 MDIO Operation ..................................................................... 181 Register Summary: Wake-Up Timer ..................................... 169 Register Summary: MDIO Interface (MDIO) ..................... 183 Register Details: Wake-Up Timer .......................................... 169 Register Details: MDIO ........................................................... 183 Pulse Width Modulator (PWM) ................................................ 173 Downloader ................................................................................... 186 PWM Features .......................................................................... 173 I2C Downloader (ADuCM320i/ADuCM322i Only)........... 186 PWM Overview ........................................................................ 173 MDIO Downloader (ADuCM322 Only) .............................. 186 PWM Operation ....................................................................... 173 Hardware Design Considerations .............................................. 191 PWM Interrupt Generation.................................................... 176 Typical System Configuration ................................................ 191 Register Summary: PWM........................................................ 177 Serial Wire Debug Interface ................................................... 195 Register Details: PWM ............................................................ 177 Rev. D | Page 4 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REVISION HISTORY 3/2020—Rev. C to Rev. D Changes to Table 117 and Table 118 ............................................88 5/2018—Rev. B to Rev. C Changes to ADC Voltage Reference Selection Section and Figure 9 .............................................................................................26 Changes to Table 14 ........................................................................29 Changes to Table 22 ........................................................................32 Changes to VDAC Operation Section .........................................41 Added Figure 14; Renumbered Sequentially ...............................41 Changes to Table 66 ........................................................................57 Changes to Table 183....................................................................129 Changes to Table 191....................................................................133 Changes to Watchdog Timer Operation Section .....................162 Changes to MDIO Downloader Section (ADuCM322 Only) Section.............................................................................................186 1/2017—Rev. A to Rev. B Changes to Clocking Architecture Operation Section ..............10 Changes to ADC Circuit Features Section ..................................19 Changes to ADC Circuit Overview Section ................................20 Changes to Single-Ended Mode Section and Differential Section...............................................................................................21 Changes to ADC Voltage Reference Selection Section..............25 Changes to Table 22 ........................................................................31 Added IDAC Thermal Shutdown Section ...................................35 Changes to Writing to the Flash Section .....................................71 Changes to Table 120......................................................................90 Changes to Table 183....................................................................127 2/2016—Rev. 0 to Rev. A Changed ADuCM320i to ADuCM320i/ADuCM322/ADuCM322i ................... Throughout Changed CS to CS0/CS1 .............................................. Throughout Added Figure 2; Renumbered Sequentially ................................... 1 Changes to Advanced Interrupt Handling Section ....................17 Changes to Table 11 ........................................................................26 Changes to Table 14 ........................................................................28 Changes to Table 20 ........................................................................31 Deleted Note 1, Table 64; Renumbered Sequentially ................ 53 Changes to Table 83........................................................................ 63 Changes to Protection, Integrity Section ..................................... 67 Added Error Checking and Correcting (ECC) Error Handling Section, ECC Error During Reading Section, and ECC Error During Execution of Sign Command Section ............................ 71 Changes to Table 94........................................................................ 75 Changes to Table 95........................................................................ 76 Added ECC Enable/Disable, Error Response Register Section and Table 111 .................................................................................. 81 Added Flash 0 Error Address Register Section, Table 112, Flash 1 ECC Error Address Register Section, and Table 113 ... 82 Changes to Figure 18 and Figure 19 ............................................. 86 Changes to Table 120 ..................................................................... 88 Changes to Table 145 ...................................................................105 Changes to Table 167 ...................................................................114 Changes to Table 183 ...................................................................125 Changes to Table 191 ...................................................................129 Changes to Table 205 ...................................................................140 Changes to Table 211 ...................................................................145 Added MDIO Interrupt Power Up Register Write Sequence Section ............................................................................................178 Added I2C Downloader (ADuCM320i/ADuCM322i Only) Section, MDIO Downloader (ADuCM322 Only) Section, and Figure 39 .........................................................................................181 Added Flash Block Partitioning Section, Program Image Section, Debug Mode Section, and Choosing the Active Block Section ............................................................................................182 Added Trial Run Mode Section, Normal Mode Section, Typical Sequence Section, and Table 301 ................................................ 183 Added Table 302 ...........................................................................184 Added to Figure 40 .......................................................................185 Changes to Typical System Configurations Section ................ 186 Changes to Figure 41 ....................................................................187 Added Figure 42 ............................................................................188 Added Figure 43 ............................................................................189 8/2015—Revision 0: Initial Version Rev. D | Page 5 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual USING THE ADUCM320i/ADUCM322/ADUCM322i REFERENCE MANUAL NUMBER NOTATIONS Table 1. Number Notations Notation Bit N V[x:y] 0xNN 0bNN NN Description Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0. Bit field representation covering Bit x to Bit y of a value or a field (V). Hexadecimal (Base 16) numbers are preceded by the prefix 0x. Binary (Base 2) numbers are preceded by the prefix 0b. Decimal (Base 10) numbers are represented using no additional prefixes or suffixes. REGISTER ACCESS CONVENTIONS Table 2. Register Access Conventions Mode RW RC R W Description Memory location has read and write access. Memory location is cleared after reading it. Memory location is read access only. A read always returns 0, unless otherwise specified. Memory location is write access only. Memory mapped register (MMR) bits that are not documented are reserved. When writing to MMRs with reserved bits, the reserved bits must be written with the value in the reset column of the relevant MMR description unless otherwise noted. Rev. D | Page 6 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 INTRODUCTION TO THE ADUCM320i/ADUCM322/ADUCM322i The ADuCM320i/ADuCM322/ADuCM322i are fully integrated, single-package devices that incorporate high performance analog peripherals together with digital peripherals controlled by an 80 MHz ARM® Cortex™-M3 processor and integral flash for code and data. The analog-to-digital converter (ADC) on the 14-bit ADuCM320i and the 12-bit ADuCM322/ADuCM322i provide 1 MSPS data acquisition on up to 16 input pins that can be programmed for single-ended or differential operation. Additionally, chip temperature and supply voltages can be measured. The ADC input voltage is 0 V to VREF. A sequencer is provided that allows a user selected set of ADC channels to be measured in sequence without software involvement during the sequence. The sequence can optionally repeat automatically at a user-selectable rate. Up to eight voltage digital-to-analog converters (VDACs) are provided with output ranges programmable to one of two voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. For the ADuCM320i only, four current output DAC (IDAC) sources are provided. The output currents are programmable with a range from 0 mA to 150 mA. A low drift, band gap reference and a voltage comparator complete the analog input peripheral set. The microcontroller core is a low power ARM Cortex-M3 processor, a 32-bit RISC machine that offers up to 100 MIPS peak performance. Also integrated on chip are two 128 kB Flash/EE memory and 32 kB of SRAM. The flash comprises two separate 128 kB blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block. The ADuCM320i/ADuCM322/ADuCM322i operate from an on-chip oscillator or a 16 MHz external crystal and a phase-locked loop (PLL) at 80 MHz. This clock can optionally be divided down to reduce current consumption. Additional low power modes can be set via software. In the normal operating mode, the ADuCM320i/ADuCM322/ADuCM322i digital core consumes approximately 300 µA/MHz. The ADuCM320i/ADuCM322/ADuCM322i integrate a range of on-chip peripherals that can be configured via software control as required in the application. These peripherals include one universal asynchronous transmitter (UART), two I2Cs, two serial peripheral interface (SPI) serial input/output communication controllers, general-purpose input/output (GPIO) pins, 32-element programmable logic array (PLA), three general-purpose timers, one wake-up timer (WUT), and one system watchdog timer (WDT). In addition, 16-bit pulse-width modulators (PWMs) with seven output signals are provided. The ADuCM320i/ADuCM322/ADuCM322i include a management data input/output (MDIO) interface capable of operating up to 4 MHz. The capability to simultaneously execute from one flash block and write or erase the other flash block makes the ADuCM320i/ ADuCM322/ADuCM322i ideal for 40 G/100 G optical applications. User programming is eased by receiving interrupts after physical address (PHYADR), device address (DEVADD), and end of frame and by having PHYADR and DEVADD hardware comparators. GPIO pins on the device power up in input mode. In output mode, the software can choose between open-drain mode and push-pull mode. The outputs can drive at least 4 mA. The pull-ups can be enabled and disabled in the software. In GPIO mode, the inputs can always be enabled to monitor the pins. The GPIO pins can also be programmed to handle digital or analog peripheral signals, in which case, the pin characteristics are matched to the specific requirement. A large support ecosystem is available for the ARM Cortex-M3 processor to ease product development of the ADuCM320i/ADuCM322/ ADuCM322i. Access is via the ARM serial wire debug port. On-chip factory firmware supports in-circuit serial download via I2C (ADuCM320i/ADuCM322i) or MDIO (ADuCM322). These features are incorporated in a low cost, QuickStart™ development system supporting this precision analog microcontroller family. Rev. D | Page 7 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual MAIN FEATURES OF THE ADUCM320i/ADUCM322/ADUCM322i ADC • • Multichannel, 14-bit (ADuCM320i)/12-bit (ADuCM322/ADuCM322i), 1 MSPS successive approximation register (SAR) ADC Low drift, on-chip voltage reference DACs • • • Eight voltage output DACs: VDACs are 12-bit monotonic Four current output DACs: IDACs are 12-bit monotonic (ADuCM320i only) Low drift, on-chip 2.5 V voltage reference source: two buffered reference outputs Communication • • • • • UART: industry standard, 16450 UART peripheral and support for direct memory access (DMA) Two I2Cs: 2-byte transmit (Tx) and receive (Rx) FIFOs for the master and slave, and support for DMA Two SPIs: master or slave mode with separate 4-byte Rx and Tx FIFOs, and Rx and Tx DMA channels 16-bit PWM with seven output channels Multiple GPIO pins Processing • • • • • ARM Cortex-M3 processor, operating from an internal 80 MHz system clock Two 128 kB Flash/EE memory, 32 kB SRAM In-circuit programming and debug via serial wire In-circuit programming via I2C downloader (ADuCM320i/ADuCM322i only) In-circuit programming via MDIO downloader (ADuCM322 only) On-Chip Peripherals • • • • Three general-purpose timers Wake-up timer Watchdog timer 32-element PLA Package and Temperature Range • 6 mm × 6 mm, 96-ball BGA package, −40°C to +85°C (ADuCM320i only) and −40°C to +105°C (ADuCM322/ADuCM322i only) Tools • • Low cost development system Third-party compiler and emulator tool support Applications • • • • Optical networking: 10 G, 40 G, and 100 G modules Industrial control and automation systems Smart sensors, precision instrumentation Base station systems MEMORY ORGANIZATION The ADuCM320i/ADuCM322/ADuCM322i memory organization is described in this section. Features • • • • Cortex-M3 memory system features include predefined memory map, support for bit band operation for atomic operations, and unaligned data access. ADuCM320i/ADuCM322/ADuCM322i on-chip peripherals are accessed via memory mapped registers, situated in the bit band region. User memory sizes options: 32 kB SRAM and two 128 kB Flash/EE memory. On-chip kernel for manufacturer data and in-circuit download. Rev. D | Page 8 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 0xFFFF FFFF VENDOR SPECIFIC 0xE010 0000 0xE00F FFFF PRIVATE PERIPHERAL BUS—EXTERNAL 0xE004 0000 0xE003 FFFF PRIVATE PERIPHERAL BUS—INTERNAL 0xE000 0000 0xE000 EF00 ADuCM320i/ADuCM322/ADuCM322i MMRs 0xE000 E000 0xDFFF FFFF EXTERNAL DEVICE 1GB (NOT AVAILABLE IN ADuCM320i) 0xA000 0000 0x9FFF FFFF EXTERNAL RAM 1GB (NOT AVAILABLE IN ADuCM320i) 0x6000 0000 0x5FFF FFFF PERIPHERAL 0.5GB 0x4000 0000 0x400A FFFF ADuCM320i/ADuCM322/ADuCM322i MMRs 0x4000 0000 0x3FFF FFFF SRAM 0.5GB 0x2000 0000 0x2000 7FFF ADuCM320i/ADuCM322/ADuCM322i 32kB SRAM 0x2000 0000 0x1FFF FFFF CODE 0.5GB 0x0004 0FFF 0x0000 0000 ADuCM320i/ADuCM322/ADuCM322i KERNEL SPACE 0x0004 0000 0x0000 0000 Figure 3. Cortex-M3 Memory Map Diagram Rev. D | Page 9 of 195 13437-002 0x0003 FFFF ADuCM320i/ADuCM322/ADuCM322i 256kB FLASH/EE MEMORY UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual CLOCKING ARCHITECTURE CLOCKING ARCHITECTURE FEATURES The ADuCM320i/ADuCM322/ADuCM322i integrates two on-chip oscillators and circuitry for an external crystal and external clock source: • • • • LFOSC is a 32 kHz low power internal oscillator that is used in low power modes. HFOSC is a 16 MHz internal oscillator that is used in active mode, which is the default input to the PLL. HFXTAL is a 16 MHz external crystal oscillator. External clock input (ECLKIN) via GPIO pin. CLOCKING ARCHITECTURE BLOCK DIAGRAM ÷4 0 HFXTAL 16MHz OSC ACLK (TO LOW VOLTAGE DIE, ADC) 80MHz SPLL 1 CLKCON5[3] CLKCON0[11] I2C0 CLKCON5[4] CDPCLK (CLKCON1[10:8]) I2C1 CLKCON5[5] 01 UART PCLK UCLK CLKCON5[6] HFOSC 16MHz OSC 00 ECLKIN P1.0 11 CDD2DCLK (CLKCON1[11]) D2D CLKCON5[0] SPI0 CLKCON5[1] CLKCON0[1:0] SPI1 CDHCLK (CLKCON1[2:0]) HCLK CORE WATCHDOG TIMER LFOSC (INTERNAL) PWM FLASH PCLK 01 11 00 WAKE-UP TIMER T4CON[9:10] PCLK HCLK 00 01 11 10 TIMER0CLK T0CON[5:6] PCLK HCLK 00 01 11 10 TIMER1CLK T1CON[5:6] 00 01 11 10 TIMER2CLK 13437-003 PCLK HCLK T2CON[5:6] Figure 4. Clocking Architecture Block Diagram Rev. D | Page 10 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 CLOCKING ARCHITECTURE OVERVIEW The system clock, UCLK, can be selected from a 16 MHz oscillator or from an 80 MHz PLL output (default). An external clock on P1.0 can also be used for test purposes. Internally, the system clock is divided into separate clocks: • • • • UCLK system clock HCLK for the flash, SRAM, and DMA PCLK for most peripherals ACLK for the analog section of the chip; this is based on UCLK/4 and goes to the low voltage analog die All ADC performance details are based on a 20 MHz ACLK. Performance at other clock speeds is not guaranteed. REGISTER SUMMARY: CLOCK ARCHITECTURE Table 3. Clocking Register Summary Address 0x40028000 0x40028004 0x40028014 0x40028018 Name CLKCON0 CLKCON1 CLKCON5 CLKSTAT0 Description Miscellaneous clock settings register Clock dividers register User clock gating control register Clocking status Reset 0x0041 0x0200 0x0040 0x0000 Access RW RW RW RW CLOCKING ARCHITECTURE OPERATION At power-up, the processor executes at 80 MHz, sourced from the 80 MHz PLL output. The clock source for the 80 MHz PLL is the internal 16 MHz oscillator by default. User code can select the clock source for the system clock and can divide the clock by a factor of 1 to 128, where the clock divider bits are controlled by CLKCON1[2:0]. Slower code execution and reduced power consumption result. Note that P1.0 must be configured as a clock input before the clock source is switched in the clock control register. When changing from one clock source to a different clock source, the user code must ensure that both clock sources are kept active for a minimum of five clock cycles to ensure that the clock switching is fully completed without any glitches. If the clock source for the 80 MHz SPLL needs to be changed from the internal 16 MHz oscillator to the external HFXTAL, use the following procedure: 1. 2. 3. 4. 5. 6. Check that HFXTAL is stable by reading CLKSTAT0[14:12]. Change the system clock to the internal 16 MHz oscillator using CLKCON0[1:0]. Wait 5 × 16 MHz clock cycles. Switch the input to the SPLL using CLKCON0[11]. Wait until the SPLL has locked by monitoring CLKSTAT0[2:0]. Change the system clock back to the SPLL clock. REGISTER DETAILS: CLOCK ARCHITECTURE Miscellaneous Clock Settings Register Address: 0x40028000, Reset: 0x0041, Name: CLKCON0 Table 4. Bit Descriptions for CLKCON0 Bit(s) 15 Bit Name HFXTALIE 14 13 RESERVED SPLLIE 12 11 RESERVED PLLMUX Description High frequency crystal interrupt enable. 0: an interrupt to the core does not generate on a HFXTALOK or HFXTALNOK. 1: an interrupt to the core generates on a HFXTALOK or HFXTALNOK. Reserved. SPLL interrupt enable. 0: SPLL interrupt does not generate. 1: SPLL interrupt generates. Reserved. PLL source selection. 0: internal oscillator is selected (HFOSC). 1: external oscillator is selected (HFXTAL). Rev. D | Page 11 of 195 Reset 0x0 Access RW 0x0 0x0 RW RW 0x0 0x0 R RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) [10:8] [7:4] Bit Name RESERVED CLKOUT [3:2] [1:0] RESERVED CLKMUX Description Reserved. GPIO clock out selection. 0000: UCLK. 0001: LFOSC (32 kHz). 0010: HFOSC(16 MHz). 0100: core clock. 0101: PCLK. 1011: General-Purpose Timer 0 clock. 1100: wake-up timer clock. 1110: HFXTAL. All other combinations are reserved. Reserved. Clock selection. 00: high frequency internal oscillator (HFOSC). 01: SPLL is selected (80 MHz). 10: reserved. 11: external GPIO port is selected (ECLKIN). Reset 0x0 0x4 Access RW RW 0x0 0x1 R RW Reset 0x0 0x0 Access R R 0x2 RW 0x0 0x0 R RW Clock Dividers Register Address: 0x40028004, Reset: 0x0200, Name: CLKCON1 Table 5. Bit Descriptions for CLKCON1 Bit(s) [15:12] 11 Bit Name RESERVED CDD2DCLK [10:8] CDPCLK [7:3] [2:0] RESERVED CDHCLK Description Reserved. D2DCLK divide bits. 0: D2D_CLK frequency is HCLK frequency. 1: D2D_CLK frequency is half of HCLK frequency. PCLK divide bits. PCLK divide bits. 000: Reserved. 001: Reserved. 010: DIV4. Divide by 4 (PCLK is quarter the frequency of root clock, 20 MHz). All ADC specifications based on this setting. Using any other setting may affect ADC performance. 011: DIV8. Divide by 8. 100: DIV16. Divide by 16. 101: DIV32. Divide by 32. 110: DIV64. Divide by 64. 111: DIV128. Divide by 128. Reserved. Always returns 0 when read. HCLK divide bits. 000: DIV1. Divide by 1 (HCLK is equal to root clock). 001: DIV2. Divide by 2 (HCLK is half the frequency of root clock). 010: DIV4. Divide by 4 (HCLK is quarter the frequency of root clock). 011: DIV8. Divide by 8. 100: DIV16. Divide by 16. 101: DIV32. Divide by 32. 110: DIV64. Divide by 64. 111: DIV128. Divide by 128. Rev. D | Page 12 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 User Clock Gating Control Register Address: 0x40028014, Reset: 0x0040, Name: CLKCON5 The user clock gating control register (CLKCON5) controls the gates of the peripheral UCLKs. Table 6. Bit Descriptions for CLKCON5 Bit(s) [15:7] 6 5 Bit Name RESERVED RESERVED UCLKUARTOFF 4 UCLKI2C1OFF 3 UCLKI2C0OFF 2 1 RESERVED UCLKSPI1OFF 0 UCLKSPI0OFF Description Reserved. Always returns 0 when read. Always set to 1. Do not write 0 to this bit. UART clock user control. This bit disables the UCLK_UART clock. It controls the gate on UCLK_UART in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the UCLK_UART is always off, and this bit has no effect. 0: clock on. 1: clock off. I2C1 clock user control. This bit disables the PCLK_I2C1 clock. It controls the gate on PCLK_I2C1 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the I2C1 PCLK is always off, and this bit has no effect. 0: clock on. 1: clock off. I2C0 clock user control. This bit disables the PCLK_I2C0 clock. It controls the gate on PCLK_I2C0 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the PCLK_I2C0 is always off, and this bit has no effect. 0: clock on. 1: clock off. Reserved. SPI1 clock user control. This bit disables the UCLK_SPI1 clock. It controls the gate on UCLK_SPI1 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the UCLK_SPI1 is always off, and this bit has no effect. 0: clock on. 1: clock off. SPI0 clock user control. This bit disables the UCLK_SPI0 clock. It controls the gate on UCLK_SPI0 in Power Mode 0 and Power Mode 1. In Power Mode 2 and Power Mode 3, the UCLK_SPI0 is always off, and this bit has no effect. 0: clock on. 1: clock off. Rev. D | Page 13 of 195 Reset 0x0 0x1 0x0 Access R RW RW 0x0 RW 0x0 RW 0x0 0x0 R RW 0x0 RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Clocking Status Register Address: 0x40028018, Reset: 0x0000, Name: CLKSTAT0 The clock status register monitors PLL and oscillator status. Table 7. Bit Descriptions for CLKSTAT0 Bit(s) 15 14 Bit Name RESERVED HFXTALNOK 13 HFXTALOK 12 HFXTALSTATUS [11:3] 2 RESERVED SPLLUNLOCK 1 SPLLLOCK 0 SPLLSTATUS Description Reserved. Always returns 0 when read. HF crystal not stable. This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1 to this location to clear it. 0: HF crystal stable signal is not deasserted. 1: HF crystal stable signal is deasserted. HF crystal stable. This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1 to this location to clear it. 0: HF crystal stable signal is not asserted. 1: HF crystal stable signal is asserted. HF crystal status. 0: HF crystal is not stable or not enabled. 1: HF crystal is stable. Reserved. System PLL unlock. This bit is sticky. SPLLUNLOCK is set when the PLL loses its lock. SPLLUNLOCK is used as the interrupt source to signal the core that a lock was lost. Writing a 1 to this bit clears it. SPLLUNLOCK does not set again unless the system PLL gains a lock and subsequently loses it again. 0: no loss of PLL lock is detected. 1: a PLL loss of lock is detected. System PLL lock. This bit is sticky. SPLLLOCK is set when the PLL locks. SPLLLOCK is used as the interrupt source to signal the core that a lock was detected. Writing a 1 to this bit clears it. SPLLLOCK does not set again unless the system PLL loses lock and subsequently locks again. 0: no PLL lock event is detected. 1: a PLL lock event is detected. System PLL status. Indicates the current status of the PLL. Initially, the system PLL is unlocked. After a stabilization period, the PLL locks and is ready for use as the system clock source. This is a read only bit. A write has no effect. 0: the PLL is not locked or properly configured. The PLL is not ready for use as the system clock source. 1: the PLL is locked and is ready for use as the system clock source. Rev. D | Page 14 of 195 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 R 0x0 0x0 R RW 0x0 RW 0x0 R ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 POWER MANAGEMENT UNIT POWER MANAGEMENT UNIT FEATURES The power management unit (PMU) controls the different power modes of the ADuCM320i/ADuCM322/ADuCM322i. Four power modes are available: • • • • Active CORE_SLEEP SYS_SLEEP Hibernate POWER MANAGEMENT UNIT OVERVIEW The Cortex-M3 sleep modes are linked to the PMU modes and are described in this section. The PMU is in the always-on section. Each mode gives a power reduction benefit with a corresponding reduction in functionality. POWER MANAGEMENT UNIT OPERATION The debug tools can prevent the Cortex-M3 from fully entering its power saving modes by setting bits in the debug logic. Only a power-on reset resets the debug logic. Therefore, the device must be power cycled after using serial wire debug with application code containing the wait for interrupt (WFI) instruction. Power Mode: Active Mode, Mode 0 The system is fully active. Memories and all user enabled peripherals are clocked, and the Cortex-M3 processor executes instructions. Note that the Cortex-M3 processor manages its internal clocks and can be in a partial clock gated state. This clock gating affects only the internal Cortex-M3 processing core. Automatic clock gating is used on all blocks. User code can use a WFI command to put the Cortex-M3 processor into sleep mode; it is independent of the power mode settings of the PMU. When the ADuCM320i/ADuCM322/ADuCM322i wakes up from any of the low power modes, the devices return to Mode 0. Power Mode: CORE_SLEEP Mode, Mode 1 In CORE_SLEEP mode, the system gates the clock to the Cortex-M3 core after the Cortex-M3 enters sleep mode. The rest of the system remains active. No instructions can be executed; however, DMA transfers can continue to occur between peripherals and memories. The Cortex-M3 processor FCLK is active, and the device wakes up using the nested vectored interrupt controller (NVIC). Power Mode: SYS_SLEEP Mode, Mode 2 In SYS_SLEEP mode, the system gates the system bus clock (HCLK) and the peripheral bus clock (PCLK) after the Cortex-M3 enters sleep mode. The gating of these clocks stops all advanced high performance bus (AHB) attached masters/slaves and all peripherals attached to the advanced peripheral bus (APB). Peripheral clocks are all off, and they are no longer user programmable. The NVIC clock (FCLK) remains active, and the NVIC processes wake-up events. Power Mode: Hibernate Mode, Mode 3 In hibernate mode, the system disables power to all combinational logic and places sequential logic in retain mode. Because FCLK is stopped, the number of sources capable of waking up the system is restricted. The sources listed in Table 54 are the only sources able to wake up the system. Power Mode 1 to Power Mode 3 must be entered when the processor is not in an interrupt handler. If Power Mode 1 to Power Mode 3 are entered when the processor is in an interrupt handler, the power-down mode can only be exited by a reset or a higher priority interrupt source. Rev. D | Page 15 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual CODE EXAMPLES Code Example to Enter Power Saving Modes SCB->SCR = 0x04; pADI_PWRCTL->PWRKEY = 0x4859; pADI_PWRCTL->PWRKEY = 0xF27B; pADI_PWRCTL->PWRMOD = 0x3; __DSB(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); __WFI(); __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); // sleep deep mode // key1 // key2 // Hibernate Code Example to Achieve Further Power Savings pADI_ADC->ADCCON = 0; pADI_IDAC0->IDACCON = 0x1; pADI_IDAC1->IDACCON = 0x1; pADI_IDAC2->IDACCON = 0x1; pADI_IDAC3->IDACCON = 0x1; pADI_VDAC0->DACCON = 0x100; pADI_VDAC1->DACCON = 0x100; pADI_VDAC2->DACCON = 0x100; pADI_VDAC3->DACCON = 0x100; pADI_VDAC4->DACCON = 0x100; pADI_VDAC5->DACCON = 0x100; pADI_VDAC6->DACCON = 0x100; pADI_VDAC7->DACCON = 0x100; pADI_CLKCTL->CLKCON0 &= 0xFFFC; pADI_CLKCTL->CLKCON1 = 0x505; pADI_CLKCTL->CLKCON5 = 0x7B; // // // // // // // // // // // // // // // // Power off the ADC Turn off IDAC0 Turn off IDAC1 Turn off IDAC2 Turn off IDAC3 Turn off VDAC0 Turn off VDAC1 Turn off VDAC2 Turn off VDAC3 Turn off VDAC4 Turn off VDAC5 Turn off VDAC6 Turn off VDAC7 Switch to 16MHz clock Slow down system clocks Turn off clocks to peripherals Rev. D | Page 16 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: POWER MANAGEMENT UNIT Table 8. Power Management Register Summary Address 0x40002400 0x40002404 Name PWRMOD PWRKEY Description Power modes Key protection for PWRMOD Reset 0x0000 0x0000 Access RW RW Reset 0x0 0x0 Access R RW Reset 0x0 Access RW REGISTER DETAILS: POWER MANAGEMENT UNIT Power Modes Register Address: 0x40002400, Reset: 0x0000, Name: PWRMOD Table 9. Bit Descriptions for PWRMOD Bit(s) [14:2] [1:0] Bit Name RESERVED PWRMOD Description Reserved. These bits must write 0 by user code. Power modes control bits. When read, these bits contain the last power mode value entered by user code. Note that, to place the Cortex in sleep deep mode for hibernate, the Cortex-M3 system control register (Address 0xE000ED10) must be configured to 0x4 or 0x06. 00: active mode 01: CORE_SLEEP mode 10: SYS_SLEEP mode 11: hibernate mode Key Protection for PWRMOD Register Address: 0x40002404, Reset: 0x0000, Name: PWRKEY Table 10. Bit Descriptions for PWRKEY Bit(s) [15:0] Bit Name PWRKEY Description Power control key register. The PWRMOD register is key protected. Two writes to the key are necessary to change the value in the PWRMOD register: first 0x4859, then 0xF27B. Then, write to the PWRMOD register. A write to any other register before writing to PWRMOD returns the protection to the lock state. Rev. D | Page 17 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ARM CORTEX-M3 PROCESSOR ARM CORTEX-M3 PROCESSOR FEATURES High Performance • • • • 1.25 DMIPS/MHz. Many instructions, including multiply, are single cycle. Separate data and instruction buses allow simultaneous data and instruction accesses to be performed. Optimized for single cycle flash usage. Low Power • • • Low standby current. Core implemented using advanced clock gating so that only the actively used logic consumes dynamic power. Power saving mode support (sleep and deep sleep modes). The design has separate clocks to allow unused parts of the processor to be stopped. Advanced Interrupt Handling • • • • • The nested vectored interrupt controller (NVIC) supports up to 240 interrupts. The ADuCM320i/ADuCM322/ADuCM322i supports 47 of these interrupts. The vectored interrupt feature greatly reduces interrupt latency because there is no need for software to determine which interrupt handler to serve. In addition, there is no need to have software to set up nested interrupt support. The ARM Cortex-M3 processor automatically pushes registers onto the stack at the entry interrupt and retrieves them at the exit interrupt. The pushing and retrieving helps reduce interrupt handling latency and allow interrupt handlers to be normal C functions. Dynamic priority control for each interrupt. Latency reduction using late arrival interrupt acceptance and tail-chain interrupt entry. Immediate execution of a nonmaskable interrupt request for safety critical applications. System Features • • Support for bit band operation and unaligned data access. Advanced fault handling features include various exception types and fault status registers. Debug Support • • • Serial wire debug interfaces (SW-DP). Flash patch and breakpoint (FPB) unit for implementing breakpoints. Limited to two hardware breakpoints. Data watchpoint and trigger (DWT) unit for implementing watchpoints trigger resources and system profiling. Limited to one hardware watchpoint. The DWT does not support data matching for watchpoint generation because it only has one comparator. ARM CORTEX-M3 PROCESSOR OVERVIEW The ADuCM320i/ADuCM322/ADuCM322i contain an embedded ARM Cortex-M3 processor, Revision r2p1. The ARM Cortex-M3 processor provides a high performance, low cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption while delivering outstanding computational performance and exceptional system response to interrupts. ARM CORTEX-M3 PROCESSOR OPERATION Several ARM Cortex-M3 processor components are flexible in their implementation. This section details the actual implementation of these components in the ADuCM320i/ADuCM322/ADuCM322i. Serial Wire Debug (SW/JTAG-DP) The ADuCM320i/ADuCM322/ADuCM322i only support the serial wire interface via the SWCLK and SWDIO pins. It does not support the 5-wire JTAG interface. ROM Table The ADuCM320i/ADuCM322/ADuCM322i implement the default ROM table. Rev. D | Page 18 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Nested Vectored Interrupt Controller Interrupts (NVICs) The ARM Cortex-M3 processor includes a NVIC, which offers several features: • • • • Nested interrupt support Vectored interrupt support Dynamic priority changes support Interrupt masking In addition, the NVIC has a nonmaskable interrupt (NMI) input. The NVIC is implemented on the ADuCM320i/ADuCM322/ADuCM322i, and more details are available in the System Exceptions and Peripheral Interrupts section. Wake-Up Interrupt Controller (WIC) The ADuCM320i/ADuCM322/ADuCM322i have a modified WIC that provides the lowest possible power-down current. More details on this feature are available in the Power Management Unit section. It is not recommended to enter power saving mode while servicing an interrupt. However, if the device does enter power saving mode while servicing an interrupt, it can only wake up by a higher priority interrupt source. µDMA The ADuCM320i/ADuCM322/ADuCM322i implement the ARM µDMA. More details are available in the Direct Memory Access (DMA) Controller section. ARM CORTEX-M3 PROCESSOR RELATED DOCUMENTS • • • • • • Cortex-M3 Revision r2p1 Technical Reference Manual (DDI 0337) ARM Processor Cortex-M3 (AT420) and Cortex-M3 with ETM AT425): Errata Notice ARMv7-M Architecture Reference Manual (DDI 0403) ARMv7-M Architecture Reference Manual Errata Markup ARM Debug Interface v5 Architecture Specification (IHI 0031) PrimeCell µDMA Controller (PL230) Technical Reference Manual Revision r0p0 (DDI 0417) Rev. D | Page 19 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ADC CIRCUIT ADC CIRCUIT FEATURES The ADuCM320i/ADuCM322/ADuCM322i incorporate a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit (ADuCM320i) or 12-bit (ADuCM322/ADuCM322i) accurate. A flexible input multiplexer supports 16 external inputs and 11 internal channels. The internal channels include the following: • • • • • • • A temperature sensor channel. An internal 2.51 V reference. An external reference. Four IDAC channels. These are the voltage at each of the IDAC output pins (ADuCM320i only). PVDD2 supply voltage (ADuCM320i only). IOVDD/2 supply voltage. AVDD/2 supply voltage. For the ADuCM320i only, the input buffer can be selected for any channel to allow very low input current/input leakage specifications on these input channels. A high precision, low drift internal 2.51 V reference source is provided. An external reference can also be connected to the ADC_REFP and ADC_REFN pins. The programmable ADC update rate is from 19.55 kSPS to 1 MSPS. An internal digital comparator is available for the AIN4 channel. An interrupt can be generated if the digital comparator detects an ADC result above/below a user defined threshold. Each channel has its own distinct data register for its conversion result. For example, when AIN0 is selected, the result appears in ADCDAT0; if AIN7 is selected, the result appears in ADCDAT7. For a differential measurement, the result always appears in the data register of the positive channel. ADC CIRCUIT BLOCK DIAGRAM I AIN+ IBUF_BYP[1] CAPACITOR ARRAY CONTROL AIN0 P BUSY PRECHARGE AIN15 INTERNAL CHANNELS CAPACITOR ARRAY COMP CONTROL LOGIC P OUTPUT CODE ADCCHA CNV I IBUF_BYP[0] I = INPUT BUFFER P = PRECHARGE BUFFER Figure 5. ADC Circuit Block Diagram Rev. D | Page 20 of 195 13437-004 AIN– ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ADC CIRCUIT OVERVIEW The ADuCM320i/ADuCM322/ADuCM322i incorporates a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit (ADuCM320i) or 12-bit (ADuCM322/ADuCM322i) accurate. It can operate from a 2.9 V to 3.6 V supply and is capable of providing a throughput of up to 1 MSPS. This ADC block provides the user with a multichannel multiplexer, input buffer for high impedance input channels (ADuCM320i only), on-chip reference, and SAR ADC. The SAR ADC circuit is implemented on the low voltage analog die. The ARM Cortex-M3 processor interfaces to the ADC via an internal parallel die to die interface. Depending on the input signal configuration, the ADC can operate in one of the following two modes: • • Differential mode measures the difference between two signals. Single-ended mode measures any signal relative to AGND. The converter accepts an analog input range of 0 to VREF when operating in single-ended mode. In fully differential mode, the input signal must be balanced around a common-mode voltage (VCM) in the 0 V to AVDD range and with a maximum amplitude of 2 × VREF. AIN+ AVDD AIN– OUTPUT CODE FS (VREF ) 13437-105 0 –FS (–VREF ) Figure 6. Examples of Balanced Signals for Differential Mode A high precision, low drift, factory-calibrated 2.51 V reference is provided on-chip. An external reference can also be connected to the ADC_REFP and ADC_REFN pins. Single or continuous conversion modes can be initiated in the software. An external pin (alternate function of P2.4) can also generate a repetitive trigger for ADC conversions. ADC CIRCUIT OPERATION The SAR ADC is based on a charge redistribution DAC. The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors that are connected to the two inputs of the comparator. The ADC converts the voltage applied to AIN+ and AIN− in the following three phases: 1. 2. 3. During the precharge phase, the precharge buffers connect the inputs to the capacitor arrays, which charges the capacitors quickly with minimal loading of the external input source. During the acquisition phase, the capacitor arrays are connected directly to the inputs to fully charge the capacitor arrays and eliminate any precharge buffer errors. The timing for the acquisition phase is set by ADCCNVC[25:16]. This value must be set to 500 ns. If the input buffer is not used when measuring AVDD/2, IOVDD/2, or temperature sensor channels, set this value to 1.5 µs. At the end of the acquisition phase, the internal CNV signal goes high and initiates the conversion phase. The conversion begins with the SW+ and SW− switches opening, which disconnects the two capacitor arrays from the analog inputs and connects the analog inputs to the AGND (−VREF) input. The conversion is completed by normal successive approximation. The ADC block operates from an internally generated 20 MHz clock. The ADC conversion rate is set by ADCCNVC[9:0]. Rev. D | Page 21 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ADC TRANSFER FUNCTION Single-Ended Mode In single-ended mode, the input range is 0 to VREF. The output coding is straight binary with 1 LSB = FS/65,536 or VREF/65,536 = 2.51 V/65,536 = 38.30 µV The data values in ADCDATx are aligned such that the MSB is in ADCDATx[27] and, therefore, the LSB is in ADCDATx[12]. The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, …, FS − 3/2 LSB). The ideal input/output transfer characteristic is shown in Figure 7. ADCDATx[31:12] 0000 1111 1111 1111 1111 0000 1111 1111 1111 1110 OUTPUT CODE 0000 1111 1111 1111 1101 0000 1111 1111 1111 1100 1LSB = VREF 65536 0000 0000 0000 0000 0011 0000 0000 0000 0000 0010 0000 0000 0000 0000 0001 0V 1LSB VREF – 1LSB VOLTAGE INPUT NOTES 1. IN ADCDATx, x IS 0 TO 27, AS SHOWN IN TABLE 10. 13437-013 0000 0000 0000 0000 0000 Figure 7. ADC Transfer Function: Single-Ended Mode Differential Mode The amplitude of the differential signal is the difference between the signals applied to the AIN+ and AIN− pins (that is, AIN+ − AIN−). The maximum amplitude of the differential signal is, therefore, −VREF to +VREF p-p (2 × VREF), regardless of the common mode (CM). The common mode is the average of the two signals (AIN+ + AIN−)/2 and is, therefore, the voltage that the two inputs are centered on. This results in the span of each input being CM ± VREF/2. This voltage must be set up externally, and its range varies with VREF. The voltage at the AIN+ and AIN− pins must be within the allowed input voltage range. The output coding is twos complement in fully differential mode, with 1 LSB = 2 × VREF/65,536 or 2 × 2.51 V/65,536 = 76.60 µV where VREF = 2.51 V. The data values in ADCDATx are aligned such that the MSB is in ADCDATx[27] and, therefore, the LSB is in ADCDATx[13]. The ideal input/output transfer characteristic is shown in Figure 8. Rev. D | Page 22 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ADCDATx[31:12] 0000 0000 1111 1111 1110 0000 0000 1111 1111 1100 1LSB = 2 × VREF 65536 OUTPUT CODE 0000 0000 1111 1111 1010 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 1111 1111 1111 1111 1110 1111 0000 0000 0000 0100 1111 0000 0000 0000 0000 –VREF + 1LSB 0LSB +VREF – 1LSB VOLTAGE INPUT (VIN+ – VIN–) NOTES 1. IN ADCDATx, x IS 0 TO 27, AS SHOWN IN TABLE 10. 13437-014 1111 0000 0000 0000 0010 Figure 8. ADC Transfer Function: Differential Mode ADC TYPICAL SETUP SEQUENCE After being configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 16-bit result in the ADC data registers. The following is an example sequence to set up the ADC and generate a single conversion on AIN0 using a single-ended measurement: 1. 2. 3. Configure the device as follows: ADCCON = 0x280; // Power up the ADC, enable reference buffer, idle mode. ADCCHA = 0x1100; // Select AIN0 as the positive ADC input (AIN+) and ADC_REFN as the negative ADC input (AIN−). ADCCNVC = 0xA00C8; // Select 100 kSPS ADC update rate and 500 ns acquisition time. ADCCON | = 0x2; // Enable single conversion. Wait for the low voltage die interrupt iADCRESULT = ADCDAT0; // Read the ADC result. Note that if the ADC is set from continuous conversion mode to idle mode after a full ADC sequence is completed, ADCSEQ[31] must be set to 1 before starting another sequence and reconfiguring the ADC back to continuous conversion mode to ensure that the sequencer restarts with the first selected channel in ADCSEQ. ADC INPUT BUFFER An optional input buffer can be enabled for any ADC input channel on the ADuCM320i only. The control register, IBUFCON, controls the input buffer switches as follows: • • IBUF_BYP (IBUFCON[1:0]) controls the bypass switches on the ADC input buffer. If the input buffer is required on either the positive or negative input, the bypass switch must be turned off. IBUF_PD (IBUFCON[3:2]) powers up or powers down the ADC input buffer. Rev. D | Page 23 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ADC INTERNAL CHANNELS Temperature Sensor Settings The ADuCM320i/ADuCM322/ADuCM322i provide a voltage output from an on-chip band gap reference that is proportional to the absolute temperature of the low voltage die. This voltage output is routed through the front end of the ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel that measures die temperature. The internal temperature sensor is not designed for use as an absolute ambient temperature calculator. Its intended use is as an approximate indicator of the temperature of the ADuCM320i/ADuCM322/ADuCM322i low voltage analog die. An ADC temperature sensor conversion differs from a standard ADC voltage. The ADC performance specifications do not apply to the temperature sensor. When the temperature sensor channel is selected, the ADC update rate must be 80 kSPS. The ADC automatically changes the ADC update rate to 80 kSPS when the temperature sensor, AVDD/2, or IOVDD/2 input channel is selected. If a different ADC sampling rate is required for other channels after the conversion on any of these three channels is completed, the ADCCNVC register must be updated. Note that when the sequencer is enabled and includes any of these three channels, the value in the ADCCNVC register does not change and the ADC sampling rate does not change. The temperature sensor settings are as follows. Enable the temperature sensor on the ADC; set ADCCHA[12:0] = 0x1116. To calculate the die temperature, use the following formula: T − TREF = (VADC − VTREF) × K where: T is the temperature result. TREF is 25°C. VADC is the average ADC result from two consecutive conversions. VTREF is the ADC result in millivolts that corresponds to TREF = 25°C. The user must measure this in their own application because this value varies from device to device. The typical value used for demonstration purposes is 1290 mV. K is the gain of the ADC in temperature sensor mode. The user must determine the gain by performing a two-point temperature calibration because this value varies from device to device. The typical value used for demonstration purposes only is 4.394 mV/°C. This 4.394 mV/°C value corresponds to 1/V TC. Using the default values from the ADuCM320i, the ADuCM322, the ADuCM322i data sheets without any calibration, the equation becomes T − 25°C = (VADC − 1290) × 1/K Therefore, assuming VADC at 25°C = 1290 mV and slope mV/C = 4.394 mV/C, T = ((VADC − 1290)/4.394) + 25 where: VADC is in millivolts. See the latest version of the ADuCM320i, the ADuCM322, the ADuCM322i data sheets for the most up to date figures. For increased accuracy, perform a two-point calibration at a controlled temperature value. The values used in this example for VTREF and K are not guaranteed values. The VTREF and K values vary from device to device; therefore, the user must derive the appropriate values by performing a calibration at ambient temperature. AVDD/2 and IOVDD/2 Supply Voltage Channels These supply voltage channels are measured via internal resistor dividers. Because the resistors used are high impedance and the divided voltage is not buffered, a slower ADC update rate must be used. The ADC automatically changes the ADC update rate to 80 kSPS when the temperature sensor, AVDD/2, or IOVDD/2 input channel is selected. If a different ADC sampling rate is required for other channels after the conversion on any of these three channels is completed, the ADCCNVC register must be updated. Note that when the sequencer is enabled and includes any of these three channels, the value in the ADCCNVC register does not change and the ADC sampling rate does not change. At rates above 80 kSPS, the accuracy is reduced on the ADuCM320i if the input buffer is disabled. Rev. D | Page 24 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ADC SUPPORT CIRCUITS IDAC Channels (ADuCM320i Only) The ADuCM320i allows the voltage on the IDAC output pins to be selected as inputs to the ADC. These channels are useful for determining the power consumed by each IDAC. ADC Digital Comparator A digital comparator is provided to allow an interrupt to be triggered if the ADC data result is above or below a programmable threshold. Only the AIN4 external input channel can be used with the digital comparator. To set up the ADC digital comparator, note the following: • • • • • • ADCCMP[17:2] set a 16-bit ADC threshold value. ADCCMP[1] configures the comparator to be triggered when the ADC result is above or below the threshold value. To enable the ADC comparator interrupt, set INTSEL[2] = 1 to enable the digital comparator to the Low Voltage Die Interrupt 1 signal. Similarly, set INTSEL[10] = 1 to enable the digital comparator interrupt to the Low Voltage Die Interrupt 0 signal. The comparator output is asserted when the value in ADCDAT4[27:12] rises above the value in ADCCMP[17:2] if ADCCMP[1] = 1. If ADCDAT4[27:12] remains above ADCCMP[17:2], no further comparator interrupts occur. The interrupt only occurs when the comparator circuit detects a rise above the threshold. Similarly, if ADCCMP[1] = 0, the comparator output is asserted when the value in ADCDAT4[27:12] falls below the value in ADCCMP[17:2]. If ADCDAT4[27:12] remains below ADCCMP[17:2], no further comparator interrupts occur. The interrupt only occurs when the comparator circuit detects a fall below the threshold value. ADC Channel Sequencer An ADC sequencer is provided to reduce the processor overhead of sampling and reading individual channels. The ADC sequencer allows the user to select the number and order of ADC input channels that the ADC samples and provides a single interrupt source that is asserted when the sequence ends. The sequencer can also be programmed to restart automatically without a delay or with a programmable delay between the end and start of sequences. Some additional details about the sequencer include the following. The sequencer reads the ADCSEQ[0:28] register to determine which channels need to be included and which need to be excluded from the execution sequence. ADCSEQ corresponds to the ADCCHA[4:0] for the list of ADC input channels. For example, to include AIN9, set ADCSEQ[9]. To enable the sequencer as the Low Voltage Die Interrupt 1 source, set INTSEL[1] = 1. To enable the sequencer as the Low Voltage Die Interrupt 0 source, set INTSEL[9] = 1. To start the sequencer, set ADCSEQ[31:30] = 0x3. The ADCSEQC[27:20] register bits set the delay between finishing one sequence of channels and starting another sequence. Normally, single-ended measurements are assumed by the ADC with AGND as the negative reference. However, for Channel 0, Channel 2, Channel 4, and Channel 6, a differential measurement can be selected by configuring the appropriate bits in ADCSEQC[19:0]. For example, ADCSEQC[4:0] selects the negative input when AIN0 is the positive. For single-ended measurements using the sequencer and AIN0, ADCSEQC[4:0] must be set to 0x11 for VREFN_NADC (ADC_REFN pin). On the ADuCM320i, take care when using the sequencer if the input buffer is enabled. The IBUFCON register controls the input buffer. If the input buffer is enabled, all channels sampled in a sequence are sampled with the input buffer enabled. It is recommended to split sequences into the following: • • • Sample unbuffered channels together in one sequence. Sample buffered channels in a separate sequence. If full accuracy results are required for the AVDD/2, IOVDD/2, or temperature channels, take care when measuring with the sequencer. With the input buffer disabled, the acquisition time must be set to 1.5 µs via ADCCONV[25:16] = 0x1E. Alternatively, enable the input buffer. Rev. D | Page 25 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual ADC Direct Memory Access (DMA) The ADC or the ADC sequencer can be selected as the source channel for the DMA controller. This reduces processor overhead by moving ADC results directly into SRAM with a single interrupt asserted when the required number of ADC conversions has been completely logged to memory. When using the ADC sequencer with the DMA controller, it is recommended to use DMA autorequest transfer types rather than basic transfer types. ADC Voltage Reference Selection The ADuCM320i/ADuCM322/ADuCM322i integrate a low drift, 2.5 V ADC reference source. By default, this internal reference is enabled and selected as the reference source for the ADC. When using the internal 2.5 V voltage reference, ensure the following: • • ADCCON[7] = 1 to power up the internal reference buffer AFEREFC[3] = 0 to select the internal reference as the ADC reference source It is also possible to select an external reference source through the ADC_REFP pin. To select an external voltage source as the ADC reference source, ensure the following: • • ADCCON[7] = 0 to power down the internal reference buffer AFEREFC[3] = 1 to select the external reference as the ADC reference source The external reference source must be capable of driving the 4.7 µF capacitor on the ADC_REFP pin. If switching from the external to internal reference voltage source, note that there is a power-on time specification given in the ADuCM320i, the ADuCM322, the ADuCM322i data sheets for the ADC reference buffer to fully power up after ADCCON[7] is set to 1. Figure 9 shows the block diagram of how the analog references are provided. AFEREFC[0] AFEREFC[1] AFEREFC[3] AFEREFC[2] 2.5V GAIN STAGE MUX 1.2V BUF_VREF2.5B DRIVER ADC BUFFER ADC CAPP 2.5V ADC ADCCON[7] VDAC DACxCON[1:0] Figure 9. System Reference Voltage Block Diagram Rev. D | Page 26 of 195 13437-005 AVDD MUX BG ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: ADC CIRCUIT The CPU accesses the ADC circuit over a die to die interface (D2D), which increases the execution times of LDR and STR instructions. The 32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. The 16-bit MMRs have addresses of 0x40082xxx and take 6 CPU cycles at 80 MHz to execute. Table 11. ADC Circuit Register Summary Address 0x40082174 0x40086000 0x40086004 0x40086008 0x4008600C 0x40086010 0x40086014 0x40086018 0x4008601C 0x40086020 0x40086024 0x40086028 0x4008602C 0x40086030 0x40086034 0x40086038 0x4008603C 0x40086040 0x40086044 0x40086048 0x4008604C 0x40086050 0x40086054 0x40086058 0x4008605C 0x40086060 0x40086064 0x40086068 0x4008606C 0x40086080 0x40086088 0x4008608C 0x40086090 0x40086094 0x40086098 0x4008609C Name ADCCON ADCDAT0 ADCDAT1 ADCDAT2 ADCDAT3 ADCDAT4 ADCDAT5 ADCDAT6 ADCDAT7 ADCDAT8 ADCDAT9 ADCDAT10 ADCDAT11 ADCDAT12 ADCDAT13 ADCDAT14 ADCDAT15 ADCDAT16 ADCDAT17 ADCDAT18 ADCDAT19 ADCDAT20 ADCDAT21 ADCDAT22 ADCDAT23 ADCDAT24 ADCDAT25 ADCDAT26 ADCDAT27 ADCCHA ADCSEQ ADCSEQC RESERVED RESERVED ADCCMP ADCCNVC Description ADC configuration ADC0 data and flags ADC1 data and flags ADC2 data and flags ADC3 data and flags ADC4 data and flags ADC5 data and flags ADC6 data and flags ADC7 data and flags ADC8 data and flags ADC9 data and flags ADC10 data and flags ADC11 data and flags ADC12 data and flags ADC13 data and flags ADC14 data and flags ADC15 data and flags ADC16 data and flags ADC17 data and flags ADC18 data and flags ADC19 data and flags ADC20 data and flags ADC21 data and flags ADC22 data and flags ADC23 data and flags ADC24 data and flags ADC25 data and flags ADC26 data and flags ADC27 data and flags ADC channel select ADC sequencer control ADC sequencer configuration Reserved Reserved Digital comparator configuration ADC conversion configuration Rev. D | Page 27 of 195 Reset 0x0280 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0x111F 0x00000000 0x0008C631 Not applicable Not applicable 0x00000 0x000A0014 Access RW R R R R R R R R R R R R R R R R R R R R R R R R R R R R RW RW RW Not applicable Not applicable RW RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER DETAILS: ADC CIRCUIT ADC Configuration Register Address: 0x40082174, Reset: 0x0280, Name: ADCCON Table 12. Bit Descriptions for ADCCON Bit(s) [15:11] 10 9 Bit Name RESERVED SOFT_RESET PUP 8 7 RESERVED REFB_PUP 6 RESTART_ADC 5 4 RESERVED SEQ_DMA 3 CNV_DMA [2:0] C_TYPE Description Reserved. Software reset ADC. ADC power up. 0: power down. 1: power up. Reserved. ADC reference buffer power up. 0: power down. 1: power up. Must be set to 1 for the ADC to operate normally. Restart ADC, reset analog part of ADC. Active high. 0: clear to 0 for normal ADC operation. 1: set to 1 to reset the ADC. Reserved. DMA request enable for ADC sequence conversion. 0: clear to 0 to disable ADC sequencer DMA access. 1: set to 1 to enable ADC sequencer DMA access. DMA request enable for ADC nonsequence conversion. 0: clear to 0 to disable ADC DMA access. 1: set to 1 to enable ADC DMA access. ADC conversion type. 000: no conversion. 001: DIO pin starts conversion (P2.4). 010: single conversion. 011: continuous conversion (use this mode for the sequencer). 100: PLA conversion. Reset 0x0 0x0 0x1 Access R W RW 0x0 0x1 R RW 0x0 W 0x0 0x0 R RW 0x0 RW 0x0 RW ADCx Data and Flags Register Address: 0x40086000 to 0x4008606C (Increments of 0x4), Reset: 0x00000000, Name: ADCDAT0 to ADCDAT27 At the end of each conversion, the ADC writes the data to the appropriate ADCDATx MMR, where x is 0 to 27. This process takes 2 ADC clock cycles, which at 20 MHz means 100 ns. During this time, the value in ADCDATx cannot be read reliably by the CPU. Therefore, during this time ADCDATx is forced to zero and specifically Bit ADCDATx[3] is zero. Therefore, if ADCDATx is read at random times, ADCDATx[3] must be checked and, if it is zero, ADCDATx must be read again. This second read must be at least 100 ns later, which is basically guaranteed by the time used to check the bit plus the time required to read the value via the D2D interface. Make sure that the second read does not coincide with any further conversion on that channel. Alternately, perform repeated reads until the read is successful. At 1 MSPS conversion speed, the read is valid 90% of the time, while at 100 kSPS, it is valid 99% of the time. When using interrupts, this problem does not occur unless the read happens exactly when a subsequent ADC conversion completes on that channel. This behavior is valid for all conversion modes (single conversions, repeated conversions, and sequencer conversions). Table 13. Bit Descriptions for ADCDAT0 to ADCDAT27 Bit(s) [31:4] Bit Name DAT 3 VALID 2 OLD Description ADCx data. The numeric value of the conversion is stored in bits 12 to 27. Bit 28 to Bit 31 are the extended sign bits. Bit 4 to Bit 11 are always zero. The format is twos complement (signed integer). Flag indicating if data is valid. 0: data is invalid. 1: data is valid. Flag data has already been read. 0: last data has not been read. 1: last data already read. Rev. D | Page 28 of 195 Reset 0x0 Acces s RW 0x0 R 0x0 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) [1:0] Bit Name RESERVED Description Reserved. UG-868 Reset 0x0 Acces s RW Reset 0x0 0x11 Acces s R RW 0x0 0x1F R RW ADC Channel Select Register Address: 0x40086080, Reset: 0x111F, Name: ADCCHA ADCCHA is the ADC channel select register for nonsequence operation. Table 14. Bit Descriptions for ADCCHA Bit(s) [15:13] [12:8] Bit Name RESERVED ADCCN [7:5] [4:0] RESERVED ADCCP Description Reserved. Selects channel for ADC negative input. 0x00: AIN0. 0x01: AIN1. 0x02: AIN2. 0x03: AIN3. 0x04: AIN4. 0x05: AIN5. 0x06: AIN6. 0x07: AIN7. 0x08: AIN8. 0x09: AIN9. 0x0A: AIN10. 0x0B: AIN11. 0x0C: AIN12. 0x0D: AIN13. 0x0E: AIN14. 0x0F: AIN15. 0x10: VREFP_NADC: connect ADC_REFP to negative input. 0x11: VREFN_NADC: connect ADC_REFN to negative input. Use this setting for single-ended measurements. 0x12: AGND. 0x13: PGND (ADuCM320i only). 0x14 to 0x1F: reserved. Reserved. Select ADC channel. 0x0: AIN0. 0x1: AIN1. 0x2: AIN2. 0x3: AIN3. 0x4: AIN4. 0x5: AIN5. 0x6: AIN6. 0x7: AIN7. 0x8: AIN8. 0x9: AIN9. 0xA: AIN10. 0xB: AIN11/BUF_VREF2V5. Note that, to measure BUF_VREF2V5, it must be first enabled in the AFEREFC[2] register. 0xC: AIN12. 0xD: AIN13. 0xE: AIN14. 0xF: AIN15. 0x10: reserved. 0x11: reserved. Rev. D | Page 29 of 195 UG-868 Bit(s) Bit Name ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description 0x12: IDAC3 (ADuCM320i only). 0x13: IDAC1 (ADuCM320i only). 0x14: IDAC0 (ADuCM320i only). 0x15: IDAC2 (ADuCM320i only). 0x16: TEMP_SENSOR. 0x17: VREFP_PADC: connect ADC_REFP to positive input. Note that this pin must not be measured relative to AGND. This selection is for measuring the differential voltage between the negative input and ADC_REFP. 0x18: PVDD_IDAC2: use this to measure the PVDD supply voltage for IDAC2 (ADuCM320i only). 0x19: IOVDD_2: use this to measure half of the IOVDD supply voltage. 0x1A: AVDD_2: use this to measure half of the AVDD supply voltage. 0x1B: VREFN_PADC: connect ADC_REFN to positive input. 0x1C to 0x1F: reserved. Reset Acces s Reset 0x0 Access W 0x0 W 0x0 0x0 R RW ADC Sequencer Control Register Address: 0x40086088, Reset: 0x00000000, Name: ADCSEQ Table 15. Bit Descriptions for ADCSEQ Bit(s) 31 Bit Name ST 30 EN 29 [28:0] RESERVED CH Description Sequence restart, used to force sequence to start at first channel when sequence is working. 1: Set to 1 to restart the sequencer. Cleared after writing 1. Sequence enable. 1: Set to 1 to enable the sequencer Reserved. Select channels included in sequence operation. Each bit corresponds to an ADC channel as defined by ADCCHA[4:0]. For example, a value of 0x33 (00110011) includes AIN0, AIN1, AIN4, and AIN5 in the sequence and excludes all other channels. For each channel: 0: channel is skipped. 1: channel is included in the sequence. ADC Sequencer Configuration Register Address: 0x4008608C, Reset: 0x0008C631, Name: ADCSEQC Table 16. Bit Descriptions for ADCSEQC Bit(s) [31:28] [27:20] Bit Name RESERVED T [19:15] DIF6 [14:10] DIF4 [9:5] DIF2 [4:0] DIF0 Description Reserved. Define programmable delay of 0 to 254 between sequences. A delay of 255 causes a halt after one sequence. Set ADCSEQ[30] if another sequence is required. Selects differential mode negative input for AIN6 in the sequence. See ADCCHA[12:8] for list of channels. 0x11: Channel 6 is single-ended. Selects differential mode negative input for AIN4 in the sequence. See ADCCHA[12:8] for list of channels. 0x11: Channel 4 is single-ended. Selects differential mode negative input for AIN2 in the sequence. See ADCCHA[12:8] for list of channels. 0x11: Channel 2 is single-ended. Selects differential mode negative input for AIN0 in the sequence. See ADCCHA[12:8] for list of channels. 0x11: Channel 0 is single-ended. Rev. D | Page 30 of 195 Reset 0x0 0x0 Access R RW 0x11 RW 0x11 RW 0x11 RW 0x11 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Digital Comparator Configuration Register Address: 0x40086098, Reset: 0x00000, Name: ADCCMP Table 17. Bit Descriptions for ADCCMP Bit(s) [17:2] 1 Bit Name THR DIR 0 EN Description Digital compare threshold. Value to compare to Channel 4 data. Select digital comparator direction. 0: ADCTH less than Channel 4 data. 1: ADCTH larger than Channel 4 data. Digital comparator enable. 0: disable. 1: enable. Reset 0x0000 0x0 Access RW RW 0x0 RW ADC Conversion Configuration Register Address: 0x4008609C, Reset: 0x000A0014, Name: ADCCNVC When ADCCP is set to 22 (temperature sensor) or 25 (IOVDD/2) or 26 (AVDD/2), the ADCCNVC register automatically changes to 0x7D00FA − (80 kSPS) for single conversions. ADCCNVC must be set to the required conversion rate after sampling these three channels if a different sample rate is required for other ADC input channels. When the sequencer is enabled and includes any of these three channels, the value in ADCCNVC does not change, and the ADC sampling rate does not change. Table 18. Bit Descriptions for ADCCNVC Bit(s) [31:26] [25:16] Bit Name RESERVED CNVD [15:10] [9:0] RESERVED CNVC Description Do not overwrite. Configure ADC acquisition time and sampling time. Acquisition time = CNVD/20 MHz. Default acquisition time is 500 ns. For best SNR results, ensure the acquisition time is set to ≥500 ns for all ADC conversion rates. Do not overwrite. Configure conversion frequency. Conversion frequency = 20 MHz/CNVC. Reset 0x0 0xA Access RW RW 0x00 0x14 RW RW REGISTER SUMMARY: ADDITIONAL REGISTERS The CPU accesses these additional registers over a die to die interface (D2D), which increases the execution times of LDR and STR instructions. The 32-bit MMRs have addresses of 0x40087xxx and take 8 CPU cycles at 80 MHz to execute. The 8-bit MMRs have addresses of 0x40081xxx and take 5 CPU cycles at 80 MHz to execute. Table 19. Register Summary Address 0x40081400 0x40087830 0x40087834 Name IBUFCON AFETEMPC AFEREFC Description Input buffer control bit register Temperature sensor configuration register Reference configuration register Rev. D | Page 31 of 195 Reset 0x000F 0x00 0x00 Access RW RW RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER DETAILS: ADDITIONAL REGISTERS Input Buffer Control Bit Register Address: 0x40081400, Reset: 0x000F, Name: IBUFCON Table 20. Bit Descriptions for IBUFCON Bit(s) [15:4] [3:2] Bit Name RESERVED IBUF_PD [1:0] IBUF_BYP ADuCM320i Description Reserved. Power down P/N input buffer separately. 00: both sides powered on (ADuCM320i only). 01: N side powered down (ADuCM320i only). 10: P side powered down (ADuCM320i only). 11: both sides powered down. Bypass P/N input buffer separately. 00: bypass neither side (ADuCM320i only). 01: N side bypassed (ADuCM320i only). 10: P side bypassed (ADuCM320i only). 11: bypass both sides. ADuCM322/ADuCM322i Description Reserved. Reserved. These bits must write 0x3 to the user code on the ADuCM322/ADuCM322i. If an attempt is made to enable power on, the internal buffers ADC measurement will be distorted. Reset 0x0 0x3 Access RW RW Reserved. These bits must write 0x3 to user code on the ADuCM322 and the ADuCM322i. 0x3 RW Reset 0x0 0x0 Access R RW 0x0 RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW Temperature Sensor Configuration Register Address: 0x40087830, Reset: 0x00, Name: AFETEMPC Table 21. Bit Descriptions for AFETEMPC Bit(s) [7:2] 1 Bit Name RESERVED CHOP 0 PD Description Reserved. Temperature sensor chopping enable. Do not use chopping mode together with the sequencer. 0: disable chopping mode. 1: enable chopping mode. Temperature sensor power down. 0: power up temperature sensor. 1: power down temperature sensor. Reference Configuration Register Address: 0x40087834, Reset: 0x00, Name: AFEREFC Table 22. Bit Descriptions for AFEREFC Bit(s) [7:4] 3 Bit Name RESERVED REF 2 B2MA_PDB 1 B2V5R_PD 0 BG_PD Description Reserved. Bypass the internal reference, and select the external reference. 0: select internal 2.51 V reference. 1: select external 2.51 V reference. Power down the reference 1.2 mA output driving Buffer B, which is on the AIN11/BUF_VREF2V5 pin. 0: power down 2.5 V reference output driving BUF_VREF2V5 1: power up 2.5 V reference output driving BUF_VREF2V5 2.5 V reference buffer power down. 0: power up 2.5 V reference buffer. 1: power down 2.5 V reference buffer. Band gap power down. 0: power up 1.2 V band gap. 1: power down 1.2 V band gap. Rev. D | Page 32 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 ANALOG COMPARATOR ANALOG COMPARATOR FEATURES The analog comparator compares two analog signals and gives an output indicating which of the input signals is bigger. This output can generate an interrupt. ANALOG COMPARATOR OVERVIEW The positive input of the comparator is shared with AIN6. The negative input of the comparator can be set by software to AVDD/2, AIN5, or DAC7. The comparator output is connected to the interrupt logic and can be used as described in the System Exceptions and Peripheral Interrupts section. ANALOG COMPARATOR OPERATION If required, change the hysteresis with AFECOMP[0], the comparator speed with AFECOMP[1:2], and the output polarity with AFECOMP[3]. Select the input source with AFECOMP[6:7]. Power up and enable the comparator with AFECOMP[8] and AFECOMP[4:5]. REGISTER SUMMARY: ANALOG COMPARATOR The CPU accesses the ADC circuit over a die to die interface (D2D) which increases the execution times of LDR and STR instructions. Accessing AFECOMP takes 8 CPU cycles at 80 MHz to execute. Table 23. Analog Comparator Register Summary Address 0x40087838 Name AFECOMP Description Analog comparator configuration register Reset 0x0000 Access RW REGISTER DETAILS: ANALOG COMPARATOR Analog Comparator Configuration Register Address: 0x40087838, Reset: 0x0000, Name: AFECOMP Table 24. Bit Descriptions for AFECOMP Bit(s) [15:9] 8 Bit Name RESERVED EN [7:6] INNEG [5:4] OUT 3 INV [2:1] SPEED 0 HYS Description Reserved. Powers up and enables comparator. 0: power down and disable comparator. 1: power up and enable comparator. Selects comparator negative input signal. 00: AVDD/2. 01: AIN5. 10: DAC7. 11: unused. Connects comparator output to interrupt logic. 0: do not connect output. 1: connect output to interrupt logic. Selects output logic state. 0: output is high if the positive input terminal of the amplifier (+ve) is above the negative input of the terminal of the amplifier (−ve). 1: output is high if +ve input is below −ve input. Selects comparator speed to falling output. Response time to rising output is 6 µs typical. 00: 6 µs. 01: 4 µs. 10: 4 µs. 11: 3 µs. Enables comparator hysteresis. 0: disable hysteresis. 1: enable hysteresis. Rev. D | Page 33 of 195 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual IDACs (ADUCM320i ONLY) IDAC FEATURES The ADuCM320i provides four IDACs, which are low noise, low drift current source outputs. IDAC0, IDAC1, IDAC2, and IDAC3 provide 0 mA to 150 mA full-scale output, bias current setting for optical laser. IDAC BLOCK DIAGRAM PVDD 3.3V AGND LDO PVDD CDAMP 10nF 2.5V OUT 11-BIT IDAC 5-BIT IDAC BUF 1.2V VREF IDAC3 BUF PGND 3.16kΩ RREF 5ppm 0.1% PGND PGND ADC INPUT MUX PGND 13437-008 PULL-DOWN 100µA SINK CURRENT Figure 10. Example IDAC Circuit—IDAC3 IDAC OVERVIEW Precision Current Generation and Fault Protection The reference current for the IDACs is generated by a precision internal band gap voltage reference (VBANDGAP) and an external precision resistor (RREF, 5 ppm, 0.1%). The reference current is equal to VBANDGAP ÷ RREF. The band gap voltage reference is a low drift, high accuracy voltage source that helps to minimize the overall IDAC gain error and gain error drift. The noise of the IDAC outputs is limited by the low-pass filter on the output stage; each IDAC requires a 10 nF capacitor between PVDD and its CDAMP pin. Figure 10 shows the typical architecture of the IDAC. The parallel 11-bit and 5-bit IDACs set the output current. The output of these IDACs are summed together and fed to a current mirror and then are gained up at the output stage. Production trimming of the low dropout (LDO) band gap reference aids performance. In addition, gain trimming and scaling of the current mirror and output stages are also included in the ATE test program. IDAC Shutdown IDAC0, IDAC1, IDAC2, and IDAC3 also have a small current sink capability to minimize the offset current when the data register is set to 0. The IDACxCON[1] bit can enable a pull-down current source to PGND. This pull-down current is typically 100 µA. IDAC Output Filter Each IDAC has a filter on the output stage to minimize noise. Each IDAC requires an external 10 nF capacitor between PVDD and its CDAMP pin, as per the ADuCM320i data sheet. The on-chip, programmable resistor is controlled by the IDACxCON[5:2] bits. Table 25. IDAC Filter Bandwidth Control Settings IDACxCON[5:2] 0000 0101 0110 0111 1000 1001 All other options are reserved R Value 60 Ω 5.6 kΩ 11.2 kΩ 22.2 kΩ 44.4 kΩ 104 kΩ Rev. D | Page 34 of 195 Cutoff Frequency (fC) 262 kHz 2.8 kHz 1.4 kHz 715 Hz 357 Hz 153 Hz ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 IDAC Data Register The IDAC output is controlled by an internal 11-bit and 5-bit DAC. 14-BIT IDAC OUTPUT 13 12 11 10 9 8 7 6 5 11-BIT DAC 27 26 25 24 23 22 21 20 19 4 3 18 17 16 15 2 1 0 14 13 12 IDACxDAT 5-BIT DAC 13437-009 The 11-bit DAC (IDACxDAT[27:17]) controls the most significant bits. The 5-bit DAC (IDACxDAT[16:12]) controls the LSBs. The two MSBs of the 5-bit DAC (IDACxDAT[16:15]) overlap the two LSBs of the 11-bit DAC (IDACxDAT[18:17]) as shown in Figure 11. Figure 11. 14-Bit IDAC Output The 11-bit DAC and the 5-bit DAC are guaranteed monotonic as individual DACs. This combination makes it possible to reach 14-bit resolution—up to 16,384 unique output values. However, monotonicity is only guaranteed for 11 bits (DNL < −1 LSB). IDACs Common Use Cases Case 1: Setting the Output Current of IDAC1 to Quarter Scale Set up IDAC1CON to 10xxxx00b: • • • • • • IDAC1CON[7] = 1: enable writes to the IDAC1DAT register. IDAC1CON[0] = 0: power up IDAC1. IDAC1CON[5:2] as per Table 25: set up the filter bandwidth as required. IDAC1CON[1] = 0: disable the IDAC1 pull-down current source. IDAC1DAT[3] = 0: clear the IDAC1 sync bit to allow immediate updating of the IDAC. IDAC1CON[6] = 0: disable the over temperature shutdown feature. Set up IDAC1DAT to give a current output of quarter scale: • • If IDAC1 is used in an open loop system or in a set and forget type operation, set IDAC1DAT = 0x03FE0000. Set IDAC1DAT[27:17] = 0x1FF. Set IDAC1DAT[16:12] = 0x00. • If IDAC1 is used in a closed loop system, set IDAC1DAT = 0x03FCF000. • Set IDAC1DAT[27:17] = 0x1FE. • Set IDAC1DAT[16:12] = [01111]b. • Adjust the 5-bit IDAC (IDAC1DAT[16:12]) up or down accordingly to attain the correct setting. Case 2: Turn on IDAC2 and Set Output to 0 mA with the Lowest Possible Offset Before powering up the IDACs, ensure that the internal reference is fully powered on. Set up the IDAC2CON register to 10xxxx00b: • • • • • IDAC2CON[7] = 1: enable writes to the IDAC2DAT register. IDAC2CON[0] = 0: power up IDAC2. IDAC2CON[5:2] as per Table 25: set up the filter bandwidth as required. IDAC2CON[1] = 0: enable the IDAC2 pull-down current sink. IDAC2CON[6] = 0: disable the overtemperature shutdown feature. Set up the IDAC2DAT register: • IDAC2DAT[27:12] = 0x0000: set the IDAC to zero scale. If any or all the IDACs are not used, connect the pins as follows: • • • • IREF: if no IDACs are used, connect a low cost 3.3 kΩ resistor to ground. If no PVDD supply is available, connect PVDDx of all IDACs to AVDD_REG1 (Ball F10). Make sure not to power up such IDACs to avoid loading AVDD_REG1 unnecessarily. Leave the CDAMPx pin of any unused IDACs unconnected. For the IDACx of individual unused IDACs: • Power down IDACx using the PD bit (IDACxCON = 1; this bit is powered down after a reset). • Set IDACxDAT = 0 (zero current; this bit is 0 after a reset). • Connect IDACx pin to PGND. Rev. D | Page 35 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual IDAC Thermal Shutdown The ADuCM320i has an internal temperature sensor that monitors the die temperature. This temperature sensor can be monitored as an ADC input channel; the measured voltage is proportional to die temperature. See the Temperature Sensor Settings section for more information. Internally, the die temperature is compared to a fixed voltage, proportional to approximately 130°C die temperature. If the die temperature exceeds 130°C, there is a risk of damaging the die because the absolute maximum junction temperature rating is 150°C. Because the IDACs potentially consume the most power, shut off the IDACs to reduce power and therefore to reduce the die temperature. Two options to enable shutdown include the following: • • Enable a thermal interrupt by setting either INTSEL[12] or INTSEL[4]. If the die temperature exceeds the threshold of approximately 130°C, this interrupt triggers and user code takes the appropriate action. It is recommended to use this procedure. Enable automatic shutdown of the IDACs by setting the individual thermal shutdown bits for each IDAC via IDACxCON[6]. If this bit is set in the appropriate IDACxCON register, the IDAC output current reduces to 0 mA, which reduces the power consumption of the device and the die temperature of the device. Note that the internal temperature sensor accuracy can be up to ±20°C, and there is no way of calibrating the thermal shutdown trip point. Therefore, it is recommended that the automatic thermal shutdown feature (IDACxCON[6] = 0) not be enabled. REGISTER SUMMARY: IDAC The CPU accesses the IDAC circuit over a die to die interface (D2D), which increases the execution times of LDR and STR instructions. The 32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. Table 26. IDAC Register Summary Address 0x40086800 0x40086804 0x40086808 0x4008680C 0x40086810 0x40086814 0x40086818 0x4008681C Name IDAC0DAT IDAC0CON IDAC1DAT IDAC1CON IDAC2DAT IDAC2CON IDAC3DAT IDAC3CON Description IDAC0 data register IDAC0 control register IDAC1 data register IDAC1 control register IDAC2 data register IDAC2 control register IDAC3 data register IDAC3 control register Reset 0x00000000 0x01 0x00000000 0x01 0x00000000 0x01 0x00000000 0x01 Access RW RW RW RW RW RW RW RW REGISTER DETAILS: IDAC IDAC0 Data Register Address: 0x40086800, Reset: 0x00000000, Name: IDAC0DAT Table 27. Bit Descriptions for IDAC0DAT Bit(s) [31:28] [27:17] [16:12] [11:4] 3 Bit Name RESERVED DATH DATL RESERVED SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 Description Reserved. Write 0. IDAC0 high data. IDAC0 low data. Reserved. IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating. When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written. IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating. When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written. IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating. When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written. IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating. When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written. Rev. D | Page 36 of 195 Reset 0x0 0x0 0x0 0x0 0x0 Access R RW RW R RW 0x0 RW 0x0 RW 0x0 RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 IDAC0 Control Register Address: 0x40086804, Reset: 0x01, Name: IDAC0CON Table 28. Bit Descriptions for IDAC0CON Bit(s) 7 Bit Name CLRB 6 SHT_EN [5:2] 1 BW PUL 0 PD Description IDAC0 clear bit. 0: clear IDAC0DAT. 1: enable write. IDAC0 shutdown enable. Enables automatic shutdown in case of overtemperature. 0: disable this function. 1: enable this function. IDAC0 bandwidth. See the IDAC Output Filter section for more details. IDAC0 pull down. 0: disable the pull-down current source. 1: enable the pull-down current source. IDAC0 power down. 0: powers up IDAC0. 1: powers down IDAC0. Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW 0x1 RW Reset 0x0 0x0 0x0 0x0 0x0 Access R RW RW R RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW 0x1 RW IDAC1 Data Register Address: 0x40086808, Reset: 0x00000000, Name: IDAC1DAT Table 29. Bit Descriptions for IDAC1DAT Bit(s) [31:28] [27:17] [16:12] [11:4] 3 Bit Name RESERVED DATH DATL RESERVED SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 Description Reserved. Write 0. IDAC1 high data. IDAC1 low data. Reserved. IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating. When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written. IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating. When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written. IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating. When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written. IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating. When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written. IDAC1 Control Register Address: 0x4008680C, Reset: 0x01, Name: IDAC1CON Table 30. Bit Descriptions for IDAC1CON Bit(s) 7 Bit Name CLRB 6 SHT_EN [5:2] 1 BW PUL 0 PD Description IDAC1 clear bit. 0: clear IDAC1DAT. 1: enable write. IDAC1 shutdown enable. Enables automatic shutdown in case of overtemperature. 0: disable this function. 1: enable this function. IDAC1 bandwidth. See the IDAC Output Filter section for more details. IDAC1 pull down. 0: disable the pull-down current source. 1: enable the pull-down current source. IDAC1 power down. 0: powers up IDAC1. 1: powers down IDAC1. Rev. D | Page 37 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual IDAC2 Data Register Address: 0x40086810, Reset: 0x00000000, Name: IDAC2DAT Table 31. Bit Descriptions for IDAC2DAT Bit(s) [31:28] [27:17] [16:12] [11:4] 3 Bit Name RESERVED DATH DATL RESERVED SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 Description Reserved. Write 0. IDAC2 high data. IDAC2 low data. Reserved. IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating. When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written. IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating. When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written. IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating. When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written. IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating. When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written. Reset 0x0 0x0 0x0 0x0 0x0 Access R RW RW R RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW 0x1 RW Reset 0x0 0x0 0x0 0x0 0x0 Access R RW RW R RW 0x0 RW 0x0 RW 0x0 RW IDAC2 Control Register Address: 0x40086814, Reset: 0x01, Name: IDAC2CON Table 32. Bit Descriptions for IDAC2CON Bit(s) 7 Bit Name CLR 6 SHT_EN [5:2] 1 BW PUL 0 PD Description IDAC2 clear bit. 0: clear IDAC2DAT. 1: enable write. IDAC2 shutdown enable. Enables automatic shutdown in case of overtemperature. 0: disable this function. 1: enable this function. IDAC2 bandwidth. See the IDAC Output Filter section for more details. IDAC2 pull down. 0: disable the pull-down current source. 1: enable the pull-down current source. IDAC2 power down. 0: powers up IDAC2. 1: powers down IDAC2. IDAC3 Data Register Address: 0x40086818, Reset: 0x00000000, Name: IDAC3DAT Table 33. Bit Descriptions for IDAC3DAT Bit(s) [31:28] [27:17] [16:12] [11:4] 3 Bit Name RESERVED DATH DATL RESERVED SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 Description Reserved. Write 0. IDAC3 high data. IDAC3 low data. Reserved. IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating. When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written. IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating. When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written. IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating. When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written. IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating. When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written. Rev. D | Page 38 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 IDAC3 Control Register Address: 0x4008681C, Reset: 0x01, Name: IDAC3CON Table 34. Bit Descriptions for IDAC3CON Bit(s) 7 Bit Name CLR 6 SHT_EN [5:2] 1 BW PUL 0 PD Description IDAC3 Clear bit. 0: clear IDAC3DAT. 1: enable write. IDAC3 shutdown enable. Enables automatic shutdown in case of overtemperature. 0: disable this function. 1: enable this function. IDAC3 bandwidth. See the IDAC Output Filter section for more details. IDAC3 pull down. 0: disable the pull-down current source. 1: enable the pull-down current source. IDAC3 power down. 0: powers up IDAC3. 1: powers down IDAC3. Rev. D | Page 39 of 195 Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW 0x1 RW UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual VDACs VDAC FEATURES The ADuCM320i/ADuCM322/ADuCM322i have eight VDACs. The specified load resistance is greater than 5 kΩ, and the specified capacitance is less than 100 pF. VDAC BLOCK DIAGRAM VREF STRING DAC DAC BUFFER 13437-010 DACOUT Figure 12. Output Mode Capacitor Load ≤ 100 pF VDAC OVERVIEW The ADuCM320i/ADuCM322/ADuCM322i have eight VDACs specified to drive 5 kΩ load, 500 µA maximum. The VDACs can select from two reference sources: • • 0 V to internal reference, VREF (0 V to 2.5 V) 0 V to AVDD (3.3 V) VDAC OPERATION The DAC is configurable through a control register and a data register. The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, as shown in Figure 12. The linearity specification of the DAC when driving a 5 kΩ resistive load to ground is guaranteed through the full transfer function except for Code 0 to Code 100; in 0 V to AVDD mode, the linearity specification is also not guaranteed for Code 3995 to Code 4095. Linearity degradation near ground and AVDD is caused by saturation of the output amplifier; a general representation of its effects (neglecting offset and gain error) is shown in Figure 13. The dotted line in Figure 13 indicates the ideal transfer function. The solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. Figure 13 represents a transfer function in 0 V to AVDD mode only. In 0 V to VREF mode, the lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line all the way to the end, showing no signs of endpoint linearity errors. 0x00000000 0x0FFF0000 13437-016 AVDD Figure 13. DAC Endpoint Nonlinearities Due to Amplifier Saturation Rev. D | Page 40 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 During power-on reset, all VDAC channels ramp up and return to normal state at 1 ms, as shown in Figure 14. 13437-213 1 CH1 100mV CH2 100mV M400µs A CH1 T 362.4000µs 100mV Figure 14. VDAC Channels Response at Power-Up Rev. D | Page 41 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual REGISTER SUMMARY: VDAC The CPU accesses the VDAC circuit over a die to die interface (D2D), which increases the execution times of LDR and STR instructions. The 32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. The 16-bit MMRs have addresses of 0x40082xxx and take 6 CPU cycles at 80 MHz to execute. Table 35. VDAC Register Summary Address 0x40082400 0x40082404 0x40082408 0x4008240C 0x40082410 0x40082414 0x40082418 0x4008241C 0x40086404 0x40086408 0x4008640C 0x40086410 0x40086414 0x40086418 0x4008641C 0x40086420 Name DAC0CON DAC1CON DAC2CON DAC3CON DAC4CON DAC5CON DAC6CON DAC7CON DAC0DAT DAC1DAT DAC2DAT DAC3DAT DAC4DAT DAC5DAT DAC6DAT DAC7DAT Description DAC0 control register DAC1 control register DAC2 control register DAC3 control register DAC4 control register DAC5 control register DAC6 control register DAC7 control register DAC0 data register DAC1 data register DAC2 data register DAC3 data register DAC4 data register DAC5 data register DAC6 data register DAC7 data register Reset 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW REGISTER DETAILS: VDAC DAC0 Control Register Address: 0x40082400, Reset: 0x0100, Name: DAC0CON Table 36. Bit Descriptions for DAC0CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC0 power down. 0: DAC0 is powered up. 1: DAC0 is powered down and output is floating. Reserved. DAC0 enable. Must be set to 1. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC0 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Rev. D | Page 42 of 195 Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DAC1 Control Register Address: 0x40082404, Reset: 0x0100, Name: DAC1CON Table 37. Bit Descriptions for DAC1CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC1 power down. 0: DAC1 is powered up. 1: DAC1 is powered down and output is floating. Reserved. DAC1 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC1 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 RW DAC2 Control Register Address: 0x40082408, Reset: 0x0100, Name: DAC2CON Table 38. Bit Descriptions for DAC2CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC2 power down. 0: DAC2 is powered up. 1: DAC2 is powered down and output is floating. Reserved. DAC2 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC2 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. DAC3 Control Register Address: 0x4008240C, Reset: 0x0100, Name: DAC3CON Table 39. Bit Descriptions for DAC3CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] RESERVED Description Reserved. DAC3 power down. 0: DAC3 is powered up. 1: DAC3 is powered down and output is floating. Reserved. Rev. D | Page 43 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 4 Bit Name EN [3:2] [1:0] RESERVED RN Description DAC3 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately 1: DAC enable. Reserved. DAC3 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Reset 0x0 Access RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW DAC4 Control Register Address: 0x40082410, Reset: 0x0100, Name: DAC4CON Table 40. Bit Descriptions for DAC4CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC4 power down. 0: DAC4 is powered up. 1: DAC4 is powered down and output is floating. Reserved. DAC4 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC4 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. DAC5 Control Register Address: 0x40082414, Reset: 0x0100, Name: DAC5CON Table 41. Bit Descriptions for DAC5CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC5 power down. 0: DAC5 is powered up. 1: DAC5 is powered down and output is floating. Reserved. DAC5 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC5 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Rev. D | Page 44 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DAC6 Control Register Address: 0x40082418, Reset: 0x0100, Name: DAC6CON Table 42. Bit Descriptions for DAC6CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC6 power down. 0: DAC6 is powered up. 1: DAC6 is powered down and output is floating. Reserved. DAC6 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC6 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW Reset 0x0 0x1 Access R RW 0x0 0x0 RW RW 0x0 0x0 RW RW DAC7 Control Register Address: 0x4008241C, Reset: 0x0100, Name: DAC7CON Table 43. Bit Descriptions for DAC7CON Bit(s) [15:9] 8 Bit Name RESERVED PD [7:5] 4 RESERVED EN [3:2] [1:0] RESERVED RN Description Reserved. DAC7 power down. 0: DAC7 is powered up. 1: DAC7 is powered down and output is floating. Reserved. DAC7 enable. Must be set to high. 0: DAC disable. Clear DAC data immediately. 1: DAC enable. Reserved. DAC7 reference selection. These bits set the DAC range. A write to these bits has immediate effect on the DAC. 00: internal reference. 01: reserved. 10: reserved. 11: AVDD/AGND. Rev. D | Page 45 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DAC0 Data Register Address: 0x40086404, Reset: 0x00000000, Name: DAC0DAT Table 44. Bit Descriptions for DAC0DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC0 data. Reserved. Write 0. Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R DAC1 Data Register Address: 0x40086408, Reset: 0x00000000, Name: DAC1DAT Table 45. Bit Descriptions for DAC1DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC1 data. Reserved. Write 0. DAC2 Data Register Address: 0x4008640C, Reset: 0x00000000, Name: DAC2DAT Table 46. Bit Descriptions for DAC2DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC2 data. Reserved. Write 0. DAC3 Data Register Address: 0x40086410, Reset: 0x00000000, Name: DAC3DAT Table 47. Bit Descriptions for DAC3DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC3 data. Reserved. Write 0. DAC4 Data Register Address: 0x40086414, Reset: 0x00000000, Name: DAC4DAT Table 48. Bit Descriptions for DAC4DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC4 data. Reserved. Write 0. DAC5 Data Register Address: 0x40086418, Reset: 0x00000000, Name: DAC5DAT Table 49. Bit Descriptions for DAC5DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC5 data. Reserved. Write 0. Rev. D | Page 46 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DAC6 Data Register Address: 0x4008641C, Reset: 0x00000000, Name: DAC6DAT Table 50. Bit Descriptions for DAC6DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC6 data. Reserved. Write 0. Reset 0x0 0x0 0x0 Access R RW R Reset 0x0 0x0 0x0 Access R RW R DAC7 Data Register Address: 0x40086420, Reset: 0x00000000, Name: DAC7DAT Table 51. Bit Descriptions for DAC7DAT Bit(s) [31:28] [27:16] [15:0] Bit Name RESERVED DAT RESERVED Description Reserved. Write 0. DAC7 data. Reserved. Write 0. Rev. D | Page 47 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS CORTEX-M3 AND FAULT MANAGEMENT The ADuCM320i/ADuCM322/ADuCM322i integrate an ARM Cortex-M3 processor, which supports several system exceptions and interrupts generated by peripherals. Table 52 lists the ARM Cortex-M3 processor system exceptions. Table 52. System Exceptions Number 1 2 Type Reset NMI Priority −3 (highest) −2 3 4 5 Hard fault Memory management fault Bus fault −1 Programmable Programmable 6 7 to 10 11 12 13 14 Usage fault Reserved SVCALL Debug monitor Reserved PENDSV Programmable Not applicable. Programmable Programmable Not applicable Programmable 15 SYSTICK Programmable Description Any reset. Nonmaskable interrupt not connected on the ADuCM320i/ADuCM322/ ADuCM322i. All fault conditions if the corresponding fault handler is not enabled. Memory management fault; access to invalid locations. Prefetch fault, memory access fault, data abort, and other address/memory related faults. Same as undefined instruction executed or invalid state transition attempt. Not applicable. System service call with SVC instruction. Used for system function calls. Debug monitor (breakpoint, watchpoint, or external debug requests). Not applicable. Pendable request for system service. Used for queuing system calls until other tasks and interrupts are serviced. System tick timer. The NVIC controls the peripheral interrupts and are listed in Table 53. All interrupt sources can wake up the device from Mode 1. Only a limited number of interrupts can wake up the processor from the low power modes (Mode 2 and Mode 3), as shown in Table 53. When the device is woken up from Mode 2 or Mode 3, it returns to Mode 0. If the processor enters any power mode from Mode 1 to Mode 3 while the processor is in an interrupt handler, only an interrupt source with a higher priority than the current interrupt can wake up the device (higher value in IPRx registers). Two steps are usually required to configure an interrupt: • • Configuring a peripheral to generate an interrupt request to the NVIC. Configuring the NVIC for that peripheral request. Table 53. Interrupt Vector Table Position No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Vector Wake-up timer External Interrupt 0 External Interrupt 1 External Interrupt 2 Reserved External Interrupt 4 External Interrupt 5 Reserved External Interrupt 7 External Interrupt 8 Watchdog timer Reserved Reserved Low Voltage Die Interrupt 0 MDIO General-Purpose Timer 0 General-Purpose Timer 1 Flash controller UART SPI0 Wake-Up Processor from Mode 1 Yes Yes Yes Yes Wake-Up Processor from Mode 2 or Mode 3 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No Rev. D | Page 48 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Position No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Vector SPI1 I2C0 slave I2C0 master PLA 0 PLA 1 DMA error DMA Channel 0 (SPI0 Tx) done DMA Channel 1 (SPI0 Rx) done DMA Channel 2 (SPI1 Tx) done DMA Channel 3 (SPI1 Rx) done DMA Channel 4 (UART Tx) done DMA Channel 5 (UART Rx) done DMA Channel 6 (I2C0 slave Tx) done DMA Channel 7 (I2C0 slave Rx) done DMA Channel 8 (I2C0 master) done DMA Channel 9 (I2C1 slave Tx) done DMA Channel 10 (I2C1 slave Rx) done DMA Channel 11 (I2C1 master) done DMA Channel 12 (ADC) done DMA Channel 13 (flash) done Reserved Reserved Reserved Reserved I2C1 slave I2C1 master PLA 2 PLA 3 General-Purpose Timer 2 Low Voltage Die Interrupt 1 PWM trip PWM Pair 0 PWM Pair 1 PWM Pair 2 PWM Pair 3 UG-868 Wake-Up Processor from Mode 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Wake-Up Processor from Mode 2 or Mode 3 No No No No No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No Internal to the ARM Cortex-M3 processor, the highest user-programmable priority (0) is treated as fourth priority, which is after a reset, an NMI, and a hard fault. The ADuCM320i/ADuCM322/ADuCM322i implement three priority bits, which means that eight priority levels are available as programmable priorities. Note that 0 is the default priority for all the programmable priorities. If the same priority level is assigned to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both SPI0 and SPI1 are Priority Level 1, SPI0 has higher priority. To enable an interrupt for any peripheral listed from 0 to 31 in Table 53, set the appropriate bit in the ISER0 register. ISER0 is a 32-bit register, and each bit corresponds to the first 32 entries in Table 53. For example, to enable External Interrupt 4 interrupt source in the NVIC, set ISER0[5] = 1. Similarly, to disable External Interrupt 4, set ICER0[5] = 1. To enable an interrupt for any peripheral listed from 32 to 54 in Table 53, set the appropriate bit in the ISER1 register. ISER1 is a 32-bit register, and ISER1 Bit 0 to Bit 22 correspond to the entries 32 to 54 in Table 53. For example, to enable the PWM Pair 0 interrupt source in the NVIC, set ISER1[20] = 1. Similarly, to disable the PWM Pair 0 interrupt, set ICER1[20] = 1. Alternatively, CMSIS provides a number of useful NVIC functions in the core_cm3.h file. The NVIC_EnableIRQ(PWM_PAIR0_IRQn) function enables the PWM Pair 0 interrupt. The interrupt can be disabled by calling the NVIC_DisableIRQ(PWM_PAIR0_IRQn) function. Rev. D | Page 49 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual To set the priority of a peripheral interrupt, the IPRx bits can be set appropriately or, alternatively, the NVIC_SetPriority() function can be called. For example, NVIC_SetPriority(TIMER0_IRQn, 2) configures the General-Purpose Timer 0 interrupt with a priority level of 2. Table 54 lists the registers to enable and disable relevant interrupts and set the priority levels. The registers in Table 54 are defined in the CMSIS core_cm3.h file, which is shipped with tools from third party vendors. Table 54. NVIC Registers Address 0xE000E004 0xE000E010 0xE000E014 0xE000E018 0xE000E01C 0xE000E100 0xE000E104 0xE000E180 Analog Devices Header File Name ICTR STCSR STRVR STCVR STCR ISER0 ISER1 ICER0 0xE000E184 ICER1 0xE000E200 0xE000E204 0xE000E280 0xE000E284 ISPR0 ISPR1 ICPR0 ICPR1 0xE000E300 0xE000E304 0xE000E400 0xE000E404 0xE000E408 0xE000E40C 0xE000E410 0xE000E414 0xE000E418 0xE000E41C 0xE000E420 0xE000E424 0xE000E428 0xE000E42C 0xE000E430 0xE000E434 0xE000ED00 0xE000ED04 0xE000ED08 0xE000ED0C 0xE000ED10 0xE000ED14 0xE000ED18 0xE000ED1C 0xE000ED20 0xE000ED24 0xE000ED28 0xE000ED2C 0xE000ED34 0xE000ED38 0xE000EF00 IABR0 IABR1 IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 IPR10 IPR11 IPR12 IPR13 CPUID ICSR VTOR AIRCR SCR CCR SHPR1 SHPR2 SHPR3 SHCRS CFSR HFSR MMAR BFAR STIR Description Shows the number of interrupt lines that the NVIC supports. SYSTICK control and status register. SYSTICK reload value register. SYSTICK current value register. SYSTICK calibration value register. Set IRQ0 to IRQ31 enable. Each bit corresponds to Interrupt 0 to Interrupt 31 in Table 53. Set IRQ32 to IRQ54 enable. Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 53. Clear IRQ0 to IRQ31 by setting appropriate bit. Each bit corresponds to Interrupt 0 to Interrupt 31 in Table 53. Clear IRQ32 to IRQ54 by setting appropriate bit. Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 53. Set IRQ0 to IRQ31 pending. Each bit corresponds to Interrupt 32 to Interrupt 38 in Table 53. Set IRQ32 to IRQ54 pending. Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 53. Clear IRQ0 to IRQ31 pending. Each bit corresponds to Interrupt 32 to Interrupt 38 in Table 53. Clear IRQ32 to IRQ54 pending. Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 53. IRQ0 to IRQ31 active bits. IRQ32 to IRQ54 active bits. IRQ0 to IRQ3 priority. IRQ4 to IRQ7 priority. IRQ8 to IRQ11 priority. IRQ12 to IRQ15 priority. IRQ16 to IRQ19 priority. IRQ20 to IRQ23 priority. IRQ24 to IRQ27 priority. IRQ28 to IRQ31 priority. IRQ32 to IRQ35 priority. IRQ36 to IRQ39 priority. IRQ40 to IRQ43 priority. IRQ44 to IRQ47 priority. IRQ48 to IRQ51 priority. IRQ52 to IRQ54 priority. CPUID base register. Interrupt control and status register. Vector table offset register. Application interrupt/reset control register. System control register. Configuration control register. System Handlers Register 1. System Handlers Register 2. System Handlers Register 3. System handler control and state. Configurable fault status. Hard fault status. Memory manage fault address register. Bus fault address. Software trigger interrupt register. Rev. D | Page 50 of 195 Access R RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW RW W ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 EXTERNAL INTERRUPT CONFIGURATION Seven external interrupts are implemented. These seven external interrupts can be separately configured to detect any combination of the following type of events: • • Edge: rising edge, falling edge, or both rising and falling edges. An interrupt signal (pulse) is sent to the NVIC upon detecting a transition from low to high, high to low, or on either high to low or low to high. Level: high or low. An interrupt signal is generated and remains asserted in the NVIC until the conditions generating the interrupt deassert. The level must be maintained for a minimum of one core clock cycle to be detected. The external interrupt detection unit block is in the always-on section and allows external interrupt to wake up the device when in hibernate mode. Ensure that the associated GPxIE register bit is enabled for the required external interrupt input. The GPxIE register enables the input path circuit for the external interrupt. For example, for External Interrupt 0, the following code disables the P0.3 output and enables the input path. The appended code also enables the External Interrupt 0 NVIC interrupt source: pADI_GP0->GPOE &= 0xf7; //Disable P0.3 output. pADI_GP0->GPIE |= 0x8; //Enable input path for P0.3 input. pADI_INTERRUPT->EI0CFG |= 0x8; //External IRQ0 enabled. NVIC_EnableIRQ(EINT0_IRQn); //Enable External Interrupt 0 source. REGISTER SUMMARY: EXTERNAL INTERRUPTS Table 55. External Interrupts Register Summary Address 0x40002420 0x40002424 0x40002428 0x40002430 Name EI0CFG EI1CFG EI2CFG EICLR Description External Interrupt Configuration 0 External Interrupt Configuration 1 External Interrupt Configuration 2 External interrupt clear Reset 0x0000 0x0000 0x0000 0x0000 Access RW RW RW RW REGISTER DETAILS: EXTERNAL INTERRUPTS External Interrupt Configuration Register 0 Address: 0x40002420, Reset: 0x0000, Name: EI0CFG Table 56. Bit Descriptions for EI0CFG Bit(s) [15:12] 11 Bit Name RESERVED IRQ2EN [10:8] IRQ2MDE 7 IRQ1EN Description Reserved. External Interrupt 2 enable bit. 0: External Interrupt 2 disabled. 1: External Interrupt 2 enabled. External Interrupt 2 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). External Interrupt 1 enable bit. 0: External Interrupt 0 disabled. 1: External Interrupt 0 enabled. Rev. D | Page 51 of 195 Reset 0 0x0 Access 0x0 RW 0x0 RW RW UG-868 Bit(s) [6:4] Bit Name IRQ1MDE 3 IRQOEN [2:0] IRQ0MDE ADuCM320i/ADuCM322/ADuCM322i Reference Manual Description External Interrupt 1 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). External Interrupt 0 enable bit. 0: External Interrupt 0 disabled. 1: External Interrupt 0 enabled. External Interrupt 0 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). Reset 0x0 Access RW 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0 0x0 RW 0x0 RW External Interrupt Configuration Register 1 Address: 0x40002424, Reset: 0x0000, Name: EI1CFG Table 57. Bit Descriptions for EI1CFG Bit(s) 15 Bit Name IRQ7EN [14:12] IRQ7MDE [11:8] 7 RESERVED IRQ5EN [6:4] IRQ5MDE Description External Interrupt 7 enable bit. 0: External Interrupt 7 disabled. 1: External Interrupt 7 enabled. External Interrupt 7 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). Reserved. External Interrupt 5 enable bit. 0: External Interrupt 5 disabled. 1: External Interrupt 5 enabled. External Interrupt 5 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). Rev. D | Page 52 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) 3 Bit Name IRQ4EN [2:0] IRQ4MDE Description External Interrupt 4 enable bit. 0: External Interrupt 4 disabled. 1: External Interrupt 4 enabled. External Interrupt 4 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). UG-868 Reset 0x0 Access RW 0x0 RW Reset 0x0 0x0 Access 0x0 RW Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW RW RW External Interrupt Configuration Register 2 Address: 0x40002428, Reset: 0x0000, Name: EI2CFG Table 58. Bit Descriptions for EI2CFG Bit(s) [15:4] 3 Bit Name RESERVED IRQ8EN [2:0] IRQ8MDE Description Reserved External Interrupt 8 enable bit. 0: External Interrupt 8 disabled. 1: External Interrupt 8 enabled. External Interrupt 8 mode registers. 000: rising edge. 001: falling edge. 010: rising or falling edge. 011: high level. 100: low level. 101: falling edge (same as 001). 110: rising or falling edge (same as 010). 111: high level (same as 011). RW External Interrupt Clear Register Address: 0x40002430, Reset: 0x0000, Name: EICLR Table 59. Bit Descriptions for EICLR Bit(s) [15:9] 8 7 6 5 4 3 2 1 0 Bit Name RESERVED IRQ8 IRQ7 RESERVED IRQ5 IRQ4 RESERVED IRQ2 IRQ1 IRQ0 Description Reserved. External Interrupt 8. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. External Interrupt 7. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. Reserved. External Interrupt 5. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. External Interrupt 4. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. Reserved. External Interrupt 2. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. External Interrupt 1. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. External Interrupt 0. Set to 1 to clear an internal interrupt flag. Cleared automatically by hardware. Rev. D | Page 53 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual LOW VOLTAGE ANALOG DIE INTERRUPT CONFIGURATION Two interrupt lines are available between the low voltage analog die and the interrupt controller on the digital die. These two interrupt lines are the outputs of two multiplexers of multiple interrupt sources from the low voltage analog die. The full list of interrupt sources from the low voltage analog die are as follows: • • • • • • • • ADC software conversion complete interrupt, which is asserted at the end of an ADC conversion when this interrupt source is enabled. ADC sequencer complete interrupt, which is the interrupt asserted by the ADC sequencer. Analog comparator interrupt. If the input signal is outside the selected threshold, this interrupt is asserted. Digital comparator interrupt. If the ADC result is outside the selected threshold, this interrupt is asserted. IDAC thermal shutdown interrupt. IDAC external reference resistor status interrupt. Read error correction and checking (ECC) interrupt source. ECC is available on the interface between the digital and analog die. If a read error occurs (for example, an error on the ADC result), this interrupt is asserted. Write ECC interrupt source. If the ECC returns an error on a value written to the low voltage die, this interrupt is asserted. Low Voltage Die Interrupt 1 is more flexible than Low Voltage Die Interrupt 0. There are two key differences. Low Voltage Die Interrupt 1 allows all seven different interrupt sources as configured by INTSEL[7:0] to be enabled. In the interrupt handler, the Low Voltage Die Interrupt 1 interrupt source can be determined by the INTSTA register. Low Voltage Die Interrupt 0 allows only one of the possible seven interrupt sources selected by INTSEL[15:8] to be enabled at a given time. The INTSTA register is not valid for Low Voltage Interrupt 0. To clear an interrupt, set the appropriate bit in the INTCLR register. Note that there is a delay period required after writing to INTCLR before the associated status bit in the INTSTA register is updated. If polling is used of the INTSTA register, the following example code can be used: pADI_LV_INT->INTCLR = 0x1; // Clear Irq source delay(10); ucLVIrqStatus = pADI_LV_INT->INTSTA; // Simple delay routine void delay (long int length) { while (length >0) length--; } REGISTER SUMMARY: LOW VOLTAGE DIE INTERRUPTS Table 60. Low Voltage Die Interrupts Register Summary Address 0x40083004 0x40083008 0x4008300C Name INTCLR INTSEL INTSTA Description Interrupt clear register Interrupt mask register Interrupt status register Rev. D | Page 54 of 195 Reset 0x0000 0x0000 0x0000 Access W RW R ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER DETAILS: LOW VOLTAGE DIE INTERRUPTS Interrupt Clear Register Address: 0x40083004, Reset: 0x0000, Name: INTCLR Table 61. Bit Descriptions for INTCLR Bit(s) 7 6 5 4 3 2 1 0 Bit Name CLR_WRECC_ERR CLR_RDECC_ERR CLR_IDAC_EXTRESLOW CLR_IDAC_TSHUT CLR_ACOMP CLR_DCOMP CLR_ADC_SEQ CLR_ADC_SOFTCONV Description Write 1 to this bit to clear the write ECC error interrupt flag. Write 1 to this bit to clear the read ECC error interrupt flag. Write 1 to this bit to clear the IDAC EXTRESLOW interrupt flag. Write 1 to this bit to clear the IDAC TSHUT interrupt flag. Write 1 to this bit to clear the analog compare interrupt flag. Write 1 to this bit to clear the digital compare interrupt flag. Write 1 to this bit to clear the ADC sequence conversion interrupt flag. Write 1 to this bit to clear the ADC software conversion interrupt flag. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access W W W W W W W W Interrupt Mask Register Address: 0x40083008, Reset: 0x0000, Name: INTSEL Table 62. Bit Descriptions for INTSEL Bit(s) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name SEL_WRECC_ERR_0 SEL_RDECC_ERR_0 SLE_IDAC_EXTRESLOW_0 SEL_IDAC_TSHUT_0 SEL_ACOMP_0 SEL_DCOMP_0 SEL_ADC_SEQ_0 SEL_ADC_SOFTCONV_0 SEL_WRECC_ERR_1 SEL_RDECC_ERR_1 SLE_IDAC_EXTRESLOW_1 SEL_IDAC_TSHUT_1 SEL_ACOMP_1 SEL_DCOMP_1 SEL_ADC_SEQ_1 SEL_ADC_SOFTCONV_1 Description Write 1 to this bit to enable write ECC error interrupt for Interrupt 0. Write 1 to this bit to enable read ECC error interrupt for Interrupt 0. Write 1 to this bit to enable IDAC EXTRESLOW interrupt for Interrupt 0. Write 1 to this bit to enable IDAC TSHUT interrupt for Interrupt 0. Write 1 to this bit to enable analog comparator interrupt for Interrupt 0. Write 1 to this bit to enable digital comparator interrupt for Interrupt 0. Write 1 to this bit to enable ADC sequence conversion interrupt for Interrupt 0. Write 1 to this bit to enable ADC software conversion interrupt for Interrupt 0. Write 1 to this bit to enable write ECC error interrupt for Interrupt 1. Write 1 to this bit to enable read ECC error interrupt for Interrupt 1. Write 1 to this bit to enable IDAC EXTRESLOW interrupt for Interrupt 1. Write 1 to this bit to enable IDAC TSHUT interrupt for Interrupt 1. Write 1 to this bit to enable analog comparator interrupt for Interrupt 1. Write 1 to this bit to enable digital comparator interrupt for Interrupt 1. Write 1 to this bit to enable ADC sequence conversion interrupt for Interrupt 1. Write 1 to this bit to enable ADC software conversion interrupt for Interrupt 1. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Interrupt Status Register Address: 0x4008300C, Reset: 0x0000, Name: INTSTA Table 63. Bit Descriptions for INTSTA Bit(s) 7 6 5 4 3 2 1 0 Bit Name WRECC_ERR RDECC_ERR IDAC_EXTRESLOW IDAC_TSHUT ACOMP DCOMP ADC_SEQ ADC_SOFTCONV Description Write data ECC error interrupt status Read data ECC error interrupt status IDAC EXTRESLOW interrupt status IDAC temperature thermal shutdown interrupt status Analog comparator interrupt status Digital comparator interrupt status ADC sequence interrupt status ADC software conversion interrupt status Rev. D | Page 55 of 195 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual RESET RESET FEATURES There are four kinds of resets: • • • • External reset Power-on reset Watchdog timeout Software system reset RESET OPERATION The software system reset is provided as part of the Cortex-M3 processor. To generate a software system reset, the NVIC_SystemReset() function must be called and this effectively writes 0x05FA to the top 16 bits of an AIRCR NVIC register. This function, along with other useful functions, are defined in the CMSIS header files that are shipped with the tools from third party vendors. The NVIC_SystemReset() function is defined in the core_cm3.h file. Analog peripherals have the option of maintaining their state after a software or watchdog reset. This function is enabled by default. It can be disabled using the LVRST register. Note that while debugging, the software tools generally only issue a software reset; therefore, an external reset is needed to return registers to their default values. The GPIO pins and PLA also have the option of maintaining their state after a software or watchdog reset. By default, this function is enabled. Writing a value of 0x1 to RSTCFG configures the GPIO pins and PLA to reset after a software or watchdog reset. Before writing to this register, 0x2009 must be written to RSTKEY followed by 0x0426. After the two keys are written to RSTKEY, RSTCFG must be immediately written. The RSTSTA register stores the cause for the reset until it is cleared by writing the RSTSTA register. RSTSTA can be used during a reset exception service routine to identify the source of the reset. The watchdog timer is enabled by default after a reset. The default timeout period is approximately 32 seconds. User code must disable the watchdog timer at the start of user code when debugging or if the watchdog timer is not required. pADI_WDT->T3CON = 0x00; // Disable watchdog timer Table 64. Device Reset Implications Reset SWRST WDRST External Reset Pin POR 1 Reset External Pins to Default State Yes/No 1 Yes/No1 Yes Yes Execute Kernel Yes Yes Yes Yes Impact Reset All MMRs Except RSTSTA Yes/No1 Yes/No1 Yes Yes Reset All Peripherals Yes/No1 Yes/No1 Yes Yes GPIOs, PLA, and analog peripherals have the option of retaining their output state during a watchdog or software reset. Rev. D | Page 56 of 195 Valid SRAM Yes Yes Yes No RSTSTA After Reset Event RSTSTA[3] = 1 RSTSTA[2] = 1 RSTSTA[1] = 1 RSTSTA[0] = 1 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 REGISTER SUMMARY: RESET Table 65. Reset Register Summary Address 0x40002408 0x4000240C 0x40002440 0x40082C34 Name RSTCFG RSTKEY RSTSTA LVRST Description Reset configuration Key protection for RSTCFG Reset status Low voltage die reset configuration Reset 0x0000 0x0000 0x0000 0x0000 Access RW RW RW RW REGISTER DETAILS: RESET Reset Configuration Register Address: 0x40002408, Reset: 0x0000, Name: RSTCFG Table 66. Bit Descriptions for RSTCFG Bit(s) 0 Bit Name GPIO_PLA_RETAIN Description GPIO/PLA retain their status after watchdog or software reset. Note that, if GPIO_PLA_RETAIN = 0, P3.4 goes high-Z for approximately 260 µs after software/watchdog reset. 1: GPIO/PLA do not retain status after watchdog or software reset. 0: GPIO/PLA retain status after watchdog or software reset. Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x0 0x0 Access R RW1C 0x0 RW1C 0x0 0x0 RW1C RW1C Reset 0x0 0x0 Access R RW Key Protection for RSTCFG Register Address: 0x4000240C, Reset: 0x0000, Name: RSTKEY Table 67. Bit Descriptions for RSTKEY Bit(s) [15:0] Bit Name RSTKEY Description Reset configuration key register. The RSTCFG register is key protected. Two writes to the key are necessary to change the value in the RSTCFG register: first 0x2009, then 0x0426. The RSTCFG register must then be written to. A write to any other register on the APB bus before writing to RSTCFG returns the protection to the lock state. Reset Status Register Address: 0x40002440, Reset: 0x0000, Name: RSTSTA Table 68. Bit Descriptions for RSTSTA Bit(s) [15:4] 3 Bit Name RESERVED SWRST 2 WDRST 1 0 EXTRST POR Description Reserved. Software reset. Set automatically to 1 when the Cortex-M3 system reset is generated. Cleared by writing 1 to the bit. Watchdog timeout. Set automatically to 1 when a watchdog timeout occurs. Cleared by writing 1 to the bit. External reset. Set automatically to 1 when an external reset occurs. Cleared by writing 1 to the bit. Power-on reset. Set automatically when a power-on reset occurs. Cleared by writing one to the bit. Low Voltage Die Reset Configuration Register Address: 0x40082C34, Reset: 0x0000, Name: LVRST Table 69. Bit Descriptions for LVRST Bit(s) [15:1] 0 Bit Name RESERVED RETAIN Description Reserved. Low voltage die retains status after watchdog or software reset. 0: low voltage die retains status after watchdog or software reset. 1: low voltage die does not retain status after watchdog or software reset. Rev. D | Page 57 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DIRECT MEMORY ACCESS (DMA) CONTROLLER DMA FEATURES The ADuCM320i/ADuCM322/ADuCM322i provide 14 dedicated and independent DMA channels. There are two programmable priority levels for each DMA channel. Each priority level arbitrates using a fixed priority that is determined by the DMA channel number. Channels with lower numbers have higher priority. For example, SPI0 transmit has the highest priority, and the next highest is the SPI0 receive. Each DMA channel can access a primary and/or alternate channel control structure. Multiple DMA transfer types are supported: • • • Memory to memory Memory to peripheral Peripheral to memory DMA OVERVIEW DMA provides high speed data transfer between peripherals and memory. Data can be moved quickly by DMA without any processor actions, which keeps processor resources free for other operations. The DMA controller has 14 channels in total. The 14 channels are dedicated to managing DMA requests from specific peripherals. Channels are assigned as shown in Table 70. Table 70. DMA Channel Assignment Channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Peripheral SPI0 Tx SPI0 Rx SPI1 Tx SPI1 Rx UART Tx UART Rx I2C0 slave Tx I2C0 slave Rx I2C0 master I2C1 slave Tx I2C1 slave Rx I2C1 master ADC Flash The channels are connected to dedicated hardware DMA requests; a software trigger is also supported on each channel. This configuration is done by software. Each DMA channel has a programmable priority level: default or high. Within a priority level, arbitration is performed using a fixed priority that is determined by the DMA channel number. Channels with lower numbers have higher priority. For example, SPI0 transmit has the highest priority, and the next highest is the SPI0 receive. The DMA controller supports multiple DMA transfer data widths: independent source and destination transfer size (byte, half word, and word). Source and destination addresses must be aligned on the data size. The DMA controller supports peripheral to memory, memory to peripheral, and memory to memory transfers and access to flash or SRAM as source and destination. DMA OPERATION The DMA controller performs direct memory transfer by sharing the system bus with the Cortex-M3 processor. The DMA request may stall the processor access to the system bus for some bus cycles when the processor and DMA are targeting the same destination (memory or peripheral). Rev. D | Page 58 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 DMA INTERRUPTS An interrupt can be produced for each DMA channel when a transfer is complete. Separate interrupt enable bits are available in the NVIC for each of the DMA channels. The DMA controller fetches channel control data structures located in the SRAM memory to perform data transfers. When enabled to use DMA operation, the DMA capable peripherals request the DMA controller for transfer. At the end of the programmed number of DMA transfers for a channel, the DMA controller generates an interrupt corresponding to that channel. This interrupt indicates the completion of the DMA transfer. DMA PRIORITY The number and priority level determines the priority of a channel. Each channel can have two priority levels: default or high. All channels at high priority level have higher priority than all channels at default priority level. At the same priority level, a channel with a lower channel number has higher priority than a channel with a higher channel number. The DMA channel priority levels can be changed by writing into the appropriate bit in the DMAPRISET register. CHANNEL CONTROL DATA STRUCTURE Every channel has two control data structures associated with it: primary and alternate. For simple transfer modes, the DMA controller uses either the primary or the alternate data structure. For more complex data transfer modes, such as ping-pong or scatter-gather, the DMA controller uses both the primary and alternate data structures. Each control data structure (primary or alternate) occupies four 32-bit locations in the memory, as shown in Table 71. The entire channel control data structure is shown in Table 72. Table 71. Channel Control Data Structure Offset 0x00 0x04 0x08 0x0C Name SRC_END_PTR DST_END_PTR CHNL_CFG Reserved Description Source end pointer Destination end pointer Control data configuration Reserved Before the controller can perform a DMA transfer, the data structure related to the DMA channel must be programmed at the designated location in system memory, SRAM. • • • The source end pointer memory location contains the end address of the source data. The destination end pointer memory location contains the end address of the destination data. The control data configuration memory location contains the channel configuration control data. The programming determines the source and destination data size, number of transfers, and the number of arbitrations. Table 72. Memory Map of Primary and Alternate DMA Structures Channel Channel 13 … Channel 1 Channel 0 Primary Structures Register Description Offset Address Reserved; set to 0 0x0DC Control 0x0D8 Destination end pointer 0x0D4 Source end pointer 0x0D0 … … Reserved; set to 0 0x01C Control 0x018 Destination end pointer 0x014 Source end pointer 0x010 Reserved; set to 0 0x00C Control 0x008 Destination end pointer 0x004 Source end pointer 0x000 Alternate Structures Register Description Offset Address Reserved; set to 0 0x1DC Control 0x1D8 Destination end pointer 0x1D4 Source end pointer 0x1D0 … … Reserved; set to 0 0x11C Control 0x118 Destination end pointer 0x114 Source end pointer 0x110 Reserved; set to 0 0x10C Control 0x108 Destination end pointer 0x104 Source end pointer 0x100 The user must define DMA structures in their source code, as shown in the examples in the Example Code: Define DMA Structures section. After the structure has been defined, its start address must be assigned to the DMA base address pointer register, DMAPDBPTR. Each register for each DMA channel is then at the offset address, as specified in Table 72, plus the value in the DMAPDBPTR register. Rev. D | Page 59 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Example Code: Define DMA Structures To define DMA structures, use the following code: memset(dmaChanDesc,0x0,sizeof(dmaChanDesc)); // Set up the DMA base address pointer register. uiBasPtr = (unsigned int)&dmaChanDesc; // Set up the DMA base pointer. pADI_DMA->DMACFG = 1; // Enable DMA controller pADI_DMA->DMAPDBPTR = uiBasPtr; CONTROL DATA CONFIGURATION For each DMA transfer, the CHNL_CFG memory location provides the control information for the DMA transfer to the controller. Table 73. Control Data Configuration Bit(s) [31:30] Name DST_INC [29:28] DST_SIZE [27:26] SRC_INC Description Destination address increment. The address increment depends on the source data width as follows: Source Data Width DST_INC Destination Address Increment Byte 00 Byte. 01 Half word. 10 Word. No increment. Address remains set to the value that the DST_END_PTR 11 memory location contains. Half Word 00 Reserved. 01 Half word. 10 Word. No increment. Address remains set to the value that the DST_END_PTR 11 memory location contains. Word 00 Reserved. 01 Reserved. 10 Word. No increment. Address remains set to the value that the DST_END_PTR 11 memory location contains. Size of the destination data. Must match SRC_SIZE. 00: byte. 01: half word. 10: word. 11: reserved. Source address increment. The address increment depends on the source data width as follows: Source Data Width DST_INC Source Address Increment Byte 00 Byte. 01 Half word. 10 Word. No increment. Address remains set to the value that the SRC_END_PTR 11 memory location contains. Half Word 00 Reserved. 01 Half word. 10 Word. No increment. Address remains set to the value that the SRC_END_PTR 11 memory location contains. Word 00 Reserved. 01 Reserved. 10 Word. No increment. Address remains set to the value that the SRC_END_PTR 11 memory location contains. Rev. D | Page 60 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Bit(s) [25:24] Name SRC_SIZE [23:18] [17:14] RESERVED R_POWER [13:4] N_MINUS_1 3 [2:0] RESERVED CYCLE_CTRL UG-868 Description Size of the source data. 00: byte. 01: half word. 10: word. 11: reserved. Undefined. Write as 0. Set these bits to control how many DMA transfers can occur before the controller rearbitrates. Must be set to 0000 for all DMA transfers involving peripherals. Note that the operation of the DMA is indeterminate if a value other than 0000 is programmed in this location for DMA transfers involving peripherals. The number of configured transfers minus 1 for that channel. The 10-bit value indicates the number of DMA transfers (not the total number of bytes) minus one. The possible values are 0x000: 1 DMA transfer. 0x001: 2 DMA transfers. 0x002: 3 DMA transfers. … 0x3FF: 1024 DMA transfers. Undefined. Write as 0. The transfer types of the DMA cycle. 000: stop (invalid). 001: basic. 010: autorequest. 011: ping-pong. 100: memory scatter-gather primary. 101: memory scatter-gather alternate. 110: peripheral scatter-gather primary. 111: peripheral scatter-gather alternate. During the DMA transfer process, but before arbitration, CHNL_CFG is written back to system memory with the N_MINUS_1 field changed to reflect the number of transfers yet to be completed. When the DMA cycle is complete, the CYCLE_CTRL bits are made invalid to indicate the completion of the transfer. DMA TRANSFER TYPES (CHNL_CFG[2:0]) The DMA controller supports five types of DMA transfers. The various types are selected by programming the appropriate values into the CYCLE_CTRL bits (Bits[2:0]) in the CHNL_CFG location of the control data structure. Invalid (CHNL_CFG[2:0] = 000) CHNL_CFG[2:0] = 000 means no DMA transfer is enabled for the channel. After the controller completes a DMA cycle, it sets the cycle type to invalid to prevent it from repeating the same DMA cycle. Basic (CHNL_ CFG[2:0] = 001) In basic mode, the controller can be configured to use either the primary or alternate data structure. The peripheral must present a request for every data transfer. After the channel is enabled, when the controller receives a request, it performs the following operations: 1. 2. 3. The controller performs a transfer. If the number of transfers remaining is zero, the flow continues at Step 3. The controller arbitrates. a. If a higher priority channel is requesting service, the controller services that channel. b. If the peripheral or software signals a request to the controller, the controller continues at Step 1. At the end of the transfer, the controller generates the corresponding DMA channel interrupt in the NVIC Rev. D | Page 61 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Autorequest (CHNL_CFG[2:0] = 010) When the controller operates in autorequest mode, it is only necessary for the controller to receive a single request to enable it to complete the entire DMA cycle. This allows a large data transfer to occur without significantly increasing the latency for servicing higher priority requests or requiring multiple requests from the processor or peripheral. This mode is very useful for a memory to memory copy application. Autorequest is not suitable for peripheral use, except for the ADC sequencer mode, where a number of peripheral operations need to be completed. In this mode, the controller can be configured to use either the primary or alternate data structure. After the channel is enabled, when the controller receives a request, it performs the following operations: 1. 2. 3. The controller performs min(2R_POWER, N) transfers for the channel, where R_POWER is Bits[17:14] of the control data configuration register, and N is the number of transfers. If the number of transfers remaining is zero, the flow continues at Step 3. A request for the channel is automatically generated. The controller arbitrates. If the channel has the highest priority, the DMA cycle continues at Step 1. At the end of the transfer, the controller generates an interrupt for the corresponding DMA channel. Ping-Pong (CHNL_CFG[2:0] = 011) In ping-pong mode, the controller performs a DMA cycle using one of the data structures and then performs a DMA cycle using the other data structure. The controller continues to alternate between using the primary and alternate data structures until it reads a data structure that is invalid, or the host processor disables the channel. This mode is useful for transferring data from peripheral to memory using different buffers in the memory. In a typical application, the host must configure both primary and alternate data structures before starting the transfer. As the transfer progresses, the host can subsequently configure primary or alternate control data structures in the interrupt service routine when the corresponding transfer ends. The DMA controller interrupts the processor after the completion of transfers associated with each control data structure. The individual transfers using either the primary or alternate control data structure work the same as a basic DMA transfer. Memory Scatter-Gather (CHNL_CFG[2:0] = 100 or 101) In memory scatter-gather mode, the controller must be configured to use both the primary and alternate data structures. The controller uses the primary data structure to program the control configuration for the alternate data structure. The alternate data structure is used for actual data transfers, which are similar to an autorequest DMA transfer. The controller arbitrates after every primary transfer. The controller needs only one request to complete the entire transfer. This mode is used when performing multiple memory to memory copy tasks. The processor can configure all of the tasks simultaneously and does not need to intervene in between each task. The controller generates the corresponding DMA channel interrupt in the NVIC when the entire scatter-gather transaction completes using a basic cycle. In this mode, the controller receives an initial request and then performs four DMA transfers using the primary data structure to program the control structure of the alternate data structure. After this transfer completes, the controller starts a DMA cycle using the alternate data structure. After the cycle completes, the controller performs another four DMA transfers using the primary data structure. The controller continues to alternate between using the primary and alternate data structures until the processor configures the alternate data structure for a basic cycle, or the DMA reads an invalid data structure. Table 74 lists the fields of the CHNL_CFG memory location for the primary data structure, which must be programmed with constant values for the memory scatter-gather mode. Table 74. CHNL_CFG for Primary Data Structure in Memory Scatter-Gather Mode, CHNL_CFG[2:0] = 100 Bit(s) [31:30] [29:28] [27:26] [25:24] [23:18] [17:14] [13: 4] 3 [2:0] Name DST_INC DST_SIZE SRC_INC SRC_SIZE RESERVED R_POWER N_MINUS_1 RESERVED CYCLE_CTRL Description 10: configures the controller to use word increments for the address. 10: configures the controller to use word transfers. 10: configures the controller to use word increments for the address. 10: configures the controller to use word transfers. Undefined. Write as 0. 0010: indicates that the DMA controller is to perform four transfers. Configures the controller to perform N DMA transfers, where N is a multiple of 4. Undefined. Write as 0. 100: configures the controller to perform a memory scatter-gather DMA cycle. Rev. D | Page 62 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Peripheral Scatter-Gather (CHNL_CFG[2:0] = 110 or 111) In peripheral scatter-gather mode, the controller must be configured to use both the primary and alternate data structure. The controller uses the primary data structure to program the control structure of the alternate data structure. The alternate data structure is used for actual data transfers, and each transfer takes place using the alternate data structure with a basic DMA transfer. The controller does not arbitrate after every primary transfer. This mode is used when there are multiple peripheral-to-memory DMA tasks to be performed. The Cortex-M3 can configure all of the tasks simultaneously and does not need to intervene in between each task. This mode is very similar to memory scatter-gather mode except for arbitration and request requirements. The controller generates the corresponding DMA channel interrupt in the NVIC when the entire scatter-gather transaction completes using a basic cycle. In peripheral scatter-gather mode, the controller receives an initial request from a peripheral and then performs four DMA transfers using the primary data structure to program the alternate control data structure. The controller then immediately starts a DMA cycle using the alternate data structure without rearbitrating. After this cycle completes, the controller rearbitrates, and if it receives a request from the peripheral that has the highest priority, it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure without rearbitrating. The controller continues to alternate between using the primary and alternate data structures until the processor configures the alternate data structure for a basic cycle, or the DMA reads an invalid data structure. Table 75 lists the fields of the CHNL_CFG memory location for the primary data structure, which must be programmed with constant values for the peripheral scatter-gather mode. Table 75. CHNL_CFG for Primary Data Structure in Peripheral Scatter-Gather Mode, CHNL_CFG[2:0] = 110 Bit(s) [31:30] [29:28] [27:26] [25:24] [23:18] [17:14] [13: 4] 3 [2:0] Name DST_INC DST_SIZE SRC_INC SRC_SIZE RESERVED R_POWER N_MINUS_1 RESERVED CYCLE_CTRL Description 10: configures the controller to use word increments for the address. 10: configures the controller to use word transfers. 10: configures the controller to use word increments for the address. 10: configures the controller to use word transfers. Undefined. Write as 0. 0010: indicates that the DMA controller performed four transfers without rearbitration. Configures the controller to perform N DMA transfers, where N is a multiple of 4. Undefined. Write as 0. 110: configures the controller to perform a memory scatter-gather DMA cycle. ADDRESS CALCULATION The DMA controller calculates the source read address based on the content of SRC_END_PTR, the source address increment setting in CHNL_CFG, and the current value of N_MINUS_1 (CHNL_CFG[13:4]). Similarly, the destination write address is calculated based on the content of DST_END_PTR, the destination address increment setting in CHNL_CFG, and the current value of N_MINUS_1 (CHNL_CFG[13:4]). Source Read Address = SRC_END_PTR − (N_MINUS_1 MDCON = 0x0006; pADI_MDIO->MDPHY = 0x0700; sta = pADI_MDIO->MDSTA; //read the MDSTA register to clear any interrupts pADI_MDIO->MDIEN = 0x000F; NVIC_ClearPendingIRQ(MDIO_IRQn); //clear any pending interrupts in the Cortex REGISTER SUMMARY: MDIO INTERFACE (MDIO) Names and short descriptions of bits refer to the active state represented by a high (1) level, unless explicitly enumerated. Table 291. MDIO Register Summary Address 0x40005C00 0x40005C04 0x40005C08 0x40005C0C 0x40005C10 0x40005C14 0x40005C18 0x40005C1C 0x40005C20 Name MDCON MDFRM MDRXD MDADR MDTXD MDPHY MDSTA MDIEN MDPIN Description MDIO block control MDIO received frame control information MDIO received data MDIO received address MDIO data for transmission MDIO PHYADDR software values and selection and DEVADD MDIO progress signaling through frame MDIO interrupt enables MDIO read PHYADDR pins Reset 0x0000 0x0000 0x000X 0x000X 0x0000 0x0400 0x0000 0x0000 0x0000 Access RW R R R RW RW RW RW RW Reset 0x0 0x0 Access R RW 0x0 RW 0x0 W REGISTER DETAILS: MDIO MDIO Block Control Register Address: 0x40005C00, Reset: 0x0000, Name: MDCON Control for MDIO block. Table 292. Bit Descriptions for MDCON Bits [15:3] 2 Bit Name RESERVED MD_DRV 1 MD_PHY 0 MD_RST Description Reserved. 0: MDIO drive open-drain. 1: MDIO drive push-pull. 0: MDIO PHY uses 5 bits. 1: MDIO PHY uses 3 bits. Unused PHY bits are ignored. Write 1 to reset MDIO block. Hardware immediately clears MD_RST again. Rev. D | Page 183 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual MDIO Received Frame Control Information Register Address: 0x40005C04, Reset: 0x0000, Name: MDFRM Contains control information of last frame received. Table 293. Bit Descriptions for MDFRM Bits [15:12] [11:7] [6:2] [1:0] Bit Name RESERVED MD_DEV MD_PHY MD_OP Description Reserved Received DEVADD Received PHYADR Received OP 00: address frame 01: write frame 10: post read increment address frame 11: read frame Reset 0x0 0x0 0x0 0x0 Access R R R R Reset 0xx Access R MDIO Received Data Register Address: 0x40005C08, Reset: 0x000X, Name: MDRXD Data received from last write frame. Table 294. Bit Descriptions for MDRXD Bits [15:0] Bit Name MD_RXD Description Received data MDIO Received Address Register Address: 0x40005C0C, Reset: 0x000X, Name: MDADR Data received from last address frame. Table 295. Bit Descriptions for MDADR Bits [15:0] Bit Name MD_ADR Description Received address Reset 0xx Access R MDIO Data for Transmission Register Address: 0x40005C10, Reset: 0x0000, Name: MDTXD Data to be transmitted by next data frame. Table 296. Bit Descriptions for MDTXD Bits [15:0] Bit Name MD_TXD Description Data that is transmitted by the next read or post read increment address frame. Before a read frame, the master sends an address frame to specify which data is to be read. After this address frame, the user software must place this requested data into MD_TXD before it is required by the read frame. The time available is at least 45 MDIO clock cycles being a minimum of the read frame preamble and up to 3 cycles before TA, which is equivalent to 900 CPU clock cycles. Reset 0x0000 Access RW Reset 0x0 0x1 0x0 Access R RW RW 0x0 RW MDIO PHYADDR Software Values and Selection and DEVADD Register Address: 0x40005C14, Reset: 0x0400, Name: MDPHY Sets expected values for control part of frame. Table 297. Bit Descriptions for MDPHY Bits 15 [14:10] [9:5] Bit Name RESERVED MD_DEVADD MD_PHYSEL [4:0] MD_PHYSW Description Reserved. Expected DEVADD. Normally 01. Selects expected PHYADR bits. For each of the 5 bits: 0: sets expected PHYADR.x = PRTADRx pin. 1: sets expected PHYADR.x = MD_PHYSW.x. Software provided PHYADR bits. Chosen according to corresponding MD_PHYSEL bits. Rev. D | Page 184 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 MDIO Progress Signaling Through Frame Register Address: 0x40005C18, Reset: 0x0000, Name: MDSTA Indicates progress through frame. Table 298. Bit Descriptions for MDSTA Bits [15:8] 7 6 5 4 3 Bit Name RESERVED MD_PHYN MD_PHYM MD_DEVN MD_DEVM MD_RDF 2 MD_INCF 1 0 MD_ADRF MD_WRF Description Reserved. Set at end of PHYADR if PHYADR nonmatching. Cleared by reading the MDSTA register. Set at end of PHYADR if PHYADR matching. Cleared by reading the MDSTA register. Set at end of DEVADD if DEVADD nonmatching. Cleared by reading the MDSTA register. Set at end of DEVADD if DEVADD matching. Cleared by reading the MDSTA register. Set at end of read frame if DEVADD and PHYADR are matching. Cleared by reading the MDSTA register. Set at end of post read increment address frame if DEVADD and PHYADR are matching. Cleared by reading MDSTA. Set at end of address frame if DEVADD and PHYADR are matching. Cleared by reading the MDSTA register. Set at end of write frame if DEVADD and PHYADR are matching. Cleared by reading the MDSTA register. Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R RC RC RC RC RC 0x0 RC 0x0 0x0 RC RC MDIO Interrupt Enables Register Address: 0x40005C1C, Reset: 0x0000, Name: MDIEN Enables interrupts on specified events. Table 299. Bit Descriptions for MDIEN Bits [15:8] 7 6 5 4 3 2 1 0 Bit Name RESERVED MD_PHYNI MD_PHYMI MD_DEVNI MD_DEVMI MD_RDFI MD_INCFI MD_ADRFI MD_WRFI Description Reserved. If set, interrupt is requested when MD_PHYN becomes active. If set, interrupt is requested when MD_PHYM becomes active. If set, interrupt is requested when MD_DEVN becomes active. If set, interrupt is requested when MD_DEVM becomes active. If set, interrupt is requested when MD_RDF becomes active. If set, interrupt is requested when MD_INCF becomes active. If set, interrupt is requested when MD_ADRF becomes active. If set, interrupt is requested when MD_WRF becomes active. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R RW RW RW RW RW RW RW RW Reset 0x0 0x0 Access R R MDIO Read PHYADDR Pins Register Address: 0x40005C20, Reset: 0x0000, Name: MDPIN Reads the MDIO address pins. Table 300. Bit Descriptions for MDPIN Bits [15:5] [4:0] Bit Name RESERVED MD_PIN Description Reserved Reads PRTADRx pins Rev. D | Page 185 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DOWNLOADER The ADuCM320i and the ADuCM322i allow users to download code to the microcontroller via an I2C interface, while the ADuCM322 allows users to download code to the microcontroller via the MDIO interface. I2C DOWNLOADER (ADUCM320i/ADUCM322i ONLY) The ADuCM320i and ADuCM322i contain firmware that is inaccessible to the user but runs after every reset to set up the device and to allow programming of the device via the I2C interface on the P0.4 and P0.5 pins. The mechanism to enter the downloader and the protocol used are described in the AN-806 Application Note, Flash Programming via I2C—Protocol Type 5. MDIO DOWNLOADER (ADUCM322 ONLY) For MDIO applications, the system memory is separated into two flash blocks, as shown in Figure 40. FLASH BLOCK 1 ACTIVE (FEECON1[3] = 1) FLASH BLOCK 0 ACTIVE (FEECON1[3] = 0) 0x3FFFF 0x1FFFF RESERVED1 RESERVED1 0x3FFE8 0x3FFFF FLASH 1 ACTIVE NVR DATA 8kB (IMAGE A) 0x3E000 FLASH 1 NOT USED KEY2' (K2B1) 0x20000 NOT USED KEY1' (K1B1) 0x1FFE8 0x1FFFF 0x3DFE8 0x3DFE0 0x0 INACTIVE NVR DATA 8kB (IMAGE A) KEY2 (K2B1) 0x1DFE8 NOT USED KEY1 (K1B1) 0x1DFE0 ACTIVE PROGRAM 120kB (IMAGE B) INACTIVE PROGRAM 120kB (IMAGE B) 0x20000 0x0 0x3FFFF 0x1FFFF RESERVED1 RESERVED1 0x3FFE8 0x1FFE8 0x1FFFF FLASH 0 INACTIVE NVR DATA 8kB (IMAGE B) 0x3FFFF 0x1E000 FLASH 0 NOT USED KEY2 (K2B0) NOT USED KEY1 (K1B0) 0x0 0x1DFE8 0x1DFE0 0x20000 ACTIVE NVR DATA 8kB (IMAGE B) 0x3E000 NOT USED KEY2' (K2B0) 0x3DFE8 NOT USED KEY1' (K1B0) 0x3DFE0 ACTIVE PROGRAM 120kB (IMAGE B) ACTIVE PROGRAM 120kB (IMAGE A) 0x0 0x20000 THE FLASH CONTROLLER SECTION FOR MORE INFORMATION ABOUT RESERVED LOCATIONS. 13437-136 1SEE 0x1E000 NOT USED NOTES 1. ADuCM322 ONLY. Figure 40. Memory Maps for MDIO Block Switching (ADuCM322 Only) Rev. D | Page 186 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 When using the kernel flash block swapping feature, the stack pointer may not have the correct value at the start of user code; therefore, it is important that the first instructions in the firmware loads the stack pointer with the value stored at Address 0x0. The following code is an example of these first instructions in µVision. Reset_Handler PROC EXPORT MOVS Reset_Handler IMPORT SystemInit IMPORT __main [WEAK] R0, #0x0 // Store value 0x0 in R0 LDR R13, [R0] //Load the stack pointer (R13) with the value at address 0x0 LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP Flash Block Partitioning In the MDIO dual program image configuration, Program Image A in Flash 0 and the NVR Data Block A in Flash 1 should be used together or, alternatively, Program Image B in Flash 1 and the NVR Data Block B in Flash 0 should be used together. Because the data and code are in different flash blocks, the code can continue executing in the active program image while flash operations are performed on the associated nonvolatile RAM (NVR) data flash block. Only one combination can be used at a time, which is known as the active combination. The other combination can be updated with new code if required, and by means of the block switching described, code can be made to execute from the new code. In unswitched mode, Flash Block 0 is mapped from 0 to 0x1FFFF, and Flash Block 1 is mapped from 0x20000 to 0x3FFFF. In switched mode, Flash Block 1 is mapped from 0 to 0x1FFFF, and Flash Block 0 is mapped from 0x20000 to 0x3FFFF. Build code to run in the 0 to 0x1FFFF address range and only run code in this range. A mechanism is provided in the kernel to run from the appropriate flash block after any reset, which is described in the subsequent subsections of the Management Data Input/Output (MDIO) section. For additional information, see Figure 41, Table 301, and Table 302. Program Image The choice of which blocks are used is determined by the kernel and based on keys placed at the top of the two 120 kB program image blocks. The six modes of operation follow: • • • • • • Debug mode Downloader mode (no valid code) Normal running from Program Image A (Flash 0) Trial run from Program Image A (Flash 0) Normal running from Program Image B (Flash 1) Trial run from Program Image B (Flash 1) Each of these modes can only be entered via a reset. Every reset causes the kernel to run, and the kernel chooses the appropriate mode according to keys in the program images. Each program image contains two keys. For the active program image, Key1 at Address 0x1DFE0 has a numeric value that indicates the update number. The higher the Key1 value, the more recent the update. Key2 at Address 0x1DFE8 manages the trial runs. A value of 0xFFFFFFFF (erased) indicates a new download. When a trial run has passed, this must be indicated by changing the value to 0. Key1’ of the other program image is at 0x3DFE0, and Key2’ of the other program image is at 0x3DFE8. The user program space CRCs can be stored at 0x1DFFC for Flash 0 and at 0x3DFFC for Flash 1. The CRC is not required as part of the block selection mechanism but to increased robustness it is recommended to included it. The user code can check this CRC periodically. Note that the keys are placed just below the 120 kB boundary, which is assumed to be the top of the program space. There is no technical reason why some code cannot be placed above this boundary or why some data cannot be placed below this boundary. Rev. D | Page 187 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual Debug Mode If after a reset the kernel determines that the download pin (P2.3) is high, the kernel enters user code regardless of the keys. This mode is intended for debugging only Choosing the Active Block After any reset, the kernel chooses the active program image. Figure 41 is the flowchart for choosing the active program image. Initially, the kernel assumes that the program image with the larger Key1 is made active. If the associated Key2 is not 0, this code has not passed the trial run and should not yet be used. Instead, the kernel investigates using the other program image. If the Key2’ of the other program image is 0, that program image is chosen. Based on these decisions, the kernel then sets the active program image and exits to the user code. If neither program image has a valid Key2, the kernel enters its own download mode. Trial Run Mode After the user code is entered, the code checks whether a trial run or a normal run should be performed. A trial run is indicated if the active Key1 is less than the Key1’. In a trial run, the old code first checks that the new program image is functioning correctly. The trial run starts in the old program image and performs initial checks, such as CRCs and other checks that the user deems necessary, on the new program image. The trial run can then continue by switching to the new image using Bit 3 (SWAP) of the FEECON1 register. It is recommended that the code that performs the switching be at a fixed location in Flash Page0 and be the same in all revisions. The code following the switching point should include sufficient identical code so that the CPU pipeline plus the flash look ahead buffers contain the expected code after switching. The user must also clear the memory cache to prevent old code from executing after the switch. The trial run should copy all necessary data from the old NVR to the new NVR. After the new flash blocks are correct, the user code must write 0 to Key2’ of the new flash block to mark the block as good. The user code can then initiate normal operation. Alternatively, a software reset can be issued, and the device then enters normal mode in the new program image. A reset may occur during a trial run, for instance, due to power loss or during a watchdog event due to program hanging or a deliberate software reset. In this case, a trial run restarts in the old code, and the trial run code then decides how to proceed. Normal Mode The user code must check whether a trial run or a normal run should be performed. A normal run is indicated if the active Key1 is larger than the other Key1. During normal operation, the MDIO master can send download information to the active user code so that new code is written to the other program image. Such a download must also write the new Key1’ with a value of one more than the active Key1. The new Key2’ must be left erased as 0xFFs. After the download, the device must be reset to allow a trial run to occur. Typical Sequence A typical sequence is shown in Table 301, and a definition of the keys is in Table 302. On a new device, the initial code can be downloaded via serial wire (SW) JTAG if P2.3 is held high during a reset; otherwise, the kernel enters its own downloader because there is no valid key. At the end of the download to Flash 0, Key1 is set to 1, and Key2 is set to 0. After a reset, normal code is run from Flash 0 because its Key1 is greater than Key1’ (0xFFs = −1) and its Key2 is 0. User code can receive MDIO frames instructing it to download code to Flash 1, which results in the new Key2’ being erased and 2 being written to the new Key1’. After a reset, the kernel activates Flash 0 for a trial run on the new code because Key2’ of Flash 1 is 0xFFs. If the trial run passes, the user code sets Key2 to 0 and issues a software reset. After a reset, the kernel selects Flash 1 because its Key1 is still larger than Key1’ and the active Key2 is 0. User code can receive MDIO frames instructing it to download code, including copying the NVR data block to Flash 0, which results in Key2 being erased and 3 being written to Key1. Changeover back to Flash 0 is then similar to the change to Flash 1. Rev. D | Page 188 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 Table 301. Example Block Switching Sequence No. of Software Download Not applicable 1 Key2 of Flash 0 0xFFFFFFFF 0 Key1 of Flash 0 0xFFFFFFFF 1 Key2 of Flash 1 0xFFFFFFFF 0xFFFFFFFF Key1 of Flash 1 0xFFFFFFFF 0xFFFFFFFF 1 0 1 0xFFFFFFFF 0xFFFFFFFF 2 0 1 0xFFFFFFFF 2 2 0 1 0xFFFFFFFF 2 2 2 0 0 1 1 0 0 2 2 3 0xFFFFFFFF 3 0 2 3 0xFFFFFFFF 3 0 2 3 3 0 0 3 3 0 0 2 2 4 0 3 0xFFFFFFFF 4 4 0 3 0xFFFFFFFF 4 4 4 0 0 3 3 0 0 4 4 … … … Table 302. Definition of Keys Key1, 2 K1B0 K1B1 K2B0 K2B1 Key1 Key2 Key1’ Key2’ 0xFFs 1 2 Description Key1 in Flash Block 0 at 0x1DFE0 Key1 in Flash Block 1 at 0x3DFE0 Key2 in Flash Block 0 at 0x1DFE8 Key2 in Flash Block 1 at 0x3DFE8 Key used to identify latest revision in active flash block at 0x1DFE0 Key used for trial runs in active flash block at 0x1DFE8 Key1 for the other flash block at 0x3DFE0 Key2 for the other flash block at 0x3DFE8 0xFFFFFFFFFFFFFFFF Key1, Key2, Key1’, and Key2’ refer to the keys as seen by the user. K1B0, K1B1, K2B0, and K2B1 refer to the keys as seen by the kernel before block switching occurs. Rev. D | Page 189 of 195 Status Initial startup Kernel has downloaded Code1 to Flash 0 Code1 normal execution in Flash 0 Code1 has downloaded Code2 to Flash 1 Code1 starts a trial run on Code2 in Flash 1 Code2 trial run complete Code 2 normal execution in Flash 1 Code2 has downloaded Code3 to Flash 0 Code2 starts trial run on Code3 in Flash 0 Code3 trial mode complete Code3 normal execution in Flash 0 Code3 has downloaded Code4 to Flash 1 Code3 starts a trial run on Code4 in Flash 1 Code 4 trial mode complete Code4 normal execution in Flash 1 … Reset Required? Yes No Yes No Yes No Yes No Yes No Yes No Yes No UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual RESET SWITCH TO FLASH 1 HARDWARE KERNEL CODE Y N P2.3 = HIGH N K1B0 < K1B1 Y Y K2B0 = 0 N Y K2B1 = 0 N K2B1 = 0 N N RUN DOWNLOADER Y K2B0 = 0 Y SWITCH TO FLASH 1 CHANGE TO USER CODE USER CODE Y N KEY1’ > KEY1 TRIAL RUN Y KEY2 = 0 N TRIAL OK N Y ERROR NORMAL RUN WRITE KEY2’ = 0 11176-137 FLASH OTHER BLOCK (KEY2’ = 0xFFs, K1’ = K1+1) NOTES 1. ADuCM322 ONLY. Figure 41. Flowchart for MDIO Memory Block Switching (ADuCM322 Only) Rev. D | Page 190 of 195 ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 HARDWARE DESIGN CONSIDERATIONS TYPICAL SYSTEM CONFIGURATION Figure 42 shows a typical ADuCM320i configuration, Figure 43 shows a typical ADuCM322 configuration, and Figure 44 shows a typical ADuCM320i configuration. Figure 42, Figure 43, and Figure 44 illustrate some of the hardware considerations. Place the four 0.47 µF capacitors on DVDD_1V8, DVDD_2V5, AVDD_REG1, and AVDD_REG2 as close as possible to the pins. VDD1 must either have a separate power supply or be filtered from the other digital supply using an inductor bead and a resistor. The same applies to the AVDD supply. Decoupling capacitors are required between each power and associated ground, as indicated in the ADuCM320i, the ADuCM322, the ADuCM322i data sheets. Place these capacitors as close as possible to the pins and in such a way that the current paths do not interfere with one another. All GNDs must be connected together in as close to a star connection as the layout allows. Rev. D | Page 191 of 195 UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual DVDD VDD1 0.47µF 0.47µF B1 D11 J1 K6 L2 K2 L1 D10 C1 E11 K1 IOVDD1 IOVDD2 IOVDD3 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 VDD1 RESET 10kΩ B2 RESET J2 XTALI H2 XTALO 12pF DGND VDD1 10kΩ PVDD PVDD1 PVDD2 A8 PVDD3 B4 CDAMP0 B8 CDAMP1 P1.0/SIN/ECLKIN/PLAI[4] B9 ADuCM320i AGND2 AGND3 AGND4 PGND AGND1 PGND B6 AVDD_REG1 A6 SWDIO E10 AVDD_REG0 CDAMP2 CDAMP3 P1.1/SOUT/PLACLK1/PLAI[5] B10 ADC_REFN B5 B7 SWCLK E9 ADC_REFP 10nF A9 A4 IREF 10nF P2.3/BM C3 VREF_1V2 10nF PVDD0 AVDD4 10nF A3 AVDD3 12pF L6 G11 F11 A11 K11 L11 F9 F10 J5 K7 L7 H11 AVDD RESET 0.47µF 0.47µF AGND RESET GND SWDIO DGND TX SWCLK RX NC DVDD VDD1 1.6Ω 10µF VIN 0.1µF 10µF SENSE 0.1µF 10kΩ 10µF 0.1µF AGND1 AVDD 1.6Ω VOUT EN 10µF 0.1µF DGND PG AGND AGND GND ADP1741ACPZ +2.5V DGND DGND1 DVDD ADP7102ARDZ-3.3 VIN 0.1µF PVDD VIN VOUT 30kΩ 10µF EN 10kΩ EP GND PGND 10µF ADJ SS PGND PGND 10µF Figure 42. Typical System Configuration for the ADuCM320i Rev. D | Page 192 of 195 13437-138 INTERFACE BOARD CONNECTOR 0.47µF 3.16kΩ 4.7µF ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 VDD1 DVDD 0.47µF 0.47µF D11 J1 K6 L2 K2 L1 D10 C1 E11 K1 IOVDD2 IOVDD3 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 10kΩ B1 IOVDD1 VDD1 RESET B2 RESET 12pF DGND J2 XTALI H2 XTALO A3 RESERVED VDD1 12pF RESERVED NC B8 RESERVED NC B5 RESERVED NC B7 RESERVED VREF_1V2 IREF ADC_REFP ADC_REFN DGND SWDIO E10 AVDD4 DGND B6 P1.1/SOUT/PLACLK1/PLA1[5] B10 AVDD3 A6 SWCLK E9 L6 G11 F11 A11 K11 L11 AGND4 NC B4 P1.0/SIN/ECLKIN/PLAI[4] B9 AGND3 RESERVED AGND2 A8 ADuCM322 AGND1 RESERVED AVDD_REG1 RESERVED F10 J5 K7 L7 H11 AVDD_REG0 A9 A4 AVDD_REG1 10kΩ P2.3/BM C3 F9 AVDD 3.3kΩ 4.7µF 0.47µF 0.47µF AGND RESET RESET GND SWDIO TX DGND SWCLK RX NC VDD1 DVDD 1.6Ω 10µF VIN ADP7102ARDZ-3.3 VIN 0.1µF 10µF SENSE EN DGND DGND1 DVDD 1.6Ω VOUT 10kΩ 0.1µF 10µF 0.1µF 10µF DGND Figure 43. Typical System Configuration for the ADuCM322 Rev. D | Page 193 of 195 AGND1 AVDD 0.1µF PG GND 0.1µF AGND AGND 13437-042 INTERFACE BOARD CONNECTOR 0.47µF UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual VDD1 DVDD 0.47µF 0.47µF D11 J1 K6 L2 K2 L1 D10 C1 E11 K1 IOVDD2 IOVDD3 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 10kΩ B1 IOVDD1 VDD1 RESET B2 RESET 12pF DGND J2 XTALI H2 XTALO A3 RESERVED VDD1 12pF RESERVED NC B8 RESERVED NC B5 RESERVED NC B7 RESERVED VREF_1V2 IREF ADC_REFP ADC_REFN DGND SWDIO E10 AVDD4 DGND B6 P1.1/SOUT/PLACLK1/PLA1[5] B10 AVDD3 A6 SWCLK E9 L6 G11 F11 A11 K11 L11 AGND4 NC B4 P1.0/SIN/ECLKIN/PLAI[4] B9 AGND3 RESERVED AGND2 A8 ADuCM322i AGND1 RESERVED AVDD_REG1 RESERVED F10 J5 K7 L7 H11 AVDD_REG0 A9 A4 AVDD_REG1 10kΩ P2.3/BM C3 F9 AVDD 3.3kΩ 4.7µF 0.47µF 0.47µF AGND RESET RESET GND SWDIO TX DGND SWCLK RX NC VDD1 DVDD 1.6Ω 10µF VIN ADP7102ARDZ-3.3 VIN 0.1µF 10µF SENSE EN DGND DGND1 DVDD 1.6Ω VOUT 10kΩ 0.1µF 10µF 0.1µF 10µF DGND Figure 44. Typical System Configuration for the ADuCM322i Rev. D | Page 194 of 195 AGND1 AVDD 0.1µF PG GND 0.1µF AGND AGND 13437-043 INTERFACE BOARD CONNECTOR 0.47µF ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868 SERIAL WIRE DEBUG INTERFACE VCC 1 2 VCC (OPTIONAL) NYU 3 4 GND NYU 5 6 GND SWDIO 7 8 GND SWCLK 9 10 GND NYU 11 12 GND SWO 13 14 GND RESET 15 16 GND NYU 17 18 GND NYU 19 20 GND 13437-038 The serial wire debug (SWD) interface provides a debug port for pin limited packages. The SWD replaces the 5-pin JTAG port with a clock (SWCLK) and a single bidirectional data pin (SWDIO), providing all the normal JTAG debug and test functionality. SWDIO and SWCLK are overlaid on the TMS and TCK pins on the ARM 20-pin JTAG interface. Figure 45. SWD 20-Pin Connector Pinout Table 303. SWD Connections Signal SWDIO SWO SWCLK VCC GND RESET Connect To Data input/output pin. Use a 100 kΩ pull-up resistor to VCC from SWDIO. No connect. Clock pin. Use a 100 kΩ pull-up resistor to VCC from SWCLK. Positive supply voltage; power supply for JTAG interface drivers. Digital ground. No connect. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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