>10 W, 0.01 GHz to 2.8 GHz,
GaN Power Amplifier
HMC8500
Data Sheet
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
HMC8500
24
23
22
21
20
19
18
17
GND
NIC
NIC
RFOUT/VDD
RFOUT/VDD
NIC
NIC
GND
PACKAGE
BASE
14694-001
Extended battery operation for public mobile radios
Power amplifier stage for wireless infrastructures
Test and measurement equipment
Commercial and military radars
General-purpose transmitter amplification
GND
NIC
NIC
RFIN/VGG
RFIN/VGG
NIC
NIC
GND
9
10
11
12
13
14
15
16
APPLICATIONS
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
FUNCTIONAL BLOCK DIAGRAM
High small signal gain: 16.0 dB
High PAE: 55% typical
Instantaneous bandwidth: 0.01 GHz to 2.8 GHz
Supply voltage: VDD = 28 V at 100 mA
Internal prematching
Simple and compact external tuning for optimal
performance
32-lead, 5 mm × 5 mm, LFCSP package
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
FEATURES
Figure 1.
GENERAL DESCRIPTION
The HMC8500 is a gallium nitride (GaN), broadband power
amplifier delivering >10 W with up to 55% power added
efficiency (PAE) across an instantaneous bandwidth of 0.01
GHz to 2.8 GHz, and with a ±1.0 dB typical gain flatness.
The HMC8500 is ideal for pulsed or continuous wave (CW)
applications, such as wireless infrastructure, radars, public
mobile radios, and general-purpose amplification.
Rev. A
The HMC8500 amplifier is externally tuned using low cost,
surface-mount components and is available in a compact
LFCSP package.
Note that throughout this data sheet, multifunction pins, such
as RFIN/VGG, are referred to either by the entire pin name or by
a single function of the pin, for example, RFIN, when only that
function is relevant.
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Tel: 781.329.4700 ©2017–2018 Analog Devices, Inc. All rights reserved.
Technical Support
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HMC8500
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................6
Functional Block Diagram .............................................................. 1
Interface Schematics .....................................................................6
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................7
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 13
Specifications..................................................................................... 3
Applications Information .............................................................. 14
Electrical Specifications ............................................................... 3
Evaluation Board ............................................................................ 15
Total Supply Current by VDD ....................................................... 4
Outline Dimensions ....................................................................... 16
Absolute Maximum Ratings............................................................ 5
Ordering Guide .......................................................................... 16
Thermal Resistance ...................................................................... 5
REVISION HISTORY
8/2018—Rev. 0 to Rev. A
Changed CG-32-1 to CG-32-2 .................................... Throughout
Changes to Figure 5 .......................................................................... 7
Updated Outline Dimensions ....................................................... 16
Changes to the Ordering Guide.................................................... 16
1/2017—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
HMC8500
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.01 GHz to 0.8 GHz.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
Output
POWER
Output Power at 30 dBm Input Power
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
TOTAL SUPPLY CURRENT
Symbol
Min
0.01
Typ
18.0
20.0
±1.5
dB
dB
7
7
dB
dB
40
55
48
5
100
dBm
%
dBm
dB
mA
POUT
PAE
IP3
NF
IDD
Max
0.8
Unit
GHz
Test Conditions/Comments
Measurement taken at POUT/tone = 30 dBm
Adjust the gate bias control voltage (VGG) between
−8 V and 0 V to achieve IDD = 100 mA typical
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.8 GHz to 1.5 GHz.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
Output
POWER
Output Power at 30 dBm Input Power
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
TOTAL SUPPLY CURRENT
Symbol
POUT
PAE
IP3
NF
IDD
Min
0.8
Typ
Max
1.5
14.0
16.0
±1.0
dB
dB
8
8
dB
dB
40
55
50
4.5
100
dBm
%
dBm
dB
mA
Rev. A | Page 3 of 16
Unit
GHz
Test Conditions/Comments
Measurement taken at POUT/tone = 30 dBm
Adjust the gate bias control voltage (VGG) between
−8 V and 0 V to achieve IDD = 100 mA typical
HMC8500
Data Sheet
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 1.5 GHz to 2.8 GHz.
Table 3.
Parameter
FREQUENCY RANGE
GAIN
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
Output
POWER
Output Power at 30 dBm Input Power
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
TOTAL SUPPLY CURRENT
Symbol
Min
1.5
Typ
12.0
15.0
±0.75
dB
dB
10
10
dB
dB
40
60
47
4.5
100
dBm
%
dBm
dB
mA
POUT
PAE
IP3
NF
IDD
Max
2.8
Unit
GHz
Test Conditions/Comments
Measurement taken at POUT/tone = 30 dBm
Adjust the gate bias control voltage (VGG) between
−8 V and 0 V to achieve IDD = 100 mA typical
TOTAL SUPPLY CURRENT BY VDD
Table 4.
Parameter
SUPPLY CURRENT
VDD = 24 V
VDD = 28 V
VDD = 32 V
Symbol
IDD
Min
Typ
100
100
100
Max
Unit
Test Conditions/Comments
Adjust the gate bias control voltage (VGG) between −8 V and 0 V to achieve
IDD = 100 mA typical
mA
mA
mA
Rev. A | Page 4 of 16
Data Sheet
HMC8500
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Drain Bias Voltage (VDD)
Gate Bias Voltage (VGG)
Radio Frequency (RF) Input Power (RFIN)
Maximum Voltage Standing Wave Ratio
(VSWR)2
Channel Temperature
Maximum Peak Reflow Temperature (MSL3)3
Continuous Power Dissipation, PDISS (TA = 85°C,
Derate 108.6 mW/°C Above 85°C)
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity (Human Body Model)
1
Rating
35 V dc
−8 V to 0 V dc
33 dBm
6:1
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
225°C
260°C
12.5 W
Package Type
CG-32-21
θJC is the junction to case thermal resistance.
Table 6. Thermal Resistance
1
−40°C to +125°C
−40°C to +85°C
Class 1B, passed
500 V
θJC
9.2
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with 36 thermal vias. See JEDEC JESD51.
ESD CAUTION
When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the Absolute Maximum
Rating is listed. For full pin names of multifunction pins, refer to the Pin
Configuration and Function Descriptions section.
2
Restricted by maximum power dissipation.
3
See the Ordering Guide for additional information.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 5 of 16
HMC8500
Data Sheet
32
31
30
29
28
27
26
25
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
HMC8500
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
NIC
NIC
RFOUT/VDD
RFOUT/VDD
NIC
NIC
GND
PACKAGE
BASE
NOTES
1. NO INTERNAL CONNECTION. THESE PINS ARE NOT
CONNECTED INTERNALLY. HOWEVER, ALL DATA
WAS MEASURED WITH THESE PINS CONNECTED
TO RF/DC GROUND EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF/DC GROUND.
14694-002
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
9
10
11
12
13
14
15
16
GND
NIC
NIC
RFIN/VGG
RFIN/VGG
NIC
NIC
GND
Figure 2. Pin Configuration
Table 7. Pad Function Descriptions
Pin No.
1, 8, 9, 16, 17, 24, 25, 32
2, 3, 6, 7, 10 to 15, 18,
19, 22, 23, 26 to 31
4, 5
Mnemonic
GND
NIC
20, 21
RFOUT/VDD
RFIN/VGG
EPAD
Description
Ground. These pins must be connected to RF/dc ground. See Figure 3 for the GND interface schematic.
No Internal Connection. These pins are not connected internally. However, all data was measured
with these pins connected to RF/dc ground externally.
RF Input/Gate Bias Control Voltage. This pin is a multifunction pin. The RFIN/VGG pin is dc-coupled
with internal prematching and requires external matching to 50 Ω, as shown in Figure 41. See
Figure 4 for the RFIN/VGG interface schematic.
RF Output/Drain Bias Voltage. This is a multifunction pin. The RFOUT/VDD pin is dc-coupled and requires
external matching to 50 Ω, as shown in Figure 41. See Figure 4 for the RFOUT/VDD interface schematic.
Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
RFIN/VGG
Figure 3. GND Interface Schematic
14694-004
14694-003
RFOUT/VDD
GND
Figure 4. RFIN/VGG and RFOUT/VDD Interface Schematic
Rev. A | Page 6 of 16
Data Sheet
HMC8500
25
20
23
15
21
10
19
GAIN (dB)
25
5
0
–5
–10
17
15
11
S11
S21
S22
0
0.5
9
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (GHz)
7
–6
–8
–10
2.5
3.0
–4
–6
–8
1.0
1.5
2.0
2.5
3.0
–12
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
14694-009
0.5
14694-006
0
Figure 6. Input Return Loss vs. Frequency at Various Temperatures
Figure 9. Output Return Loss vs. Frequency at Various Temperatures
28
26
26
24
24
22
22
20
20
GAIN (dB)
28
18
16
50mA
100mA
150mA
200mA
18
16
14
14
12
12
24V
28V
32V
0
0.5
10
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
3.0
Figure 7. Gain vs. Frequency at Various Supply Voltages
8
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
Figure 10. Gain vs. Frequency at Various Supply Currents
Rev. A | Page 7 of 16
3.0
14694-010
10
14694-007
GAIN (dB)
2.0
–10
FREQUENCY (GHz)
8
1.5
+85°C
+25°C
–40°C
–2
OUTPUT RETURN LOSS (dB)
INPUT RETURN LOSS (dB)
0
–4
–12
1.0
Figure 8. Gain vs. Frequency at Various Temperatures
+85°C
+25°C
–40°C
–2
0.5
FREQUENCY (GHz)
Figure 5. Gain and Return Loss vs. Frequency
0
0
14694-008
–15
–20
+85°C
+25°C
–40°C
13
14694-005
GAIN AND RETURN LOSS (dB)
TYPICAL PERFORMANCE CHARACTERISTICS
Data Sheet
45
45
43
43
41
41
39
39
37
37
P4dB (dB)
35
33
31
29
32V
28V
24V
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 11. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Supply Voltages
45
54
48
37
46
IP3 (dBm)
50
39
33
40
38
27
36
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
34
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Figure 15. Output Third-Order Intercept (IP3) vs. Frequency at
Various Temperatures, POUT/Tone = 30 dBm
56
54
54
52
50
52
48
50
48
IP3 (dB)
IP3 (dBm)
2.5
FREQUENCY (GHz)
Figure 12. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Temperatures
46
44
46
44
42
40
42
38
32V
28V
24V
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
50mA
100mA
150mA
200mA
36
3.0
34
14694-013
40
38
2.0
42
29
0.5
1.5
44
31
0
1.0
+85°C
+25°C
–40°C
52
35
0.5
Figure 14. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Supply Currents
41
25
0
FREQUENCY (GHz)
14694-012
P4dB (dBm)
25
+85°C
+25°C
–40°C
43
50mA
100mA
150mA
200mA
27
14694-011
27
14694-015
29
25
33
14694-014
31
35
Figure 13. Output Third-Order Intercept (IP3) vs. Frequency at Various Supply
Voltages, POUT/Tone = 30 dBm
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
14694-016
P4dB (dBm)
HMC8500
Figure 16. Output Third-Order Intercept (IP3) vs. Frequency at Various Supply
Currents, POUT/Tone = 30 dB
Rev. A | Page 8 of 16
Data Sheet
HMC8500
65
70
0.4GHz
1.0GHz
1.6GHz
2.2GHz
2.8GHz
60
55
60
55
IMD3 (dBc)
45
40
50
45
40
35
30
12
14
16
18
20
22
24
26
28
30
32
POUT/TONE (dBm)
25
10
14694-017
25
10
0
45
40
35
24
26
28
30
32
–20
–30
–40
12
14
16
18
20
22
24
26
28
30
32
POUT/TONE (dBm)
–60
14694-018
25
10
500
40
400
30
300
20
200
10
100
2
4
6
POUT (dBm), GAIN (dB), PAE (%)
600
50
8
10
12
14
16
18
20
22
24
26
28
2.0
2.5
3.0
3.5
900
POUT
GAIN
PAE
IDD
80
700
0
INPUT POWER (dBm)
Figure 19. Power Output (POUT), Gain, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 0.5 GHz
70
800
700
60
600
50
500
40
400
30
300
20
200
10
100
0
14694-019
60
1.5
90
IDD (mA)
70
1.0
Figure 21. Reverse Isolation vs. Frequency at Various Temperatures
800
POUT
GAIN
PAE
IDD
0.5
FREQUENCY (GHz)
Figure 18. Output Third-Order Intermodulation (IMD3) vs. POUT/Tone
at VDD = 28 V
80
0
14694-021
–50
30
POUT (dBm), GAIN (dB), PAE (%)
22
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
0
INPUT POWER (dBm)
Figure 22. Power Output (POUT), Gain, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 1 GHz
Rev. A | Page 9 of 16
14694-022
IMD3 (dBc)
50
0
20
+85°C
+25°C
–40°C
–10
REVERSE ISOLATION (dB)
55
18
Figure 20. Output Third-Order Intermodulation (IMD3) vs. POUT/Tone
at VDD = 32 V
0.4GHz
1.0GHz
1.6GHz
2.2GHz
2.8GHz
60
16
POUT/TONE (dBm)
Figure 17. Output Third-Order Intermodulation (IMD3) vs. POUT/Tone
at VDD = 24 V
65
14
12
14694-020
30
IDD (mA)
IMD3 (dBc)
50
35
0
0.4GHz
1.0GHz
1.6GHz
2.2GHz
2.8GHz
65
HMC8500
Data Sheet
500
40
400
30
300
20
200
10
100
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
0
INPUT POWER (dBm)
40
600
30
450
20
300
10
150
0
2
42
700
40
600
SUPPLY CURRENT (mA)
800
38
36
34
32
22dBm
24dBm
26dBm
28dBm
30dBm
28
0
0.5
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
200
22dBm
24dBm
26dBm
28dBm
30dBm
40
40
OUTPUT POWER (dBm)
42
38
36
34
32
+85°C AT 28dBm
+25°C AT 28dBm
–40°C AT 28dBm
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
38
36
34
32
+85°C AT 30dBm
+25°C AT 30dBm
–40°C AT 30dBm
30
28
14694-025
1.0
0
Figure 27. Supply Current vs. Frequency at Various Input Powers
42
0.5
0
FREQUENCY (GHz)
44
0
10 12 14 16 18 20 22 24 26 28 30 32
300
44
28
8
400
0
Figure 24. Output Power vs. Frequency at Various Input Powers
30
6
500
100
1.0
4
INPUT POWER (dBm)
44
30
OUTPUT POWER (dBm)
0
Figure 26. Power Output (POUT), Gain, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 2.8 GHz
14694-024
OUTPUT POWER (dBm)
Figure 23. Power Output (POUT), Gain, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 1.8 GHz
750
IDD (mA)
50
50
14694-026
600
900
POUT
GAIN
PAE
IDD
14694-027
60
0
POUT (dBm), GAIN (dB), PAE (%)
700
IDD (mA)
70
800
14694-023
POUT (dBm), GAIN (dB), PAE (%)
80
0
60
900
POUT
GAIN
PAE
IDD
Figure 25. Output Power vs. Frequency at Various Temperatures at 28 dBm
Input Power
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
14694-028
90
Figure 28. Output Power vs. Frequency at Various Temperatures at 30 dBm
Input Power
Rev. A | Page 10 of 16
Data Sheet
HMC8500
30
30
+85°C
+25°C
–40°C
25
SECOND HARMONIC (dBc)
20
15
10
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
Figure 29. Second Harmonic vs. Frequency at Various Temperatures
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
44
42
15
10
5dBm
10dBm
15dBm
20dBm
25dBm
5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
40
38
36
34
32
2.2
FREQUENCY (GHz)
Figure 30. Second Harmonic vs. Frequency at Various Input Power Levels
28
42
40
40
OUTPUT POWER (dBm)
42
36
34
32
32V AT 30dBm
28V AT 30dBm
24V AT 30dBm
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
Figure 31. Output Power vs. Frequency at Various Supply Voltages at 30 dBm
Input Power
1.0
1.5
2.0
2.5
3.0
38
36
34
32
50mA AT 28dBm
100mA AT 28dBm
150mA AT 28dBm
200mA AT 28dBm
30
28
14694-031
0
0.5
Figure 33. Output Power vs. Frequency at Various Supply Voltages at 28 dBm
Input Power
44
38
0
FREQUENCY (GHz)
44
30
32V AT 28dBm
28V AT 28dBm
24V AT 28dBm
30
14694-033
OUTPUT POWER (dBm)
20
14694-030
SECOND HARMONIC (dBc)
0.2
Figure 32. Second Harmonic vs. Frequency at Various Supply Voltages
25
28
0
FREQUENCY (GHz)
30
OUTPUT POWER (dBm)
10
14694-032
0.2
14694-029
0
FREQUENCY (GHz)
0
15
5
5
0
20
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
14694-034
SECOND HARMONIC (dBc)
25
32V
28V
24V
Figure 34. Output Power vs. Frequency at Various Supply Currents at 28 dBm
Input Power
Rev. A | Page 11 of 16
HMC8500
Data Sheet
10
9
+85°C
+25°C
–40°C
9
8
7
7
NOISE FIGURE (dB)
6
5
4
3
1.0
1.5
2.0
2.5
3.0
0
0
0.5
1.0
1.5
2.0
2.5
9
0.1GHz
0.5GHz
1.0GHz
1.8GHz
2.8GHz
50mA
100mA
150mA
200mA
8
7
NOISE FIGURE (dB)
10
3.0
Figure 38. Noise Figure vs. Frequency at Various Supply Voltages
12
8
6
4
6
5
4
3
2
2
1
5
10
15
20
25
30
INPUT POWER (dBm)
0
14694-036
0
42
GATE CURRENT (mA)
40
34
32
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
14694-037
50mA AT 30dBm
100mA AT 30dBm
150mA AT 30dBm
200mA AT 30dBm
30
1.0
1.5
2.0
2.5
3.0
Figure 39. Noise Figure vs. Frequency at Various Supply Currents
44
36
0.5
FREQUENCY (GHz)
Figure 36. Power Dissipation vs. Input Power at Various Frequencies,
TA = 85°C
38
0
14694-039
POWER DISSIPATION (W)
32V
28V
24V
FREQUENCY (GHz)
Figure 35. Noise Figure vs. Frequency at Various Temperatures
OUTPUT POWER (dBm)
3
14694-038
0.5
14694-035
0
FREQUENCY (GHz)
28
4
1
1
0
5
2
2
0
6
Figure 37. Output Power vs. Frequency at Various Supply Currents at 30 dBm
Input Power
Rev. A | Page 12 of 16
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
+85°C
+25°C
–40°C
0
5
10
15
20
25
30
35
INPUT POWER (dBm)
Figure 40. Gate Current vs. Input Current at Various Temperatures
14694-040
NOISE FIGURE (dB)
8
Data Sheet
HMC8500
THEORY OF OPERATION
The HMC8500 is a >10 W, gallium nitride (GaN), power amplifier
that consists of a single gain stage that effectively operates like a
single field effect transistor (FET). The device is internally
prematched so that simple, external matching networks at the
RF input and RF output ports optimize the performance across
the entire operating frequency range. The recommended dc bias
conditions place the device in deep Class AB operation, resulting
in high saturated output power (41 dBm typical) at improved
levels of power efficiency (55% typical).
Rev. A | Page 13 of 16
HMC8500
Data Sheet
APPLICATIONS INFORMATION
The recommended power-down bias sequence follows:
The drain bias voltage is applied through the RFOUT/VDD pin,
and the gate bias voltage is applied through the RFIN/VGG pin.
For operation of a single application circuit across the entire
frequency range, it is recommended to use the external matching
components specified in the typical application circuit (L1, C1, C8,
C11, and R2) shown in Figure 41. If operation is only required
across a narrower frequency range, performance can be optimized
additionally through the implementation of alternate matching
networks. Capacitive bypassing of VDD and VGG is recommended.
1.
2.
3.
4.
All measurements for this device were taken using the typical
application circuit, configured as shown in the assembly diagram
(see Figure 41). The bias conditions shown in the electrical
specifications table (see Table 1 to Table 3) are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown was taken using the
recommended bias conditions. Operation of the HMC8500
under other bias conditions may provide performance that
differs from that shown in the Typical Performance Characteristics
section.
The recommended power-up bias sequence follows:
5.
Connect the power supply ground to circuit ground.
Set VGG to −8 V to pinch off the drain current.
Set VDD to 28 V (drain current is pinched off).
Adjust VGG more positive (approximately −2.5 V to −3.0 V)
until a quiescent of IDD = 100 mA is obtained.
Apply the RF signal.
The evaluation PCB provides the HMC8500 in its typical
application circuit, allowing easy operation using standard dc
power supplies and 50 Ω RF test equipment.
VGG
1
6
7
25
GND
NIC
NIC
NIC
NIC
NIC
HMC8500
RFOUT/VDD
RFOUT/VDD
NIC
NIC
NIC
NIC
GND
9
GND
8
RFIN/VGG
RFIN/VGG
14 NIC
15
NIC
16
GND
C11
10pF
NIC
NIC
12 NIC
13 NIC
5
VGG
VGG
2
1
4
3
6
8
10
7
12
11
14
13
16
18
17
5
9
GND
24
23
22
21
20
19
19
20
21
23
25
J1
L2
910nH
C3
2.2nF
L1
1.2nH
J3
RFOUT
C1
0.8pF
18
17
NOTES
1. CONNECT NIC PINS TO GND FOR BETTER THERMAL PERFORMANCE.
Figure 41. Typical Application Circuit
Rev. A | Page 14 of 16
VGG
VGG
15
24
26
NIC
NIC
C8
2pF
2
VDD
VDD
22
GND
EPAD
NIC
NIC
4
NIC
32
3
GND
11
C2
2.2nF
2
10
J2
RFIN
R2
10Ω
GND
1
26
C5
2.2nF
27
C4
2.2nF
29
C10
10µF
28
C7
10µF
30
C9
10µF
31
C6
10µF
L4
3.6nH
R1
25Ω
J4
14694-041
1.
2.
3.
4.
Turn off the RF signal.
Set VGG to −8 V to pinch off the drain current.
Set VDD to 0 V.
Set VGG to 0 V.
Data Sheet
HMC8500
EVALUATION BOARD
The HMC8500 evaluation board is a 2-layer board fabricated
using Rogers 4350 and using best practices for high frequency
RF design. The RF input and RF output traces have a 50 Ω
characteristic impedance. The board is attached to a heat sink
using an electrically and thermally conductive epoxy providing
a low thermal and low dc resistance path. Components are
mounted using SN63 solder allowing rework of the surfacemount components without compromising the circuit board to
heat sink attachment.
The evaluation board and populated components are designed
to operate over the ambient temperature range of −40°C to +85°C.
During operation, attach the evaluation board to a temperature
controlled plate to control the temperature of the HMC8500
during operation. For the proper bias sequence, see the
Applications Information section.
14694-042
A fully populated and tested evaluation board, shown in Figure 42,
is available from Analog Devices, Inc., upon request.
Figure 42. Evaluation PCB
Table 8. Bill of Materials for Evaluation PCB EV1HMC8500LP5D
Item
J2, J3
J1
J4
C1
C2, C3, C4, C5
C6, C7, C9, C10
C8
C11
L1
L2
L4
R1
R2
Heat sink
U1
PCB
Description
K connector
Preform surface terminal strip
Surface-mount jumper
0.8 pF capacitor, 0402 package
2.2 nF capacitors, 0603 package
10 μF capacitors, 1210-2 package
2 pF capacitor, 0603 package
10 pF capacitor, 0402 package
1.2 nH inductor, 0402 package
910 nH inductor, 1008CS package
3.6 nH inductor, 0603 package
25 Ω high precision resistor, 0603package
10 Ω resistor, 0402 package
Used for thermal transfer from the HMC8500 amplifier
Amplifier
EV1HMC8500LP5D Circuit board material: Rogers 4350
Rev. A | Page 15 of 16
Manufacturer/Part Number
SRI/25-146-1000-92
SAMTEC/TSM-113-01-L-DV
Components corporation/SJ-1206-01-T
Murata/GRM1555C1HR80BA01D
TDK/C1608C0G1H222J
TDK/ C3225X7S1H106K250AB
Murata/GQM1875C2E2R0BB12
Phycomp (Yageo)/CC0402JRNP09BN100
Panasonic/ ELJ-RF1N2DF
Coilcraft/1008CS-911XGLB
Coilcraft/0603CS-3N6XGLU
Vishay/P0603E25R0BNT
Panasonic/ERJ-2RKF10R0X
Not applicable
Analog Devices/HMC8500
Analog Devices/EV1HMC8500LP5D
HMC8500
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
0.30
0.25
0.20
25
0.50
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
8
17
0.45
0.40
0.35
PKG-005068
1.35
1.25
1.15
0.60 REF SIDE VIEW
9
16
0.40
BOTTOM VIEW
3.50 REF
0.050 MAX
0.035 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
(SEE DETAIL A)
1
24
TOP VIEW
PIN 1
INDICATOR AREA OPTIONS
32
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-15-2018-A
5.10
5.00 SQ
4.90
Figure 43. 32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
5 mm × 5 mm Body and 1.25 mm Package Height
(CG-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
HMC8500LP5DE
HMC8500LP5DETR
EV1HMC8500LP5D
Temperature
−40°C to +85°C
−40°C to +85°C
MSL Rating3
MSL3
MSL3
1
Description4
32-Lead LFCSP_CAV
32-Lead LFCSP_CAV
Evaluation PCB
The HMC8500LP5DE and the HMC8500LP5DETR are LFCSP premolded copper alloy lead frame and RoHS compliant.
When ordering the evaluation board only, reference the model number, EV1HMC8500LP5D.
3
See the Absolute Maximum Ratings section for additional information.
4
The lead finish of the HMC8500LP5DE and the HMC8500LP5DETR is nickel palladium gold (NiPdAu).
2
©2017–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14694-0-8/18(A)
Rev. A | Page 16 of 16
Package Option
CG-32-2
CG-32-2
工商网监
湘ICP备2023018690号
