Preliminary Technical Data
SigmaDSPTM 28-/56-Bit Audio Processor
Evaluation Board
EVAL-AD1940AZ
EVALUATION BOARD OVERVIEW
PACKAGE CONTENTS
This document explains the design and setup of the AD1940
SigmaDSP evaluation board.
The EVAL-AD1940AZ package contains these items:
•
AD1940 evaluation board
The EVAL-AD1940AZ provides a full range of analog and
digital inputs and outputs to and from the AD1940. The
SigmaDSP can connect to analog I/O signals through the
AD1939 codec and AD1974 ADC. Digital I/O connections are
available in both S/PDIF and 3-wire serial data formats. The
DSP is controlled by Analog Devices’ SigmaStudioTM software,
which interfaces to the evaluation boards with a USB cabke via
the EVAL-ADUSB2EBZ add-on board, also known as the USBi.
Power is distributed by a single DC supply, which is regulated to
the necessary voltages on the board. The PCB is an 7” × 5” 4layer design with split analog and digital power and ground
planes on the two inner layers.
•
EVAL-ADUSB2EBZ (USBi) communications adapter
•
6V DC power supply with standard US plug
•
USB cable with mini-B plug
•
Evaluation board/software quick-start guide
•
SigmaStudio software
The AD1940 evaluation board should be used for AD1941
evaluation. There is no AD1941 evaluation board.
OTHER SUPPORTING DOCUMENTATION
AD1940/AD1941 datasheet
AD1939 datasheet
AD1974 datasheet
SigmaStudio Help (included in the software installation)
AN-1006: Using the EVAL-ADUSB2EBZ
FUNCTIONAL BLOCK DIAGRAM
ANALOG INPUTS
EXTERNAL DIGITAL
(I2S/TDM INPUTS)
AD1974
AD1939
ADC
CODEC
INPUT
SIGNAL
ROUTING
JUMPERS
S/PDIF RECEIVER
DSP
PERFORMANCE AUDIO
AD1940
EXTERNAL DIGITAL
(I2S/TDM OUTPUTS)
S/PDIF TRANSMITTER
XXXXX-XXX
POWER SUPPLY
REGULATION
ANALOG OUTPUTS
USBi INTERFACE
(USB TO SPI)
Figure 1. Functional Block Diagram
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
EVAL-AD1940AZ
Preliminary Technical Data
BOARD LAYOUT BLOCK DIAGRAM
ANALOG OUTPUTS
ANALOG INPUTS
POWER
SUPPLY
REGULATION
USBi
CONTROL
INTERFACE
AD1974
ADC
AD1939
CODEC
AD1940
DSP
MASTER
CLOCK
ROUTING
DATA/CLOCK INPUT ROUTING
S/PDIF RECEIVER/TRANSMITTER
EXTERNAL DIGITAL AUDIO (I2S/TDM) HEADERS
Figure 2. Board Layout Block Diagram
Rev. PrA | Page 2 of 30
Preliminary Technical Data
EVAL-AD1940AZ
TABLE OF CONTENTS
Evaluation Board Overview.............................................................1
Clocking the Evaluation Board ...................................................7
Package Contents ..............................................................................1
Input Routing ................................................................................8
Other Supporting Documentation .................................................1
Analog Audio Inputs ....................................................................8
Functional Block Diagram ...............................................................1
External Digital Audio (I2S/TDM) Inputs .................................9
Board Layout Block Diagram ......................................................2
S/PDIF Receiver ............................................................................9
Table of Contents...............................................................................3
Output Routing ...........................................................................10
Revision History................................................................................3
Analog Audio Outputs ...............................................................10
Setting Up the Evaluation Board.....................................................4
External Digital Audio (I2S/TDM) Outputs............................10
SigmaStudio Software Installation..............................................4
S/PDIF Transmitter.....................................................................10
Powering the board.......................................................................4
Example Configurations ................................................................11
Hardware Setup - USBi.................................................................4
Board Schematics ............................................................................15
Connecting the audio cables........................................................4
Board Silkscreen and Parts Placement .........................................25
Switch and Jumper settings..........................................................4
Bill of Materials ...............................................................................26
Your First SigmaStudio Project – EQ and Volume Control ....5
Ordering Guide ...............................................................................29
Using the Evaluation Board .............................................................7
Ordering Guide ...........................................................................29
AD1940 SigmaDSP .......................................................................7
ESD Caution ................................................................................29
Power ..............................................................................................7
Rev. PrA | Page 3 of 30
EVAL-AD1940AZ
Preliminary Technical Data
SETTING UP THE EVALUATION BOARD
SIGMASTUDIO SOFTWARE INSTALLATION
• Check the box for “Include this location in the search.”
1.
Open the provided .zip file and extract the files to
your PC. Alternately, insert the SigmaStudio CD into the
computer’s optical drive and browse the CD to the SigmaStudio
folder.
• The USBi driver is located in C:\Program Files\Analog
Devices Inc\Sigma Studio\USB drivers, click Next.
2.
Install Microsoft .NET Framework ver2.0, if you do
not already have it installed. (Do this by double-clicking
dotnetfx.exe)
• In XP click Continue Anyway if you are prompted saying the
software hasn’t passed Windows Logo testing.
3.
Install SigmaStudio by double-clicking setup.exe, and
following the prompts. A computer restart is not required.
For this example, we will set up the board to have stereo analog
inputs and stereo analog outputs.
POWERING THE BOARD
7.
Connect the audio source to the ANALOG INPUT
CHANNEL 0-1 jack J15 (marked blue in Figure 1) on the top of
the board, using a 1/8” cable.
The board is powered by the included 6V DC power supply,
which should be connected to power jack J14. The power
indicator LEDs D3 and D2 should be lit.
HARDWARE SETUP - USBI
4.
Plug the USBi into the PC’s USB port using the
included mini USB cable. Plug in the USBi into the control port
J2 on the eval board (marked yellow on Figure 1).
5.
USBi.
Connect the USB cable to your computer, and to the
6.
When prompted for drivers:
• Choose “Install from a list or a specific location.”
• If prompted to choose driver, select CyUSB.sys
CONNECTING THE AUDIO CABLES
8.
Connect the ANALOG OUTPUT CHANNEL 0-1 jack
J18 (marked green in Figure 1) to your active speakers or
headphones.
SWITCH AND JUMPER SETTINGS
In order to configure the board for stereo analog in and out,
make sure the switches and jumpers are set as indicated in
Figure 3.
A black rectangle indicates a connected jumper or switch
position.
• Choose “Search for the best driver in these locations.”
Rev. PrA | Page 4 of 30
Preliminary Technical Data
EVAL-AD1940AZ
Figure 3. Evaluation Board Default Setup and Configuration
YOUR FIRST SIGMASTUDIO PROJECT – EQ AND
VOLUME CONTROL
1.
Create a new project. The Hardware Configuration
Tab will be open.
2.
space.
Drag an AD1940 and a USBi cell into the blank white
3.
Connect the USBi cell to the AD1940 cell by clicking
and dragging from the top blue output pin to the green input
pin.
Your screen should now look something like Figure 4.
Figure 4. Hardware Configuration Tab
4.
Click on the Schematic tab at the top of the screen.
5.
In the cell Toolbox expand the IO → Input.
Click&Drag an Input cell to the work area.
6.
Similarly, expand Filters → Second Order → Double
Precision → 2 Ch and click&drag Medium Size Eq
7.
Right click the General (2nd Order) cell labeled Gen
Filter1, click Grow Algorithm → 1. 2 Channel – Double
Rev. PrA | Page 5 of 30
EVAL-AD1940AZ
Preliminary Technical Data
Precision → 4. This creates a five band EQ. Each band’s general
filter settings can be modified by clicking the blue boxes on the
cell.
8.
Expand Volume Controls → Adjustable Gain → Shared
Slider→ Clickless SW Slew and click&drag Single slew
9.
cells
Expand the IO → Output. Click&Drag two Output
10.
Connect all the cells as depicted in Figure 3.
11.
Make sure your board is powered and connected to
the PC. Click the Link-Compile-Download button in
SigmaStudio.
12.
If the project compiled without error you will be in
Ready-Download mode.
Your screen should now look something like Figure 5.
Figure 5. Schematic Tab Full Design
13.
Start your audio source playing, and you should hear
audio. You can now move the volume control and filter sliders
and hear the effect on the output audio in real time.
The online documentation contains more tutorials and detailed
information about every cell available.
Rev. PrA | Page 6 of 30
Preliminary Technical Data
EVAL-AD1940AZ
USING THE EVALUATION BOARD
AD1940 SIGMADSP
The AD1940 is a complete 28-bit, single-chip, multi-channel
audio SigmaDSP™ for equalization, multiband dynamic
processing, delay compensation, speaker compensation, and
image enhancement. These algorithms can be used to compensate for the real world limitations of speakers, amplifiers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1940 is comparable to that
found in high end studio equipment. Most of the processing is
done in full, 56-bit double-precision mode, resulting in very
good, low level signal performance and the absence of limit
cycles or idle tones. The dynamics processor uses a
sophisticated, multiple-breakpoint algorithm often found in
high end broadcast compressors.
The AD1940 is a fully programmable DSP. Easy to use software
allows the user to graphically configure a custom signal
processing flow using blocks such as biquad filters, dyna-mics
processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.
sources, and is used to clock the AD1940 DSP, AD1974 ADCs,
AD1939 ADCs/DACs, External Digital Audio Interfaces, and
the S/PDIF Transmitter.
In most common board configurations, MCLK will be
generated by the on-board AD1939. The AD1939 has an
internal oscillator that drives a 12.288 MHz crystal to produce a
12.288 MHz master clock suitable for 48 kHz, 96 kHz, and
192 kHz processing applications.
For configurations utilizing the S/PDIF receiver, MCLK must be
supplied to the system by the recovered MCLk of the S/PDIF
stream. This recovered MCLK has a frequency 256 times the
sample rate of the S/PDIF data.
A master clock can also be supplied from an external (offboard) source on the digital audio interface headers J22, J23,
and J24. The corresponding MCLK direction switch should be
set to IN or OUT as required.
A description of the jumpers used to route MCLK is given in
Table 1. Examples of common MCLK configurations are given
in the Example Configurations section of this document and in
Figure 6.
Table 1. Master Clock Routing
The AD1940’s digital input and output ports allow a glueless
connection to ADCs and DACs by multiple, 2-channel serial
data streams or TDM data streams. When in TDM mode, the
AD1940/AD1941 can input 8 or 16 channels of serial data, and
can output 8 or 16 channels of serial data. The input and output
port configurations can be individually set. The AD1940 is
controlled by a 4-wire SPI® port.
The EVAL-AD1940AZ should be used to evaluate both the
AD1940 and the AD1941, which is equivalent to the AD1940
except for its I2C control interface.
Component
J1
J3
SW3
SW4
SW5
Function
Select MCLK Source/Destination
Enable AD1939 Crystal Oscillator Circuit
Set direction of MCLK on H1 (J22)
Set direction of MCLK on H2 (J23)
Set direction of MCLK on H3 (J24)
J1
J1
J1
1939
J1
1939
DIR
H1
H1
POWER
The evaluation board uses two ADP3339 low-dropout voltage
reulators to generate the 3.3 V analog and digital supplies. The
current consumption of the board is approximately 500 mA at a
maximum.
The regulators’ inputs should be supplied with +5 to +6 V DC
power on connector J14. The power supply should have a
female cord plug with a 2.1 mm inner diameter, 5.5 mm outer
diameter, and 9.5 mm length. The polarization should be
positive-center.
J3
J3
J3
XTAL
XTAL
EXT
SW3
EXT
SW3
OUT
OUT
AD1939 CRYSTAL
OSCILLATOR MCLK
A lab supply can also be used to power the board, and should be
connected across test points TP48 (VIN+) and TP70 (GND).
J3
RECOVERED
MCLK FROM
S/PDIF RX
SW3
IN
EXTERNAL MCLK
DIGITAL AUDIO
INTERFACE J22
SW3
OUT
AD1939 CRYSTAL
OSCILLATOR MCLK,
OUTPUT ON
DIGITAL AUDIO
INTERFACE J22
Figure 6. Example Master Clock Routing Settings
CLOCKING THE EVALUATION BOARD
The EVAL-AD1940AZ requires a master clock (MCLK) to
operate. The master clock can be supplied from a variety of
The AD1940 must be set up to properly receive MCLK as an
input to its PLL. The board will most often be used with a
12.288 MHz master clock, which is equivalent to 256×Fs, with
Rev. PrA | Page 7 of 30
EVAL-AD1940AZ
Preliminary Technical Data
Fs= 48 kHz. In order to set up the AD1940 PLL in 256×Fs mode,
switch SW1 must be set up as shown in .
AD1940
MODE SELECTION
Proper configuration for inputting all analog audio to the DSP
is shown in Figure 8. Note that it is not necessary to use all
analog audio inputs simultaneously, and the jumpers can be set
in any desired configuration to allow for flexibility in routing a
combination of analog, digital, and S/PDIF inputs.
PLL-CTRL0
PLL-CTRL1
PLL-CTRL2
ADR-SEL
1
SW1
the converted audio data to the AD1940 DSP, it must be routed
appropriately using the audio data routing jumpers.
2
3
4
Figure 7. PLL Mode Selection for 12.288 MHz Master Clock
A description of all possible PLL settings is shown in , with 0
corresponding to setting the switch to the right, a 1
corresponding to setting the switch to the left, and “don’t care”
represented as an “X.”
J4
J5
J6
J7
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
1939_ DATA1
1939_ DATA2
1974_ DATA1
DON’T CARE
Figure 8. Input Routing Jumpers - Analog Configuration
Table 2. PLL Settings
PLL
Mode
64×fs
256×fs
384×fs
512×fs
Bypass
PLL-CTRL0
SW1-1
0
0
X
1
1
PLL-CTRL1
SW1-2
0
1
X
0
1
In an analog input configuration the AD1939 will most
commonly be used as the source for LRCLK and BCLK signals.
To route this signals to the AD1940’s LRCLK_IN and BCLK_IN
pins, configure the jumpers J8 and J9 as shown in Figure 9.
PLL-CTRL2
SW1-3
0
0
1
0
0
J8
The ADR-SEL switch (SW1-4) determines the SPI address of
the AD1940. The default is 0 (switch to the right).
J9
LRCLK_IN
BCLK_IN
1939_L RCLK
1939_BCLK
INPUT ROUTING
Audio data is routed to the AD1940 via four jumpers: J4, J5, J6,
and J7. A description of these jumpers is in Table 3.
With the jumpers configured as shown in Figure 8 and Figure 9,
the analog input signals will appear in SigmaStudio as input
channels 0-5, as shown in Figure 10.
Table 3. SDATA_INx Routing
Component
J4
J5
J6
J7
Figure 9. LRCLK_IN/BCLK_IN Routing Jumpers - Analog Configuration
Function
Select data to input to AD1940 – SDATA_IN0
Select data to input to AD1940 – SDATA_IN1
Select data to input to AD1940 – SDATA_IN2
Select data to input to AD1940 – SDATA_IN3
Input clocks are configured via two jumpers: J8 and J9. A
description of these jumpers is in Table 4.
Table 4. LRCLK_IN/BCLK_IN Routing
Component
J8
J9
Function
Select frame clock source for AD1940 serial
input ports
Select bit clock source for AD1940 serial input
ports
ANALOG INPUT 0
ANALOG INPUT 1
ANALOG INPUT 2
ANALOG INPUT 3
ANALOG INPUT 4
ANALOG INPUT 5
The AD1940 serial input ports are always configured as slaves,
so clocks must always be supplied from another source in order
for them to function.
ANALOG AUDIO INPUTS
The EVAL-AD1940AZ has three stereo 1/8’ input jacks,
allowing for a total of 6 channels of analog audio input. Input
channels 0-3 are routed to the AD1939 ADCs and input
channels 4-5 are routed to the AD1974 ADCs. In order to input
Rev. PrA | Page 8 of 30
Figure 10. Analog Inputs in SigmaStudio
Preliminary Technical Data
EVAL-AD1940AZ
EXTERNAL DIGITAL AUDIO (I2S/TDM) INPUTS
EXTERNAL I2S INPUT 0
EXTERNAL I2S INPUT 1
EXTERNAL I2S INPUT 2
EXTERNAL I2S INPUT 3
EXTERNAL I2S INPUT 4
EXTERNAL I2S INPUT 5
EXTERNAL I2S INPUT 6
EXTERNAL I2S INPUT 7
The EVAL-AD1940AZ has a digital interface input header (J22)
with connections for MCLK, LRCLK, BCLK, and four serial
data lines, allowing for a total of 8 channels of serial audio input
(I2S, right-justified, or left-justified) or up to 16 channels when
TDM modes are used. In order to input the audio data to the
AD1940 DSP, it must be routed appropriately using the audio
data routing jumpers.
Proper configuration for inputting all I2S/TDM audio to the
DSP is shown in Figure 11.
J4
J5
J6
J7
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
INTF_IN0
INTF_IN1
INTF_IN2
INTF_IN3
Figure 11. Input Routing Jumpers - I2S/TDM Configuration
When data is supplied on the digital interface input header,
there are two options for LRCLK and BCLK routing. First, the
AD1939 can be the clock master. This configuration is shown in
Figure 12.
J8
J9
LRCLK_IN
BCLK_IN
1939_L RCLK
1939_BCLK
Figure 14. I2S Inputs in SigmaStudio
If the input serial ports are configured in TDM modes (allowing
for up to 16 channels), the input channels will appear in
SigmaStudio as input channels 0-15, as shown in Figure 15.
EXTERNAL TDM INPUT 0
EXTERNAL TDM INPUT 1
EXTERNAL TDM INPUT 2
EXTERNAL TDM INPUT 3
EXTERNAL TDM INPUT 4
EXTERNAL TDM INPUT 5
EXTERNAL TDM INPUT 6
EXTERNAL TDM INPUT 7
EXTERNAL TDM INPUT 8
EXTERNAL TDM INPUT 9
EXTERNAL TDM INPUT 10
EXTERNAL TDM INPUT 11
EXTERNAL TDM INPUT 12
EXTERNAL TDM INPUT 13
EXTERNAL TDM INPUT 14
EXTERNAL TDM INPUT 15
Figure 12. LRCLK_IN/BCLK_IN Routing Jumpers - I2S/TDM Configuration AD1939 Master
Alternatively, the LRCLK and BCLK signals can be taken from
an external source over the LRCLK_IN and BCLK_IN pins of
the digital interface input header J22. This configuration is
shown in Figure 13.
J8
J9
LRCLK_IN
BCLK_IN
LRCLK_INTF_IN
BCLK_INTF_IN
Figure 15. TDM Inputs in SigmaStudio
S/PDIF RECEIVER
Figure 13. LRCLK_IN/BCLK_IN Routing Jumpers - I2S/TDM Configuration External Master
With the jumpers configured as shown in Figure 12 and Figure
13, the external I2S input signals will appear in SigmaStudio as
input channels 0-7, as shown in Figure 14.
The EVAL-AD1940AZ has an S/PDIF receiver with both optical
and coaxial connections, allowing for a total of 2 channels of
S/PDIF audio to be input to the AD1940. In order to input the
audio data to the AD1940 DSP, it must be routed appropriately
using the audio data routing jumpers.
Proper configuration for inputting all S/PDIF audio to the DSP
is shown in Figure 16.
Rev. PrA | Page 9 of 30
EVAL-AD1940AZ
Preliminary Technical Data
J4
J5
J6
J7
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
DON’T CARE
DON’T CARE
DON’T CARE
SPDIF_RX_ DATA
Figure 16. Input Routing Jumpers -S/PDIF Configuration
Because the S/PDIF receiver is always a clock master to the
AD1940, the LRCLK_IN and BCLK_IN lines must be
connected to the S/PDIF receiver as shown in Figure 17.
J8
J9
LRCLK_IN
BCLK_IN
SPDIF_LRCLK
SPDIF_BCLK
OUTPUT ROUTING
The AD1940 serial output ports are always connected to the
DACs, digital audio output headers, and S/PDIF transmitter.
These data signals do not require any jumpers or switches to be
output properly. The AD1940 serial output ports can be
configured as either masters or slaves. If the AD1940’s serial
output ports are configured as masters, then jumpers J10, J11,
J12 and J13 can be left disconnected. If the AD1940’s serial
output ports are configured as slaves, then jumpers J10, J11, J12
and J13 must be connected in order to output data. The
functionality of these jumpers is described in Table 5.
Table 5. Output Clock Routing
Component
J10
J11
Figure 17. LRCLK_IN/BCLK_IN Routing Jumpers - S/PDIF Configuration
The master clock must also be provided from the S/PDIF
receiver. For proper operation, J1 should have a jumper on
“DIR” and J3 should be set to “EXT.”
J12
The S/PDIF receiver can only input data from one connector at
a time. To select the optical connector, set switch SW6 in the up
position. To select the coaxial electrical connector, set switch
SW6 in the down position.
With the jumpers configured as shown in Figure 16 and Figure
17, the S/PDIF inputs will appear in SigmaStudio as shown in
Figure 18.
J13
Function
Connect LRCLK_OUT0 to LRCLK_IN. Must be
connected if serial output channels 0-7 are
configured as slaves and not externally
clocked.
Connect BCLK_OUT0 to BCLK_IN. Must be
connected if serial output channels 0-7 are
configured as slaves and not externally
clocked.
Connect LRCLK_OUT1 to LRCLK_IN. Must be
connected if serial output channels 8-15 are
configured as slaves and not externally
clocked.
Connect BCLK_OUT1 to LRCLK_IN. Must be
connected if serial output channels 8-15 are
configured as slaves and not externally
clocked.
ANALOG AUDIO OUTPUTS
The EVAL-AD1940AZ has four stereo 1/8’ input jacks, allowing
for a total of 8 channels of analog audio output. Output
channels 0-7 are routed to the AD1939 DACs. The analog
outputs are hardwired to the AD1940’s serial output ports and
are always active.
The analog outputs 0-7 correspond to outputs 0-7 in
SigmaStudio.
EXTERNAL DIGITAL AUDIO (I2S/TDM) OUTPUTS
S/PDIF INPUT 0
S/PDIF INPUT 1
The EVAL-AD1940AZ has two external digital interface output
headers, J23 and J24, with connections to all eight
SDATA_OUT data lines, and two pairs of output LRCLK/BCLK
lines. These output headers are hardwired to the AD1940’s
serial output ports and are always active.
The I2S/TDM outputs 0-15 correspond to outputs 0-15 in
SigmaStudio.
S/PDIF TRANSMITTER
Figure 18. S/PDIF Inputs in SigmaStudio
The EVAL-AD1940AZ has an S/PDIF transmitter with both
optical and coaxial electrical outputs. These outputs are
hardwired to the AD1940 and are always active.
The S/PDIF outputs 0-1 correspond to outputs 8-9 in
SigmaStudio.
Rev. PrA | Page 10 of 30
Preliminary Technical Data
EVAL-AD1940AZ
EXAMPLE CONFIGURATIONS
ANALOG IN/OUT MODE
ACTIVE CHANNELS:
0
1
2
3
4
5
6
7
8 10 12 14
9 11 13 15
ANALOG IN
ANALOG OUT
I2S/TDM IN
I2S/TDM OUT
S/PDIF IN
S/PDIF OUT
= NOT ACTIVE
= ACTIVE INPUT
= ACTIVE OUTPUT
J1
SW3
J8
J9
J4
J5
J6
J7
MCLK
H1=MCLK
LRCLK_IN
BCLK_IN
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
1939
OUT
1939_L RCLK
1939_BCLK
1939_DATA1
1939_DATA2
1974_DATA1
INTF_IN3
J10/12 J11/13
LR/BCLK0
LR/BCLK1
XTAL
AD1940 SERIAL OUT MA STER:
CONN ECT ALL JUMPE RS J10‐J13
AD1940 SERIAL OUT SL AVE
DISCONN ECT ALL JUMPE RS J10‐J13
Rev. PrA | Page 11 of 30
J3
MCLK
EVAL-AD1940AZ
Preliminary Technical Data
S/PDIF IN/OUT MODE
ACTIVE CHANNELS:
0
1
2
3
4
5
6
7
8 10 12 14
9 11 13 15
ANALOG IN
ANALOG OUT
DIGITAL IN
DIGITAL OUT
S/PDIF IN
S/PDIF OUT
= NOT ACTIVE
= ACTIVE INPUT
= ACTIVE OUTPUT
J1
SW3
J8
J9
J4
J5
J6
J7
MCLK
H1=MCLK
LRCLK_IN
BCLK_IN
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
DIR
OUT
SPDIF_LRCLK
SPDIF_BCLK
1939_DATA1
1939_DATA2
1974_DATA1
SPDIF_RX_ DATA
J10/12 J11/13
LR/BCLK0
LR/BCLK1
EXT
AD1940 SERIAL OUT MA STER:
CONN ECT ALL JUMPE RS J10‐J13
AD1940 SERIAL OUT SL AVE
DISCONN ECT ALL JUMPE RS J10‐J13
Rev. PrA | Page 12 of 30
J3
MCLK
Preliminary Technical Data
EVAL-AD1940AZ
I2S/TDM IN/OUT MODE
(AD1939 X TAL GENER ATES MCLK)
ACTIVE CHANNELS:
0
1
2
3
4
5
6
7
8 10 12 14
9 11 13 15
ANALOG IN
ANALOG OUT
DIGITAL IN
DIGITAL OUT
S/PDIF IN
S/PDIF OUT
= NOT ACTIVE
= ACTIVE INPUT
= ACTIVE OUTPUT
J1
SW3
J8
J9
J4
J5
J6
J7
MCLK
H1=MCLK
LRCLK_IN
BCLK_IN
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
H1
IN
LRCLK_INTF_IN
BCLK_INTF_IN
INTF_IN0
INTF_IN1
INTF_IN2
INTF_IN3
J10/12 J11/13
LR/BCLK0
LR/BCLK1
EXT
AD1940 SERIAL OUT MA STER:
CONN ECT ALL JUMPE RS J10‐J13
AD1940 SERIAL OUT SL AVE
DISCONN ECT ALL JUMPE RS J10‐J13
Rev. PrA | Page 13 of 30
J3
MCLK
EVAL-AD1940AZ
Preliminary Technical Data
I2S/TDM IN/OUT MODE
(EXTERNAL MCLK INPUT ON H1)
ACTIVE CHANNELS:
0
1
2
3
4
5
6
7
8 10 12 14
9 11 13 15
ANALOG IN
ANALOG OUT
DIGITAL IN
DIGITAL OUT
S/PDIF IN
S/PDIF OUT
= NOT ACTIVE
= ACTIVE INPUT
= ACTIVE OUTPUT
J1
SW3
J8
J9
J4
J5
J6
J7
MCLK
H1=MCLK
LRCLK_IN
BCLK_IN
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
1939, H1 (OUT)
OUT
1939_L RCLK
1939_BCLK
INTF_IN0
INTF_IN1
INTF_IN2
INTF_IN3
J10/12 J11/13
LR/BCLK0
LR/BCLK1
XTAL
AD1940 SERIAL OUT MA STER:
CONN ECT ALL JUMPE RS J10‐J13
AD1940 SERIAL OUT SL AVE
DISCONN ECT ALL JUMPE RS J10‐J13
Rev. PrA | Page 14 of 30
J3
MCLK
Figure 19. AD1940 SigmaDSP and Communications Interface Schematics
10
9
8
7
6
5
4
3
2
1
NET_BUS_8RES_SMD_10K0
R5
TP9
TP10
TP11
TP12
TP13
1940_SDATA_IN1
1940_SDATA_IN2
1940_SDATA_IN3
1940_LRCLK_IN
1940_BCLK_IN
D3V3
SW1
8
7
6
5
SPST_4SEC_SMD
1
2
3
4
2
AD1940 Inputs are always Slave
1
B0
2
4
6
8
10
12
TP1
AD1940 Serial Input Port:
A0
O0
U2-A
1940_PLL_CTRL0
1940_PLL_CTRL1
1940_PLL_CTRL2
1940_ADR_SEL
AD1940 Mode Selection
TP8
74HC125
3
TP4
1
3
5
7
9
11
J1
HEADER_12WAY_UNSHROUD
1940_SDATA_IN0
MCLK
1939_MCLKO
SPDIF_RX_MCLK
EXT_MCLK_H1
EXT_MCLK_H2
EXT_MCLK_H3
Master Clock Source Selection
+
SPI_COUT
SPI_CCLK
SPI_CLATCH
1940_SDATA_IN0
1940_SDATA_IN1
1940_SDATA_IN2
1940_SDATA_IN3
1940_LRCLK_IN
1940_BCLK_IN
Pass Transistor beta>100
MCLK
3
RSVD
9
NC
14
SDATA_IN0
15
SDATA_IN1
16
SDATA_IN2
17
SDATA_IN3
10
LRCLK_IN
11
BCLK_IN
4
PLL_CTRL0
5
PLL_CTRL1
6
PLL_CTRL2
2
SDA
2
4
6
8
10
U1
5V00_USB
TP5
SPI_CDATA
MASTER_RESET
USB_CLK
USBi Header
1
3
5
7
9
J2
HEADER_10WAY_POL
SCL
2.5V
TP2
C16
10uF
C3
C4
C2
C1
AD1940YSTZ
USB Control Interface
C8
1k0
R1
ZXTP25040DFHTA
Power dissipation > 140 mW
2
TP7
1940_D3V3
1940_PLL_CTRL0
1940_PLL_CTRL1
1940_PLL_CTRL2
1940_MCLK
C13
10uF
3.3V to 2.5V
Core Supply Regulation
3
C12
Q1
1
0R00 R4
C9
VDD2P5V
44
VSUPPLY
47
VREF
46
VDRIVE
45
VSENSE
D3V3
+
1
VDD
13
VDD
25
VDD
37
VDD
TP3
YELLOW
D1
604r
12
GND
24
GND
36
GND
48
GND
Power Supply Bypass
L2
RESET
TP29
TP28
TP27
SPI_CLATCH
10uF
1940_ADR_SEL
TP26
SPI_COUT
C10
C17
C6
L1
D3V3
SPI_COUT
SPI_CCLK
SPI_CLATCH
SPI_CDATA
SPI_CCLK
23
18
+
SPI_CDATA
RESETB
ADR_SEL
19
COUT
20
CCLK
21
CLATCH
22
CDATA
26
LRCLK_OUT0
27
BCLK_OUT0
34
LRCLK_OUT1
35
BCLK_OUT1
29
30
31
32
38
39
41
42
TP6
C14
as possible during board layout
Keep capacitors as close to the IC
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
28
ODVDD
33
ODVDD
40
ODVDD
10uF
INVDD3V3
43
INVDD
+
AD1940 SigmaDSP
PLL_GND
7
Rev. PrA | Page 15 of 30
R6
8
PLL_VDD
C11
C5
C7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
AD1940 SIGMADSP AND COMMUNICATIONS INTERFACE
56R0
R3
56R0
R2
C15
10uF
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1940_SDATA_OUT7
1940_SDATA_OUT6
1940_SDATA_OUT5
1940_SDATA_OUT4
AD1940 Outputs can be Master or Slave
AD1940 Serial Output Port:
1940_BCLK_OUT1
1940_LRCLK_OUT1
1940_SDATA_OUT3
1940_SDATA_OUT2
1940_SDATA_OUT1
1940_SDATA_OUT0
1940_BCLK_OUT0
1940_LRCLK_OUT0
TP22
TP23
TP24
TP25
1940_BCLK_OUT0
1940_LRCLK_OUT1
1940_BCLK_OUT1
TP21
TP20
TP19
TP18
TP17
TP16
TP15
TP14
1940_LRCLK_OUT0
1940_SDATA_OUT7
1940_SDATA_OUT6
1940_SDATA_OUT5
1940_SDATA_OUT4
1940_SDATA_OUT3
1940_SDATA_OUT2
1940_SDATA_OUT1
1940_SDATA_OUT0
Preliminary Technical Data
EVAL-AD1940AZ
BOARD SCHEMATICS
+
Figure 20. Power Supplies and Reset Schematics
Rev. PrA | Page 16 of 30
5 to 6 Volts, >700mA
Coax Power Jack
J14
1
3
2
DC-IN
VIN+
TP48
L5
A
D4
K
REGVIN
+
C179
100uF
16V
Linear Regulators
ADP3339-3.3V
2
1.0uF
4
1.0uF
OUT
OUT
C49
IN
U6
C50
3
1.0uF
4
2
C47
3.3V Analog Supply
OUT
OUT
1.0uF
IN
ADP3339-3.3V
3.3V Digital Supply
C48
3
U5
C61
TP52
TP51
TP50
TP49
GREEN
D3
604r
MR
2
3
Master Reset Switch
SW2
ADM811TARTZ
GNDRESET
VCC
Reset Threshold = 3.08V
U17
1
4
Reset Generator
D3V3
A3V3
RED
604r
D3V3
R13
1
AK
2
GND
1
GND
1
D2
R14
1
2
POWER SUPPLIES AND RESET
D3V3
R15
RESET
EVAL-AD1940AZ
Preliminary Technical Data
1939_MCLKO
49R9
R9
100R
R7
C19
27pF
Y1
12.288 MHz
B
A
J3
2
1
FILTR
C18
22pF
3
set AD1940 outputs to slave and external device as LRCLK/BCLK master
AD1939 DAC Serial Port:
AD1939 DACs are always Slaves
Set AD1940 Serial Output 0 to Master
AD1940 Output Channels 0-7 in I2S Mode
To use DACs and Digital output header 2 simultaneously,
CM
C27
390pF
D3V3
A3V3
+
TP30
C31
0.10uF
TP31
+
C28
10uF
R8
562R
C26
5.6nF
C29
0.10uF
MCLK
C30
100uF
52
47
61
2
3
CM
FILTR
LF
MCLKI/MCLKXI
MCLKO/MCLKXO
31
COUT
34
CCLK
30
CIN
35
CLATCH
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
57
ADC2LP
58
ADC2LN
59
ADC2RP
60
ADC2RN
1939_IN2L+
1939_IN2L1939_IN2R+
1939_IN2R22
21
20
19
18
15
53
ADC1LP
54
ADC1LN
55
ADC1RP
56
ADC1RN
C20
AVDD
C21
AVDD
C22
1939_IN1L+
1939_IN1L1939_IN1R+
1939_IN1R-
1940_LRCLK_OUT0
1940_BCLK_OUT0
1940_SDATA_OUT0
1940_SDATA_OUT1
1940_SDATA_OUT2
1940_SDATA_OUT3
45
AGND
1
AVDD
+
C33
AD1939
U3
TP32
1939_OUT4+
1939_OUT41939_OUT5+
1939_OUT5-
1939_OUT6+
1939_OUT61939_OUT7+
1939_OUT7-
6
DAC3LP
7
DAC3LN
8
DAC3RP
9
DAC3RN
10
DAC4LP
11
DAC4LN
12
DAC4RP
13
DAC4RN
RESET
1939_OUT2+
1939_OUT21939_OUT3+
1939_OUT3-
40
DAC2LP
41
DAC2LN
42
DAC2RP
43
DAC2RN
PD/RST
14
29
ALRCLK
28
ABCLK
27
ASDATA1
26
ASDATA2
1939_OUT0+
1939_OUT01939_OUT1+
1939_OUT1-
36
DAC1LP
37
DAC1LN
38
DAC1RP
39
DAC1RN
C25
C24
62
AVDD
32
DVDD
10uF
24
VSENSE
C23
51
AGND
4
AGND
44
AGND
46
VDRIVE
DGND
5
L3
600Z
D3V3
23
VSUPPLY
10uF
+
17
DVDD
AGND
48
Rev. PrA | Page 17 of 30
16
Figure 21. AD1939 Codec Schematics
33
DGND
C32
A3V3
25
AD1939 CODEC
1
2
3
4
5
6
7
8
56R0
R10
16
15
14
13
12
11
10
9
1939_ADC_LRCLK
1939_ADC_BCLK
1939_ASDATA1
1939_ASDATA2
AD1939 ADCs are always Master
AD1940 Input is always Slave
AD1940 Input Channels 0-3 in I2S Mode
AD1939 ADC Serial Port:
Preliminary Technical Data
EVAL-AD1940AZ
1974_ASDATA1
1939_ADC_LRCLK
1939_ADC_BCLK
RESET
49R9
AD1939 ADCs are always Master
AD1974 and AD1940 Input are always Slaves
AD1940 Input Channels 4-5 in I2S Mode
AD1974 ADC Serial Port:
1974_IN3R+
1974_IN3R-
1974_IN3L+
1974_IN3L-
A3V3
C38
10uF
C40
R11
2
1
+
10
23
24
26
27
19
20
22
21
16
15
14
11
18
17
45
46
43
44
41
42
39
40
PD/RST
CDATA
COUT
CCLK
CLATCH
ASDATA2
ASDATA1
ALRCLK
ABCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
DLRCLK
DBCLK
ADC2RP
ADC2RN
ADC2LP
ADC2LN
ADC1RP
ADC1RN
ADC1LP
ADC1LN
U4
L4
600Z
A3V3
+
1
10uF
37
D3V3
TP33
AD1974
C39
2
3
35
38
47
9
8
7
6
31
30
29
28
A3V3
MCLKI/XI
MCLKO/XO
FILTR
CM
LF
DAC4R
DAC4L
DAC3R
DAC3L
DAC2R
DAC2L
DAC1R
DAC1L
C34
C35
C36
C37
2
AD1974 ADC
DVDD
13
DGND
12
DGND
25
33
AVDD1
5
AVDD1
AGND1
4
AGND1
34
48
AVDD2
AGND2
AVDD2
AGND2
1
AGND2
Rev. PrA | Page 18 of 30
32
Figure 22. AD1974 ADC Schematics
36
R12
562R
C41
5.6nF
MCLK
C42
390pF
C45
100uF
+
C46
0.10uF
C43
10uF
C44
0.10uF
+
EVAL-AD1940AZ
Preliminary Technical Data
J15
TIP
RING
Rev. PrA | Page 19 of 30
R45
49k9
TP54
SLEEVE
Analog Inputs 0-1
R44
49k9
TP53
+
+
C83
100pF
FILTR
C66
10uF
C82
100pF
FILTR
C65
10uF
R19
Figure 23. Analog Audio Input Filters Schematics
R26
OPEN
C60
6
2
-
3
1
AD8606AR
U19-A
R16
237r
R23
237r
R29
237r
R22
237r
V+
V4
8
C58
V+
V4
8
C51
U19-C
AD8606AR
U18-C
AD8606AR
Op-Amp Supplies
+
5k76
5k76
7
AD8606AR
U19-B
R24
+
-
R25
5
120pF
C67
5k76
0.10uF
7
AD8606AR
5k76
6
+
U18-B
5k76
1
AD8606AR
U18-A
R21
+
-
R28
2
5
3
120pF
R27
R65 100R
C99
OPEN
5k76
R20
R48 100R
C86
0.10uF
5k76
C64
R17
5k76
R18
C68
C69
C63
C62
U20-C
V+
V4
8
A3V3
C53
AD8606AR
V+
V4
8
C52
AD8606AR
U21-C
1939_IN1R+
1939_IN1R-
1939_IN1L+
C79
C78
1939_IN1L-
J16
U22-C
V+
V4
8
C59
AD8606AR
TIP
RING
R47
49k9
4
8
AD8606AR
V+
V-
+
FILTR
C73
10uF
C85
100pF
5k76
R41
5k76
R32
5k76
R33
5k76
R34
0.10uF
R67 100R
C101
OPEN
R40
R39
0.10uF
R66 100R
C100
OPEN
+
FILTR
C74
10uF
C84
100pF
U23-C
TP56
SLEEVE
Analog Inputs 2-3
R46
49k9
TP55
3
2
5
6
5
6
+
-
7
1
AD8606AR
U21-A
AD8606AR
U21-B
120pF
R35
+
-
7
AD8606AR
C72
5k76
R31
1
AD8606AR
U20-B
5k76
+
-
120pF
U20-A
R38
+
-
5k76
3
2
C75
5k76
R42
237r
R36
237r
R30
237r
R37
237r
R43
C71
C70
C76
C77
ANALOG AUDIO INPUT FILTERS
C81
C80
1939_IN2R+
1939_IN2R-
1939_IN2L+
J17
1939_IN2L-
TIP
RING
R64
49k9
TP58
SLEEVE
Analog Inputs 4-5
R63
49k9
TP57
+
+
C98
100pF
FILTR
C91
10uF
C97
100pF
FILTR
C90
10uF
R51
R60
5k76
R59
OPEN
5k76
R58
0.10uF
R69 100R
C103
OPEN
R52
5k76
R53
R68 100R
C102
0.10uF
5k76
3
2
5
6
5
6
3
2
+
-
1
AD8606AR
U23-A
5k76
7
AD8606AR
U23-B
R57
+
120pF
C92
5k76
-
7
AD8606AR
U22-B
R61
1
AD8606AR
U22-A
R54
+
-
C89
120pF
5k76
+
-
R50
5k76
R49
237r
R56
237r
R62
237r
R55
237r
C93
C94
C88
C87
1974_IN3R+
1974_IN3R-
1974_IN3L+
C96
C95
1974_IN3L-
Preliminary Technical Data
EVAL-AD1940AZ
Rev. PrA | Page 20 of 30
Figure 24. Analog Audio Output Filters (1) Schematics
C56
A3V3
CM
1939_OUT1+
1939_OUT1-
CM
1939_OUT0+
1939_OUT0-
R73
R72
R81
V+
V-
4
8
C57
V+
V4
8
U25-C
AD8606AR
U24-C
OPEN
C117
1%
2k74
1k65
1%
R79
C116
680pF
3k32
1%
C115
330pF
1%
5k49
R83
OPEN
C110
1%
2k74
1k65
1%
R70
C109
680pF
3k32
1%
C108
330pF
1%
AD8606AR
0R00
R87
5k49
1%
R80
11k0
1%
R82
0R00
R78
5k49
1%
R71
11k0
1%
R75
R84
5k49
5
6
3
2
7
AD8606AR
U24-B
C112
220pF
+
-
C113
100pF
1
AD8606AR
U24-A
C105
220pF
+
-
C106
100pF
604r
1%
R86
604r
1%
R77
+
+
C111
C104
R85
49k9
1%
1%
R76
49k9
TP60
TP59
C114
2.2nF
C107
2.2nF
SLEEVE
TIP
RING
1V RMS
Analog Outputs 0-1
J18
CM
1939_OUT3+
1939_OUT3-
CM
1939_OUT2+
1939_OUT2-
R91
0R00
R105
5k49
1%
R98
11k0
1%
R100
0R00
R96
5k49
1%
R89
11k0
1%
R102
R74
R93
R90
R99
OPEN
C131
1%
2k74
1k65
1%
R97
C130
680pF
3k32
1%
C129
330pF
1%
5k49
R101
OPEN
C124
1%
2k74
1k65
1%
R88
C123
680pF
3k32
1%
C122
330pF
1%
5k49
R92
ANALOG AUDIO OUTPUT FILTERS (1)
5
6
3
2
7
AD8606AR
U25-B
C126
220pF
+
-
C127
100pF
1
AD8606AR
U25-A
C119
220pF
+
-
C120
100pF
604r
1%
R104
604r
1%
R95
+
+
C125
C118
R103
49k9
1%
1%
R94
49k9
TP62
TP61
C128
2.2nF
C121
2.2nF
SLEEVE
TIP
RING
1V RMS
Analog Outputs 2-3
J19
EVAL-AD1940AZ
Preliminary Technical Data
Rev. PrA | Page 21 of 30
Figure 25. Analog Audio Output Filters (2) Schematics
CM
1939_OUT5+
1939_OUT5-
CM
1939_OUT4+
1939_OUT4-
0R00
R123
5k49
1%
R116
11k0
1%
R118
0R00
R114
5k49
1%
R107
11k0
1%
R109
R111
R108
R117
1
4
8
C55
V+
V4
8
U27-C
AD8606AR
AD8606AR
7
AD8606AR
U26-B
C140
220pF
+
-
C141
100pF
C133
220pF
+
-
U26-C
5
6
3
2
U26-A
C134
100pF
AD8606AR
V+
V-
OPEN
C145
2k74
1%
1k65
1%
R115
C144
680pF
3k32
1%
C143
330pF
1%
5k49
R119
OPEN
C138
2k74
1%
1k65
1%
R106
C137
680pF
3k32
1%
C136
330pF
1%
A3V3
C54
R120
5k49
604r
1%
R122
604r
1%
R113
+
+
C139
C132
R121
49k9
1%
R112
49k9
1%
TP64
TP63
C142
2.2nF
C135
2.2nF
SLEEVE
TIP
RING
1V RMS
Analog Outputs 4-5
J20
CM
1939_OUT7+
1939_OUT7-
CM
1939_OUT6+
1939_OUT6-
0R00
R141
5k49
1%
R134
11k0
1%
R136
0R00
R132
5k49
1%
R125
11k0
1%
R127
R138
R110
R129
R126
R135
OPEN
C159
2k74
1%
1k65
1%
R133
C158
680pF
3k32
1%
C157
330pF
1%
5k49
R137
OPEN
C152
2k74
1%
1k65
1%
R124
C151
680pF
3k32
1%
C150
330pF
1%
5k49
R128
ANALOG AUDIO OUTPUT FILTERS (2)
5
6
3
2
7
AD8606AR
U27-B
C154
220pF
+
-
C155
100pF
1
AD8606AR
U27-A
C147
220pF
+
-
C148
100pF
604r
1%
R140
604r
1%
R131
+
+
C153
C146
R139
49k9
1%
TP66
R130
49k9
1%
TP65
C156
2.2nF
C149
2.2nF
SLEEVE
TIP
RING
1V RMS
Analog Outputs 6-7
J21
Preliminary Technical Data
EVAL-AD1940AZ
Figure 26. Digital Audio I/O Schematics
Rev. PrA | Page 22 of 30
EXT_MCLK_H3
EXT_MCLK_H2
TP69
TP68
C177
1.0uF
R151
Digital Header 1
J22
2
74HC125
D3V3
6
9
O3
B1
4
SW4
R147
R146
A1
O1
U33-B
U33-C
B3
11
74HC125
1
3
5
8
OUT
IN
74HC125
10 A3
1
3 H1_MCLK
5 LRCLK_INTF_IN
7 BCLK_INTF_IN
9 SDATA_INTF_IN0
11 SDATA_INTF_IN1
13 SDATA_INTF_IN2
15 SDATA_INTF_IN3
17
19
O0
B2
13
SW5
R150
R149
A2
O2
U33-D
U33-A
B0
1
3
12
3
IN
OUT
Digital Header 3 MCLK Direction
2
74HC125
D3V3
11
2
74HC125
1 A0
Digital Header 2 MCLK Direction
C178
1.0uF
D3V3
2
4
6
8
10
12
14
16
18
20
22r1
12
R142
SW3
1940_LRCLK_OUT1
1940_BCLK_OUT1
1940_SDATA_OUT4
1940_SDATA_OUT5
1940_SDATA_OUT6
1940_SDATA_OUT7
Digital Header 3
1940_LRCLK_OUT0
1940_BCLK_OUT0
1940_SDATA_OUT0
1940_SDATA_OUT1
1940_SDATA_OUT2
1940_SDATA_OUT3
6
9
1
3
IN
OUT
A1
74HC125
O1
R143
4
B1
U2-B
U2-C
B3
H2_MCLK
J23
H3_MCLK
1940_SDATA_OUT7
1940_SDATA_OUT6
1940_SDATA_OUT5
1940_SDATA_OUT4
1940_BCLK_OUT1
1940_LRCLK_OUT1
1
3
5
7
9
11
13
15
17
19
J24
2
4
6
8
10
12
14
16
18
20
HEADER_20WAY_POL
Digital Header 3
1940_SDATA_OUT3
1940_SDATA_OUT2
1940_SDATA_OUT1
1940_BCLK_OUT0
1
3
5
7
9
11
13
15
17
19
D3V3
1940_LRCLK_OUT0
D3V3
TP67
Digital Header 2
R145
22r1
2
4
6
8
10
12
14
16
18
20
HEADER_20WAY_POL
Digital Header 1 MCLK Direction
2
A3 10
O3
AD1940 Output 0 can be Master or Slave
AD1940 Output Channels 0-7 in I2S Mode
Dual Wire 8-Channel TDM: Ch 0-7 on SDATA_OUT0
Single Wire 16-Channel TDM: Ch 0-15 on SDATA_OUT0
Digital Header 2
R171
5
D3V3
AD1940 Output 1 can be Master or Slave
AD1940 Output Channels 8-15 in I2S Mode
Dual Wire 8-Channel TDM: Ch 8-15 on SDATA_OUT4
Single Wire 16-Channel TDM: No outputs on this header
B2
U2-D
O2
A2 13
LRCLK_INTF_IN
BCLK_INTF_IN
SDATA_INTF_IN0
SDATA_INTF_IN1
SDATA_INTF_IN2
SDATA_INTF_IN3
8
74HC125
DIGITAL AUDIO I/O
AD1940 Input is Slave by Default
Set external source to LRCLK/BCLK Master
AD1940 Input Channels 0-7 in I2S Mode
Digital Header 1
HEADER_20WAY_POL Dual Wire 8-Channel TDM: Ch 0-7 on SDATA_IN3, Ch 8-15 on SDATA_IN2
Single Wire 16-Channel TDM: Ch 0-15 on SDATA_IN3
D3V3
R148
22r1
EXT_MCLK_H1
EVAL-AD1940AZ
Preliminary Technical Data
GND
J25
ISOLATE GROUND
75R0
R153
CTP-021A-S-YEL
OUT
10k0
R152
1
96KHZ
74HC04D-T
AUDIO
NV/RERR
U35
TORX147L(FT)
3
DVDD
600 Ohm @ 100 MHz
ISOLATE GROUND
0.10uF
2
C162
9
4Y
8
74HC04D-T
74HC04D-T
4A
U40-D
74HC04D-T
C165
22nF
3k01
R154
11
5
13
6Y
3Y
5A
5Y
U40-E
3A
U40-C
6A
10nF
FILT
RXN
RXP0
3
RXP1
2
RXP2
1
RXP3
8
5
4
VA
6
L7
D3V3
RST
Red Diffused
TP70
9
Green Diffused
L8
R167
D3V3
22
R166
20
C167
25
47k5
R157
47k5
R156
0.10uF
0.10uF
10uF
19
C
18
U
17
RCBL
14
NV/RERR
15
AUDIO
16
96KHZ
OMCK
DGND
R165
TX
+
C169
C164
26
SDOUT
28
OLRCK
27
OSCLK
24
RMCK
VL
21
7
CS8416
U36
VD
23
600 Ohm @ 100 MHz
AGND
10
RXSEL1
11
RXSEL0
12
TXSEL1
13
TXSEL0
Yellow Diffused
96kHz
10
Audio
6
10uF
+
0.10uF
C168
10nF
D3V3
Error
12
C161
C160
C166
1.0nF
U40-F
RESET
S/PDIF Input Selection
SW6
DPDT Slide
C163
D5
L6
2
2
2
47k5
47k5
R155
47k5
R158
R159
1
2
3
4
5
6
7
8
D3V3
D3V3
16
15
14
13
12
11
10
9
C176
0.10uF
SPDIF_RX_LRCLK
SPDIF_RX_BCLK
SPDIF_RX_SDATA
SPDIF_RX_MCLK
S/PDIF Rx Serial Port:
RESET
MCLK
1940_BCLK_OUT1
1940_LRCLK_OUT1
1940_SDATA_OUT4
S/PDIF Tx Serial Port:
CS8406 is Slave by Default
Set AD1940 Serial Output 1 to Master
AD1940 Output Channels 8-9 in I2S Mode
S/PDIF INTERFACE
CS8416 is Master by Default
AD1940 Input is Slave by Default
AD1940 Input Channels 6-7 in I2S Mode
NV/RERR
AUDIO
96KHZ
R160
56R0
0R00
15
9
18
5
4
28
1
16
3
21
13
12
14
TCBL
RST
U
SFMT1
SFMT0
ORIG
+
0.10uF
COPY/C
CEN
EMPH
OMCK
ISCLK
ILRCLK
SDIN
10uF
C173
C171
D3V3
6
U39
TCBLD
APMS
AUDIO
H/S
TXN
TXP
10uF
C174
SPDIF Transmitter
V
NC3
NC2
NC1
HWCK1
17
8
7
2
27
20
11
10
19
24
25
26
C172
HWCK0
+
0.10uF
D3V3
CS8406_HARDWARE
VD
23
VL
D3V3
1
1
D6
1
D7
392R
4
2Y
2A
GND
22
600 Ohm @ 100 MHz
392R
392R
U40 -B
U40 -A
3
R168
2
1Y
1A
1
74 HC 04 D -T
74 HC 04 D -T
Rev. PrA | Page 23 of 30
0R00
Figure 27. S/PDIF Interface Schematics
R169
47k5
R164
10nF
C175
90R9
R162
374R
R161
10k0
R163
3
INPUT
L9
2
U37
8
6
5
HI
0.10uF
C170
LO
J26
CTP-021A-S-YEL
SC937-02_AES_TRANSFORMER
4
1
1
GND
TOTX147L(FT)
U38
2
DVDD
600 Ohm @ 100 MHz
D3V3
Preliminary Technical Data
EVAL-AD1940AZ
SDATA_INTF_IN3
SPDIF_RX_SDATA
SDATA_INTF_IN2
1974_ASDATA1
SDATA_INTF_IN1
1939_ASDATA2
SDATA_INTF_IN0
1939_ASDATA1
TP47
TP46
TP45
TP44
TP43
TP42
TP40
TP41
1940_SDATA_IN3
1940_SDATA_IN2
1940_SDATA_IN1
1940_SDATA_IN0
SPDIF_RX_BCLK
BCLK_INTF_IN
1939_ADC_BCLK
SPDIF_RX_LRCLK
LRCLK_INTF_IN
1939_ADC_LRCLK
TP39
TP38
TP37
TP36
TP35
TP34
J9
J8
1940_BCLK_IN
1940_LRCLK_IN
I n p u t A u d i o C l o c k R o u t in g
1940_BCLK_IN
1940_BCLK_IN
1940_LRCLK_IN
1940_LRCLK_IN
AUDIO DATA AND CLOCK ROUTING
3
I n p u t A u d i o D a t a R o u t in g
J4 1
A
B
3
J5 1
A
B
3
2
2
2
2
J6 1
A
B
3
J7 1
A
4
4
B
A
2
1
3
B
A
2
1
Rev. PrA | Page 24 of 30
B
Figure 28. Audio Data and Clock Routing Schematics
3
1
1
1
1
J13
J12
J11
J10
2
2
2
2
1940_BCLK_OUT1
1940_BCLK_OUT0
1940_LRCLK_OUT1
1940_LRCLK_OUT0
O u t p u t A u d i o C l o c k R o u t in g
EVAL-AD1940AZ
Preliminary Technical Data
Preliminary Technical Data
EVAL-AD1940AZ
BOARD SILKSCREEN AND PARTS PLACEMENT
Figure 29. Board Top Layer Layout
Rev. PrA | Page 25 of 30
EVAL-AD1940AZ
Preliminary Technical Data
BILL OF MATERIALS
Reference
C105 C112 C119 C126
C133 C140 C147 C154
C107 C114 C121 C128
C135 C142 C149 C156
C108 C115 C122 C129
C136 C143 C150 C157
C109 C116 C123 C130
C137 C144 C151 C158
C11‐12 C15‐17 C32‐33
C39‐40 C168‐169 C173‐
174
Qty
Value
Manufacturer
8
220pF
8
2.2nF NP0
Murata ENA
Murata
Electronics
8
330pF
Murata ENA
8
680pF
Panasonic EC
Part Number
GRM1555C1H221J
A01D
GRM1885C1H222J
A01D
GRM1555C1H331J
A01D
GRM1555C1H681J
A01D
13
10uF
Rohm
TCP0J106M8R
C160‐161
2
10nF
TDK Corp
C165
C1‐7 C9‐10 C13‐14 C20‐
25 C29 C31 C34‐38 C44
C46 C51‐61 C86 C99‐103
C162‐164 C167 C170‐172
C176
1
22nF
Murata ENA
C1608C0G1E103J
GRM21B5C1H223J
A01L
0.10uF
Panasonic EC
ECJ‐0EX1C104K
ECJ‐1VB1H103K
GRM1555C1H220J
Z01D
GRM1555C1H270J
Z01D
51
Description
Multilayer Ceramic 50V NP0
(0402)
Multilayer Ceramic 50V NP0
(0603 )
Multilayer Ceramic 50V NP0
(0402)
Multilayer Ceramic 50V NP0
(0402)
SMD Tantalum Capacitor 0805
6.3V
Multilayer Ceramic 25V NP0
(0603)
Multilayer Ceramic 25V NP0
(0805)
Multilayer Ceramic 16V X7R
(0402)
Multilayer Ceramic 50V X7R
(0603)
Multilayer Ceramic 50V NP0
(0402)
Multilayer Ceramic 50V NP0
(0402)
Multilayer Ceramic 25V NP0
(0603)
Multilayer Ceramic 50V NP0
(0402)
C175
1
10nF
Panasonic EC
C18
1
22pF
Murata ENC
C19
1
27pF
Murata ENA
C26 C41
2
5.6nF
TDK Corp
C27 C42
C28 C43 C65‐66 C73‐74
C90‐91 C104 C111 C118
C125 C132 C139 C146
C153
2
390pF
Murata ENA
C1608C0G1E562J
GRM1555C1H391J
A01D
16
10uF
Panasonic EC
EEE‐FC1C100R
C30 C45 C179
3
100uF
Panasonic EC
C47‐50 C177‐178
6
1.0uF
Taiyo Yuden
C64 C67 C72 C75 C89 C92
C78‐81 C95‐96 C110 C117
C124 C131 C138 C145
C152 C159
C8 C62‐63 C68‐71 C76‐77
C87‐88 C93‐94 C166
C82‐85 C97‐98 C106 C113
C120 C127 C134 C141
C148 C155
6
120pF
Murata ENA
EEE‐FC1C101P
EMK107BJ105KA‐
TR
GRM1555C1H121J
A01D
Alum Electrolytic Capacitor FC
105deg SMD_B
Alum Electrolytic Capacitor FC
105deg SMD_E
Multilayer Ceramic 16V X7R
(0603)
Multilayer Ceramic 50V NP0
(0402)
14
OPEN
n/a
14
1.0nF
Murata ENA
n/a
GRM1555C1H102J
A01D
Do not stuff anything here
Multilayer Ceramic 50V NP0
(0402)
14
100pF
Yellow
Diffused
Murata ENA
CML Innovative
Tech
GCM1555C1H101J
Z13D
CMD15‐
21VYD/TR8
Red Diffused
Green
Diffused
Lumex Opto
DL4001‐TP
CMD15‐
21VYD/TR8
Multilayer Ceramic 50V NP0
(0402)
Yellow Diffused 4.0millicandela
585nm 1206
Red Diffused 6.0millicandela
635nm 1206
Green Diffused 10millicandela
565nm 1206
Passivated Rectifier 1A 50V
MELF
Yellow Diffused 4.0millicandela
585nm 1206
PBC06DAAN
or cut PBC36DAAN
D1
1
D2 D5
2
D3 D6
2
D4
1
D7
J1
1
Yellow
Diffused
Lumex Opto
Micro
Commercial Co.
CML Innovative
Tech
1
2x6
3M
SML‐LX1206IW‐TR
SML‐LX1206GW‐
TR
Rev. PrA | Page 26 of 30
Vendor
Vendor Order #
Digi‐Key
490‐1293‐1‐ND
Digi‐Key
490‐1459‐1‐ND
Digi‐Key
490‐1295‐1‐ND
Digi‐Key
490‐3240‐1‐ND
Digi‐Key
511‐1447‐1‐ND
Digi‐Key
445‐2664‐1‐ND
Digi‐Key
490‐1644‐1‐ND
Digi‐Key
PCC13490CT‐
ND
Digi‐Key
PCC1784CT‐ND
Digi‐Key
490‐1283‐1‐ND
Digi‐Key
490‐1284‐1‐ND
Digi‐Key
445‐2666‐1‐ND
Digi‐Key
490‐1296‐1‐ND
Digi‐Key
PCE3995CT‐ND
Digi‐Key
PCE3996CT‐ND
Digi‐Key
587‐1241‐1‐ND
Digi‐Key
490‐1292‐1‐ND
n/a
n/a
Digi‐Key
490‐3244‐1‐ND
Digi‐Key
490‐4756‐1‐ND
Digi‐Key
L62307CT‐ND
Digi‐Key
67‐1003‐1‐ND
Digi‐Key
Digi‐Key
67‐1002‐1‐ND
DL4001‐
TPMSCT‐ND
Digi‐Key
L62307CT‐ND
Digi‐Key
S2011E‐06‐ND
Preliminary Technical Data
EVAL-AD1940AZ
PBC02SAAN; or
cut PBC36SAAN
2‐pin Header Unshrouded
Jumper 0.10"; use Shunt Tyco
881545‐2
Digi‐Key
S1011E‐02‐ND
J10‐13
4
2‐Jumper
Sullins
Electronics Corp
J14
1
RAPC722X
Switchcraft Inc.
RAPC722X
Mini Power Jack 0.08" R/A TH
Digi‐Key
J15‐21
7
SJ‐3523‐SMT
CUI Inc.
SJ‐3523‐SMT
Digi‐Key
J2
1
2x5
3M
N2510‐6002RB
Digi‐Key
MHC10K‐ND
J22‐24
3
2x10
3M
N2520‐6002RB
Sterero Mini Jack SMT
10‐way Shroud Polarized
Header
20‐way Shroud Polarized
Header
SC1313‐ND
CP‐3523SJCT‐
ND
MHC20K‐ND
J25‐26
2
CTP‐021A‐S‐
YEL
Connect‐Tech
Products Corp.
RCA Jack PCB TH Mount R/A
Yellow
Digi‐Key
connect‐
tech‐
products
.com
J3‐7
5
Sullins
3‐pos SIP Header
Digi‐Key
J8‐9
2
Digi‐Key
8
Digi‐Key
445‐2205‐1‐ND
L5
1
3‐pos SIP Header + 1 extra pin
Chip Ferrite Bead 600 Ohm @
100 MHz
Chip Ferrite Bead 600 Ohm @
100 MHz
S1011E‐03‐ND
S1011E‐03‐ND
+S1011E‐01‐ND
L1‐4 L6‐9
Digi‐Key
Q1
1
3‐Jumper
3jumper +
1jumper
600 Ohm @
100 MHz
600 Ohm @
100 MHz
ZXTP25040D
FHTA
240‐2415‐1‐ND
ZXTP25040DFH
CT‐ND
R1
1
R145 R148 R151
R15 R142‐143 R146‐147
R149‐150 R152 R163
Sullins
CTP‐021A‐S‐YEL
PBC03SAAN; or
cut PBC36SAAN
PBC03SAAN; or
cut PBC36SAAN
TDK Corp
MPZ1608S601A
Steward
HZ1206E601R‐10
Zetex Inc.
ZXTP25040DFHTA
1k00
Panasonic EC
3
22R1
Vishay/Dale
ERJ‐2RKF1001X
CRCW040222R1FK
ED
9
10k0
Rohm
MCR01MZPF1002
R153
1
75R0
Panasonic EC
ERJ‐3EKF75R0V
R154
1
3k01
Rohm
MCR03EZPFX3011
R155‐159 R164
R16 R22‐23 R29‐30 R36‐
37 R43 R49 R55‐56 R62
6
47k5
Rohm
12
237R
Vishay/Dale
MCR01MZPF4752
CRCW0402237RFK
ED
R161
1
374R
Rohm
MCR03EZPFX3740
R162
1
90R9
Rohm
MCR03EZPFX90R9
R165‐167
R17‐18 R20‐21 R24‐25
R27‐28 R31‐32 R34‐35
R38‐39 R41‐42 R50‐51
R53‐54 R57‐58 R60‐61
3
392R
Rohm
MCR03EZPFX3920
PNP Transistor 40V 3A SOT‐23
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 100mW Thick
Film 0603
Chip Resistor 1% 100mW Thick
Film 0603
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 100mW Thick
Film 0603
Chip Resistor 1% 100mW Thick
Film 0603
Chip Resistor 1% 100mW Thick
Film 0603
24
5k76
Panasonic EC
ERJ‐2RKF5761X
R19 R26 R33 R40 R52 R59
6
OPEN
Do Not Stuff
R2‐3 R10 R160
R4 R78 R87 R96 R105
R114 R123 R132 R141
R168‐169 R171
R44‐47 R63‐64 R76 R85
R94 R103 R112 R121
R130 R139
4
56R0
12
R5
R6 R13‐14 R77 R86 R95
R104 R113 R122 R131
R140
R7 R48 R65‐69
Digi‐Key
Digi‐Key
Digi‐Key
Digi‐Key
Digi‐Key
Digi‐Key
Digi‐Key
P1.00KLCT‐ND
541‐22.1LCT‐
ND
RHM10.0KLCT‐
ND
P75.0HCT‐ND
RHM3.01KHCT‐
ND
RHM47.5KLCT‐
ND
Digi‐Key
541‐237LCT‐ND
RHM374HCT‐
ND
RHM90.9HCT‐
ND
RHM392HCT‐
ND
Chip Resistor 1% 63mW Thick
Film 0402
Digi‐Key
P5.76KLCT‐ND
OPEN
Do Not Stuff
OPEN
CTS Corp.
741X163560JP
Resistor Network Isolated 8Res
Digi‐Key
OPEN
741X163560JPC
T‐ND
0R00
Panasonic EC
ERJ‐3GEY0R00V
Chip Resistor 5% 125mW Thick
Film 0603
Digi‐Key
P0.0GCT‐ND
14
49k9
Vishay/Dale
CRCW040249K9FK
ED
Chip Resistor 1% 63mW Thick
Film 0402
Digi‐Key
541‐49.9KLCT‐
ND
1
10k0
Panasonic EC
EXB‐D10C103J
Resistor Network Bussed 8Res
Digi‐Key
U9103CT‐ND
11
604R
Vishay/Dale
CRCW0402604RFK
ED
Digi‐Key
7
100R
Rohm
MCR01MZPF1000
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
541‐604LCT‐ND
RHM100LCT‐
ND
Rev. PrA | Page 27 of 30
Digi‐Key
CTP‐021A‐S‐YEL
Digi‐Key
Digi‐Key
Digi‐Key
EVAL-AD1940AZ
R70 R79 R88 R97 R106
R115 R124 R133
R71 R74 R80 R83 R89 R92
R98 R101 R107 R110
R116 R119 R125 R128
R134 R137
R72 R81 R90 R99 R108
R117 R126 R135
R73 R82 R91 R100 R109
R118 R127 R136
R75 R84 R93 R102 R111
R120 R129 R138
Preliminary Technical Data
CRCW04021K65FK
ED
Chip Resistor 1% 63mW Thick
Film 0402
8
1k65
Vishay/Dale
16
5k49
Rohm
8
3k32
Vishay/Dale
8
11k0
Yageo
8
2k74
Vishay/Dale
R8 R12
2
562R
Vishay/Dale
RC0402FR‐0711KL
CRCW04022K74FK
ED
CRCW0402562RFK
ED
R9 R11
2
49R9
Rohm
MCR01MZPF49R9
SW1
1
8x SPST
CTS Corp
219‐4LPST
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
Chip Resistor 1% 63mW Thick
Film 0402
4 Section SPST SMD Switch
Raised Act
SW2
1
SPST‐NO
Tyco/Alcoswitch
FSM6JSMA
SW3‐5
3
SPDT
Copal Electronics
CAS‐120TA
SW6
1
DPDT Slide
5002
E‐Switch
Keystone
Electronics
TP1‐70
70
MCR01MZPF5491
CRCW04023K32FK
ED
Digi‐Key
Digi‐Key
Digi‐Key
Digi‐Key
Digi‐Key
RHM5.49KLCT‐
ND
541‐3.32KLCT‐
ND
311‐11.0KLRCT‐
ND
541‐2.74KLCT‐
ND
Digi‐Key
541‐562LCT‐ND
RHM49.9LCT‐
ND
CT2194LPST‐
ND
Tact Switch 6mm Gull Wing
Digi‐Key
450‐1133‐ND
SPDT Slide Switch SMD J Hook
Digi‐Key
CAS120JCT‐ND
EG2207
DPDT Slide Switch Vertical
Digi‐Key
EG1940‐ND
5002
Mini Test Point White .1" OD
5002K‐ND
SigmaDSP Multi‐Channel 28‐bit
Audio Processor
Digi‐Key
Analog
Devices
Inc.
Analog
Devices
Inc.
Analog
Devices
DigiKey
Analog
Devices
74AC125SC‐ND
U1
1
AD1940YSTZ
Analog Devices
Inc.
AD1940YSTZ
U17
1
ADM811TAR
TZ‐REEL7
Analog Devices
Inc.
ADM811TARTZ‐
REEL7
U18‐27
10
AD8606ARZ
AD8606ARZ
U2 U33
2
74AC125SC
Analog Devices
Texas
Instruments
74AC125SC
U3
1
Analog Devices
AD1939YSTZ
U35
1
AD1939YSTZ
TORX147L(F
T)
Toshiba
TORX147L(FT)
4 ADC/8 DAC with PLL
15Mb/s Fiber Optic Receiving
Module w/ Shutter
U36
1
CS8416‐CZZ
Cirrus Logic
CS8416‐CZZ
192KHZ DGTL RCVR 28‐TSSOP
U37
1
Scientific
Conversion
SC937‐02
U38
1
SC937‐02
TOTX147L(FT
)
Toshiba
TOTX147L(FT)
U39
1
CS8406‐CZZ
Cirruc Logic
CS8406‐CZZ
U4
1
AD1974YSTZ
Analog Devices
AD1974YSTZ
U40
1
74HC04D‐T
NXP Semi
74HC04D‐T
192kHz SPDIF Transmiter
4 ADC 8DAC with PLL 192kHz
24‐bit CODEC
IC INVERTER HEX TTL/LSTTL
14SOIC
U5‐6
2
ADP3339AK
CZ‐3.3‐R7
Y1
1
12.288MHz
Analog Devices
Inc.
Citizen America
Corp
ADP3339AKCZ‐
3.3‐R7
HCM49‐
12.288MABJ‐UT
High‐Accuracy low‐Dropout
3.3VDC Voltage Regulator
CRYSTAL 12.288 MHZ SMT
18PF
Rev. PrA | Page 28 of 30
uP Voltage Supervisor Logic
Low RESET Output
Low‐Noise Rail‐to‐Rail CMOS
Op Amp
IC BUFFER QUAD 3 STATE 14‐
SOIC
110 Ohm AES/EBU
Transformer
Fiber Optic Transmit Module
15Mb/s w/ Shutter
Digi‐Key
541‐1.65KLTR‐
ND
Digi‐Key
Digi‐Key
AD1940YSTZ
ADM811TARTZ‐
REEL7
AD8606ARZ
AD1939YSTZ
TORX147LFT‐
ND
Digi‐Key
www.sci
entificon
version.c
om
598‐1124‐5‐ND
Digi‐Key
Newark
In One
Analog
Devices
TOTX147L‐ND
DigiKey
Analog
Devices
Inc.
568‐1384‐1‐ND
Digi‐Key
300‐8550‐1‐ND
SC937‐02
88H6508
AD1974YSTZ
ADP3339AKCZ‐
3.3‐R7
Preliminary Technical Data
EVAL-AD1940AZ
ORDERING GUIDE
ORDERING GUIDE
Model
EVAL-AD1940AZ
Description
Evaluation Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 29 of 30
EVAL-AD1940AZ
Preliminary Technical Data
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
EB08138-0-3/09(PrA)
Rev. PrA | Page 30 of 30
