256-Position SPI/I2C Selectable
Digital Potentiometer
AD5161
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Pin selectable SPI/I2C compatible interface
Extra package address decode pin AD0
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 8 μA
Wide operating temperature −40°C to +125°C
SDO output allows multiple device daisy-chaining
Evaluation board available
APPLICATIONS
VDD
SDO/NC
SDI/SDA
A
CLK/SCL
DIS
SPI OR I2C
INTERFACE
W
CS/AD0
WIPER
REGISTER
B
GND
Figure 1.
PIN CONFIGURATION
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Gain control and offset adjustment
10 W
A 1
AD5161
9 VDD
8 DIS
TOP VIEW
SDO/NC 4 (Not to Scale) 7 GND
B 2
CS/ADO 3
6 CLK/SCL
SDI/SDA 5
Figure 2.
GENERAL DESCRIPTION
The AD5161 provides a compact 3 mm × 4.9 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
The wiper settings are controllable through a pin selectable SPI
or I2C compatible digital interface, which can also be used to
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I2C mode,
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 μA allows for usage in portable battery-operated
applications.
Rev. C
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Technical Support
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AD5161
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SPI Interface .................................................................................... 13
Applications ....................................................................................... 1
I2C Interface .................................................................................... 14
General Description ......................................................................... 1
Theory of Operation ...................................................................... 15
Functional Block Diagram .............................................................. 1
Programming the Variable Resistor ......................................... 15
Pin Configuration ............................................................................. 1
Programming the Potentiometer Divider ............................... 16
Revision History ............................................................................... 2
Pin Selectable Digital Interface................................................. 16
Electrical Characteristics—5 kΩ Version ........................................ 3
Level Shifting for Bidirectional Interface ................................ 18
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ......... 4
ESD Protection ........................................................................... 18
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions .. 5
Terminal Voltage Operating Range ......................................... 18
Absolute Maximum Ratings ............................................................ 6
Power-Up Sequence ................................................................... 18
ESD Caution .................................................................................. 6
Layout and Power Supply Bypassing ....................................... 18
Pin Configuration and Function Descriptions ............................. 7
Outline Dimensions ....................................................................... 19
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 19
Test Circuits ..................................................................................... 12
REVISION HISTORY
6/15—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 19
8/12—Rev. A to Rev. B
Changes to Applications Section .................................................... 1
Updated Outline Dimensions ....................................................... 19
4/09—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 19
5/03—Revision 0: Initial Version
Rev. C | Page 2 of 20
Data Sheet
AD5161
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity 2
R-DNL
RWB, VA = no connect
Resistor Integral Nonlinearity2
R-INL
RWB, VA = no connect
Nominal Resistor Tolerance 3
∆RAB
TA = 25°C
Resistance Temperature Coefficient
∆RAB/∆T
VAB = VDD, Wiper = no connect
Wiper Resistance
RW
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
Differential Nonlinearity 4
DNL
Integral Nonlinearity4
INL
Voltage Divider Temperature Coefficient
∆VW/∆T
Code = 0x80
Full-Scale Error
VWFSE
Code = 0xFF
Zero-Scale Error
VWZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range 5
VA,B,W
Capacitance 6 A, B
CA,B
f = 1 MHz, measured to GND,
Code = 0x80
Capacitance6 W
CW
f = 1 MHz, measured to GND,
Code = 0x80
Shutdown Supply Current 7
IDD_SD
VDD = 5.5 V
Common-Mode Leakage
ICM
VA = VB = VDD/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
Input Logic Low
VIL
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Input Current
IIL
VIN = 0 V or 5 V
6
Input Capacitance
CIL
POWER SUPPLIES
Power Supply Range
VDD RANGE
Supply Current
IDD
VIH = 5 V or VIL = 0 V
Power Dissipation 8
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
Power Supply Sensitivity
PSS
∆VDD = +5 V ± 10%,
Code = Midscale
DYNAMIC CHARACTERISTICS6, 9
Bandwidth −3dB
BW_5K
RAB = 5 kΩ, Code = 0x80
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
VW Settling Time
tS
VA = 5 V, VB = 0 V, ±1 LSB error band
Resistor Noise Voltage Density
eN_WB
RWB = 2.5 kΩ, RS = 0
Rev. C | Page 3 of 20
Min
Typ 1
Max
Unit
−1.5
−4
−30
±0.1
±0.75
+1.5
+4
+30
LSB
LSB
%
ppm/°C
Ω
45
50
−1.5
−1.5
−6
0
±0.1
±0.6
15
−2.5
+2
GND
120
8
+1.5
+1.5
0
+6
VDD
Bits
LSB
LSB
ppm/°C
LSB
LSB
45
V
pF
60
pF
0.01
1
1
2.4
0.8
2.1
0.6
±1
5
2.7
3
±0.02
1.2
0.05
1
6
5.5
8
0.2
±0.05
µA
nA
V
V
V
V
µA
pF
V
µA
mW
%/%
MHz
%
µs
nV/√Hz
AD5161
Data Sheet
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Symbol
Conditions
R-DNL
R-INL
∆RAB
∆RAB/∆T
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
VAB = VDD,
Wiper = no connect
Wiper Resistance
RW
VDD = 5 V
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
Differential Nonlinearity4
DNL
Integral Nonlinearity4
INL
Voltage Divider Temperature Coefficient
∆VW/∆T
Code = 0x80
Full-Scale Error
VWFSE
Code = 0xFF
Zero-Scale Error
VWZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range5
VA,B,W
Capacitance6 A, B
CA,B
f = 1 MHz, measured to
GND, Code = 0x80
Capacitance6 W
CW
f = 1 MHz, measured to
GND, Code = 0x80
Shutdown Supply Current7
IDD_SD
VDD = 5.5 V
Common-Mode Leakage
ICM
VA = VB = VDD/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
Input Logic Low
VIL
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Input Current
IIL
VIN = 0 V or 5 V
Input Capacitance6
CIL
POWER SUPPLIES
Power Supply Range
VDD RANGE
Supply Current
IDD
VIH = 5 V or VIL = 0 V
Power Dissipation8
PDISS
VIH = 5 V or VIL = 0 V,
VDD = 5 V
Power Supply Sensitivity
PSS
∆VDD = +5 V ± 10%,
Code = Midscale
DYNAMIC CHARACTERISTICS6, 9
Bandwidth −3dB
BW
RAB = 10 kΩ/50 kΩ/100 kΩ,
Code = 0x80
Total Harmonic Distortion
THDW
VA =1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
tS
VA = 5 V, VB = 0 V,
±1 LSB error band
Resistor Noise Voltage Density
eN_WB
RWB = 5 kΩ, RS = 0
Rev. C | Page 4 of 20
Min
Typ1
Max
Unit
−1
−2
−30
±0.1
±0.25
+1
+2
+30
LSB
LSB
%
ppm/°C
120
Ω
8
+1
+1
Bits
LSB
LSB
ppm/°C
LSB
LSB
45
50
−1
−1
−3
0
±0.1
±0.3
15
−1
1
GND
0
3
45
VDD
V
pF
60
pF
0.01
1
1
2.4
0.8
2.1
0.6
±1
5
2.7
µA
nA
V
V
V
V
µA
pF
3
5.5
8
0.2
V
µA
mW
±0.02
±0.05
%/%
600/100/40
kHz
0.05
%
2
µs
9
nV/√Hz
Data Sheet
AD5161
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)
Clock Frequency
fCLK
Input Clock Pulsewidth
tCH, tCL
Clock level high or low
Data Setup Time
tDS
Data Hold Time
tDH
tCSS
CS Setup Time
tCSW
CS High Pulsewidth
tCSH0
CLK Fall to CS Fall Hold Time
tCSH1
CLK Fall to CS Rise Hold Time
tCS1
CS Rise to Clock Rise Setup
I2C INTERFACE TIMING CHARACTERISTICS6, 11 (Specifications Apply to All Parts)
SCL Clock Frequency
fSCL
tBUF Bus Free Time between STOP and START
t1
tHD;STA Hold Time (Repeated START)
t2
After this period, the first clock pulse is
generated.
tLOW Low Period of SCL Clock
t3
tHIGH High Period of SCL Clock
t4
tSU;STA Setup Time for Repeated START Condition
t5
tHD;DAT Data Hold Time
t6
tSU;DAT Data Setup Time
t7
tF Fall Time of Both SDA and SCL Signals
t8
tR Rise Time of Both SDA and SCL Signals
t9
tSU;STO Setup Time for STOP Condition
t10
Min
Typ1
Max
Unit
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
400
kHz
µs
µs
20
5
5
15
40
0
0
10
1.3
0.6
1.3
0.6
0.6
50
0.9
100
300
300
0.6
NOTES
1
Typical specifications represent average readings at +25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, Wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use VDD = 5 V.
10
See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11
See timing diagrams for locations of measured values.
Rev. C | Page 5 of 20
µs
µs
µs
µs
ns
ns
ns
µs
AD5161
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4.
Parameter
VDD to GND
VA, VB, VW to GND
IMAX1
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2
θJA (10-Lead MSOP)
Value
−0.3 V to +7 V
VDD
±20 mA
0 V to +7 V
−40°C to +125°C
150°C
−65°C to +150°C
300°C
ESD CAUTION
200°C/W
NOTES
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (TJMAX − TA)/θJA.
Rev. C | Page 6 of 20
Data Sheet
AD5161
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10 W
A 1
AD5161
9 VDD
8 DIS
TOP VIEW
SDO/NC 4 (Not to Scale) 7 GND
B 2
CS/ADO 3
SDI/SDA 5
6 CLK/SCL
Figure 3. Pin Configuration
Table 5. Pin Function Description
Pin No.
1
2
3
Mnemonic
A
B
CS/AD0
4
SDO/NC
5
SDI/SDA
6
7
8
9
10
CLK/SCL
GND
DIS
VDD
W
Description
A Terminal.
B Terminal.
Chip Select (CS) Input, Active Low. When CS returns high, data will be loaded into the DAC register.
Programmable address bit 0 (AD0) for multiple package decoding.
Serial Data Output (SDO). Open-drain transistor requires pull-up resistor.
No Connect (NC).
Serial Data Input (SDI).
Serial Data Input/Output (SDA).
Serial Clock Input. Positive edge triggered.
Digital Ground.
Digital Interface Select (SPI/I2C Select). SPI when DIS = 0, I2C when DIS = 1.
Positive Power Supply.
W Terminal.
Rev. C | Page 7 of 20
AD5161
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
5V
0.8
–40°C
+25°C
+85°C
+125°C
0.8
POTENTIOMETER MODE DNL (LSB)
RHEOSTAT MODE INL (LSB)
3V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
0
32
64
96
128
160
192
224
0
256
32
64
160
192
224
256
1.0
1.0
0.8
0.8
5V
3V
0.6
POTENTIOMETER MODE INL (LSB)
RHEOSTAT MODE DNL (LSB)
128
Figure 7. DNL vs. Code, VDD = 5 V
Figure 4. R-INL vs. Code vs. Supply Voltages
0.4
0.2
0
–0.2
–0.4
–0.6
5V
3V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
0
32
64
96
128
160
192
224
0
256
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 8. INL vs. Code vs. Supply Voltages
Figure 5. R-DNL vs. Code vs. Supply Voltages
1.0
1.0
_40°C
+25°C
+85°C
+125°C
0.6
5V
0.8
POTENTIOMETER MODE DNL(LSB)
0.8
POTENTIOMETER MODE INL (LSB)
96
CODE (Decimal)
CODE (Decimal)
0.4
0.2
0
–0.2
–0.4
–0.6
3V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
0
32
64
96
128
160
192
224
0
256
32
64
96
128
160
192
CODE (Decimal)
CODE (Decimal)
Figure 9. DNL vs. Code vs. Supply Voltages
Figure 6. INL vs. Code, VDD = 5 V
Rev. C | Page 8 of 20
224
256
Data Sheet
AD5161
1.0
2.5
RHEOSTAT MODE INL (LSB)
0.6
ZSE, ZERO-SCALE ERROR (A)
–40 °C
+25°C
+85°C
+125°C
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
2.0
VDD = 5.5V
1.5
VDD = 2.7V
1.0
0.5
–0.8
0
–40
–1.0
0
64
32
96
128
160
192
224
256
0
80
120
Figure 13. Zero-Scale Error vs. Temperature
Figure 10. R-INL vs. Code, VDD = 5 V
10
1.0
_40°C
0.8
+25°C
+85°C
+125°C
0.6
IDD SUPPLY CURRENT (A)
RHEOSTAT MODE DNL (LSB)
40
TEMPERATURE (°C)
CODE (Decimal)
0.4
0.2
0
–0.2
–0.4
VDD = 5.5V
1
VDD = 2.7V
–0.6
–0.8
0.1
–40
–1.0
0
32
64
96
128
160
192
224
256
0
40
80
120
TEMPERATURE (°C)
CODE (Decimal)
Figure 14. Supply Current vs. Temperature
Figure 11. R-DNL vs. Code, VDD = 5 V
2.5
70
IA SHUTDOWN CURRENT (nA)
FSE, FULL-SCALE ERROR (LSB)
60
2.0
1.5
VDD = 2.7V
1.0
VDD = 5.5V
0.5
50
40
30
VDD = 5V
20
10
0
–40
0
40
80
0
–40
120
TEMPERATURE (°C)
0
40
80
TEMPERATURE (°C)
Figure 12. Full-Scale Error vs. Temperature
Figure 15. Shutdown Current vs. Temperature
Rev. C | Page 9 of 20
120
RHEOSTAT MODE TEMPCO (ppm/°C)
AD5161
Data Sheet
200
REF LEVEL
0.000dB
0
150
–6
0x80
–12
0x40
–18
0x20
100
/DIV
6.000dB
0x10
–24
50
MARKER 510 634.725Hz
MAG (A/R)
–9.049dB
0x08
–30
0x04
–36
0
0x02
0x01
–42
–48
–50
–54
0
32
64
96
128
160
192
224
256
–60
CODE (Decimal)
1k
START 1 000.000Hz
100k
1M
STOP 1 000 000.000Hz
Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
140
REF LEVEL
0.000dB
0
120
–6
160
POTENTIOMETER MODE TEMPCO (ppm/°C)
10k
/DIV
6.000dB
0x80
0x40
–12
100
0x20
–18
80
0x10
–24
60
0x08
–30
40
0x04
–36
20
MARKER 100 885.289Hz
MAG (A/R)
–9.014dB
0x02
–42
0x01
0
–48
–20
–54
0
32
64
96
128
160
192
224
256
–60
CODE (Decimal)
1k
START 1 000.000Hz
Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
REF LEVEL
0.000dB
0
/DIV
6.000dB
–6
0x80
–12
0x40
–18
0x20
10k
Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ
MARKER 1 000 000.000Hz
MAG (A/R)
–8.918dB
REF LEVEL
0.000dB
0
/DIV
6.000dB
–6
0x80
–12
0x40
–18
0x20
–24
0x10
0x04
–30
0x08
0x02
0x01
–36
0x04
–42
–42
0x02
–48
–48
–54
–54
0x10
–24
100k
1M
STOP 1 000 000.000Hz
MARKER 54 089.173Hz
MAG (A/R)
–9.052dB
0x08
–30
–36
–60
0x01
–60
1k
START 1 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
1k
START 1 000.000Hz
Figure 18. Gain vs. Frequency vs. Code, RAB = 5 kΩ
10k
100k
1M
STOP 1 000 000.000Hz
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Rev. C | Page 10 of 20
Data Sheet
REF LEVEL
–5.000dB
AD5161
/DIV
0.500dB
–5.5
5k – 1.026 MHz
10k – 511 MHz
50k – 101 MHz
100k – 54 MHz
–6.0
–6.5
–7.0
1
VW
–7.5
–8.0
CLK
–8.5
R = 50k
R = 5k
2
–9.0
R = 10k
R = 100k
–9.5
Ch 1
200mV BW Ch 2
5.00 V BW M 100ns
A CH2 3.00 V
–10.0
–10.5
10k
100k
1M
START 1 000.000Hz
10M
STOP 1 000 000.000Hz
Figure 25. Digital Feedthrough
Figure 22. −3 dB Bandwidth @ Code = 0x80
60
CODE = 0x80, VA= VDD, VB = 0V
VA = 5V
VB = 0V
PSRR (dB)
40
1
VW
PSRR @ VDD = 3V DC ± 10% p-p AC
CS
20
2
Ch 1
PSRR @ VDD = 5V DC ± 10% p-p AC
0
100
1k
10k
100k
100mV BW Ch 2
5.00 V BW M 200ns A CH1 152mV
1M
FREQUENCY (Hz)
Figure 26. Midscale Glitch, Code 0x80−0x7F
Figure 23. PSRR vs. Frequency
900
VDD = 5V
800
VA = 5V
VB = 0V
700
IDD (A)
600
500
1
400
CS
300
CODE = 0xFF
2
200
Ch 1
100
0
10k
VW
CODE = 0x55
100k
1M
FREQUENCY (Hz)
5.00V BW Ch 2
5.00 V BW M 200ns
A CH1 3.00 V
10M
Figure 27. Large Signal Settling Time, Code 0xFF−0x00
Figure 24. IDD vs. Frequency
Rev. C | Page 11 of 20
AD5161
Data Sheet
TEST CIRCUITS
Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables.
5V
OP279
V+ = VDD
1LSB = V+/2N
DUT
A
VIN
W
V+
OFFSET
GND
B
W
A
VMS
VOUT
DUT
B
OFFSET
BIAS
Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 33. Test Circuit for Noninverting Gain
NO CONNECT
A
DUT
A
+15V
IW
W
W
VIN
DUT
AD8610
OFFSET
GND
B
VMS
2.5V
Figure 29. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
–15V
Figure 34. Test Circuit for Gain vs. Frequency
RSW =
DUT
W
VMS2
0.1V
ISW
CODE = 0x00
DUT
A
VOUT
B
W
I W = VDD / RNOMINAL
VW
B
0.1V
ISW
B
VMS1
RW = [VMS1 – VMS2]/I W
VSS TO VDD
Figure 35. Test Circuit for Incremental ON Resistance
Figure 30. Test Circuit for Wiper Resistance
VA
NC
V+ = VDD 10%
VDD
PSRR (dB) = 20 LOG
A
V+
W
PSS (%/%) =
B
V MS%
V MS
(V DD )
V DD%
VDD
DUT
A
VSS
GND
B
VCM
A
DUT
B
5V
W
OP279
NC = NO CONNECT
Figure 36. Test Circuit for Common-Mode Leakage Current
Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
OFFSET
GND
ICM
VMS
NC
VIN
W
VOUT
OFFSET
BIAS
Figure 32. Test Circuit for Inverting Gain
Rev. C | Page 12 of 20
Data Sheet
AD5161
SPI INTERFACE
1
SDI
Table 6. AD5161 Serial Data-Word Format
B7
D7
MSB
27
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
B0
D0
LSB
20
CLK
0
RDAC REGISTER LOAD
1
CS
0
1
VOUT
0
Figure 37. SPI Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
1
SDI
(DATA IN)
Dx
Dx
0
tCH
1
tDS
tCH
tCS1
CLK
0
tCL
tCSHO
tCSH1
tCSS
1
CS
tCSW
0
tS
VDD
VOUT
±1LSB
0
Figure 38. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
Rev. C | Page 13 of 20
AD5161
Data Sheet
I2C INTERFACE
Table 7. Write Mode
S 0 1 0 1 1 0
AD0
A
W
X
RS
SD
Slave Address Byte
X
X
X
X
X
A
D7
D6
D5
D4
Instruction Byte
D3
D2
D1
D0
A P
D0
A
P
Data Byte
Table 8. Read Mode
S
0
1
0
1
1
0
Slave Address Byte
AD0
R
A
D7
D6
D5
D4
D3
Data Byte
D2
D1
S = Start Condition
R = Read
P = Stop Condition
RS = Reset wiper to Midscale 80H
A = Acknowledge
X = Don’t Care
SD = Shutdown connects wiper to B terminal and open circuits
A terminal. It does not change contents of wiper register.
W = Write
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
t8
t2
t9
SCL
t6
t2
t3
t7
t4
t10
t5
t9
t8
SDA
t1
P
S
S
P
2
Figure 39. I C Interface Detailed Timing Diagram
1
9
1
9
9
1
SCL
SDA
START BY
MASTER
0
1
1
0
1
0
AD0
X
R/W
SD
RS
ACK BY
AD5161
FRAME 1
SLAVE ADDRESS BYTE
X
X
X
X
X
D7
D6
D5
ACK BY
AD5161
FRAME 2
INSTRUCTION BYTE
D4
D3
D2
FRAME 3
DATA BYTE
Figure 40. Writing to the RDAC Register
1
9
1
9
SCL
SDA
START BY
MASTER
0
1
0
1
1
0
AD0
FRAME 1
SLAVE ADDRESS BYTE
D7
R/W
D6
ACK BY
AD5161
D5
D4
D3
D2
D1
FRAME 2
RDAC REGISTER
Figure 41. Reading Data from a Previously Selected RDAC Register in Write Mode
Rev. C | Page 14 of 20
D0
NO ACK
BY MASTER
STOP BY
MASTER
D1
D0
ACK BY
AD5161
STOP BY
MASTER
Data Sheet
AD5161
THEORY OF OPERATION
The AD5161 is a 256-position digitally controlled variable
resistor (VR)1 device.
The general equation determining the digitally programmed
output resistance between W and B is
An internal power-on preset places the wiper at midscale during
power-on, which simplifies the fault condition recovery at power-up.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two
or three digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 50 kΩ = 50. The nominal resistance (RAB) of
the VR has 256 contact points accessed by the wiper terminal,
plus the B terminal contact. The 8-bit data in the RDAC latch is
decoded to select one of the 256 possible settings. Assume a 10 kΩ
part is used, the wiper’s first connection starts at the B terminal
for data 0x00. Since there is a 60 Ω wiper contact resistance, such
connection yields a minimum of 60 Ω resistance between
Terminals W and B. The second connection is the first tap point,
which corresponds to 99 Ω (RWB = RAB/256 + RW = 39 Ω + 60 Ω)
for data 0x01. The third connection is the next tap point,
representing 177 Ω (2 × 39 Ω + 60 Ω) for data 0x02 and so on. Each
LSB data value increase moves the wiper up the resistor ladder
until the last tap point is reached at 9961 Ω (RAB − 1 LSB + RW).
Figure 42 shows a simplified diagram of the equivalent RDAC
circuit where the last resistor string will not be accessed;
therefore, there is 1 LSB less of the nominal resistance at full
scale in addition to the wiper resistance.
A
SD BIT
RS
D7
D6
D5
D4
D3
D2
D1
D0
D
R AB R W
256
In summary, if RAB = 10 kΩ and the A terminal is open circuited,
the following output resistance RWB will be set for the indicated
RDAC latch codes.
Table 9. Codes and Corresponding RWB Resistance
D (Dec.)
255
128
1
0
RWB (Ω)
9,961
5,060
99
60
Output State
Full Scale (RAB − 1 LSB + RW)
Midscale
1 LSB
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
60 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
R WA (D )
RS
256 D
R AB R W
256
W
For RAB = 10 kΩ and the B terminal open circuited, the
following output resistance RWA will be set for the indicated
RDAC latch codes.
B
Table 10. Codes and Corresponding RWA Resistance
RDAC
Figure 42. AD5161 Equivalent RDAC Circuit
The terms digital potentiometer, VR, and RDAC are used interchangeably.
(1)
where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, RAB is the end-to-end resistance, and
RW is the wiper resistance contributed by the on resistance of
the internal switch.
RS
LATCH
RS
AND
DECODER
1
R WB (D )
D (Dec.)
255
128
1
0
RWA (Ω)
99
5,060
9,961
10,060
(2)
Output State
Full Scale
Midscale
1 LSB
Zero Scale
Typical device to device matching is process lot dependent and
may vary by up to ±30%. Since the resistance element is processed
in thin film technology, the change in RAB with temperature has
a very low 45 ppm/°C temperature coefficient.
Rev. C | Page 15 of 20
AD5161
Data Sheet
PROGRAMMING THE POTENTIOMETER DIVIDER
Daisy-Chain Operation
Voltage Output Operation
The serial data output (SDO) pin contains an open-drain
N-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. This allows for
daisy-chaining several RDACs from a single processor serial
data line. The pull-up resistor termination voltage can be larger
than the VDD supply voltage. It is recommended to increase the
clock period when using a pull-up resistor to the SDI pin of the
following device because capacitive loading at the daisy-chain
node SDO-SDI between devices may induce time delay to
subsequent devices. Users should be aware of this potential
problem to achieve data transfer successfully (see Figure 43). If
two AD5161s are daisy-chained, a total of at least 16 bits of data
is required. The first eight bits, complying with the format
shown in Table 6, go to U2 and the second eight bits with the
same format go to U1. CS should be kept low until all 16 bits are
clocked into their respective serial registers. After this, CS is
pulled high to complete the operation and load the RDAC latch.
If the data word during the CS low period is greater than 16
bits, any additional MSBs will be discarded.
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
VW ( D )
D
256 D
VA
VB
256
256
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW, can be found as
VW (D )
R (D )
RWB (D )
V A WA
VB
256
256
VDD
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
C
MOSI
CLK SC
AD5161
U1
SDI
CS
AD5161
RP
U2
2.2k
SDO
CLK
SDI
CS
SDO
CLK
Figure 43. Daisy-Chain Configuration
PIN SELECTABLE DIGITAL INTERFACE
The AD5161 provides the flexibility of a selectable interface.
When the digital interface select (DIS) pin is tied low, the SPI
mode is engaged. When the DIS pin is tied high, the I2C mode
is engaged.
SPI Compatible 3-Wire Serial Bus (DIS = 0)
The AD5161 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table 6.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 37).
I2C Compatible 2-Wire Serial Bus (DIS = 1)
The AD5161 can also be controlled via an I2C compatible serial
bus with DIS tied high. The RDACs are connected to this bus as
slave devices.
The first byte of the AD5161 is a slave address byte (see Table 7
and Table 8). It has a 7-bit slave address and a R/W bit. The six
MSBs of the slave address are 010110, and the following bit is
determined by the state of the AD0 pin of the device. AD0
allows the user to place up to two of the I2C compatible devices
on one bus.
The 2-wire I2C serial bus protocol operates as follows:
1.
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5161 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
Rev. C | Page 16 of 20
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 40). The
following byte is the slave address byte, which consists of
the 7-bit slave address followed by an R/W bit (this bit
determines whether data will be read from or written to
the slave device).
Data Sheet
AD5161
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. On the other hand, if the R/W bit is
low, the master will write to the slave device.
2.
A write operation contains an extra instruction byte that a
read operation does not contain. Such an instruction byte
in write mode follows the slave address byte. The first bit
(MSB) of the instruction byte is a don’t care.
The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper to the center tap where RWA = RWB.
This feature effectively writes over the contents of the
register, and thus, when taken out of reset mode, the
RDAC will remain at midscale.
The third MSB, SD, is a shutdown bit. A logic high causes
an open circuit at terminal A while shorting the wiper to
terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to
note that the shutdown operation does not disturb the
contents of the register. When brought out of shutdown,
the previous setting will be applied to the RDAC. Also,
during shutdown, new settings can be programmed. When
the part is returned from shutdown, the corresponding VR
setting will be applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
cares (see Table 7).
3.
4.
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 7).
5.
When all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 40). In read mode, the master will
issue a No Acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse which goes high
to establish a STOP condition (see Figure 41).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte will
update the RDAC output. For example, after the RDAC has
acknowledged its slave address and instruction bytes, the RDAC
output will update after these two bytes. If another byte is written to
the RDAC while it is still addressed to a specific slave device
with the same instruction, this byte will update the output of
the selected slave device. If different instructions are needed, the
write mode has to start again with a new slave address, instruction,
and data byte. Similarly, a repeated read function of the RDAC
is also allowed.
Readback RDAC Value
The AD5161 allows the user to read back the RDAC values in the
read mode. Refer to Table 7 and Table 8 for the programming format.
Multiple Devices on One Bus
Figure 44 shows two AD5161 devices on the same serial bus.
Each has a different slave address since the states of their AD0
pins are different. This allows each RDAC within each device to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully I2C
compatible interface.
+5V
RP
RP
SDA
MASTER
In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 41).
Rev. C | Page 17 of 20
SCL
+5V
SDA SCL
SDA SCL
AD0
AD0
AD5161
AD5161
Figure 44. Multiple AD5161 Devices on One I2C Bus
AD5161
Data Sheet
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
TERMINAL VOLTAGE OPERATING RANGE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two systems
operate the same signal at two different voltages, proper level
shifting is needed. For instance, one can use a 3.3 V E2PROM to
interface with a 5 V digital potentiometer. A level shifting scheme is
needed to enable a bidirectional communication so that the setting
of the digital potentiometer can be stored to and retrieved from
the E2PROM. Figure 45 shows one of the implementations. M1
and M2 can be any N-channel signal FETs, or if VDD falls below
2.5 V, low threshold FETs such as the FDV301N.
The AD5161 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed VDD or GND will be clamped by the internal forward
biased diodes (see Figure 48).
VDD1 = 3.3V
VDD
A
W
VDD2 = 5V
RP
RP
RP
B
RP
VSS
G
S
SDA1
D
S
SCL1
D
M2
3.3V
Figure 48. Maximum Terminal Voltages Set by VDD and VSS
SDA2
G
M1
SCL2
POWER-UP SEQUENCE
5V
AD5161
E2PROM
Figure 45. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 46 and Figure 47.
This applies to the digital input pins SDI/SDA, CLK/SCL, and
CS/AD0.
340
LOGIC
Vss
Figure 46. ESD Protection of Digital Pins
A,B,W
VSS
Figure 47. ESD Protection of Resistor Terminals
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 48), it is important to power
VDD/GND before applying any voltage to terminals A, B, and W;
otherwise, the diode will be forward biased such that VDD will
be powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/B/W. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic
capacitors of 0.01 μF to 0.1 μF. Low ESR 1 μF to 10 μF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 49). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
VDD
VDD
C1
C3 +
0.1F
10F
AD5161
GND
Figure 49. Power Supply Bypassing
Rev. C | Page 18 of 20
Data Sheet
AD5161
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 50. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD5161BRMZ5
AD5161BRMZ5-RL7
AD5161BRM10
AD5161BRM10-RL7
AD5161BRMZ10
AD5161BRMZ10-RL7
AD5161BRM50
AD5161BRM50-RL7
AD5161BRMZ50
AD5161BRMZ50-RL7
AD5161BRMZ100
AD5161BRMZ100-RL7
EVAL-AD5161DBZ
1
2
RAB (Ω)
5k
5k
10k
10k
10k
10k
50k
50k
50k
50k
100k
100k
See Note 2
Temperature
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
D0C#
D0C#
D0D
D0D
D0D#
D0D#
D0E
D0E
D0E#
D0E#
D0F#
D0F#
Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
The EVAL-AD5161DBZ evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
The AD5161 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2358 sq. mil.
Rev. C | Page 19 of 20
AD5161
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2003−2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03435-0-6/15(C)
Rev. C | Page 20 of 20
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