EVAL-AD5391EBZ

8-/16-Channel, 3 V/5 V, Serial Input, Single-Supply, 12-/14-Bit Voltage Output AD5390/AD5391/AD5392 Data Sheet FEATURES I2C-compatible interface Integrated functions channel monitor simultaneous output update via LDAC clear function to user-programmable code amplifier boost mode to optimize slew rate user-programmable offset and gain adjust toggle mode enables square wave generation thermal monitor Robust 6.5 kV HBM and 2 kV FICDM ESD rating AD5390: 16-channel, 14-bit voltage output DAC AD5391: 16-channel, 12-bit voltage output DAC AD5392: 8-channel, 14-bit voltage output DAC Guaranteed monotonic INL ±1 LSB max (AD5391) ±3 LSB max (AD5390-5/AD5392-5) ±4 LSB max (AD5390-3/AD5392-3) On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: −40°C to +85°C Rail-to-rail output amplifier Power-down mode Package types 64-lead LFCSP (9 mm × 9 mm) 52-lead LQFP (10 mm × 10 mm) User interfaces Serial SPI-, QSPI-, MICROWIRE-, and DSP-compatible (featuring data readback) APPLICATIONS Instrumentation and industrial control Power amplifier control Level setting (ATE) Control systems Microelectromechanical systems (MEMs) Variable optical attenuators (VOAs) Optical transceivers (MSA 300, XFP) FUNCTIONAL BLOCK DIAGRAM DVDD (×3) DGND (×3/×4) AVDD (×2) AGND (×2) DAC_GND (×2) 14 DCEN/AD1 INPUT REG 0 DIN/SDA SYNC/AD0 STATE MACHINE AND CONTROL LOGIC INTERFACE CONTROL LOGIC SDO INPUT REG 1 DAC REG 0 14 DAC 0 VOUT 0 m REG0 14 14 14 14 14 SCLK/SCL REFOUT/REFIN SIGNAL_GND (×2) 1.25V/2.5V REFERENCE AD5390 SPI/I2C REF_GND c REG0 14 14 14 R DAC REG 1 14 R DAC 1 VOUT 1 VOUT 2 m REG1 14 c REG1 R BUSY R VOUT 3 VOUT 4 PD 14 CLR RESET VIN15 INPUT REG 7 14 MON_IN1 MUX MON_IN2 14 DAC REG 6 14 VOUT 5 DAC 6 VOUT 6 m REG6 14 14 14 14 14 POWER-ON RESET VIN0 INPUT REG 6 c REG6 R 14 14 DAC REG 7 14 R DAC 7 VOUT 7 m REG7 c REG7 VOUT 8 R ×2 R LDAC MON_OUT 03773-001 VOUT 15 Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5390/AD5391/AD5392 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 I2C Write Operation ....................................................................... 28 Applications ....................................................................................... 1 4-Byte Mode ................................................................................ 28 Functional Block Diagram .............................................................. 1 3-Byte Mode ................................................................................ 29 Revision History ............................................................................... 3 2-Byte Mode ................................................................................ 30 General Description ......................................................................... 4 Specifications..................................................................................... 5 AD5390/AD5391/AD5392 On-Chip Special Function Registers ....................................................................................... 31 AD5390-5/AD5391-5/AD5392-5 Specifications ..................... 5 Control Register Write............................................................... 33 AD5390-5/AD5391-5/AD5392-5 AC Characteristics............. 7 Hardware Functions ....................................................................... 35 AD5390-3/AD5391-3/AD5392-3 Specifications ..................... 8 Reset Function ............................................................................ 35 AD5390-3/AD5391-3/AD5392-3 AC Characteristics........... 10 Asynchronous Clear Function.................................................. 35 Timing Characteristics................................................................... 11 BUSY and LDAC Functions...................................................... 35 Serial SPI-, QSPI-, MICROWIRE-, and DSP-Compatible Interface ....................................................................................... 11 Power-On Reset .......................................................................... 35 2 Power-Down ............................................................................... 35 I C Serial Interface...................................................................... 13 Microprocessor Interfacing ....................................................... 35 Absolute Maximum Ratings.......................................................... 14 Application Information ................................................................ 37 ESD Caution ................................................................................ 14 Power Supply Decoupling ......................................................... 37 Pin Configuratons and Function Descriptions .......................... 15 Power Supply Sequencing ......................................................... 38 Terminology .................................................................................... 18 Typical Configuration Circuit .................................................. 39 Typical Performance Characteristics ........................................... 19 AD5390/AD5391/AD5392 Monitor Function ....................... 40 Functional Description .................................................................. 23 Toggle Mode Function............................................................... 40 DAC Architecture ....................................................................... 23 Thermal Monitor Function ....................................................... 40 Data Decoding ............................................................................ 24 Outline Dimensions ....................................................................... 42 Interfaces .......................................................................................... 25 Ordering Guide .......................................................................... 43 DSP-, SPI-, and MICROWIRE-Compatible Serial Interface...... 25 I2C Serial Interface...................................................................... 27 Rev. F | Page 2 of 44 Data Sheet AD5390/AD5391/AD5392 REVISION HISTORY 6/14—Rev. E to Rev. F 1/09—Rev. B to Rev. C Deleted Table 1; Renumbered Sequentially ................................... 4 Changed AD5390-3/AD5391-3/AD5392-3 Input Current from ±10 µA (max) to ±1 µA (max); Table 3 .......................................... 8 Changes to Table 5 ..........................................................................11 Changes to Soft Reset Section .......................................................31 Changes to Reset Function Section ..............................................35 Replaced ADSP2101 with ADSP-BF527 ......................................36 Added Power Supply Sequencing Section ...................................38 Changes to Ordering Guide ...........................................................43 Updated Format ................................................................. Universal Changes to Figure 33 ...................................................................... 27 Added Figure 34 and Renumbered Sequentially ........................ 27 Changes to Figure 34 ...................................................................... 28 Changes to Table 28 ........................................................................ 33 Change order of Figure 41 and Figure 42 .................................... 36 Changes to Toggle Mode Function Section ................................. 37 6/12—Rev. D to Rev. E Changes to Table 1 ............................................................................ 4 Change to Accuracy Parameter, Gain Error, Table 2 .................... 5 Change to Accuracy Parameter, Gain Error, Table 4 .................... 8 Added Exposed Pad Notation to Figure 7 and Figure 8 ............15 5/12—Rev. C to Rev. D Changes to Product Title and Features Section ............................ 1 Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Table 5 ............................................................................ 9 Changes to Table 6 ..........................................................................10 Changes to Table 8 ..........................................................................13 Changes to Figure 8 and Figure 10 ...............................................14 Changes to Table 9 ..........................................................................16 Changes to Figure 17, Figure 18, Figure 19, And Figure 22 ......19 Changes to Figure 23, Figure 24, Figure 25, and Figure 26 .......20 Changes to Table 26 ........................................................................32 Changes to Ordering Guide ...........................................................40 3/06—Rev. A to Rev. B Changes to Figure 1 .......................................................................... 1 Changes to Table 9 .......................................................................... 14 Changes to Table 12 and Table 15 ................................................. 23 Updated Outline Dimensions........................................................ 39 Changes to Ordering Guide ........................................................... 40 10/04—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Figure 36 ...................................................................... 35 Changes to Figure 37 ...................................................................... 36 Changes to Figure 38 ...................................................................... 36 Changes to Ordering Guide ........................................................... 41 4/04—Revision 0: Initial Version Rev. F | Page 3 of 44 AD5390/AD5391/AD5392 Data Sheet GENERAL DESCRIPTION The AD5390/AD5391 are complete single-supply, 16-channel, 14-bit and 12-bit DACs, respectively. The AD5392 is a complete single-supply, 8-channel, 14-bit DAC. The devices are available in either a 64-lead LFCSP or a 52-lead LQFP. All channels have an on-chip output amplifier with rail-to-rail operation. All devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that optimizes the output amplifier slew rate. The AD5390/AD5391/AD5392 contain a 3-wire serial interface with interface speeds in excess of 30 MHz that are compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and an I2C-compatible interface supporting a 400 kHz data transfer rate. An input register followed by a DAC register provides doublebuffering, allowing DAC outputs to be updated independently or simultaneously using the LDAC input. Each channel has a programmable gain and offset adjust register, letting the user fully calibrate any DAC channel. Power consumption is typically 0.25 mA per channel. Rev. F | Page 4 of 44 Data Sheet AD5390/AD5391/AD5392 SPECIFICATIONS AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient2 DC Crosstalk2 REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output3 Output Voltage Reference TC Output Impedance OUTPUT CHARACTERISTICS2 Output Voltage Range4 Short-Circuit Current Load Current Capacitive Load Stability RL = ∞ RL = 5 kΩ DC Output Impedance MONITOR OUTPUT PIN Output Impedance Three-State Leakage Current LOGIC INPUTS2 VIH, Input High Voltage VIL, Input Low Voltage DVDD > 3.6 V DVDD ≤ 3.6 V Input Current Pin Capacitance AD5390-51 AD5392-51 AD5391-51 Unit Test Conditions/Comments 14 ±3 −1/+2 4 ±4 12 ±1 ±1 4 ±4 Bits LSB max LSB max mV max mV max Guaranteed monotonic over temperature ±5 ±0.05 ±0.06 2 1 ±5 ±0.05 ±0.06 2 1 µV/°C typ % FSR max % FSR max ppm FSR/°C typ LSB max 2.5 2.5 V 1 ±1 1 V to AVDD/2 1 ±1 1 V to AVDD/2 MΩ min µA max V min/max 2.495/2.505 1.22/1.28 ±10 ±15 800 2.495/2.505 1.22/1.28 ±10 ±15 800 V min/max V min/max ppm max ppm max Ω typ 0/AVDD 40 ±1 0/AVDD 40 ±1 V min/max mA max mA max 200 1000 0.6 200 1000 0.6 pF max pF max Ω max 1000 100 1000 100 Ω typ nA typ 2 2 V min 0.8 0.6 ±10 10 0.8 0.6 ±10 10 V max V max µA max pF max Measured at Code 32 in the linear region (AD5390-5/AD5391-5); measured at Code 8 in the linear region (AD5391-5) At 25°C TMIN to TMAX ±1% for specified performance, AVDD = 2 × REFIN + 50 mV Typically 100 MΩ Typically ±30 nA Enabled via internal/external bit in control register; REF select bit in control register selects the reference voltage At ambient, optimized for 2.5 V operation At ambient when 1.25 V reference is selected Temperature range: 25°C to 85°C Temperature range: −40°C to +85°C DVDD = 2.7 V to 5.5 V Rev. F | Page 5 of 44 Total for all pins, TA = TMIN to TMAX AD5390/AD5391/AD5392 Data Sheet AD5390-51 AD5392-51 AD5391-51 Unit Test Conditions/Comments 0.7 × DVDD 0.3 × DVDD ±1 0.05 × DVDD 8 50 0.7 × DVDD 0.3 × DVDD ±1 0.05 × DVDD 8 50 V min V max µA max V min pF typ ns max SMBus-compatible at DVDD < 3.6 V SMBus-compatible at DVDD < 3.6 V 0.4 DVDD − 1 0.4 DVDD − 0.5 ±1 5 0.4 DVDD − 1 0.4 DVDD − 0.5 ±1 5 V max V min V max V min µA max pF typ DVDD = 5 V ± 10%, sinking 200 µA DVDD = 5 V ± 10%, SDO only, sourcing 200 µA DVDD = 2.7 V to 3.6 V, sinking 200 µA DVDD = 2.7 V to 3.6 V SDO only, sourcing 200 µA 0.4 0.6 ±1 8 0.4 0.6 ±1 8 V max V max µA max pF typ ISINK = 3 mA ISINK = 6 mA 4.5/5.5 2.7/5.5 4.5/5.5 2.7/5.5 V min/max V min/max −85 0.375 −85 0.375 AIDD 0.475 0.475 DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation 1 20 20 35 1 20 20 35 dB typ mA/channel max mA/channel max mA max µA max µA max mW max 20 20 mW max Parameter LOGIC INPUTS (SCL, SDA Only) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection LOGIC OUTPUTS (BUSY, SDO)2 Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity2 ∆Midscale/∆AVDD AIDD Input filtering suppresses noise spikes of 3.6 V DVDD ≤ 3.6 V Input Current Pin Capacitance AD5390-31 AD5392-31 AD5391-31 Unit 14 ±4 −1/+2 4 ±4 ±5 ±0.05 ±0.1 2 1 12 ±1 ±1 4 ±4 ±5 ±0.05 ±0.1 2 1 Bits LSB max LSB max mV max mV max µV/°C typ % FSR max % FSR max ppm FSR/°C typ LSB max 1.25 1 ±1 1 V to AVDD/2 1.25 1 ±1 1 V to AVDD/2 V MΩ min µA max V min/max 1.245/1.255 2.47/2.53 ±10 ±15 800 1.245/1.255 2.47/2.53 ±10 ±15 800 V min/max V min/max ppm max ppm max Ω typ 0/AVDD 40 ±1 0/AVDD 40 ±1 V min/max mA max mA max 200 1000 0.6 200 1000 0.6 pF max pF max Ω max 1000 100 1000 100 Ω typ nA typ 2 2 V min 0.8 0.6 ±1 10 0.8 0.6 ±1 10 V max V max µA max pF max Test Conditions/Comments Guaranteed monotonic over temperature Measured at code 64 in the linear region At 25°C TMIN to TMAX ±1% for specified performance Typically 100 MΩ Typically ±30 nA Enabled via internal/external bit in control register; REF select bit in control register selects the reference voltage At ambient, optimized for 1.25 V operation At ambient when 2.5 V reference is selected Temperature range: 25°C to 85°C Temperature range: −40°C to +85°C DVDD = 2.7 V to 5.5 V Rev. F | Page 8 of 44 Total for all pins. TA = TMIN to TMAX Data Sheet AD5390/AD5391/AD5392 AD5390-31 AD5392-31 AD5391-31 Unit Test Conditions/Comments 0.7 × DVDD 0.3 × DVDD ±1 0.05 × DVDD 50 0.7 × DVDD 0.3 × DVDD ±1 0.05 × DVDD 50 V min V max µA max V min ns max SMBus-compatible at DVDD < 3.6 V SMBus-compatible at DVDD < 3.6 V 0.4 DVDD − 0.5 DVDD − 0.1 ±1 5 0.4 DVDD − 0.5 DVDD − 0.1 ±1 5 V max V min V min µA max pF typ DVDD = 2.7 V to 5.5 V, sinking 200 µA DVDD = 2.7 V to 3.6 V, SDO only, sourcing 200 µA DVDD = 4.5 V to 5.5 V, SDO only, sourcing 200 µA 0.4 0.6 ±1 8 0.4 0.6 ±1 8 V max V max µA max pF typ ISINK = 3 mA ISINK = 6 mA 2.7/3.6 2.7/5.5 2.7/3.6 2.7/5.5 V min/max V min/max −85 0.375 −85 0.375 AIDD 0.475 0.475 DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation 1 20 20 21 1 20 20 21 dB typ mA/channel max mA/channel max mA max µA max µA max mW max 12 12 mW max Parameter Logic Inputs (SCL, SDA Only) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis Glitch Rejection Logic Outputs (BUSY, SDO)2 Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance Logic Output (SDA)2 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity2 ∆Midscale/∆AVDD AIDD Input filtering suppresses noise spikes