EVAL-AD5560EBUZ

Data Sheet 1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs AD5560 FEATURES Programmable device power supply (DPS) FV, MI, MV, FNMV functions 5 internal current ranges (on-chip RSENSE) ±5 µA, ±25 µA, ±250 µA, ±2.5 mA, ±25 mA 2 external high current ranges (external RSENSE) EXTFORCE1: ±1.2 A maximum EXTFORCE2: ±500 mA maximum Integrated programmable levels All 16-bit DACs: force DAC, comparator DACs, clamp DACs, offset DAC, OSD DAC, DGS DAC Programmable Kelvin clamp and alarm Offset and gain correction registers on-chip Ramp mode on force DAC for power supply slewing Programmable slew rate feature, 1 V/μs to 0.3 V/μs DUTGND Kelvin sense and alarm 25 V FV span with asymmetrical operation within −22 V/+25 V On-chip comparators Gangable for higher current Guard amplifier System PMU connections Current clamps Die temperature sensor and shutdown feature On-chip diode thermal array Diagnostic register allows access to internal nodes Open-drain alarm flags (temperature, current clamp, Kelvin alarm) SPI-/MICROWIRE-/DSP-compatible interface 64-lead (10 mm × 10 mm) TQFP with exposed pad (on top) 72-ball (8 mm × 8 mm) flip-chip BGA APPLICATIONS Automatic test equipment (ATE) Device power supply GENERAL DESCRIPTION The AD5560 is a high performance, highly integrated device power supply consisting of programmable force voltages and measure ranges. This part includes the required DAC levels to set the programmable inputs for the drive amplifier, as well as clamping and comparator circuitry. Offset and gain correction is included on-chip for DAC functions. A number of programmable measure current ranges are available: five internal fixed ranges and two external customer-selectable ranges (EXTFORCE1 and EXTFORCE2) that can supply currents up to ±1.2 A and ±500 mA, respectively. The voltage range possible at this high current level is limited by headroom and the maximum power Rev. E dissipation. Current ranges in excess of ±1.2 A or at high current and high voltage combinations can be achieved by paralleling or ganging multiple DPS devices. Open-drain alarm outputs are provided in the event of overcurrent, overtemperature, or Kelvin alarm on either the SENSE or DUTGND line. The DPS functions are controlled via a simple 3-wire serial interface compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards running at clock speeds of up to 50 MHz. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5560 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Adjusting the Autocompensation Mode ................................. 39 Applications ....................................................................................... 1 Dealing with Parallel Load Capacitors .................................... 39 General Description ......................................................................... 1 DAC Levels .................................................................................. 39 Revision History ............................................................................... 3 Force and Comparator DACs ................................................... 39 Functional Block Diagram .............................................................. 4 Clamp DACs ............................................................................... 39 Specifications..................................................................................... 5 OSD DAC .................................................................................... 40 Timing Characteristics .............................................................. 13 DUTGND DAC .......................................................................... 40 Timing Diagrams........................................................................ 13 Offset DAC .................................................................................. 40 Absolute Maximum Ratings .......................................................... 15 Offset and Gain Registers.......................................................... 40 ESD Caution ................................................................................ 15 Reference Selection .................................................................... 41 Pin Configurations and Function Descriptions ......................... 16 Calibration................................................................................... 41 Typical Performance Characteristics ........................................... 20 Additional Calibration ............................................................... 41 Terminology .................................................................................... 28 System Level Calibration ........................................................... 41 Theory of Operation ...................................................................... 29 Choosing AVDD/AVSS Power Supply Rails ............................... 42 Force Amplifier ........................................................................... 29 Choosing HCAVSSx and HCAVDDx Supply Rails ................... 42 DAC Reference Voltage (VREF) ............................................... 29 Power Dissipation....................................................................... 42 Open-Sense Detect (OSD) Alarm and Clamp ....................... 29 Package Composition and Maximum Vertical Force ............ 43 Device Under Test Ground (DUTGND)................................. 29 Slew Rate Control ....................................................................... 43 GPO .............................................................................................. 29 Serial Interface ................................................................................ 45 Comparators................................................................................ 30 SPI Interface ................................................................................ 45 Current Clamps .......................................................................... 30 SPI Write Mode .......................................................................... 45 Short-Circuit Protection ............................................................ 30 SDO Output ................................................................................ 45 Guard Amplifier ......................................................................... 30 RESET Function ......................................................................... 45 Compensation Capacitors ......................................................... 30 BUSY Function ........................................................................... 45 Current Range Selection ............................................................ 31 LOAD Function .......................................................................... 45 High Current Ranges ................................................................. 31 Register Update Rates ................................................................ 46 Ideal Sequence for Gang Mode................................................. 32 Control Registers ............................................................................ 47 Compensation for Gang Mode ................................................. 32 DPS and DAC Addressing ........................................................ 47 System Force/Sense Switches .................................................... 32 Readback Mode .......................................................................... 58 Die Temperature Sensor and Thermal Shutdown.................. 33 DAC Readback............................................................................ 58 Measure Output (MEASOUT) ................................................. 33 Power-On Default ...................................................................... 58 VMID Voltage ................................................................................ 33 Using the HCAVDDx and HCAVSSx Supplies .......................... 60 Force Amplifier Stability............................................................ 36 Power Supply Sequencing ......................................................... 60 Poles and Zeros in a Typical System ........................................ 37 Required External Components ............................................... 61 Minimizing the Number of External Compensation Components ................................................................................ 37 Power Supply Decoupling ......................................................... 62 Extra Poles and Zeros in the AD5560...................................... 37 Compensation Strategies ........................................................... 38 Optimizing Performance for a Known Capacitor Using Autocompensation Mode .......................................................... 38 Applications Information .............................................................. 63 Thermal Considerations............................................................ 63 Temperature Contour Map on the Top of the Package ......... 64 Outline Dimensions ....................................................................... 65 Ordering Guide .......................................................................... 66 Rev. E | Page 2 of 66 Data Sheet AD5560 REVISION HISTORY 5/2016—Rev. D to Rev. E Changes to Figure 1........................................................................... 4 Changes to High Current Ranges Section ...................................31 Added Calibration Section, Reducing Zero-Scale Error Section, Reducing Gain Error Section, Calibration Example Section, Additional Calibration Section, and System Level Calibration Section ..............................................................................................41 Added Figure 58; Renumbered Sequentially ...............................42 Changes to Table 25 ........................................................................57 9/2009—Rev. A to Rev. B Changes to Table 1, Measure Current and Measure Voltage Parameters .......................................................................................... 6 Changes to Die Temperature Sensor and Thermal Shutdown Section ........................................................................... 31 Changes to Table 10 and Table 11 ................................................. 32 Changes to Table 18, Bit 15 ............................................................ 45 Changes to Table 23, Bits[15:12] ................................................... 50 Changes to Table 25 ........................................................................ 54 8/2012—Rev. C to Rev. D Added 72-Ball Flip-Chip BGA (Throughout) ............................... 1 Added Figure 7 and Table 5 (Renumbered Sequentially) ..........18 Added Applications Information Section ....................................62 Updated Outline Dimensions ........................................................64 Changes to Ordering Guide ...........................................................65 12/2008—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 4 Changes to Table 1 ............................................................................ 4 Changes to Table 2 .......................................................................... 13 Changes to Table 3 .......................................................................... 15 Changes to Open-Sense Detect (OSD) Alarm and Clamp ....... 27 Changes to Figure 53 ...................................................................... 30 Change to gm Maximum Rating, Table 13 ................................... 34 Changes to Table 19 ........................................................................ 46 Changes to Bit 7, Bit 8 Functions, Table 21 ................................. 48 Changes to Power Supply Decoupling Section ........................... 59 10/2010—Rev. B to Rev. C Changes to Force Output Voltage Parameter and Load Transient Response Parameter, Table 1............................................................ 5 Changes to Figure 52 ......................................................................29 Changes to Table 9 ..........................................................................32 11/2008—Revision 0: Initial Version Rev. E | Page 3 of 66 VREF Rev. E | Page 4 of 66 Figure 1. SW16 MEASOUT RESET GPO 16 16 OFFSET OFFSET 16-BIT DAC ISENSE VSENSE KSENSE TSENSE DUTGND SENSE DIAGNOSTIC A DIAGNOSTIC B ×2 REG 16 SDO SCLK SDI SYNC BUSY SERIAL SPI INTERFACE ×1/×0.2 MUX AND GAIN ×8 ×8 ×2 REG 16-BIT DAC R4 A B TMPALM DIE TEMP SENSOR AND THERMAL SHUTDOWN SW3 FIN CLAMP CONTROL S/W INH R3 OFFSET 16-BIT DAC OFFSET DAC OFFSET CLL 16-BIT 16-BIT DAC THERMAL SHUTDOWN R2 16 16 16 CLH CLEN/ LOAD CLALM CPL ×1 REG M REG C REG ×1 REG M REG C REG AGND R1 CLH DAC OFFSET DAC CLH 16-BIT ×2 REG ×2 REG ×2 REG DGND CPOL POWER-ON RESET ×1 ×1 RAMP REG ×1 REG M REG C REG ×1 ×1 REG M REG C REG ×1 REG M REG C REG DVCC CPH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 AV DD CPOH/ CPO HW_INH/LOAD RCLK REFGND AGND B A SW1 C VREF SW2 A B C 6kΩ VREF 16 AGND VSENSE ISENSE 16 OSD DAC ×1 – + ×10 + OR ×20 – DAC MID CODE VOLTAGE TO CENTER IRANGE LOCAL FEEDBACK EXTFORCE1 EXTFORCE2 SLEW RATE CONTROL gm 40µA/V 80µA/V 300µA/V 900µA/V RZ: 500Ω TO 1.6MΩ CC0 CC1 CC2 CC3 25kΩ DGS DAC RP: 200Ω TO 1MΩ 100kΩ + – + – + – + – SW4 KELALM ALARM BLOCK KSENSE DUTGND SENSE GUARD DUTGND SENSE AND ALARM INHIBIT OPEN SENSE DETECT 8pF RSENSE SW7 25mA SW17 5µA 25µA 250µA 2.5mA AD5560 GUARD AMP SW15 SW14 SW13 100kΩ 20kΩ 2kΩ 200Ω 20Ω SW5a SW5b HCAV DD1x HCAV SS1x HCAV SS2x HCAV DD2x SW18 SW9 10kΩ SW11 SW8 UP TO ±500mA UP TO ±1.2A MUX SW6 DUTGND GUARD/ SYS_DUTGND SENSE EXTMEASIL EXTMEASIH2 EXTMEASIH1 SYS_SENSE FORCE SYS_FORCE CF0 TO CF4 EXTFORCE2 EXTFORCE1 CF0 TO CF4 MASTER_OUT SLAVE_IN DUT EXT RSENSE2 EXT RSENSE1 FUNCTIONAL BLOCK DIAGRAM 07779-001 AV SS AD5560 Data Sheet Data Sheet AD5560 SPECIFICATIONS HCAVDDx ≤ (AVSS + 33 V), HCAVDDx ≤ AVDD, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, DVCC = 2.3 V to 5.5 V, VREF = 5 V, gain (m), offset (c), and DAC offset registers are at default values; AGND = DGND = 0 V; TJ = 25°C to 90°C, maximum specifications, unless otherwise noted. FSV is full-scale voltage, FSVR is full-scale voltage range, FSC is full-scale current, FSCR is full-scale current range. Table 1. Parameter FORCE VOLTAGE Force Output Voltage1 EXTFORCE1 Max Unit Test Conditions/Comments AVSS + 2.25 HCAVSS1x + 1.75 HCAVSS1x + 1.25 AVDD − 2.25 HCAVSS1x − 1.75 HCAVDD1x − 1.25 V V V EXTFORCE2 AVSS + 2.25 HCAVSS2x + 1.75 HCAVSS2x + 1.25 AVDD − 2.25 HCAVDD2x − 1.75 HCAVDD2x − 1.25 V V V FORCE AVSS + 2.75 AVDD − 2.75 V Headroom/Footroom1 −2.75 +2.75 V Headroom/Footroom1 −2.25 +2.25 V Force Output Voltage Span −22 +25 V Allow ±500 mV for external RSENSE voltage drop Allow ±500 mV for external RSENSE voltage drop Allow ±500 mV for external RSENSE voltage drop; reduced headroom/footroom, clamps must be enabled2 Allow ±500 mV for external RSENSE voltage drop Allow ±500 mV for external RSENSE voltage drop Allow ±500 mV for external RSENSE voltage drop; reduced headroom/footroom, clamps must be enabled2 Internal current ranges, includes ±500 mV for internal RSENSE voltage drop Internal current ranges to AVDD/AVSS, includes ±500 mV for internal RSENSE voltage drop. External current ranges, EXTFORCE1/ EXTFORCE2 to HCAVDDx and HCAVSSx supplies; includes ±500 mV for external RSENSE voltage drop.\ May be a skewed range but within headroom requirements and maximum power dissipation for current range Forced Voltage Linearity Error Forced Voltage Offset Error −2 −50 +2 +50 mV mV +25 μV/°C mV ppm/°C Forced Voltage Offset Error Tempco1 Forced Voltage Gain Error Forced Voltage Gain Error Tempco1 Short-Circuit Current Limit3 EXTFORCE1 EXTFORCE2 FORCE Min Typ 27 −25 4 −3.5 −1.25 −75 ±2.7 ±0.9 ±50 +3.5 +1.25 +75 A A mA −20 ±10 +20 mA +64 +1 +0.4 70 mA mV mV mV 140 mV NSD1 MEASURE CURRENT RANGES 350 nV/√Hz Internal Sense Resistors1 100 20 2 200 20 kΩ kΩ kΩ Ω Ω Active CFx Buffer DC Load Regulation1 Load Transient Response1 −64 −1 −0.4 Rev. E | Page 5 of 66 Uncalibrated, use c register to calibrate, measured at midscale Standard deviation = 23 μV/°C Uncalibrated, use m register to calibrate Standard deviation = 3 ppm/°C Clamps off Positive and negative dc short-circuit current Positive and negative dc short-circuit current ±25 mA range, positive and negative dc shortcircuit current All other ranges, positive and negative dc shortcircuit current EXTFORCE1 range, ±1 A load current change EXTFORCE2 range, ±0.5 A load current change 1.2 A load step into 100 μF DUT capacitance (10 mΩ ESR), autocompensation mode 1.2 A load step into 30 µF DUT capacitance (10 mΩ ESR), autocompensation mode Measured at 1 kHz, at output of FORCE Sense resistors are trimmed to within 1%, nominal ±500 mV VRSENSE ±5 µA current range ±25 µA current range ±250 µA current range ±2.5 mA current range ±25 mA current range AD5560 Parameter Measure Current Ranges Data Sheet Min Typ Max Unit ±5 ±25 ±250 ±2.5 ±25 ±500 µA µA µA mA mA mA ±1200 mA MEASURE CURRENT Differential Input Voltage Range1 Output Voltage Span1 Offset Error Offset Error Tempco1 Offset Error Offset Error Tempco1 Offset Error Offset Error Tempco1 Offset Error Offset Error Tempco1 Gain Error Gain Error1 Gain Error Tempco1 MEASOUT Gain = 1 Linearity Error MEASOUT Gain = 0.2 Linearity Error Linearity Error MEASOUT Gain = 0.2 Linearity Error Linearity Error MEASOUT Gain = 0.2 Linearity Error Linearity Error Common-Mode Error −0.64 −0.7 25 −1 +1 −1 −1.5 +1.5 −1 −1.5 +1.5 3 −3 +3 8 −2 −1 +2 +1 20 V V V % FSC ppm of FSC/°C % FSC ppm of FSC/°C % FSC ppm of FSC/°C % FSC ppm of FSC/°C % FSC % FSC ppm/°C −0.01 +0.01 % FSCR −0.06 −0.05 +0.06 +0.05 % FSCR % FSCR −0.125 −0.175 +0.125 +0.175 % FSCR % FSCR −0.0875 −0.1 −0.005 +0.0875 +0.1 +0.005 % FSCR % FSCR %FSVR/V NSD1 MEASURE VOLTAGE Measure Voltage Range1 Gain Error Gain Error Tempco1 MEASOUT Gain = 1 Linearity Error Offset Error Offset Error Tempco1 NSD1 +0.64 +0.7 900 nV/√Hz 550 nV/√Hz 170 nV/√Hz 110 nV/√Hz AVSS + 2.75 −0.1 AVDD − 2.75 +0.1 3 −2 −12 +2 +12 2 100 Rev. E | Page 6 of 66 V % FS ppm/°C mV mV µV/°C nV/√Hz Test Conditions/Comments Specified current ranges with VREF = 5 V and MI gain = 20, or with VREF = 2.5 V and MI gain = 5 Set using internal sense resistor Set using internal sense resistor Set using internal sense resistor Set using internal sense resistor Set using internal sense resistor EXTFORCE2, set by user with external sense resistor, limited by headroom requirements and maximum power dissipation EXTFORCE1, set by user with external sense resistor, limited by headroom requirements and maximum power dissipation All offset DAC/supply combinations settings, all gain settings are measure current = (IDUT × RSENSE × MI gain), unless otherwise noted Maximum voltage across RSENSE, MI gain = 20 Maximum voltage across RSENSE, MI gain = 10 Measure current block alone (internal node) At 0 A, MI gain = 20, MEASOUT gain = 1 Standard deviation = 13 ppm/°C At 0 A, MI gain = 10, MEASOUT gain = 1 Standard deviation = 13 ppm/°C At 0 A, MI gain = 20, MEASOUT gain = 0.2 Standard deviation = 13 ppm/°C At 0 A, MI gain = 10, MEASOUT gain = 0.2 Standard deviation = 15 ppm/°C Internal current ranges, all gain settings External current ranges, excluding RSENSE Standard deviation = 5 ppm/°C All supply conditions MI gain = 20 and 10 Nominal supply (±16.5 V, 0x8000 offset DAC) MI gain = 20 MI gain = 10 Low supply (−25 V/+8 V, 0xD4EB offset DAC) MI gain = 20 MI gain = 10 High supply (−5 V/+28 V, 0xD1D offset DAC) MI gain = 20 MI gain = 10 % of FS change at measure output per volts change in DUT voltage MI gain = 20, MEASOUT gain = 1, measured at MEASOUT at 1 kHz, inputs grounded MI gain = 10, MEASOUT gain = 1, measured at MEASOUT at 1 kHz, inputs grounded MI gain = 20, MEASOUT gain = 0.2, measured at MEASOUT at 1 kHz, inputs grounded MI gain = 10, MEASOUT gain = 0.2, measured at MEASOUT at 1 kHz, inputs grounded MEASOUT Gain 1 and MEASOUT Gain 0.2 All voltage ranges Standard deviation = 2 ppm/°C Standard deviation = 12 µV/°C At 1 kHz, at MEASOUT, inputs grounded Data Sheet Parameter MEASOUT Gain = 0.2 Linearity Error Offset Error Offset Error Tempco1 AD5560 Min Max Unit Test Conditions/Comments −5.5 +5.5 mV −9 +24 mV −4 +13 mV +20 10 mV µV/°C 50 nV/√Hz Referred to MV input, nominal supply (±16.5 V, 0x8000 offset DAC) Referred to MV input, low supply (−25 V/+8 V, 0xD4EB offset DAC) Referred to MV input, high supply (−5 V/+28 V, 0xD1D offset DAC) Referred to MV output Standard deviation = 12 µV/°C, referred to MV output At 1 kHz, at MEASOUT, inputs grounded Includes SYS_SENSE, SYS_FORCE, EXTFORCE1, EXTFORCE2, EXTMEASIH1, EXTMEASIH2, EXTMEASIL, FORCE, and SENSE; measured with PD = 1, SW-INH = 0 (power up and tristate) −30 NSD1 COMBINED LEAKAGE Leakage Current Leakage Current Tempco1 SENSE INPUT Leakage Current Leakage Current Tempco1 Pin Capacitance1 EXTMEASIH1, EXTMEASIH2, EXTMEASIL Leakage Current Leakage Current Tempco1 Pin Capacitance1 FORCE OUTPUT, FORCE Maximum Current Drive1 Leakage Current Leakage Current Tempco1 Pin Capacitance1 EXTFORCE1 OUTPUTS Maximum Current Drive1 Leakage Current Leakage Current Tempco1 Pin Capacitance1 EXTFORCE2 OUTPUTS Maximum Current Drive1 Leakage Current Leakage Current Tempco1 Pin Capacitance1 SYS_SENSE Voltage Range Leakage Current Leakage Current Tempco1 Path On Resistance Pin Capacitance1 Typ −37.5 −30 ±0.1 −2.5 +37.5 +30 ±0.4 nA nA nA/°C +2.5 nA ±0.01 10 −2.5 ±0.01 5 nA ±0.03 120 mA nA +1200 mA −7.5 +7.5 nA ±0.06 nA/°C pF −500 +500 mA −5 +5 nA ±0.05 nA/°C pF AVDD +2.5 ±0.025 280 V nA nA/°C Ω pF AVSS −2.5 ±0.005 Measured with PD = 1, SW-INH = 0 (power-up and tristate) nA/°C pF −1200 ±0.02 100 Measured with PD = 1, SW-INH = 0 (power-up and tristate) nA/°C pF +30 +10 ±0.03 275 Measured with PD = 1, SW-INH = 0 (power-up and tristate) nA/°C pF +2.5 −30 −10 TJ = 25°C to 70°C 5 Rev. E | Page 7 of 66 Set with external sense resistor, limited by headroom and power dissipation Measured with PD = 1, SW-INH = 0 (power-up and tristate) Set with external sense resistor, limited by headroom and power dissipation Measured with PD = 1, SW-INH = 0 (power-up and tristate) SYS_SENSE high-Z, force amplifier inhibited AVDD = 16.5 V, AVSS = −16.5 V AD5560 Parameter SYS_FORCE Voltage Range Current Carrying Capability1 Leakage Current Leakage Current Tempco1 Path On Resistance Pin Capacitance1 SYS_DUTGND Voltage Range Path On Resistance CURRENT CLAMP Clamp Accuracy Data Sheet Min Typ AVSS −25 −2.5 ±0.005 Max Unit AVDD +25 +2.5 ±0.025 35 V mA nA nA/°C Ω pF AVDD 400 V Ω Programmed clamp value + 10 Programmed clamp value + 20 % of FS 5 AVSS 300 VCLL to VCLH1 Programmed clamp value Programmed clamp value 2 VCLL to 0 A1 1 V VCLH to 0 A1 1 V % of FS V Clamp Activation Response Time1 20 100 μs Clamp Recovery1 Alarm Delay 1 2 50 5 μs μs FORCE AMPLIFER Slew Rate1 Maximum Stable Load Capacitance1 Voltage Overshoot/Undershoot1 SETTLING TIME (FORCE AMPLIFER) FV (1200 mA EXTFORCE1 Range)1 FV (900 mA EXTFORCE1 Range)1 FV (500 mA EXTFORCE2 Range)1 FV (300 mA EXTFORCE2 Range)1 FV (25 mA Range)1, 3 FV (2.5 mA Range)1, 3 FV (250 µA Range)1, 3 FV (25 µA Range)1, 3 FV (5 µA Range)1, 3 FV (180 mA EXTFORCE1 Range)1 FV (100 mA EXTFORCE2 Range)1 FV (180 mA EXTFORCE1 Range)1 FV (100 mA EXTFORCE2 Range)1 FV (180 mA EXTFORCE1 Range)1 FV (100 mA EXTFORCE2 Range)1 1 0.312 160 5 Compensation Register 1 = 0x4880 (229 nF to 380 nF, ESR 74 to 140 mΩ) 16 25 18 30 34 53 25 50 125 180 300 500 300 500 400 600 20 40 Compensation Register 1 = 0x8880 (1.7 μF to 2.9 μF, ESR 74 to 140 mΩ) 16 25 60 80 Compensation Register 1 = 0xB880 (7.9μF to 13 μF, ESR 74 to 140 mΩ) 55 70 210 260 Compensation Register 1 = 0xC880 (13 μF to 22 μF, ESR 74 to 140 mΩ) 65 80 310 370 Rev. E | Page 8 of 66 V/µs V/µs µF % Test Conditions/Comments SYS_FORCE high-Z, force amplifier inhibited AVDD = 16.5 V, AVSS = −16.5 V AVDD = 16.5 V, AVSS = −16.5 V MI gain = 20, with clamp separation of 2 V, and 1 V separation from AGND/0 A MI gain = 10, with clamp separation of 2 V, and 1 V separation from AGND/0 A 10% of FSCR (MI gain = 20), 20% of FSCR (MI gain = 10), restriction to prevent both clamps activating together 5% of FSCR (MI gain = 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level 5% of FSCR (MI gain 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level Measured from BUSY going low to visible clamping Measured from BUSY going low to visible recovery Time for CLALM to flag Fastest slew rate, controlled via serial interface Slowest slew rate, controlled via serial interface Of programmed value (≥1 V) To within 10 mV of programmed value µs µs µs µs µs µs µs µs µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 400 kΩ, CDUT = 0.22 µF, full dc load 1 V step, RDUT = 200 kΩ, CDUT = 0.22 µF, full dc load µs µs 3 V step, CDUT = 2.2 µF, full dc load 8 V step, CDUT = 2.2 µF, full dc load µs µs 3 V step, CDUT = 10 µF, full dc load 8 V step, CDUT = 10 µF, full dc load µs µs 3 V step, CDUT = 20 µF, full dc load 8 V step, CDUT = 20 µF, full dc load Data Sheet AD5560 Parameter SETTLING TIME (FV, MEASURE CURRENT) MI (1200 mA EXTFORCE1 Range)1 MI (900 mA EXTFORCE1 Range)1 MI (500 mA EXTFORCE2 Range)1 MI (300 mA EXTFORCE2 Range)1 MI (25 mA Range)1, 3 MI (2.5 mA Range)1, 3 MI Buffer Alone1 Min Typ Max Compensation Register 1 = 0x4880 (229 nF to 380 nF, ESR 74 to 140 mΩ) 30 40 32 42 69 95 70 100 650 6400 10 15 Unit Test Conditions/Comments To within 10 mV of programmed value µs µs µs µs µs µs µs SETTLING TIME (FV, MEASURE VOLTAGE) MV (1200 mA Range)1 MV (900 mA Range)1 MV (500 mA Range)1 MV (300 mA Range)1 MV (25 mA Range)1, 3 MV (2.5 mA Range)1, 3 MV (250 µA Range)1, 3 MV Buffer Alone1 Compensation Register 1 = 0x4880 (229 nF to 380 nF, ESR 74 to 140 mΩ) 16 20 34 25 125 180 300 500 300 500 2 5 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load 0.5 V step using MEASOUT high-Z to within 10 mV of final value To within 10 mV of programmed value µs µs µs µs µs µs µs µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load 10 V step using MEASOUT high-Z to within 10 mV of final value To within 100 mV of programmed value 3.7 V step, RDUT = 3.1 Ω, CDUT = 0.22 µF, full dc load 3 V step, RDUT = 16 Ω, CDUT = 0. 22 µF to 20 μF, full dc load 8 V step, RDUT = 33.3 Ω, CDUT = 0. 22 µF to 20 μF, full dc load 20 V step, RDUT = 400 Ω, CDUT = 0.22 µF, full dc load SETTLING TIME (FV) SAFE MODE FV (1200 mA EXTFORCE1 Range1 FV (180 mA EXTFORCE1 Range)1 25 303 µs µs FV (100 mA EXTFORCE2 Range)1 660 µs FV (25 mA Range)1, 3 SWITCHING TRANSIENTS Range Change Transient1 760 1000 µs 0.5 % of FV 20 DAC SPECIFICATIONS Force/Comparator/Offset DACs Resolution Voltage Output Span Differential Nonlinearity1 Offset DAC Gain Error Clamp DAC Resolution Voltage Output Span Differential Nonlinearity1 OSD DAC Resolution Voltage Output Span Differential Nonlinearity1 DGS DAC Resolution Voltage Output Span Differential Nonlinearity1 Comparator DAC Dynamic Output Voltage Settling Time1 Slew Rate1 Digital-to-Analog Glitch Energy1 Glitch Impulse Peak Amplitude1 mV CDUT = 10 μF, changing from higher to adjacent lower ranges (except EXTFORCE1 to EXTFORCE2) CDUT = 10 μF, changing from lower (5 µA) to higher range (EXTFORCE1) CDUT = 100 μF, changing between all ranges 0.5 % of FV −22 +25 Bits V −1 +1 LSB −20 +20 mV −22 +25 Bits V −1 +1 LSB 5 +2 Bits V LSB VREF = 5 V 5 +2 Bits V LSB VREF = 5 V 16 VREF = 5 V, minimum and maximum values set by offset DAC Guaranteed monotonic CLL < CLH 16 16 0.62 −2 16 0 −2 3.5 1 10 6 40 µs V/µs nV-s mV Rev. E | Page 9 of 66 VREF = 5 V, minimum and maximum values set by offset DAC Guaranteed monotonic 1 V change to 1 LSB AD5560 Data Sheet Parameter REFERENCE INPUT VREF DC Input Impedance VREF Input Current VREF Range1 COMPARATOR Min Error VOLTAGE COMPARATOR Propagation Delay1 Error1 CURRENT COMPARATOR Propagation Delay1 Error1 MEASURE OUTPUT, MEASOUT Measure Output Voltage Span1 −7 Typ 1 −10 2 Max Unit Test Conditions/Comments +10 5 MΩ µA V Typically 100 MΩ Per input; typically ±30 nA Measured directly at comparator; does not include measure block errors Uncalibrated With respect to the measured voltage +7 mV +12 µs mV Uncalibrated −1.5 1 +1.5 µs % Of programmed current range, uncalibrated −12.81 +12.81 V Measure Output Voltage Span1 Measure Output Voltage Span1 −6.405 0 +6.405 5.125 V V Measure Output Voltage Span1 Measure Pin Output Impedance Output Leakage Current 0 2.56 115 +100 V Ω nA +10 pF mA Output Capacitance1 Short-Circuit Current1 OPEN-SENSE DETECT/CLAMP/ALARM Measurement Accuracy Clamp Accuracy Alarm Delay1 DUTGND Voltage Range1 Pull-Up Current Leakage Current Trip Point Accuracy Alarm Delay1 GUARD AMPLIFIER Voltage Range1 Voltage Span1 Output Offset Short-Circuit Current1 Load Capacitance1 Output Impedance Alarm Delay1 DIE TEMPERATURE SENSOR Accuracy1 Output Voltage at 25°C Output Scale Factor1 Output Voltage Range1 0.25 −12 0.25 −100 5 −10 −200 600 50 −1 +50 −1 −30 +200 900 mV mV μs +1 +70 V μA +1 μA +10 mV μs AVDD − 2.25 25 +10 +20 100 V V mV mA nF Ω μs 50 AVSS + 2.25 −10 −20 100 200 −10 +10 1.54 4.7 1 2 Rev. E | Page 10 of 66 % V mV/°C V MEASOUT gain = 1, VREF = 5 V, offset DAC = 0x8000 MEASOUT gain = 1, VREF = 2.5 V MEASOUT gain = 0.2, VREF = 5 V, offset DAC = 0x8000 MEASOUT gain = 0.2, VREF = 2.5 V When HW_INH is low Pull-up for purpose of detecting open circuit on DUTGND, can be disabled When pull-up disabled, DGS DAC = 0x3333 (1 V with VREF = 5 V); if DUTGND voltage is far away from one of comparator thresholds, more leakage may be present If it moves 100 mV away from input level Relative to a temperature change Data Sheet Parameter SPI INTERFACE LOGIC Logic Inputs Input High Voltage, VIH AD5560 Min Typ Max 1.7/2.0 Input Low Voltage, VIL Unit Test Conditions/Comments V (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant input levels (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant input levels 0.7/0.8 V +1 10 µA pF 0.4 +1 10 V V μA pF 0.4 10 V pF 4 28 V HCAVSS1x HCAVDD2x −25 4 −5 28 V V HCAVSS2x AVDD AVSS DVCC AIDD4 AISS4 DICC AIDD4 −25 8 −25 2.3 −5 28 −5 5.5 30 V V V V mA mA mA mA AISS4 −27 Input Current, IINH, IINL Input Capacitance, CIN1 CMOS Logic Outputs Output High Voltage, VOH Output Low Voltage, VOL Tristate Leakage Current Output Capacitance1 Open-Drain Logic Outputs Output Low Voltage, VOL Output Capacitance1 POWER SUPPLIES HCAVDD1x HCAIDD1 HCAIDD1 HCAISS1 HCAISS1 HCAIDD2 HCAIDD2 HCAISS2 HCAISS2 POWER-DOWN CURRENTS HCAIDD HCAISS HCAIDD HCAISS AIDD AISS DICC Maximum Power Dissipation EXTFORCE1 EXTFORCE2 Power-Up Overshoot1 −1 SDO, CPOL, CPOH, GPO, CPO DVCC − 0.4 −1 10 10 −30 3 27 mA 20 0.5 −20 −0.5 15 0.25 −15 −0.25 250 mA mA mA mA mA mA mA mA 3 μA μA μA μA mA mA mA 10 5 5 W W % −250 250 −250 5 −5 Rev. E | Page 11 of 66 IOL = 500 µA SDO, CPOL, CPOH, CPO SDO, CPOL, CPOH, CPO BUSY, TMPALM, CLALM, KELALM IOL = 500 µA, CL = 50 pF, RPULLUP = 1 kΩ |HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS, HCAVDDx ≤ AVDD |HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS, HCAVDDx ≤ AVDD |AVDD – AVSS| < 33 V All ranges All ranges Channel inhibited/tristate, HW_INH or SW-INH low Channel inhibited/tristate, HW_INH or SW-INH low HCAVDDx and HCAVSSx supply currents shown are excluding load currents; however, for power budget calculations, the supply currents here are consumed by the load When enabled, excluding load conditions When disabled When enabled, excluding load condition When disabled When enabled, excluding load conditions When disabled When enabled, excluding load conditions When disabled Supply currents on power-up or during a power-down condition Of programmed value AD5560 Parameter Power Supply Sensitivity1 ΔForced Voltage/ΔAVDD ΔForced Voltage/ΔAVSS ΔForced Voltage/ΔHCAVDDx ΔForced Voltage/ΔHCAVSSx ΔMeasured Current/ΔAVDD ΔMeasured Current/ΔAVSS ΔMeasured Current/ΔHCAVDDx ΔMeasured Current/ΔHCAVSSx ΔMeasured Voltage/ΔAVDD ΔMeasured Voltage/ΔAVSS ΔMeasured Voltage/ΔHCAVDDx ΔMeasured Voltage/ΔHCAVSSx ΔForced Voltage/ΔDVCC ΔMeasured Current/ΔDVCC ΔMeasured Voltage/ΔDVCC Data Sheet Min Typ Max −65 −65 −90 −90 −50 −43 −90 −90 −65 −65 −90 −90 −80 −80 −80 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Guaranteed by design and characterization, not subject to production test. Programmable clamps must be enabled if taking advantage of reduced headroom/footroom. 3 Clamps disabled. 4 Not including internal pull-up current between AVDD/AVSS and HCAVDDx/HCAVSSx pins. 1 2 Rev. E | Page 12 of 66 Test Conditions/Comments DC to 1 kHz −30 dB at 100 kHz −25 dB at 100 kHz −60 dB at 100 kHz −62 dB at 100 kHz −25 dB at 100 kHz −20 dB at 100 kHz −60 dB at 100 kHz −60 dB at 100 kHz −30 dB at 100 kHz −25 dB at 100 kHz −60 dB at 100 kHz −65 dB at 100 kHz −46 dB at 100 kHz −36 dB at 100 kHz −46 dB at 100 kHz Data Sheet AD5560 TIMING CHARACTERISTICS HCAVDDx ≤ AVSS + 33 V, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, VREF = 5 V (TJ = 25°C to 90°C, maximum specifications, unless otherwise noted). Table 2. SPI Interface Parameter1, 2, 3 tUPDATE t1 t2 t3 t4 t5 t6 t7 t8 t94 t10 t11 t12 t13 t145, 6 t15 LOAD TIMING t16 t17 t18 t19 DVCC = 2.3 V to 2.7 V 600 25 10 10 10 15 5 5 4.5 40 1.5 280 25 400 250 45 30 DVCC = 2.7 V to 3.3 V 600 20 8 8 10 15 5 5 4.5 35 1.5 280 20 400 250 35 30 DVCC = 4.5 V to 5.5 V 600 20 8 8 10 15 5 5 4.5 30 1.5 280 10 400 250 25 30 Unit ns max ns min ns min ns min ns min ns min ns min ns min ns min ns max μs max ns max ns min µs max ns min ns max ns max Description Channel update cycle time SCLK cycle time; 60/40 duty cycle SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time Minimum SYNC high time 24th SCLK falling edge to SYNC rising edge Data setup time Data hold time SYNC rising edge to BUSY falling edge BUSY pulse width low for DAC x1 write BUSY pulse width low for other register write RESET pulse width low RESET time indicated by BUSY low Minimum SYNC high time in readback mode SCLK rising edge to SDO valid SYNC rising edge to SDO high-Z 20 150 0 150 150 20 150 0 150 150 20 150 0 150 150 ns min ns min ns min ns min ns min LOAD pulse width low BUSY rising edge to force output response time BUSY rising edge to LOAD falling edge LOAD rising edge to FORCE output response time LOAD rising edge to current range response 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 4 and Figure 5. 4 This is measured with the load circuit shown in Figure 2. 5 This is measured with the load circuit shown in Figure 3. 6 Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications. 2 TIMING DIAGRAMS 200µA RLOAD 2.2kΩ CLOAD 50pF VOL TO OUTPUT PIN CLOAD 50pF 07779-002 TO OUTPUT PIN IOL VOH (MIN) – VOL (MAX) 2 200µA Figure 2. Load Circuit for Open Drain IOL Figure 3. Load Circuit for CMOS Rev. E | Page 13 of 66 07779-003 DVCC AD5560 Data Sheet t1 SCLK 1 24 2 t2 t3 t4 t6 SYNC t5 t7 t8 DB0 DB23 SDI t9 t10 BUSY t16 LOAD1,3 FORCE EXTFORCE1 EXTFORCE21 t17 t18 t16 LOAD2,3 FORCE EXTFORCE1 EXTFORCE22,3 t19 t11 RESET t12 1LOAD ACTIVE DURING BUSY. 2LOAD ACTIVE AFTER BUSY. 3LOAD FUNCTION IS AVAILABLE 07779-004 BUSY VIA CLEN OR HW_INH AS DETERMINED BY DPS REGISTER 2. Figure 4. SPI Write Timing SCLK 48 24 t14 t13 SYNC t15 DB23 D0B INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB0 DB23 NOP CONDITION DB23 DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 5. SPI Read Timing Rev. E | Page 14 of 66 07779-005 SDI Data Sheet AD5560 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AVDD to AVSS AVDD to AGND AVSS to AGND HCAVDDx to HCAVSSx HCAVDDx to AGND HCAVSSx to AGND HCAVDDx to AVSS HCAVDDx to AVDD HCAVSSx to AVSS DVCC to DGND AGND to DGND REFGND to AGND Digital Inputs to DGND Analog Inputs to AGND EXTFORCE1 and EXTFORCE2 to AGND1 Storage Temperature Operating Junction Temperature Reflow Profile Junction Temperature Power Dissipation ESD HBM FICDM 1 Rating 34 V −0.3 V to +34 V −34 V to +0.3 V 34 V −0.3 V to +34 V −34 V to +0.3 V −0.3 V to AVSS + 34 V −0.3 V to AVDD + 0.3 V +0.3 V to AVSS − 0.3 V −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to DVCC + 0.3 V AVSS − 0.3 V to AVDD + 0.3 V AVDD − 28 V −65°C to +125°C 25°C to 90°C J-STD 20 (JEDEC) 150°C max 10 W max (EXTFORCE1 stage) 5 W max (EXTFORCE2 stage) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 1500 V 500 V When an EXTFORCE1 or EXTFORCE2 stage is enabled and the supply differential |AVDD − AVSS| > 28 V, take care to ensure that these pins are not directly shorted to AVSS voltage at any time because this can cause damage to the device. Rev. E | Page 15 of 66 AD5560 Data Sheet EXTFORCE1A HCAV DD1A HCAV SS1A HCAV SS2A EXTFORCE2A HCAV DD2A HCAV DD1B EXTFORCE1B HCAV SS1B HCAV SS2B EXTFORCE2B HCAV DD2B HCAV DD1C EXTFORCE1C HC_V SS1C GPO PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 EXTMEASIH2 47 EXTMEASIH1 TMPALM 3 46 AVDD CPOH/CPO 4 45 AVSS CPOL 5 44 AGND BUSY 6 43 GUARD/SYS_DUTGND 42 EXTMEASIL 41 SENSE 40 DUTGND 39 CF0 SDI 11 38 CF1 SYNC 12 37 CF2 RCLK 13 36 CF3 RESET 14 35 CF4 CLEN/LOAD 15 34 NC HW_INH/LOAD 16 33 AVDD CLALM 1 PIN 1 KELALM 2 SDO 7 AD5560 DVCC 8 TOP VIEW (Not to Scale) DGND 9 EXPOSED PAD ON TOP SCLK 10 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD ON TOP OF PACKAGE. EXPOSED PAD IS INTERNALLY CONNECTED TO MOST NEGATIVE POINT, AVSS. 07779-006 FORCE SYS_FORCE AVSS SYS_SENSE MASTER_OUT SLAVE_IN CC2 CC1 CC0 CC3 MEASOUT AVDD AVSS AGND VREF REFGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 6. TQFP_EP Pin Configuration Table 4. TQFP_EP Pin Function Descriptions Pin No. Mnemonic Description 1 CLALM 2 KELALM 3 TMPALM 4 5 6 7 CPOH/CPO CPOL BUSY SDO 8 9 10 11 12 13 DVCC DGND SCLK SDI SYNC RCLK 14 15 RESET CLEN/LOAD 16 HW_INH/LOAD 17 REFGND Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either latched or unlatched. Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. Comparator High Output (CPOH) or Window Comparator Output (CPO). Comparator Low Output. Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels. Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic purposes. Digital Supply Voltage. Digital Ground Reference Point. Clock Input, Active Falling Edge. Serial Data Input. Frame Sync, Active Low. Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to this input to drive the ramp circuitry. Tie RCLK low if it is unused. Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value. Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as LOAD input (see the system control register, Address 0x1). Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system control register, Address 0x1). Accurate Ground Reference for Applied Voltage Reference. Rev. E | Page 16 of 66 Data Sheet Pin No. 18 19, 44 20, 30, 45 Mnemonic VREF AGND AVSS 21, 33, 46 AVDD 22 23 24 25 26 27 28 29 31 32 34 35 36 37 38 39 40 41 42 43 MEASOUT CC3 CC0 CC1 CC2 SLAVE_IN MASTER_OUT SYS_SENSE SYS_FORCE FORCE NC CF4 CF3 CF2 CF1 CF0 DUTGND SENSE EXTMEASIL GUARD/SYS_DUTGND 47 48 49, 55, 61 EXTMEASIH1 EXTMEASIH2 HCAVDD1A, HCAVDD1B, HCAVDD1C EXTFORCE1A, EXTFORCE1B, EXTFORCE1C HCAVSS1A, HCAVSS1B, HCAVSS1C HCAVSS2A, HCAVSS2B EXTFORCE2A, EXTFORCE2B HCAVDD2A, HCAVDD2B GPO EP AD5560 Description Reference Input for DAC Channels, Input Range 2 V to 5 V. Analog Ground. Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as measure blocks. Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as measure blocks. Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND. Compensation Capacitor Input 3. Compensation Capacitor Input 0. Compensation Capacitor Input 1. Compensation Capacitor Input 2. Slave Input When Ganging Multiple DPS Devices. Master Output When Ganging Multiple DPS Devices. External Sense Signal Output. External Force Signal Input. Output Force Pin for Internal Current Ranges. No Connect. Feedforward Capacitor 4. Feedforward Capacitor 3. Feedforward Capacitor 2. Feedforward Capacitor 1. Feedforward Capacitor 0. Device Under Test Ground. Input Sense Line. Low Side Measure Current Line for External High Current Ranges. Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19 for addressing details. 50, 56, 62 51, 57, 63 52, 58 53, 59 54, 60 64 65 Input High Measure Line for External High Current Range 1. Input High Measure Line for External High Current Range 2. High Current Positive Analog Supply Voltage, for EXTFORCE1 Range. Output Force. This pin is used for high Current Range 1, up to a maximum of ±1.2 A. High Current Negative Analog Supply Voltage, for EXTFORCE1 Range. High Current Negative Analog Supply Voltage, for EXTFORCE2 Range. Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. High Current Positive Analog Supply Voltage, for EXTFORCE2 Range. Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT. The exposed pad is internally connected to AVSS. Rev. E | Page 17 of 66 Data Sheet 9 8 7 6 5 4 3 2 1 A EXTFORCE1A EXTFORCE1A EXTFORCE2A EXTFORCE1B EXTFORCE1B EXTFORCE2B EXTFORCE1C EXTFORCE1C GPO B HCAV DD1A HCAV SS1A HCAV DD2A HCAV DD1B HCAV SS1B HCAV DD2B HCAV DD1C HCAV SS1C CLALM C HCAVDD1A HCAVSS1A HCAVSS2A HCAVDD1B HCAVSS1B HCAVSS2B HCAVDD1C HCAVSS1C KELALM D AVDD EXTMEASIH1 EXTMEASIH2 CPOL CPOH/CPO TMPALM E AVSS AGND GUARD/ SYS_DUTGND DVCC SDO BUSY F DUTGND EXTMEASIL SENSE SDI SCLK DGND G CF0 CF2 SYS_FORCE SYS_SENSE CC0 AVSS RESET RCLK SYNC H CF1 CF3 SLAVE_IN MASTER_OUT CC1 MEASOUT AVDD VREF CLEN/ LOAD J CF4 AVDD FORCE CC2 CC3 AVSS AGND REFGND HW_INH/ LOAD 3 × 3 ARRAY IS VOID OF BALLS 07779-062 AD5560 Figure 7. Flip-Chip BGA Pin Configuration, Bottom Side (BGA Balls Are Visible) Table 5. Flip-Chip BGA Pin Function Descriptions Pin No. A1 A2, A3 A4 A5, A6 A7 A8, A9 B1 Mnemonic GPO EXTFORCE1C EXTFORCE2B EXTFORCE1B EXTFORCE2A EXTFORCE1A CLALM B2, C2 B3, C3 B4 B5, C5 B6, C6 B7 B8, C8 B9, C9 C1 HCAVSS1C HCAVDD1C HCAVDD2B HCAVSS1B HCAVDD1B HCAVDD2A HCAVSS1A HCAVDD1A KELALM C4 C7 HCAVSS2B HCAVSS2A Description Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT. Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. High Current Negative Analog Supply Voltage for EXTFORCE1 Range. High Current Positive Analog Supply Voltage for EXTFORCE1 Range. High Current Positive Analog Supply Voltage for EXTFORCE2 Range. High Current Negative Analog Supply Voltage for EXTFORCE1 Range. High Current Positive Analog Supply Voltage for EXTFORCE1 Range. High Current Positive Analog Supply Voltage for EXTFORCE2 Range. High Current Negative Analog Supply Voltage for EXTFORCE1 Range. High Current Positive Analog Supply Voltage for EXTFORCE1 Range. Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either latched or unlatched. High Current Negative Analog Supply Voltage for EXTFORCE2 Range. High Current Negative Analog Supply Voltage for EXTFORCE2 Range. Rev. E | Page 18 of 66 Data Sheet Pin No. D1 Mnemonic TMPALM D2 D3 D7 D8 D9,H3, J8 CPOH/CPO CPOL EXTMEASIH2 EXTMEASIH1 AVDD E1 E2 BUSY SDO E3 E7 DVCC GUARD/SYS_DUTGND E8 E9, G4, J4 AGND AVSS F1 F2 F3 F7 F8 F9 G1 G2 DGND SCLK SDI SENSE EXTMEASIL DUTGND SYNC RCLK G3 G5 G6 G7 G8 G9 H1 RESET CC0 SYS_SENSE SYS_FORCE CF2 CF0 CLEN/LOAD H2 H4 H5 H6 H7 H8 H9 J1 VREF MEASOUT CC1 MASTER_OUT SLAVE_IN CF3 CF1 HW_INH/LOAD J2 J3 J5 J6 J7 J9 REFGND AGND CC3 CC2 FORCE CF4 AD5560 Description Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. Comparator High Output (CPOH) or Window Comparator Output (CPO). Comparator Low Output. Input High Measure Line for External High Current Range 2. Input High Measure Line for External High Current Range 1. Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as measure blocks. Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels. Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic purposes. Digital Supply Voltage. Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19 for addressing details. Analog Ground. Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as measure blocks. Digital Ground Reference Point. Clock Input, Active Falling Edge. Serial Data Input. Input Sense Line. Low Side Measure Current Line for External High Current Ranges. Device Under Test Ground. Frame Sync, Active Low. Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to this input to drive the ramp circuitry. Tie RCLK low if it is unused. Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value. Compensation Capacitor Input 0. External Sense Signal Output. External Force Signal Input. Feedforward Capacitor 2. Feedforward Capacitor 0. Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as LOAD input (see the system control register, Address 0x1). Reference Input for DAC Channels, Input Range is 2 V to 5 V. Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND. Compensation Capacitor Input 1. Master Output When Ganging Multiple DPS Devices. Slave Input When Ganging Multiple DPS Devices. Feedforward Capacitor 3. Feedforward Capacitor 1. Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system control register, Address 0x1). Accurate Ground Reference for Applied Voltage Reference. Analog Ground. Compensation Capacitor Input 3. Compensation Capacitor Input 2. Output Force Pin for Internal Current Ranges. Feedforward Capacitor 4. Rev. E | Page 19 of 66 AD5560 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.2 12 1.0 10 8 MV LINEARITY (mV) 0.6 0.4 0.2 6 MEASOUT GAIN = 0.2 4 2 0 MEASOUT GAIN = 1 –2 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE –4 07779-026 –0.2 0 10,000 20,000 30,000 40,000 Figure 8. Force Voltage Linearity vs. Code, VREF = 5 V, No Load 60,000 Figure 11. Measure Voltage Linearity vs. Code (MEASOUT Gain 1, MEASOUT Gain = 0.2, Negative Skew Supply) 2.0 0.0100 TJ = 25°C AVDD = 16.25V AVSS = –16.25V VREF = 5V 1.5 HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D LOW: AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 VREF = 5V 0.0075 1.0 0.5 LINEARITY (%) 0.0050 MEASOUT GAIN = 0.2 0 –0.5 –1.0 0.0025 0 LOW SUPPLIES –0.0025 –0.0050 –1.5 NOMINAL SUPPLIES –0.0075 MEASOUT GAIN = 1 0 10,000 20,000 40,000 30,000 50,000 60,000 CODE 07779-027 HIGH SUPPLIES –2.0 –0.0100 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 CODE Figure 9. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1, MEASOUT Gain = 0.2, Nominal Supplies) Figure 12. Measure Current Linearity vs. Code (MEASOUT Gain = 1, MI Gain = 20), TJ = 25°C 0.010 5 TJ = 25°C AVDD = 28V AVSS = –5V VREF = 5V OFFSET DAC = 0xD1D 4 HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D LOW: AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 VREF = 5V 0.005 3 MI LINEARITY (%) MV LINEARITY (mV) 50,000 CODE 07779-034 0 07779-035 LINEARITY (mV) 0.8 MV LINEARITY ERROR (mV) TJ = 25°C AVDD = 8V AVSS = –25V VREF = 5V OFFSET DAC = 0xD4EB MEASOUT GAIN = 0.2 2 1 0 LOW SUPPLIES 0 –0.005 MEASOUT GAIN = 1 –1 NOMINAL SUPPLIES 10,000 20,000 30,000 CODE 40,000 50,000 60,000 –0.010 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 CODE Figure 10. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1, MEASOUT Gain = 0.2, Positive Skew Supply) Figure 13. Measure Current Linearity vs. Code (MEASOUT Gain = 1, MI Gain = 10) Rev. E | Page 20 of 66 07779-036 0 07779-033 HIGH SUPPLIES –2 Data Sheet 0.0500 HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D LOW: AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 VREF = 5V ±25mA RANGE 0.0375 AVDD = +16.25V AVSS = –16.25V 0.0375 V REF = 5V OFFSET DAC = 0x8000 0.0250 MI GAIN = 20 MEASOUT GAIN = 0.2 NOMINAL SUPPLIES 0.0125 LINEARITY (%) LOW SUPPLIES 0 –0.0125 –0.0375 0 –0.0125 10,000 20,000 30,000 40,000 50,000 60,000 70,000 CODE Figure 14. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2, MI Gain = 20) 0.100 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE Figure 17. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 0.2, MI Gain = 20) 1.5 HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D LOW : AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB NOM : AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 VREF = 5V ±25mA RANGE 0.075 25mA RANGE –0.0500 07779-037 0 2.5mA –0.0375 HIGH SUPPLIES –0.0500 TJ = 25°C 1.0 0.5 HIGH SUPPLIES 0.025 0 –0.025 NOMINAL SUPPLIES –0.050 LOW SUPPLIES 0 EXTFORCE1A EXTFORCE2B FORCE EXTFORCE1B EXTMEASIH1 SENSE EXTFORCE1C EXTMEASIH2 SYS_FORCE EXTFORCE2A EXTMEASIL SYS_SENSE COMBINED LEAKAGE –0.5 –1.0 –1.5 –2.0 –0.075 –2.5 0 10,000 20,000 30,000 40,000 50,000 60,000 –3.0 –10 07779-038 –0.100 70,000 CODE 0.0100 VSTRESS = 9V 6 LEAKAGE CURRENT (nA) 25µA RANGE 0.0025 0 –0.0025 2.5mA –0.0050 30,000 40,000 50,000 60,000 4 3 2 CODE Figure 16. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 1, MI Gain = 20) 0 25 07779-039 –0.0100 20,000 5 1 25mA RANGE 10,000 10 7 AVDD = +16.25V AVSS = –16.25V 0.0075 V REF = 5V OFFSET DAC = 0x8000 MI GAIN = 20 0.0050 MEASOUT GAIN = 1 0 5 STRESS VOLTAGE (V) Figure 18. Leakage Current vs. Stress Voltage (Force and Combined Leakage) Figure 15. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2, MI Gain = 10) –0.0075 0 5 07779-030 LEAKAGE CURRENT (nA) 0.050 LINEARITY (%) 0.0125 –0.0250 –0.0250 LINEARITY (%) 25µA RANGE EXTFORCE1A EXTFORCE2B FORCE EXTFORCE1B EXTMEASIH1 SENSE EXTFORCE1C EXTMEASIH2 SYS_FORCE EXTFORCE2A EXTMEASIL SYS_SENSE COMBINED LEAKAGE 35 45 55 65 TEMPERATURE (°C) 75 85 95 07779-031 LINEARITY (%) 0.0250 07779-040 0.0500 AD5560 Figure 19. Leakage Current vs. Temperature (Force and Combined Leakage), VSTRESS = 9 V Rev. E | Page 21 of 66 AD5560 Data Sheet 0 0.15 EXTFORCE1A EXTFORCE2B EXTFORCE1B EXTMEASIH1 SENSE EXTFORCE1C EXTMEASIH2 SYS_FORCE EXTFORCE2A EXTMEASIL SYS_SENSE 0.05 0 TJ = 25°C –0.02 GAIN ERROR (%) LEAKAGE CURRENT (nA) 0.10 –0.05 –0.04 HIGH NOMINAL –0.06 LOW –0.08 –0.10 –0.10 –0.15 5 10 STRESS VOLTAGE (V) 25 35 45 55 0.8 0 AV DD = ±16.25V AV SS = –16.25V VREF = 5V OFFSET DAC = 0x8000 1.6 0.6 EXTFORCE1A EXTFORCE2B EXTFORCE1B EXTMEASIH1 SENSE EXTFORCE1C EXTMEASIH2 SYS_FORCE EXTFORCE2A EXTMEASIL SYS_SENSE 1.2 –1.0 1.0 0.8 –1.5 0.6 0.4 0.1 –2.0 0.2 35 45 55 65 75 85 95 TEMPERATURE (°C) –2.5 0 25 07779-061 0 25 –0.5 35 45 55 65 75 07779-043 0.2 1.4 POSITIVE GAIN ERROR (mV) LEAKAGE CURRENT (nA) 0.7 0.3 85 1.8 VSTRESS = 9V 0.4 75 Figure 23. MI Positive Gain Error vs. Temperature, MI Gain = 20, MEASOUT Gain = 1 Figure 20. Leakage Current vs. Stress Voltage 0.5 65 TEMPERATURE (°C) NEGATIVE GAIN ERROR (mV) 0 07779-032 5 07779-48 –0.12 –0.20 –10 85 TEMPERATURE (°C) Figure 21. Leakage Current vs. Temperature, VSTRESS = 9 V Figure 24. FV Gain Error vs. Temperature 0.10 23.0 HIGH 0.2 LOW 0.05 22.5 OFFSET ERROR (mV) NOMINAL 0.2 HIGH –0.05 –0.10 LOW 0.2 HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D LOW : AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB NOM : AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 VREF = 5V LOW0.2/HIGH0.2/NOM0.2 MEAN FOR MEASOUT GAIN = 0.2 –0.15 –0.20 25 35 45 55 65 75 85 TEMPERATURE (°C) 22.0 21.5 21.0 20.5 Figure 22. MI Offset Error vs. Temperature, MI Gain = 20, MEASOUT Gain = 1 and 0.2 20.0 25 35 45 55 65 75 TEMPERATURE (°C) Figure 25. FV Offset Error vs. Temperature Rev. E | Page 22 of 66 85 07779-041 0 07779-047 OFFSET ERROR (%) NOMINAL Data Sheet AD5560 0 5 HIGH 4 –0.001 3 –0.003 LOW NOMINAL 2 OFFSET ERROR (mV) –0.004 –0.005 1 0 –2 HIGH –3 –0.006 LOW –4 35 45 55 65 75 85 TEMPERATURE (°C) –5 25 07779-045 –0.007 25 NOMINAL –1 35 45 55 65 75 07779-044 GAIN ERROR (%) –0.002 85 TEMPERATURE (°C) Figure 26. MV Gain Error vs. Temperature, MEASOUT Gain = 1 Figure 29. MV Offset Error vs. Temperature, MEASOUT Gain = 0.2 1.0 0.9 CH1 p-p 27mV CH1 AREA 10.92µVs HIGH OFFSET ERROR (mV) 0.8 NOMINAL 0.7 LOW 0.6 FORCE 0.5 1 0.4 0.3 0.2 07779-015 SYNC 0.1 0 25 35 45 55 65 75 85 TEMPERATURE (°C) 07779-042 3 CH1 50mV CH3 5V B W B W M200µs T 10.4% 0.030 CH1 p-p 16mV CH1 AREA –5.336µVs NOMINAL 0.025 0.020 HIGH 0.015 FORCE 1 0.010 0.005 07779-016 0 25 SYNC 3 35 45 55 65 75 85 TEMPERATURE (°C) Figure 28. MV Gain Error vs. Temperature, MEASOUT Gain = 0.2 07779-046 GAIN ERROR (%) 1.5V Figure 30. Range Change 2.5 mA to 25 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load Figure 27. MV Offset Error vs. Temperature, MEASOUT Gain = 1 LOW A CH3 CH1 50mV CH3 5V B W B W M200µs T 10.4% A CH3 1.5V Figure 31. Range Change 25 mA to 2.5 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load Rev. E | Page 23 of 66 AD5560 Data Sheet CH1 p-p 159mV CH1 AREA 14.31µVs CH1 p-p 84mV TRIGGER 2 FORCE 1 FORCE 1 3 CH1 50mV CH3 5V M200µs T 10.4% B W B W A CH3 07779-020 07779-017 SYNC 1.5V CH1 100mV B W CH2 5V M40µs T 120.4µs A CH2 1.6V Figure 35. Autocompensation Mode 90% to 10% ILOAD Change, EXTFORCE2 Range, 10 μF Load Figure 32. Range Change 25 mA to EXTFORCE2, Safe Mode, 25 mA ILOAD, 10 μF Load CH1 p-p 36mV CH1 AREA –9.738µVs TRIGGER CH1 p-p 86mV 2 FORCE 07779-018 SYNC 3 CH1 50mV CH3 5V FORCE 1 07779-021 1 M200µs T 10.4% A CH3 CH1 100mV 1.5V B W CH2 5V M40µs T 120.4µs A CH2 4V Figure 36. Autocompensation Mode 10% to 90% ILOAD Change, EXTFORCE2 Range, 10 μF Load Figure 33. Range Change EXTFORCE2 to 25 mA, Safe Mode, 25 mA ILOAD, 10 μF Load 350 10µF LOAD 30µF LOAD 100µF LOAD PEAK-TO-PEAK (mV) 300 CH1 p-p 172mV 250 TRIGGER 2 200 FORCE 1 150 100 07779-022 50 EXT RANGE 1 SAFE MODE AUTO COMP EXT RANGE 2 SAFE MODE AUTO COMP 25mA RANGE SAFE MODE AUTO COMP 07779-019 0 CH1 100mV B W CH2 5V M40µs T 120.4µs A CH2 1.6V Figure 37. Safe Mode 80% to 10%, EXTFORCE2 Range, 10 μF Load Figure 34. Kick/Droop Response vs. IRANGE, Compensation, and CLOAD,, 10% to 90% to 10% ILOAD Change Rev. E | Page 24 of 66 Data Sheet AD5560 CH1 p-p 174mV TRIGGER FORCE MEASOUT – MI 2 FORCE 1 2 07779-023 BUSY B CH1 100mV CH2 5V W M40µs T 120.4µs A CH2 07779-055 1 TA = 25°C AVDD = +16.25V AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = 25mA 0 TO 10V STEP RLOAD = 40kΩ CLOAD = 220nF AUTOCOMP MODE 0x4480 MEASOUT GAIN 1, MI GAIN 20 4 3 4.6V CH1 5V CH3 5V Figure 38. Safe Mode 10% to 90%, EXTFORCE2 Range, 10 μF Load CH2 2V BW CH4 10V M20µs T 1.4% A CH3 2.9V Figure 41. Transient Response FVMI Mode, 25 mA Range, Autocompensation Mode 2.0 AVDD = +16.5V AVSS = –16.5V FORCE MEASOUT VOLTAGE (V) 1.9 MEASOUT – MI 1.8 1 1.6 2 1.5 BUSY 35 45 55 65 75 4 3 07779-024 1.4 25 85 FORCED TEMPERATURE (°C) TA = 25°C AVDD = +16.25V AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = 250µA 0 TO 10V STEP RLOAD = 40kΩ CLOAD = 220nF SAFE MODE MEASOUT GAIN 1, MI GAIN 20 07779-056 1.7 CH1 5V CH3 5V CH2 2V BW CH4 10V M100µs T 7.2% A CH3 2.9V Figure 42. Transient Response FVMI Mode, 25mA Range, Safe Mode Figure 39. MEASOUT TSENSE Temperature Sensor vs. Temperature (Multiple Devices) FORCE MEASOUT – MI MEASOUT – MI 1 2 2 07779-054 BUSY 4 3 CH1 5V CH3 5V CH2 2V BW CH4 10V M400µs T 10.2% TA = 25°C AVDD = +16.25V AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = EXTFORCE1/1.2A 0 TO 3.7V STEP CLOAD = 10µF CERAMIC AUTOCOMP MODE 0x9680 MEASOUT GAIN 1, MI GAIN 20 1 A CH3 BUSY 4 3 2.9V CH1 5V CH3 5V Figure 40. Transient Response FVMI Mode, ±250 μA Range, Autocompensation Mode CH2 1V BW CH4 10V M4µs T 3% A CH3 07779-057 FORCE TA = 25°C AVDD = +16.25V AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = 250µA 0 TO 10V STEP RLOAD = 40kΩ CLOAD = 220nF AUTOCOMP MODE 0x4880 MEASOUT GAIN 1, MI GAIN 20 2.9V Figure 43. Transient Response FVMI Mode, EXTFORCE1 Range, Autocompensation Mode Rev. E | Page 25 of 66 AD5560 Data Sheet 1000 PART H1 PART H2 PART H3 900 800 700 NSD (nV/√Hz) MEASOUT – MI TA = 25°C AVDD = +16.25V AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = EXTFORCE1/1.2A 0 TO 3.7V STEP CLOAD = 10µF CERAMIC SAFE MODE MEASOUT GAIN 1, MI GAIN 20 100 Figure 44. Transient Response FVMI Mode, EXTFORCE1 Range, Safe Mode 07779-025 GAIN = 11 FVMI GAIN = 10 2.9V FNMV GAIN = 01 FVMV GAIN = 00 A CH3 FVMN GAIN = 10 M20µs T 4.6% 0 GAIN = 00 BUSY GAIN = 10 CH2 1V BW CH4 10V 200 FORCE 4 3 CH1 5V CH3 5V 400 GAIN = 00 2 500 300 07779-058 1 600 Figure 47. NSD vs. Amplifier Stage and Gain Setting at 1 kHz 20 DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V 0 4 3 CH1 5V CH3 5V CH2 2V BW CH4 10V M10µs T 9.8% A CH3 –40 FOH MV: GAIN 0 MV: GAIN 1 MV: GAIN 2 MV: GAIN 3 MI: GAIN 0 MI:GAIN 1 MI: GAIN 2 MI: GAIN 3 –60 –80 –100 10 2.9V 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 45. Transient Response FVMI Mode, EXTFORCE2 Range, Autocompensation Mode 07779-049 2 ACPSRR (dB) 1 –20 07779-059 TA = 25°C AVDD = +16.25V MEASOUT – MI AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = EXTFORCE2/ 300mA FORCE 0 TO 10V STEP CLOAD = 220nF AUTOCOMP MODE 0x4880 MEASOUT GAIN 1, MI GAIN 20 BUSY Figure 48. ACPSRR of AVDD vs. Frequency 0 FORCE –20 MEASOUT – MI BUSY 4 3 CH1 5V CH3 5V CH2 2V BW CH4 10V M100µs T 9.8% A CH3 ACPSRR (dB) –60 FOH MV: GAIN 0 MV: GAIN 1 MV: GAIN 2 MV: GAIN 3 MI: GAIN 0 MI:GAIN 1 MI: GAIN 2 MI: GAIN 3 –80 –100 –120 –140 10 2.9V DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 46. Transient Response FVMI Mode, EXTFORCE2 Range, Safe Mode Rev. E | Page 26 of 66 Figure 49. ACPSRR of AVSS vs. Frequency 10M 07779-050 2 TA = 25°C AVDD = +16.25V AVSS = –16.25V VREF = 5V OFFSET DAC = 0x8000 IRANGE /ILOAD = EXTFORCE2/300mA 0 TO 10V STEP CLOAD = 220nF SAFE MODE MEASOUT GAIN 1, MI GAIN 20 07779-060 1 –40 Data Sheet AD5560 0 0 MI: GAIN 0 –20 –20 FOH MI: GAIN 0 –40 ACPSRR (dB) ACPSRR (dB) –40 –60 MV: GAIN 0 –60 MV: GAIN 0 –80 –80 –100 –100 –120 100 1k 10k 100k 1M 10M FREQUENCY (Hz) –140 10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 50. ACPSRR of DVCC vs. Frequency Figure 52. ACPSRR of HCAVSSx vs. Frequency 1600 0 MI: GAIN 0 1400 –20 CABLE L = CABLE L = CABLE L = CABLE L = 2µH, CLAMP AT 1.2A 1µH, CLAMP AT 1.2A 0.2µH, CLAMP AT 1.2A 0µH, CLAMP AT 1.2A CABLE L = CABLE L = CABLE L = CABLE L = 2µH, CLAMP AT 800mA 1µH, CLAMP AT 800mA 0.2µH, CLAMP AT 800mA 0µH, CLAMP AT 800mA CABLE L = CABLE L = CABLE L = CABLE L = 2µH, CLAMP AT 400mA 1µH, CLAMP AT 400mA 0.2µH, CLAMP AT 400mA 0µH, CLAMP AT 400mA CABLE L = CABLE L = CABLE L = CABLE L = 2µH, CLAMP AT 100mA 1µH, CLAMP AT 100mA 0.2µH, CLAMP AT 100mA 0µH, CLAMP AT 100mA 1200 ICLAMP VALUE (mA) –40 MV: GAIN 0 –60 –80 –100 1000 800 600 400 FOH –120 200 –140 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M Figure 51. ACPSRR of HCAVDDx vs. Frequency 0 0.001 0.01 0.1 1 RLOAD (Ω) Figure 53. ICLAMP Value vs. RLOAD – Cal at 1Ohm Rev. E | Page 27 of 66 10 07779-063 DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V 07779-052 ACPSRR (dB) 100 07779-053 10 07779-051 –120 FOH DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V AD5560 Data Sheet TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in millivolts (mV) or percentage of full-scale range (%FSR). Gain Error Gain error is the difference between full-scale error and zeroscale error. It is expressed in percentage of full-scale range (%FSR). Gain Error = Full-Scale Error − Zero-Scale Error where: Full-Scale Error is the difference between the actual voltage and the ideal voltage at full scale. Zero-Scale Error is the difference between the actual voltage and the ideal voltage at zero scale. Linearity Error Linearity error, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the full-scale range. It is measured after adjusting for offset error and gain error and is expressed in millivolts (mV). Common-Mode (CM) Error CM error is the error at the output of the amplifier due to the common-mode input voltage. It is expressed in percentage of full-scale voltage range per volt (%FSVR/V). Clamp Limit Clamp limit is a measure of where the clamps begin to function fully and limit the clamped voltage or current. Slew Rate The slew rate is the rate of change of the output voltage expressed in volts per microsecond (V/μs). Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Energy Digital-to-analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. It is specified as the area of the glitch in nanovolts per second (nV-sec). It is measured by toggling the DAC register data between 0x7FFF and 0x8000. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is a measure of the part’s ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.2 V p-p. The ratio of the amplitude of the signal on the output to the amplitude of the modulation is the ACPSRR. It is expressed in decibels (dB). VSTRESS VSTRESS is the stress voltage applied to each pin during leakage testing. Leakage Current Leakage current is the current measured at an output pin when the circuit connected to that pin is in high impedance state. Rev. E | Page 28 of 66 Data Sheet AD5560 THEORY OF OPERATION The AD5560 is a single-channel, device power supply for use in semiconductor automatic test equipment. All the DAC levels required to operate the device are available on chip. This device contains programmable modes to force a pin voltage and measure the corresponding current (FVMI) covering a wide current measure range of up to ±1.2 A. A voltage sense amplifier allows measurement of the DUT voltage. Measured current or voltage is available on the MEASOUT pin. • • FORCE AMPLIFIER The force amplifier is a unity gain amplifier forcing voltage directly to the device under test (DUT). This high bandwidth amplifier allows suppression of load transient induced glitching on the amplifier output. Headroom and footroom requirements for the amplifier are 2.25 V and an additional ±500 mV dropped across the selected sense resistor with full-scale current flowing. The amplifier is designed to drive high currents up to ±1.2 A with the capability of ganging together outputs of multiple AD5560 devices for currents in excess of ±1.2 A. The force amplifier can be compensated to ensure stability when driving DUT capacitances of up to 160 μF. The device is capable of supplying transient currents in excess of ±1.2 A when powering a DUT with a large decoupling capacitor. A clamp enable pin (CLEN) allows disabling of the clamp circuitry to allow the amplifier to quickly charge this large capacitance. An extra control bit (GPO) is available to switch out DUT decoupling when making low current measurements. HW_INH Function A hardware inhibit pin (HW_INH/LOAD) allows disabling of the force amplifier, making the output high impedance. This function is also available through the serial interface (see the SW-INH bit in the DPS Register 1, Address 0x2). This pin can also be configured as a LOAD function to allow multiple devices to be synchronized. Note that either CLEN or HW_INH can be chosen as a LOAD function. DAC REFERENCE VOLTAGE (VREF) One analog reference input, VREF, supplies all DAC levels with the necessary reference voltage to generate the required dc levels. OPEN-SENSE DETECT (OSD) ALARM AND CLAMP The open-sense detect (OSD) circuitry protects the DUT from overvoltage when the force and sense lines of the force amplifier becoming disconnected from each other. This block performs three functions related to the force and sense lines. • It clamps the sense line to within a programmable threshold level (plus a VBE) of the force line, where the programmable threshold is set by the OSD DAC voltage level. This limits the maximum or minimum voltage that can appear on the FORCE pin; it can be driven no higher than [V(FIN DAC) + threshold + VBE] and no lower than [V(FIN DAC) − threshold − VBE]. It triggers an alarm on KELALM if the force line goes more than the threshold voltage away (OSD DAC level) from the sense line. It translates the V(force − sense) voltage to a level relative to AGND so that it can be measured through the MEASOUT pin. The open-sense detect level is programmable over the range 0.62 V to 5 V (16-bit OSD DAC plus one diode drop). The 5 V OSD DAC can be accessed through the serial interface (see the DAC register addressing portion of Table 24). There is a 10 kΩ resistor that can be connected between the FORCE and SENSE pins by use of SW11. This 10 kΩ resistor is intended to maintain a force/sense connection when a DUT is not in place. It is not intended to be connected when measurements are being made because this defeats the purpose of the OSD circuit in identifying an open circuit between FORCE and SENSE. In addition, the sense path has a 2.5 kΩ resistor in series; therefore, if the 10 kΩ switch is closed, errors may become apparent when in high current ranges. DEVICE UNDER TEST GROUND (DUTGND) DUTGND is the ground level of the DUT. DUTGND Kelvin Sense KELALM flags when the voltage at the DUTGND pin moves too far away from the AGND line (>1 V default setting of the DGS DAC). This alarm trigger is programmable via the serial interface. The threshold for the alarm function is programmable using the DUTGND SENSE DAC (DGS DAC) (see Table 24). The DUTGND pin has a 50 μA pull-up resistor that allows the alarm function to detect whether DUTGND is open. Setting the disable DUTALM bit high (Register 0x6, Bit 10) disables the 50 μA pull-up resistor and also disables the alarm feature. The alarm feature can also be set to latched or unlatched (Register 0x6, Bit 11). Kelvin Alarm (KELALM) The open-drain active low Kelvin alarm pin flags the user when an open occurs in either the sense or DUTGND line; it can be programmed to be either latched or unlatched (Register 0x6, Bit 13, Bit 11, Bit 7). The delay in the alarm flag is 50 μs. GPO The GPO pin can be used as an extra control bit for external switching functions, such as for switching out DUT decoupling when making low current measurements. The GPO pin is also internally connected to an array of thermal diodes scattered across the AD5560. The diagnostic register Rev. E | Page 29 of 66 AD5560 Data Sheet (Address 0x7) details the addressing and location of the diodes. These can be used for diagnostic purposes to determine the thermal gradients across the die and across a board containing many AD5560 devices. When selected, the anode of these diodes is connected to GPO and the cathode to AGND. The AD5560 evaluation board uses the ON Semiconductor® ADT7461 temperature sensor for the purpose of analyzing the temperature at different points across the die. COMPARATORS 1 0 1 CPOH 0 1 This pin can also be configured as LOAD to allow multiple devices to be synchronized. Note that either CLEN or HW_INH can be chosen as a LOAD function. SHORT-CIRCUIT PROTECTION 1 To minimize the number of comparator output lines routed back to the controller, it is possible to change the comparator function to a window comparator that outputs on one single pin, CPO. This pin is shared with CPOH and, when configured through the serial interface, it provides information on whether the measured DUT current or voltage is inside or outside the window set by the CPL and CPH DAC levels (see Table 24). Table 7. Comparator Output Function in CPO Mode Test Condition (VDUT or IDUT) > CPL and < CPH (VDUT or IDUT) < CPL or > CPH The CLALM open-drain output flags the user when a clamp limit has been hit; it can be programmed to be either latched or unlatched. Pin 15 (CLEN) allows the user to disable the clamping function when powering a device with large DUT capacitance, thus allowing increased current drive to the device and, therefore, speeding up the charging time of the load capacitance. CLEN is active high. Table 6. Comparator Output Function CPOL Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) The DUT measured value is monitored by two comparators (CPOL, CPOH). These comparators give the advantage of speed for go-no-go testing. Test Condition (VDUT or IDUT) > CPH (VDUT or IDUT) < CPH (VDUT or IDUT) > CPL (VDUT or IDUT) < CPL CPH > (VDUT or IDUT) > CPL The clamp register limits the CLL clamp to the range 0x0000 to 0x7FFF; any code in excess of this is seen as 0x7FFF. Similarly, the CLH clamp registers are limited to the range 0x8000 to 0xFFFF (see Table 24). CPO Output 1 0 The AD5560 force amplifier stage has built-in short-circuit protection per stage as noted in the Specifications section. When the current clamps are disabled, the user must minimize the duration of time that the device is left in a short-circuit condition (for all current ranges). GUARD AMPLIFIER A guard amplifier allows the user to force the shield of the coaxial cable to be driven to the same forced voltage at the DUT, ensuring minimal voltage drops across the cable to minimize errors from cable insulation leakage. The guard amplifier also has an alarm function that flags the open-drain KELALM pin when the guard output is shorted. The delay in the alarm flag is 200 μs. CURRENT CLAMPS High and low current clamps are included on chip. These protect the DUT in the event of a short circuit. The CLH and CLL levels are set by the 16-bit DAC levels. The clamp works to limit the current supplied by the force amplifier to within the set levels. The clamp circuitry compares the voltage across the sense resistor (multiplied by an in-amp gain of 10 or 20) to compare to the programmed clamp limit and activates the clamp circuit if either the high level or low level is exceeded, thus ensuring that the DUT current can never exceed the programmed clamp limit + 10% of full-scale current. If a clamp level is exceeded, this is flagged via the latched opendrain CLALM pin, and the resulting alarm information can be read back via the SPI interface. The clamp levels should not be set to the same level; instead, they should be set a minimum of 2 V apart (irrespective of the MI gain setting). This equates to 10% of FSCR (MI gain = 20) (20% of FSCR, MI gain of 10) apart. They should also be 1 V away from the 0 A level. The guard amplifier output (GUARD/SYS_DUTGND, Pin 43) can also be configured to function as a SYS_DUTGND pin; to do this, the guard amplifier must be tristated via software (see DPS Register 2, Table 19). COMPENSATION CAPACITORS The force amplifier is capable of driving DUT capacitances up to 160 μF. Four external compensation capacitor (CCx) inputs are provided to ensure stability into the maximum load capacitance while ensuring that settling time is optimized. In addition, five CFx capacitor inputs are provided to switch across the sense resistors to further optimize stability and settling time performance. The AD5560 has three compensation modes: safe mode, autocompensation mode, and manual compensation mode, all of which are described in more detail in the Force Amplifier Stability section. The range of suggested compensation capacitors allows optimum performance for any capacitive load from 0 pF to 160 μF using one of the modes previously listed. Rev. E | Page 30 of 66 Data Sheet AD5560 Although there are four compensation input pins and five feedforward capacitor inputs pins, all capacitor inputs may be used only if the user intends to drive large variations of DUT load capacitances. If the DUT load capacitance is known and does not change for all combinations of voltage ranges and test conditions, then it is possible only one set of CCx and CFx capacitors may be required. Table 8. Suggested Compensation Capacitor Selection Value 100 pF 100 pF 330 pF 3.3 nF 4.7 nF 22 nF 100 nF 470 nF 2.2 μF All devices are placed in force voltage (FV) mode. One device acts as the master device and the other devices act as slaves. By connecting in this manner, any device can be configured as the master. Here, the MASTER_OUT pin of the master device is connected to the output of the force amplifier, and it feeds the inputs of each slave force amplifier (via the SLAVE_IN pin ). All devices are connected externally to the DUT. For current to be shared equally, there must be good matching between each of the paths to the DUT. Settings for DPS Register 2 are master = 0x0000, slave = 0x0400. Clamps should be disabled in the slave devices. MASTER DPS SLAVE IN SW5-a SW6 MASTER OUT SW16 SW5-b FIN DAC SW5-a LOCAL FEEDBACK The voltage range for the CCx and CFx pins is the same as the voltage range expected on FORCE; therefore, choice of capacitors should take this into account. CFx capacitors can have 10% tolerance; this extra variation directly affects settling times, especially when measuring current in the low current ranges. Selection of CCx should be at ≤5% tolerance. ×20 OR ×W EXTFORCE2 EXTMEASIH1 RSENSE EXTMEASIL ISENSE AMP VSENSE AMP EXTFORCE1 SENSE ×1 SLAVE DPS 1 SLAVE IN SW5-a SW6 MASTER OUT SW16 The measure current amplifier has two gain settings, 10 and 20. The two gain settings allow users to achieve the quoted/ specified current ranges with large or small voltage swings. The gain of 20 setting is intended for use with a 5 V reference, and the gain of 10 setting is for use with a 2.5 V reference. Both combinations ensure the specified current ranges. Other VREF/gain setting combinations should only be used to achieve smaller current ranges. Attempting to achieve greater current ranges than the specified ranges is outside the intended operation of the AD5560. The maximum guaranteed voltage across RSENSE is ±0.64 V (gain of 20) or ±0.7 V (gain of 10). SW5-b FIN DAC SW5-a LOCAL FEEDBACK ×20 OR ×W EXTFORCE2 EXTMEASIH1 EXTMEASIL ISENSE AMP VSENSE AMP EXTFORCE1 SENSE ×1 SLAVE DPS 2 SLAVE IN SW5-a SW6 MASTER OUT SW16 SW5-b FIN DAC SW5-a LOCAL FEEDBACK ×20 OR ×W EXTFORCE1 EXTFORCE2 EXTMEASIH1 EXTMEASIL ISENSE AMP ×1 SENSE VSENSE AMP HIGH CURRENT RANGES DUT For currents in excess of 1200 mA, a gang mode is available whereby multiple devices are ganged together to achieve higher currents. In gang mode, the loop is controlled by the master AD5560. This loop drives a maximum capacitance of 160 µF for this mode. There are two methods of ganging channels together; these are described in the Master and Slaves in Force Voltage (FV) Mode section and the Master in FV Mode, Slaves in Force Current (FI) Mode section. Rev. E | Page 31 of 66 DUTGND Figure 54. Simplified Block Diagram of High Current Ganging Mode 07779-007 Integrated thin film resistors minimize external components and allow easy selection of current ranges from ±5 µA to ±25 mA. Using external current sense resistors, two higher current ranges are possible: EXTFORCE1 can drive currents up to ±1.2 A, while EXTFORCE2 is designed to drive currents up to ±500 mA. The voltage drop across the selected sense resistor is ±500 mV when full-scale current is flowing through it. RSENSE CURRENT RANGE SELECTION RSENSE Capacitor CC0 CC1 CC2 CC3 CF0 CF1 CF2 CF3 CF4 Master and Slaves in Force Voltage (FV) Mode AD5560 Data Sheet Master in FV Mode, Slaves in Force Current (FI) Mode The master device is placed into FV mode, and all slave devices into force current (FI) mode. The measured current of the master device (MASTER_OUT) is applied to the input of all slave devices (SLAVE_IN), and the slaves act as followers. All channels work to share the current equally among all devices in the gang. Because the slaves force current, matching the DUT paths is not so critical. Settings for DPS Register 2 are master = 0x0200, slave = 0x0600. Clamps should be disabled in the slave devices. MASTER DPS SLAVE IN SW5-a FIN DAC SW5-b SW5-a For example, ganging five 25 V/25 mA devices using the 25 mA range achieves a 25 V/625 mA range, whereas five 15 V/200 mA devices using the EXTFORCE2 path can achieve a 15 V/1 A range. Similarly, ganging four 3.5 V/1.2 A devices using the EXTFORCE1 path results in a 3.5 V/4.8 A DPS. IDEAL SEQUENCE FOR GANG MODE Use the following steps to bring devices into and out of gang mode: SW6 MASTER OUT SW16 The EXTFORCE1, EXTFORCE2, or ±25 mA ranges can be used for the gang mode. Therefore, it is possible to gang devices to get a high voltage/high current combination, or a low voltage/high current combination. 1. EXTFORCE1 2. EXTFORCE2 SENSE MEASOUT BUFFER AND GAIN 3. 4. EXTMEASIH1 ×20 RSENSE EXTMEASIL ISENSE AMP SLAVE DPS 1 5. SLAVE IN SW5-a To remove devices from the gang, the master device should be programmed to force 0 V out again. The procedure for removing devices should be the reverse of Step 1 through Step 5. SW6 MASTER OUT SW16 FIN DAC SW5-b SW5-a EXTFORCE1 Note that this may not always be possible in practice; therefore, it is also possible to gang and ungang while driving a load. Just ensure that the slave devices are in high-Z mode while configuring them into the required range and gang setting. EXTFORCE2 SENSE EXTMEASIH1 ×20 RSENSE MEASOUT BUFFER AND GAIN EXTMEASIL ISENSE AMP SLAVE DPS 2 Gang mode extends only to the ±25 mA range and the two high current ranges, EXTFORCE1 and EXTFORCE2. Therefore, where an accurate measurement is required at a low current, the user should remove slaves from the gang to move to the appropriate lower current range to make the measurement. Similarly, slaves can be brought back into the gang if needed. SLAVE IN SW5-a SW6 MASTER OUT SW16 FIN DAC SW5-b SW5-a EXTFORCE1 COMPENSATION FOR GANG MODE EXTFORCE2 SENSE ×20 ISENSE AMP EXTMEASIL When ganging, the slave devices should be set to the fastest response. DUT DUTGND Figure 55. Simplified Block Diagram of Gang Mode, Using an FV/FI Combination 07779-008 EXTMEASIH1 RSENSE MEASOUT BUFFER AND GAIN Choose the master device and force 0 V output, corresponding to zero current. Select slave DPS 1 and place it in slave mode (keep slaves in high-Z mode via SW-INH or HW_INH until ready to gang). Select to gang in either current or voltage mode. Repeat Step 2 and Step 3 one at a time through the chain of slaves. Load the required voltage to the master device. The other devices copy either voltage or current as programmed. When slaves are in FI mode, the AD5560 force amplifier overrides other compensation settings to enforce CFx = 0, RZ = 0, and gmx ≤ 1. This is done internally to the force amplifier; therefore, readback does not show that the signals inside the force amplifier actually change. SYSTEM FORCE/SENSE SWITCHES System force/sense switches allow easy connection of a central or system parametric measurement unit (PMU) for calibration or additional measurement purposes. The system device under test ground (SYS_DUTGND) switch is shared with the GUARD/SYS_DUTGND pin (Pin 43). See the DPS Register 2 in Table 19 for addressing details. Rev. E | Page 32 of 66 Data Sheet AD5560 DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN These diodes can be muxed out onto the GPO pin. The diagnostic register (Address 0x7) details the addressing and location of the diodes. These can be used for diagnostic purposes to determine the thermal gradients across the die and across a board containing many AD5560 devices. When selected, the anode of each diode is connected to GPO and the cathode to AGND. The AD5560 evaluation board uses the ON Semiconductor ADT7461 temperature sensor for the purpose of analyzing the temperature at different points across the die. There are three types of temperature sensors in the AD5560. • The first is a temperature sensor available on the MEASOUT pin and expressed in voltage terms. Nominally at 25°C, this sensor reads 1.54 V. It has a temperature coefficient of 4.7 mV/°C. This sensor is active during power-down mode. Die Temp = (VMEASOUT(TSENSE) − 1.54)/0.0047 + 25°C Based on typical temperature sensor output voltage at 25°C and output scaling factor. • The second type of temperature sensor is related to the thermal shutdown feature in the device. Here, there are sensors located in the middle of the enabled power stage, which are used to trip the thermal shutdown. The thermal shutdown feature senses only the power stages, and the power stage that it senses is determined by the active stage. If ranges of (R0/5), then the ESR is large enough to make the DUT look resistive. Choose RZ[2:0] = 0, RP[2:0] = 0. This ends the algorithm Calculate the unity gain frequency (Fug), the ideal unity gain frequency of the force amplifier, from Fug = gmx/2πCC0. Using the previously suggested values (gm[1:0] = 2 gives gmx = 300 µA/V and CC0 = 100 pF), Fug calculates to 480 kHz. Calculate FP, the load pole frequency, using FP = 1/(2πR0CC0). Data Sheet AD5560 10. Calculate FZ, the ESR zero frequency, using FZ = 1/(2πRcCr). 11. If FP > Fug, the load pole is above the bandwidth of the AD5560. Ignore it with RZ[2:0] = 0, RP[2:0] = 0. This ends the algorithm 12. If RC < (R0/25), then the ESR is negligible. Attempt to cancel the load pole with RZ zero. Choose an ideal zero frequency of 2 × FP for some safety margin and then choose the RZ[2:0] value that gives the closest frequency on a logarithmic scale. This ends the algorithm 13. Otherwise, this is a troublesome window in which a load pole and a load zero cannot be ignored. Use the following steps: • To cancel the load pole at FP, choose an ideal zero frequency of 6 × FP (this is more conservative than the 2 × FP suggested earlier, but there is more that can go wrong with miscalculation). Then choose the RZ[2:0] value that gives the closest zero to this ideal frequency of 6 × FP on a logarithmic scale. • To cancel the ESR zero at FZ, choose an ideal pole frequency of 2 × FZ. • Then choose the RP[2:0] value that gives the closest pole to this ideal frequency of 2 × FZ on a logarithmic scale. This ends the algorithm ADJUSTING THE AUTOCOMPENSATION MODE A more complex alternative is to calculate the overall impedance at the expected unity gain bandwidth and use this to calculate an equivalent series CR and RC that have the same complex impedance at that particular frequency. DAC LEVELS This device contains all the dedicated DAC levels necessary for operation: a 16-bit DAC for the force amplifier, two 16-bit DACs for the clamp high and low levels, two 16-bit DACs for the comparator high and low levels, a 16-bit DAC to set a programmable open sense voltage, and a 16-bit offset DAC to bias or offset a number of DACs on chip (FORCE, CLL, CLH, CPL, CPH). FORCE AND COMPARATOR DACS The architecture of the main force amplifier DAC consists of a 16-bit R-2R DAC, whereas the comparator DACs are resistorstring DACs followed by an output buffer amplifier. This resistor-string architecture guarantees DAC monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. The comparator DAC is similarly arranged. The force and comparator DACs have a 25.62 V span, including overrange to enable offset and gain errors to be calibrated out. The transfer function for these 16-bit DACs is The autocompensation algorithm assumes that there is 1 Ω of resistance (RC) from the AD5560 to the DUT. If a particular application has resistance that differs greatly from this, then it is likely that the autocompensation algorithm is nonoptimal. If using the autocompensation algorithm as a starting point, consider that overstating the CR capacitance and understating the ESR RC is likely to give a faster response but could cause oscillations. Understating CR and overstating RC is more likely to slow things down and reduce phase margin but not create an oscillator. It is often advisable to err on the side of simplicity. Rather than insert a pole and zero at similar frequencies, it may be better to add none at all. Set RP[2:0] = RZ[2:0] = 0 to push them beyond the AD5560 bandwidth. DEALING WITH PARALLEL LOAD CAPACITORS In the event that the load capacitance consists of two parallel capacitors with different ESRs, it is highly likely that the overall complex impedance at the unity gain bandwidth is dominated by the larger capacitor and its ESR. Assuming that the smaller capacitor does not exist normally is a safer simplifying assumption.  DAC CODE  VOUT = 5.125 × VREF ×   − 5.125 × VREF × 216    OFFSET _ DAC _ CODE   + DUTGND  216   where DAC CODE is X2 (see the Offset and Gain Registers section). CLAMP DACS The architecture of the clamp DAC consists of a 16-bit resistorstring DAC followed by an output buffer amplifier. This resistorstring architecture guarantees DAC monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. The clamp DACs have a 25.62 V span, including overrange, to enable offset and gain errors to be calibrated out. Rev. E | Page 39 of 66 AD5560 Data Sheet Table 15. Offset DAC Relationship with Other DACs, VREF = 5 V The transfer function for these 16-bit DACs is  DAC CODE  VCLH , VCLL = 5.125 × VREF ×   − 5.125 × VREF × 216    OFFSET _ DAC _ CODE    + DUTGND 216   The transfer function for the clamp current value is  DAC CODE − 32768  5.125 × VREF ×   216   ICLL, ICLH = RSENSE × MI _ AMP _ GAIN where: RSENSE is the sense resistor. MI_AMP_GAIN is the gain of the MI amp (either 10 or 20). OSD DAC The OSD DAC is a 16-bit DAC function, again a resistor string DAC guaranteeing monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. The OSD function is used to program the voltage difference needed between the force and sense lines before the alarm circuit flags an error. The OSD DAC has a range of 0.62 V to 5 V. The transfer function is as follows:  DAC CODE  VOUT = VREF ×   216   (1) The offset DAC does not affect the OSD DAC output range. Offset DAC Code 0 0 0 … 32,768 32,768 32,768 … 57,344 57,344 57,344 … 65,355 1 DAC Code1 0 32,768 65,535 … 0 32,768 65,535 … 0 32,768 65,535 … … DAC Output Voltage Range 0.00 12.81 25.62 … −12.81 0.00 12.81 … −22.42 −9.61 3.20 … Footroom limitations DAC code shown for 16-bit force DAC. OFFSET AND GAIN REGISTERS Each DAC level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. These registers give the user the ability to calibrate out errors in the complete signal chain (including the DAC) using the internal m and c registers, which hold the correction factors. The digital input transfer function for the DACs can be represented as x2 = [x1 × (m + 1)/2n] + (c – 2n – 1) DUTGND DAC Similarly, the DUTGND DAC (DGS) is a 16-bit DAC and uses a resistor string DAC to guarantee monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. This function is used to program the voltage difference needed between the DUTGND and AGND lines before the alarm circuit flags an error. where: x2 is the data-word loaded to the resistor string DAC. x1 is the 16-bit data-word written to the DAC input register. m is the code in the gain register (default code = 216 – 1). n is the DAC resolution (n = 16). c is the code in the offset register (default code = 215). Offset and Gain Registers for the Force Amplifier DAC The force amplifier input (FIN) DAC level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. There is one set of registers for the force voltage range: x1, m, and c. The DUTGND DAC has a range of 0 V to 5 V. The transfer function for this 16-bit DAC is shown in Equation 1. The offset DAC does not affect the OSD DAC output range. OFFSET DAC Offset and Gain Registers for the Comparator DACs In addition to the offset and gain trim, there is also a 16-bit offset DAC that offsets the output of each DAC on chip. Therefore, depending on headroom available, the input to the force amplifier can be arranged either symmetrically or asymmetrically about DUTGND but always within a voltage span of 25 V. Some extra gain is included to allow for system error correction using the m (gain) and c (offset) registers. The usable voltage range is −22 V to +25 V. Full scale loaded to the offset DAC does not give a useful output voltage range because the output amplifiers are limited by available footroom. Table 15 shows the effect of the offset DAC on other DACs in the device (clamp, comparator, and force DACs). The comparator DAC levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. There are seven sets of registers consisting of a combination of x1, m, and c, one set each for the five internal force current ranges and one set each for the two external high current ranges. Offset and Gain Registers for the Clamp DACs The clamp DAC levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. One set of registers covers the VSENSE range, the five internal force current ranges, and the two external high current ranges. Both clamp DAC x1 registers and their associated offset and gain registers are 16 bit. Rev. E | Page 40 of 66 Data Sheet AD5560 REFERENCE SELECTION Calibration Example The voltage applied to the VREF pin determines the output voltage range and span applied to the force amplifier, clamp, and comparator inputs and the current ranges. Nominal offset coefficient = 32,768 (0x8000) This device can be used with a reference input ranging from 2 V to 5 V. However, for most applications, a reference input of 5 V is able to meet all voltage range requirements. The DAC amplifier gain is 5.125, which gives a DAC output span of 25.625 V. The DACs have gain and offset registers that can be used to calibrate out system errors. In addition, the gain register can be used to reduce the DAC output range to the desired force voltage range. Using a 5 V reference and setting the m (gain) register to onefourth scale or 0x4000 gives an output voltage span of 6.25 V. Because the force DAC has 18 bits of resolution even with only one-fourth of the output voltage span, it is still possible to achieve 16-bit resolution in this 6.25 V range. The measure current amplifier has two gain settings, 10 and 20. The two gain settings allow users to achieve the quoted/specified current ranges with large or small voltage swings. The 20 gain setting is intended for use with a 5 V reference, and the 10 gain setting is for use with a 2.5 V reference. Both combinations ensure the specified current ranges. Other VREF/gain setting combinations should be used only to achieve smaller current ranges. See Table 27 for suggested references for use with the AD5560. CALIBRATION Calibration involves determining the gain and offset of each channel in each mode and overwriting the default values in the m and c registers of the individual DACs. Nominal gain coefficient = 65,535 (0xFFFF) For example, the gain error = 0.5%, and the offset error = 100 mV. Gain error (0.5%) calibration is as follows: 65,535 × 0.995 = 65,207 Therefore, load Code 1111 1110 1011 0111 (0xFEB7) to the m register. Offset error (100 mV) calibration is as follows: LSB size = 10.25/65,535 = 156 µV Offset coefficient for 100 mV offset = 100/0.156 = 641 LSBs Therefore, load Code 0111 1101 0111 1111 (0x7D7F) to the c register. ADDITIONAL CALIBRATION The techniques described in the Calibration section are usually sufficient to reduce the zero-scale and gain errors. However, there are limitations whereby the errors may not be sufficiently reduced. For example, the offset (c) register can only be used to reduce the offset caused by negative zero-scale error. A positive offset cannot be reduced. Likewise, if the maximum voltage is below the ideal value, that is, a negative gain error, the gain (m) register cannot be used to increase the gain to compensate for the error. These limitations can be overcome by increasing the reference value. SYSTEM LEVEL CALIBRATION Zero-scale error can be reduced as follows: There are many ways to calibrate the device on power-on. Following is an example of how to calibrate the FIN DAC registers (Register 0x8 to Register 0xA) of the device without a DUT or DUT board connected. The calibration procedure for the force and measure circuitry is as follows: 1. Set the output to the lowest possible value. 1. 2. Measure the actual output voltage and compare it to the required value. This is the zero-scale error. 3. Calculate the number of LSBs equivalent to the zero-scale error, and add or subtract this number to the default value of the c register. Reducing Zero-Scale Error Reducing Gain Error Gain error can be reduced as follows: 1. 2. 3. 4. Measure the zero-scale error. Set the output to the highest possible value. Measure the actual output voltage and compare it to the required value. This is the gain error. Calculate the number of LSBs equivalent to the gain error and subtract this number from the default value of the m register. Note that only positive gain error can be reduced. 2. Rev. E | Page 41 of 66 Calibrate the force voltage (two-point calibration). a. Write zero scale to the FIN DAC registers (Register 0x8 to Register 0xA). b. Connect SYS_FORCE to FORCE (via SW8) and SYS_SENSE to SENSE (via SW9), and close the internal force/sense switch (SW11). c. Using the system PMU, measure the error between the voltage at FORCE/SENSE and the desired value. d. Similarly, load full scale to the FIN DAC registers (Register 0x8 to Register 0xA) and measure the error between the voltage at FORCE/SENSE and the desired value. e. Calculate the m and c values. f. Load these values to the appropriate FIN DAC m and FIN DAC c registers (Register 0x9 and Register 0xA). Calibrate the measure voltage (two-point calibration). a. Connect SYS_FORCE to FORCE (via SW8) and SYS_SENSE to SENSE (via SW9), and close the internal force/sense switch (via SW11). AD5560 Data Sheet b. 3. 4. Force the voltage on FORCE via SYS_FORCE and measure the voltage at MEASOUT. The difference is the error between the actual forced voltage and the voltage at MEASOUT. Calibrate the measure current (two-point calibration). a. In FV mode, write zero scale to the FIN DAC registers (Register 0x8 to Register 0xA). b. Disconnect the FORCE pin and the SENSE pin. Connect SYS_FORCE to FORCE (via SW8) and SYS_SENSE to SENSE (via SW9). c. Connect the SYS_FORCE pin to an external ammeter and its other terminal to the SYS_SENSE pin. d. Connect the SYS_SENSE pin to a precision resistor (RDUT), where RDUT = RSENSE × 20 of the current range, and connect its other terminal to ground (see Figure 58). e. Measure the error between the ammeter reading and the MEASOUT reading by forcing ±10 V to the FIN DAC registers (Register 0x8 to Register 0xA). f. Repeat Step 3a through Step3e across all current ranges. Similarly, calibrate the comparator and clamp DACs, and load the appropriate gain and offset registers. Calibrating these DACs requires some successive approximation to determine where the comparator trips or the clamps engage. RSENSE SW8 FORCE EXTERNAL AMMETER ISENSE MEASOUT For simplicity, when VREF = 5 V, minimum |AVDD − AVSS| = 31.125 V (VREF × 5.125 + headroom + footroom); otherwise, there can be unanticipated effects resulting from headroom/ footroom issues. This does not take into account cable loss or DUTGND contributions. Similarly, when VREF = 2.5 V, minimum |AVDD − AVSS| = 18.3 V and, when VREF = 2 V, minimum |AVDD − AVSS| = 16 V. Selection of HCAVSSx and HCAVDDx supplies is determined by the EXTFORCE1 and EXTFORCE2 output ranges. The supply rails chosen must take into account headroom and footroom, DUTGND voltage range, cable loss, supply tolerance, and VRSENSE. If diodes are used in series with the HCAVSSx and HCAVDDx supplies pins (shown in Figure 60), the diode voltage drop should also be factored into the supply rail calculation. SW9 RDUT AD5560 WHERE: RDUT = RSENSE × 20 07779-100 SENSE As the nominal, VRSENSE is ±0.5 V for the full-scale specified current flowing for all ranges. If this is gained by 20, the measure current amplifier output (internal node) voltage range is ±10 V with full-scale current and the default offset DAC setting. The measure current block needs ±2.25 V footroom/headroom for correct operation in addition to the ±0.5 V VRSENSE. CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS SYS_SENSE VSENSE When choosing AVDD, remember to take into account the specified current ranges. The measure current block has either a gain of 20 or 10 and must have sufficient headroom/ footroom to operate correctly. The AD5560 is designed to settle fast into large capacitive loads; therefore, when slewing, the device draws 2× to 3× the current range from the AVDD/AVSS supplies. When supply rails are chosen, they should be capable of supplying each DPS channel with sufficient current to slew. SYS_FORCE FIN DAC where: AVSS_Headroom is the 2.75 V headroom (includes the RSENSE voltage drop). VDUTGND is the voltage range anticipated at DUTGND. RCABLE is the cable/path resistance. ILOAD is the maximum load current. Figure 58. Measure Current Calibration CHOOSING AVDD/AVSS POWER SUPPLY RAILS As noted in the Specifications section, the minimum supply variation across the part is |AVDD − AVSS| ≥ 16 V and ≤ 33 V, AVDD ≥ 8 V, and AVSS ≤ −5 V. For the AD5560 circuits to operate correctly, the supply rails must take into account not only the force voltage range but also the internal DAC minimum voltage level, as well as headroom/footroom. The DAC amplifier gains VREF by 5.125, and the offset DAC centers that range about some chosen point. Because the DAC minimum voltage (VMIN) is used in other parts of the circuit (MEASOUT gain of 0.2), it is important that AVSS be chosen based on the following: AVSS ≤ −5.125 × (VREF × (OFFSET_DAC_CODE/216)) − AVSS_Headroom − VDUTGND − (RCABLE × ILOAD) The AD5560 is designed to settle fast into large capacitive loads in high current ranges; therefore, when slewing, the device draws 2× to 3× the current range from the HCAVSSx and HCAVDDx supplies. When choosing supply rails, ensure that they are capable of supplying each DPS channel with sufficient current to slew. All output stages of the AD5560 are symmetrical; they can source and sink the rated current. Supply design/bypassing should account for this. POWER DISSIPATION The maximum power dissipation allowed in the EXTFORCE1 stage is 10 W, whereas in the EXTFORCE2 stage, it is 5 W. Take care to ensure that the device is adequately cooled to remove the heat. The quiescent current is ~0.8 W with an Rev. E | Page 42 of 66 Data Sheet AD5560 internal current range enabled and ~1 W with external current ranges, EXTFORCE1 or EXTFORCE2, enabled. This device is specified for performance up to 90°C junction temperature (TJ). PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE The exposed pad and leads of the TQFP package have a 100% tin finish. The exposed paddle is connected internally to AVSS. The simulated maximum allowable force for a single lead is 0.18 lbs; total allowable force for the package is 11.5 lbs. The quoted maximum force may cause permanent lead bending. Other package failure (die, mold, board) may occur first at lower forces. SLEW RATE CONTROL There are two methods of achieving different slew rates using the AD5560. One method is using the programmable slew rate feature that gives eight programmable rates. The second method is using the ramp feature and an external clock. Programmable Slew Rate Eight programmable modes of slew rates are available to choose from through the serial interface, enabling the user to choose different rates to power up the DUT. The different slew rates are achieved by variation in the internal compensation of the force DAC output amplifier. The slew rates available are 1.000 V/µs, 0.875 V/µs, 0.750 V/µs, 0.625 V/µs, 0.5 V/µs, 0.4375 V/µs, 0.35V µs, and 0.313 V/µs. Ramp Function Included in the AD5560 is a ramp function that enables the user to apply a rising or falling voltage ramp to the DUT. The user supplies a clock, RCLK, to control the timing. This function is controlled via the serial interface and requires programming of a number of registers to determine the end value, the ramp size, and the clock divider register to determine the update rate. The contents of the FIN DAC x1 register are the ramp start value. The user must load the end code register and the step size register. The sign is now generated from the difference between the FIN DAC x1 register and the end code; then the step size value is added to or subtracted from FIN DAC x1, calibrated and stored. The user must supply a clock to the RCLK pin to load the new code to the DAC. The output settles in 1.2 µs for a step of 10 mV with CDUT in the lowest range of