Evaluation Board for the AD7265/AD7266
EVAL-AD7265/AD7266
FEATURES
Full details on the AD7265 and the AD7266 are available in the
device data sheets, which are available from Analog Devices,
Inc., and should be consulted in conjunction with this data
sheet when using the evaluation board.
Full-featured evaluation board for the AD7265 and AD7266
EVAL-CED1Z compatible
Standalone capability
On-board analog buffering and voltage reference
On-board single-ended-to-differential conversion
Various linking options
PC software for control and data analysis when used with
EVAL-CED1Z
On-board components include an AD780, which is a pin
programmable 2.5 V or 3 V ultrahigh precision band gap
reference, nine AD8022 dual op amps, and a 7S04 digital buffer.
Various link options are explained in Table 1.
Interfacing to this evaluation board is through a 96-way connector.
This 96-way connector is compatible with the EVAL-CED1Z,
which is available from Analog Devices. External sockets are
provided for a number of signals, including the VREF input, the
analog inputs, and the digital inputs and outputs.
GENERAL DESCRIPTION
This data sheet describes the evaluation board for the AD7265
and the AD7266, which are dual, 12-bit, high speed, low power
successive approximation ADCs that operate from a single 2.7 V to
5.25 V power supply and feature throughput rates up to 2 MSPS.
FUNCTIONAL BLOCK DIAGRAM
EXTERNAL SUPPLY
BIPOLAR
SINGLE-ENDED
INPUT
S/E TO DIFF
CONVERSION USING
AD8138
..
..
VA1
S/E TO DIFF
CONVERSION USING
AD8138
VA6
AVDD DVDD
VDRIVE
..
..
A0
A1
SCLK
SINGLE-ENDED
INPUT BUFFERING
UNIPOLAR
SINGLE-ENDED
INPUTS
VB1
..
..
..
..
VB6
96-WAY EDGE CONNECTOR
BIPOLAR
SINGLE-ENDED
INPUT
CS
DOUTA
DOUTB
AD7265/AD7266
DCAP A/DCAP B
BIPOLAR
INPUT
OPTIONAL BIAS-UP
CIRCUITRY FOR
S/E TO DIFF
OPERATION
UNIPOLAR
OUTPUT
UNIPOLAR
OUTPUT
EXTERNAL
VREF
POWER
SUPPLY
CIRCUITS
07921-001
BIPOLAR
INPUT
Figure 1.
Rev. 0
Evaluation boards are only intended for device evaluation and not for production purposes.
Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or
statutory including, but not limited to, any implied warranty of merchantability or fitness for a
particular purpose. No license is granted by implication or otherwise under any patents or other
intellectual property by application or use of evaluation boards. Information furnished by Analog
Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result
from its use. Analog Devices reserves the right to change devices or specifications at any time
without notice. Trademarks and registered trademarks are the property of their respective owners.
Evaluation boards are not authorized to be used in life support devices or systems.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
EVAL-AD7265/AD7266
TABLE OF CONTENTS
Features .............................................................................................. 1
Operating with the EVAL-CED1Z ........................................... 13
General Description ......................................................................... 1
Evaluation Board Software ............................................................ 14
Functional Block Diagram .............................................................. 1
Installing the Software ............................................................... 14
Revision History ............................................................................... 2
Setting Up the EVAL-CED1Z ................................................... 14
Evaluation Board Hardware ............................................................ 3
Software Operation .................................................................... 15
Power Supplies .............................................................................. 3
Using the Software ..................................................................... 16
Link Options ................................................................................. 3
Taking Samples ........................................................................... 17
Setup Conditions .......................................................................... 8
Evaluation Board Schematics and Artwork ................................ 18
Sockets ......................................................................................... 11
Ordering Information .................................................................... 23
Connectors .................................................................................. 11
Bill of Materials ........................................................................... 23
Interfacing the Evaluation Board to the EVAL-CED1Z ........ 12
Ordering Guide .......................................................................... 23
Test Points .................................................................................... 12
ESD Caution................................................................................ 23
REVISION HISTORY
4/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
EVAL-AD7265/AD7266
EVALUATION BOARD HARDWARE
POWER SUPPLIES
When using this evaluation board with the EVAL-CED1Z, all
supplies are provided from the EVAL-CED1Z through the
96-way connector. When using the board as a standalone unit,
external supplies must be provided. This evaluation board has
the following power supply inputs: +12 V, −12 V, AVDD (+5 V),
DVDD (+5 V), AGND, VDRIVE, and DGND. The +12 V supply is
only required if the external AD780 voltage reference and op
amps are to be used.
The supplies are decoupled to the relevant ground plane with
10 µF tantalum and 0.1 µF multilayer ceramic capacitors at the
point where they enter the board. The supply pins for the exter-
nal reference are also decoupled to AGND with a 470 nF ceramic
capacitor. The AD7265/AD7266 AVDD and VDRIVE supply pins
are also decoupled to AGND, while DVDD is decoupled to DGND,
with a 0.1 µF multilayer ceramic capacitor and a 10 µF tantalum
capacitor at the device pins. Extensive ground planes are used
on this board to minimize the effect of high frequency noise
interference. There are two ground planes, AGND and DGND.
These are connected at one location close to the AD7265/AD7266.
LINK OPTIONS
There are 49 link options that must be set correctly to select the
appropriate operating setup before using the evaluation board.
The functions of the link options are outlined in Table 1.
Table 1. Link Function Descriptions
Link No.
LK1
LK2
LK3
LK4
LK5
LK6
Description
This link option selects the source of the VA1 analog input.
In Position A, VA1 is supplied from the output of the unity gain buffer, U3-A, in which case a signal must be applied to the SVIN1
SMB socket via J13.
In Position B, VA1 is supplied from the positive output (V1+) of the single-ended-to-differential converter, U5-B, in which case a
single-ended signal must be applied to V1 DIFF via Socket J17.
In Position C, VA1 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VA2 analog input.
In Position A, VA2 is supplied from the output of the unity gain buffer, U3-B, in which case a signal must be applied to the SVIN2
socket via J14.
In Position B, VA2 is supplied from the negative output (V1−) of the single-ended-to-differential converter, U5-A, in which case a
single-ended signal must be applied to V1 DIFF via Socket J17.
In Position C, VA2 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VA3 analog input.
In Position A, VA3 is supplied from the output of the unity gain buffer, U3-A, in which case a signal must be applied to the SVIN1
socket via J13.
In Position B, VA3 is supplied from the positive output (V2+) of the single-ended-to-differential converter, U6-B, in which case a
single-ended signal must be applied to V2 DIFF via Socket J19.
In Position C, VA3 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VA4 analog input.
In Position A, VA4 is supplied from the output of the unity gain buffer, U3-B, in which case a signal must be applied to the SVIN2
socket via J14.
In Position B, VA4 is supplied from the negative output (V2−) of the single-ended-to-differential converter, U6-A, in which case a
single-ended signal must be applied to V2 DIFF via Socket J19.
In Position C, VA4 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VA5 analog input.
In Position A, VA5 is supplied from the output of the unity gain buffer, U3-A, in which case a signal must be applied to the SVIN1
socket via J13.
In Position B, VA5 is supplied from the positive output (V1+) of the single-ended-to-differential converter, U5-B, in which case a
single-ended signal must be applied to V1 DIFF via Socket J17.
In Position C, VA5 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VA6 analog input.
In Position A, VA6 is supplied from the output of the unity gain buffer, U3-B, in which case a signal must be applied to the SVIN2
socket via J14.
In Position B, VA6 is supplied from the negative output (V1−) of the single-ended-to-differential converter, U5-A, in which case a
single-ended signal must be applied to V1 DIFF via Socket J17.
In Position C, VA6 is tied to AGND. If this channel is not in use, this link should be in Position C.
Rev. 0 | Page 3 of 24
EVAL-AD7265/AD7266
Link No.
LK7
LK8
LK9
LK10
LK11
LK12
LK13
LK14
LK15
Description
This link option selects the source of the VB1 analog input.
In Position A, VB1 is supplied from the output of the unity gain buffer, U4-A, in which case a signal must be applied to the SVIN3
socket via J15.
In Position B, VB1 is supplied from the positive output (V3+) of the single-ended-to-differential converter, U7-B, in which case a
single-ended signal must be applied to V3 DIFF via Socket J20.
In Position C, VB1 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VB2 analog input.
In Position A, VB2 is supplied from the output of the unity gain buffer, U4-B, in which case a signal must be applied to the SVIN4
socket via J16.
In Position B, VB2 is supplied from the negative output (V3−) of the single-ended-to-differential converter, U7-A, in which case a
single-ended signal must be applied to V3 DIFF via Socket J20.
In Position C, VB2 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VB3 analog input.
In Position A, VB3 is supplied from the output of the unity gain buffer, U4-A, in which case a signal must be applied to the SVIN3
socket via J15.
In Position B, VB3 is supplied from the positive output (V4+) of the single-ended-to-differential converter, U8-B, in which case a
single-ended signal must be applied to V4 DIFF via Socket J22.
In Position C, VB3 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VB4 analog input.
In Position A, VB4 is supplied from the output of the unity gain buffer, U4-B, in which case a signal must be applied to the SVIN4
socket via J16.
In Position B, VB4 is supplied from the negative output (V4−) of the single-ended-to-differential converter, U8-A, in which case a
single-ended signal must be applied to V4 DIFF via Socket J22.
In Position C, VB4 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VB5 analog input.
In Position A, VB5 is supplied from the output of the unity gain buffer, U4-A, in which case a signal must be applied to the SVIN3
socket via J15.
In Position B, VB5 is supplied from the positive output (V3+) of the single-ended-to-differential converter, U7-B, in which case a
single-ended signal must be applied to V3 DIFF via Socket J20.
In position C, VB5 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source of the VB6 analog input.
In Position A, VB6 is supplied from the output of the unity gain buffer, U4-B, in which case a signal must be applied to the SVIN4
socket via J16.
In Position B, VB6 is supplied from the negative output (V3−) of the single-ended-to-differential converter, U7-A, in which case a
single-ended signal must be applied to V3 DIFF via Socket J20.
In Position C, VB6 is tied to AGND. If this channel is not in use, this link should be in Position C.
This link option selects the source or destination of the reference voltage applied to or received from the DCAPA pin of the
AD7265/AD7266.
In Position A, an external reference signal can be applied to the DCAPA pin via J24, or the internal reference voltage from the
AD7266/AD7265 can be accessed via J24. This link should be used in conjunction with LK19, which determines whether an
internal or external reference is used with the device.
In Position B, the AD780 provides an external 2.5 V reference to the DCAPA pin. This link should be set up in conjunction with
LK16.
If both Link Option A and Link Option B are inserted, the AD780 provides the reference voltage for the AD7265/AD7266, which
is also output via J24.
This link option selects the source or destination of the reference voltage applied to or received from the DCAPB pin of the
AD7265/AD7266.
In Position A, an external reference signal can be applied to the DCAPB pin via J25, or the internal reference voltage from the
AD7265/AD7266 can be accessed via J25. This link should be used in conjunction with LK19, which determines whether an
internal or external reference is used with the device.
In Position B, the AD780 provides an external 2.5 V reference to the DCAPB pin. This link should be set up in conjunction with LK16.
If both Link Option A and Link Option B are inserted, the AD780 provides the reference voltage, which is output via J25.
This link option selects the source of the AVDD and DVDD supply for the AD7265/AD7266.
In Position A, VDD (+5 V) is supplied from the EVAL-CED1Z.
In Position B, the VDD voltage must be supplied from an external source via J2.
Rev. 0 | Page 4 of 24
EVAL-AD7265/AD7266
Link No.
LK16
LK17
LK18
LK19
LK20
LK21
LK22
LK23
LK24
LK25
LK26
LK27
LK28
LK29
LK30
Description
This link option sets the output reference voltage delivered by the AD780.
When this link is inserted, the AD780 output voltage is set to +3.0 V.
When this link is removed, the AD780 output voltage is set to +2.5 V.
This link option selects the source of the VDRIVE supply for the AD7265/AD7266.
In Position A, VDRIVE is supplied from the EVAL-CED1Z. The value of VDRIVE in this case is 3.3 V.
In Position B, the VDRIVE supply must be supplied from an external source via J3. Note that the logic interface on the EVAL-CED1Z
operates at 3.3 V.
Not populated.
This link option selects the logic input to the REF SELECT pin.
In Position A, the REF SELECT pin is tied to VDRIVE (Logic 1). Therefore, an external reference must be supplied through the
DCAPA/DCAPB pins.
In Position B, the REF SELECT pin is tied to DGND (Logic 0). Therefore, the internal on-chip 2.5 V reference is used.
This link option selects the logic input to the RANGE pin.
In Position A, the RANGE pin is tied to VDRIVE (Logic 1). Therefore, the device is configured for an analogue input range of 0 V
to 2 VREF.
In Position B, the RANGE pin is tied to DGND (Logic 0). Therefore, the analogue input range is 0 V to VREF.
This link option selects the logic input to the SGL/DIFF pin.
In Position A, the ADC is tied to VDRIVE and, therefore, the ADC is configured to operate in single-ended mode.
In Position B, the ADC is tied to DGND and, therefore, the ADC is configured to operate in differential mode.
This link option selects the source of the logic input to the A0 pin. It should be used in conjunction with LK23 and LK24 to
determine the pair of channels to be simultaneously converted.
In Position A, the A0 pin is tied to a VDRIVE, a high logic level.
In Position B, the logic level applied to the A0 pin is controlled via the channel selection option in the software.
In Position C, the A0 pin is tied to DGND, a low logic level.
In Position D, an external A0 logic level can be applied through the external socket, J6.
This link option selects the source of the logic input to the A1 pin; it should be used in conjunction with LK22 and LK24, to
determine the pair of channels to be simultaneously converted.
In Position A, the A1 pin is tied to VDRIVE, a high logic level.
In Position B, the logic level applied to A1 is controlled via the channel selection icon in the software.
In Position C, the A1 pin is tied to DGND, a low logic level.
In Position D, an external A1 logic level can be applied through the external socket, J7.
This link option selects the source of the logic input to the A2 pin; it should be used in conjunction with LK22 and LK23 to
determine the pair of channels to be simultaneously converted.
In Position A, the A2 pin is tied to VDRIVE, a high logic level.
In Position B, the logic level applied to A1 is controlled via the channel selection option in the software.
In Position C, the A2 pin is tied to DGND, a low logic level.
In Position D, an external A2 value can be applied through the external socket, J8.
This link option selects the source of the CS input.
In Position A, the CS input is provided by the EVAL-CED1Z.
In Position B, the CS input is provided via the external SMB socket, J9.
Not populated.
This link option selects the source of the SCLK input.
In Position A, the SCLK input is provided via the external SMB socket, J10.
In Position B, the SCLK input is provided by the EVAL-CED1Z.
This link option selects the destination of the serial data output (DOUTA).
In Position A, the data is supplied to the EVAL-CED1Z.
In Position B, the data is supplied to the external SMB socket, J11.
This link option selects the destination of the serial data output (DOUTB).
In Position A, the data is supplied to the EVAL-CED1Z.
In Position B, the data is supplied to the external SMB socket, J12.
Not populated.
Rev. 0 | Page 5 of 24
EVAL-AD7265/AD7266
Link No.
LK31
LK32 and
LK34
LK33
LK35
LK36
LK37 and
LK39
LK38
LK40
LK41
LK42 and
LK44
LK43
LK45
LK46
LK47 and
LK49
Description
This link option adds a 50 Ω termination to AGND at the V1 DIFF socket (J17) for differential operation.
This link is removed when using the single-ended-to-differential converter.
When this link is inserted, a 50 Ω termination is added to the input signal applied to VI DIFF socket (J17). This link should be
inserted if this circuit is not being used to ground the input to U5-B.
These link options are used in conjunction with each other to set up the AD8022 (U5) dual op amp configuration to convert
either a bipolar or unipolar single-ended signal into a differential signal centered on the common-mode voltage.
Both links should be closed when the bipolar analog input signal biased around 0 V is applied to J17.
Both links should be open when a unipolar analog input biased around 2.5 V is applied to J17.
LK32 should be closed when this circuit is not being used.
This link option selects the common-mode voltage applied to U5-A, the AD8022 dual op amp configuration used to perform
single-ended-to-differential conversion on the analog input.
In Position A, an external common-mode voltage can be applied to U5-A via J18.
In Position B, the +VS input to the AD8022 is tied to AGND, in which case the AD8022 dual op amp is not used.
In Position C, a portion of VREF is applied to U5-A to set up the common-mode voltage.
Not populated.
This link option adds a 50 Ω termination to AGND at the V2 DIFF socket (J19) used for differential operation.
This link is removed when using the single-ended-to-differential converter.
When this link is inserted, a 50 Ω termination is added to the input signal applied to the V2 DIFF socket (J19). This link should be
inserted if this circuit is not being used to ground the input to U6-B.
These link options are used in conjunction with each other to set up the AD8022 (U6) dual op amp configuration to convert
either a bipolar or unipolar single-ended signal into a differential signal centered on the common-mode voltage.
Both links should be closed when the bipolar analog input signal biased around 0 V is applied to J19.
Both links should be open when a unipolar analog input biased around 2.5 V is applied to J19.
LK39 should be closed when this circuit is not being used.
This link option selects the common-mode voltage applied to U6-A, the AD8022 dual op amp configuration used to perform
single-ended-to-differential conversion on the analog input.
In Position A, an external common-mode voltage can be applied to U6-A via J19.
In Position B, the +IN input is tied to AGND, in which case the AD8022 dual op amp is not used.
In Position C, a portion of VREF is applied to U6-A to set up the common-mode voltage.
Not populated.
This link option adds a 50 Ω termination to AGND at the V3 DIFF socket (J20) for differential operation.
This link is removed when using the single-ended-to-differential converter.
When this link is inserted, a 50 Ω termination is added to the input signal applied to the V3 DIFF socket (J20). This link should be
inserted if this circuit is not being used to ground the input to U7-B.
These link options are used in conjunction with each other to set up the AD8022 (U7) dual op amp configuration to convert
either a bipolar or unipolar single-ended signal into a differential signal centered on the common-mode voltage.
Both links should be closed when the bipolar analog input signal biased around 0 V is applied to J20.
Both links should be open when a unipolar analog input biased around 2.5 V is applied to J20.
LK42 should be closed when this circuit is not being used.
This link option selects the common-mode voltage applied to U7-A, the AD8022 dual op amp configuration used to perform
single-ended-to-differential conversion on the analog input.
In Position A, an external common-mode voltage can be applied to U7-A via J21.
In Position B, the +IN input is tied to AGND, in which case the AD8022 dual op amp is not used.
In Position C, a portion of VREF is applied to U7-A to set up the common-mode voltage.
Not populated.
This link option adds a 50 Ω termination to AGND at the V4 DIFF socket (J22) for differential operation.
This link is removed when using the single-ended-to-differential converter.
When this link is inserted, a 50 Ω termination is added to the input signal applied to the V4 DIFF socket (J22). This link should be
inserted if this circuit is not being used to ground the input to U8-B.
These link options are used in conjunction with each other to set up the AD8022 (U8) dual op amp configuration to convert
either a bipolar or unipolar single-ended signal into a differential signal centered on the common-mode voltage.
Both links should be closed when the bipolar analog input signal biased around 0 V is applied to J22.
Both links should be open when a unipolar analog input biased around 2.5 V is applied to J22.
LK47 should be closed when this circuit is not being used.
Rev. 0 | Page 6 of 24
EVAL-AD7265/AD7266
Link No.
LK48
LK50
LK51
LK52
LK53
LK54
LK55
LK56
LK57
Description
This link option selects the common-mode voltage applied to U8-A, the AD8022 dual op amp configuration used to perform
single-ended-to-differential conversion on the analog input.
In Position A, an external common-mode voltage can be applied to U8-A via J23.
In Position B, the +IN input is tied to AGND, in which case the AD8022 dual op amp is not used.
In Position C, a portion of VREF is applied to U8-A to set up the common-mode voltage.
This link option sets the dc bias voltage level that is applied to the optional bias-up circuit used in single-ended mode.
In Position A, the bias voltage is set to VREF/2. This configuration is used in 0 V to 2 VREF mode to set up the bias voltage for a
bipolar single-ended signal.
In Position B, the bias voltage is set to VREF/4. This configuration is used in 0 V to VREF mode to set up the bias voltage for a bipolar
single-ended signal.
This link option adds a 50 Ω termination to AGND at the VIN A socket (J26) of the bias-up circuit for the single-ended input.
When this link is inserted, a 50 Ω termination is added to the input signal applied to the VIN A socket (J26). This link should be
inserted if this circuit is not being used to ground the −IN input terminal of U10-A.
This link option sets the dc bias voltage that is applied to the optional bias-up circuit used in single-ended mode.
In Position A, the bias voltage is set to VREF/2. This configuration is used in 0 V to 2 VREF mode to set up the bias voltage for a
bipolar single-ended signal.
In Position B, the bias voltage is set to VREF/4. This configuration is used in 0 V to VREF mode to set up the bias voltage for a bipolar
single-ended signal.
This link option adds a 50 Ω termination to AGND at the VIN B socket (J27) of the bias-up circuit for the single-ended input.
When this link is inserted, a 50 Ω termination is added to the input signal applied to the VIN B socket (J27). This link should be
inserted if this circuit is not being used to ground the −IN input terminal of U11-B.
Not populated.
Not populated.
This link option is used to select the source of the V− (−12 V) supply, which is used to power the op amps.
In Position A, V− is supplied by the EVAL-CED1Z through the 96-way connector.
In Position B, V− is supplied from an external source via the power connector, J30.
This link option is used to select the source of the V+ (+12 V) supply, which is used to power the op amps.
In Position A, V+ is supplied by the EVAL-CED1Z through the 96-way connector.
In Position B, V+ is supplied from an external source via the power connector, J30.
Rev. 0 | Page 7 of 24
EVAL-AD7265/AD7266
SETUP CONDITIONS
Take care to ensure that all link positions are set according to
the required operating mode before applying power and signals
to the evaluation board. There are a few different modes in
which to operate the evaluation board. Either the user can
operate the board with the EVAL-CED1Z or it can be used as a
standalone board. The board can accept differential and singleended analog input voltages.
Table 2 shows the position in which all the links are set when
the evaluation board is packaged. When the board is shipped,
the assumption is that the user is operating with the EVAL-CED1Z.
The links are set so that all power supplies and control signals
are supplied by the EVAL-CED1Z. The board is configured for
single-ended mode of operation on VA1 and VB1 with a 0 V to
VREF input range. The AD780 provides an external reference
voltage. If the differential mode of operation is required, the link
positions must be configured as outlined in Table 4, Table 5, and
Table 6.
Table 2. Link Positions on the Packaged EVAL-AD7265/AD7266 (Single-Ended Mode of Operation, Channel VA1 and VB1 Selected)
Link No.
LK1
Position
A
LK2
C
LK3
C
LK4
C
LK5
C
LK6
C
LK7
A
LK8
C
LK9
C
LK10
C
LK11
C
LK12
C
LK13
LK14
LK15
LK16
LK17
LK19
LK20
LK21
B
B
A
Open
A
A
B
A
LK22
LK23
LK24
LK25
LK27
LK28
LK29
LK31
LK32, LK34
B
B
C
A
B
A
A
Closed
Closed
Function
VA1 input is supplied from the output of the unity gain buffer U3-A. In this case, a unipolar signal must be
applied to the SVIN1 socket via J13.
VA2 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VA2 is to be converted. In this case, a unipolar signal should be applied to the SVIN2 SMB (J14).
VA3 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VA3 is to be converted. In this case, a unipolar signal should be applied to the SVIN1 SMB (J13).
VA4 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VA4 is to be converted. In this case, a unipolar signal should be applied to the SVIN2 SMB (J14).
VA5 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VA5 is to be converted. In this case, a unipolar signal should be applied to the SVIN1 SMB (J13).
VA6 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VA6 is to be converted. In this case, a unipolar signal should be applied to the SVIN2 SMB (J14).
VB1 is supplied from the output of the unity gain buffer U4-A. In this case, a unipolar signal must be applied to
the SVIN1 socket via J15.
VB2 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VB2 is to be converted. In this case, a unipolar signal should be applied to the SVIN4 SMB (J16).
VB3 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VB3 is to be converted. In this case, a unipolar signal should be applied to the SVIN3 SMB (J15).
VB4 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VB4 is to be converted. In this case, a unipolar signal should be applied to the SVIN4 SMB (J16).
VB5 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VB5 is to be converted. In this case, a unipolar signal should be applied to the SVIN3 SMB (J15).
VB6 input is tied to AGND. Once power supplies are applied to the ADC, this link can be changed to Position A if
VB6 is to be converted. In this case, a unipolar signal should be applied to the SVIN4 SMB (J16).
The AD780 voltage reference provides a 2.5 V reference to the DCAPA pin.
The AD780 voltage reference provides a 2.5 V reference to the DCAPB pin.
The VDD supply (5 V) for the AD7265/AD7266 is provided by the EVAL-CED1Z.
The AD780 reference voltage is set to output +2.5 V.
The VDRIVE 3.3 V supply for the AD7265/AD7266 is provided by the EVAL-CED1Z.
REF SELECT is tied to VDRIVE (Logic 1). The AD780 provides an external reference (2.5 V) to the AD7265/AD7266.
RANGE is tied to DGND (Logic 0). The analog input range is 0 V to VREF.
SGL/DIFF is tied to VDRIVE, enabling single-ended mode. If differential mode is required, then this link option
should be in Position B.
A0 is controlled by channel selection in the evaluation software.
A1 is controlled by channel selection in the evaluation software.
A2 is held low. This input must be changed manually by the user.
CS is provided by the EVAL-CED1Z.
SCLK is provided by the EVAL-CED1Z.
Data from DOUTA is read by the EVAL-CED1Z.
Data from DOUTB is read by the EVAL-CED1Z.
The input to U5-B is tied to AGND because it is not used in single-ended mode.
The inputs to U5-A are tied to AGND because they are not used in single-ended mode.
Rev. 0 | Page 8 of 24
EVAL-AD7265/AD7266
Link No.
LK33
LK36
LK37, LK39
LK38
LK41
LK42, LK44
LK43
LK46
LK47, LK49
LK48
LK50
LK51
LK52
LK53
LK56
LK57
Position
B
Closed
Closed
B
Closed
Closed
B
Closed
Closed
B
B
Open
B
Open
A
A
Function
The input to U5-A is tied to AGND because it is not used in single-ended mode.
The input to U6-B is tied to AGND because it is not used in single-ended mode.
The inputs to U6-A are tied to AGND because they are not used in single-ended mode.
The input to U6-A is tied to AGND because it is not used in single-ended mode.
The input to U7-B is tied to AGND because it is not used in single-ended mode.
The inputs to U7-A are tied to AGND because they are not used in single-ended mode.
The input to U7-A is tied to AGND because it is not used in single-ended mode.
The input to U8-B is tied to AGND because it is not used in single-ended mode.
The inputs to U8-A are tied to AGND because they are not used in single-ended mode.
The input to U8-A is tied to AGND because it is not used in single-ended mode.
The bias input for U12-A is set to VREF/4.
Bias-up circuit is in use.
The bias input for U12-B is set to VREF/4.
Bias-up circuit is in use.
V− is supplied by the EVAL-CED1Z.
V+ is supplied by the EVAL-CED1Z.
Table 3. Link Positions for Single-Ended Mode of Operation with a 0 V to 2 VREF Input Range When a Bipolar Single-Ended Signal Is Used
Link No.
LK20
LK21
LK50
LK51
LK52
LK53
Position
A
A
A
Open
A
Open
Function
RANGE is tied to VDRIVE (Logic 1). The analog input range is 0 V to 2 VREF.
SGL/DIFF is tied to VDRIVE, enabling single-ended mode.
The bias input for U12-A is set to VREF/2.
Bias-up circuit is in use.
The bias input for U12-B is set to VREF/2.
Bias-up circuit is in use.
Table 4. Link Positions for Differential Mode of Operation with a 0 V to VREF Input Range When a Bipolar Single-Ended Signal Is
Used with the Single-Ended-to-Differential Converter
Link No.
LK1
Position
B
LK2
B
LK20
LK21
LK31
LK32, LK34
LK33
B
B
Open
Closed
C
Function
VA1 is supplied from the positive output (V1+) of the single-ended-to-differential converter, U5-B, in which
case a single-ended signal must be applied to V1 DIFF via Socket J17.
VA2 is supplied from the negative output (V1-) of the single-ended-to-differential converter U5-A in which case
a single-ended signal must be applied to V1 DIFF via Socket J17.
The RANGE pin is tied to DGND (Logic 0). Therefore, the analog input range is 0 V to VREF.
The ADC is tied to DGND and, therefore, the ADC is configured to operate in differential mode.
The single-ended-to-differential converter, U5-B, is in use.
These links should be closed when the bipolar analog input signal biased around 0 V is applied to J17.
A portion of VREF is applied to U5-A to set up the common-mode voltage.
Rev. 0 | Page 9 of 24
EVAL-AD7265/AD7266
Table 5. Link Positions for Differential Mode of Operation with a 0 V to 2 VREF Input Range When a Bipolar Single-Ended Signal Is
Used with the Single-Ended-to-Differential Converter
Link No.
LK1
Position
B
LK2
B
LK20
A
LK21
LK31
LK32, LK34
LK33
B
Open
Closed
C
Function
VA1 is supplied from the positive output (V1+) of the single-ended-to-differential converter, U5-B, in which
case a single-ended signal must be applied to V1 DIFF via Socket J17.
VA2 is supplied from the negative output (V1−) of the single-ended-to-differential converter, U5-A, in which
case a single-ended signal must be applied to V1 DIFF via Socket J17.
The RANGE pin is tied to VDRIVE (Logic 1). Therefore, the device is configured for an analog input range of 0 V to
2 VREF.
The ADC is tied to DGND and, therefore, the ADC is configured to operate in differential mode.
The single-ended-to-differential converter, U5-B, is in use.
These links should be closed as the bipolar analog input signal biased around 0 V is applied to J17.
A portion of VREF is applied to U5 to set up the common-mode voltage.
Table 6. Link Positions for Differential Mode of Operation When a Unipolar Input Signal Is Used with the Single-Ended-toDifferential Converter
Link No.
LK1
Position
B
LK2
B
LK21
LK31
LK32, LK34
LK33
LK50
B
Open
Open
C
A
Function
VA1 is supplied from the positive output (V1+) of the single-ended-to-differential converter, U5, in which case a
single-ended signal must be applied to V1 DIFF via Socket J17.
VA2 is supplied from the negative output (V1−) of the single-ended-to-differential converter, U5, in which case
a single-ended signal must be applied to V1 DIFF via Socket J17.
The ADC is tied to DGND and, therefore, the ADC is configured to operate in differential mode.
The single-ended to differential converter, U5, is in use.
These links should be open as the bipolar analog input signal biased around 2.5 V is applied to J17.
A portion of VREF is applied to U5-A to set up the common-mode voltage.
The bias input for U12-A is set to VREF/2.
Rev. 0 | Page 10 of 24
EVAL-AD7265/AD7266
SOCKETS
CONNECTORS
There are 25 SMB input/output sockets relevant to the operation of
the AD7265/AD7266 on this evaluation board. All of these sockets
are used for applying an externally generated signal to the evaluation board or for accessing an output signal from the AD7265/
AD7266. When operating the board with the EVAL-CED1Z
board, the only external sockets necessary are those used to
supply the analog input signals to the ADC (that is, VA1 to VA6
and VB1 to VB6). All of the other sockets are optional and if they
are not used, their signals are supplied by the EVAL-CED1Z.
Most of these sockets are used when operating the board as a
standalone unit because all the signals required are supplied
from external sources. The functions of these sockets are
outlined in Table 8.
There are four connectors on the EVAL-AD7265/AD7266 as
outlined in Table 7.
Table 7. Connector Functions
Connector
J1
J2
J3
J30
Function
96-way connector for the digital interface and
power supply connections
External VDD power connector
External VDRIVE power connector
External +12 V, −12 V and AGND power connector
Table 8. Socket Functions
Reference
Designator
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
Socket
EXT COM2
A0
A1
A2
CS
SCLK
DOUTA
DOUTB
SVIN1
SVIN2
SVIN3
SVIN4
V1 DIFF
J18
J19
EXT COM1
V2 DIFF
J20
V3 DIFF
J21
J22
EXT COM3
V4 DIFF
J23
J24
EXT COM4
DCAPA
J25
DACPB
J26
J27
J28
J29
VIN A
VIN B
VBIASED-A
VBIASED-B
Function
Subminiature BNC socket for an external common-mode voltage to be applied to U6.
Subminiature BNC socket for an external A0 logic level.
Subminiature BNC socket for an external A1 logic level.
Subminiature BNC socket for an external A2 logic level.
Subminiature BNC socket for an external CS signal.
Subminiature BNC socket for an external SCLK input.
Subminiature BNC socket for the DOUTA output.
Subminiature BNC socket for DOUTB output.
Subminiature BNC socket for a unipolar signal that is buffered by U3-A and applied to the ADC.
Subminiature BNC socket for a unipolar signal that is buffered by U3-B and applied to the ADC.
Subminiature BNC socket for a unipolar signal that is buffered by U4-A and applied to the ADC.
Subminiature BNC socket for a unipolar signal that is buffered by U4-B and applied to the ADC.
Subminiature BNC socket for a bipolar or unipolar single-ended input that is applied to the single-endedto-differential conversion circuit (U5-B).
Subminiature BNC socket for an external common-mode voltage to be applied to U6.
Subminiature BNC socket for a bipolar or unipolar single-ended input that is applied to the single-endedto-differential conversion circuit (U6-B).
Subminiature BNC socket for a bipolar or unipolar single-ended input that is applied to the single-ended
to-differential conversion circuit (U7-B).
Subminiature BNC socket for an external common-mode voltage to be applied to U7.
Subminiature BNC socket for a bipolar or unipolar single-ended input that is applied to the single-ended
to-differential conversion circuit (U8-B).
Subminiature BNC socket for an external common-mode voltage applied to U8.
Subminiature BNC socket for an external reference voltage to be applied to DCAPA or to access the internal
reference from the AD7265/AD7266.
Subminiature BNC socket for an external reference voltage to be applied to DCAPB or to access the internal
reference from the AD7265/AD7266.
Subminiature BNC socket for a bipolar single-ended input to be applied to Bias-Up Circuit A.
Subminiature BNC socket for a bipolar single-ended input to be applied to Bias-Up Circuit B.
Output from Bias-Up Circuit A, which can be applied to SVINx for single-ended mode of operation.
Output from Bias-Up Circuit B, which can be applied to SVINx for single-ended mode of operation.
Rev. 0 | Page 11 of 24
EVAL-AD7265/AD7266
INTERFACING THE EVALUATION BOARD TO THE
EVAL-CED1Z
1
8
16
24
32
1
8
16
24
32
A
B
C
07921-002
Interfacing the EVAL-CED1Z board to the evaluation board is
via a 96-way connector, J1. The pinout for the J1 connector is
shown in Figure 2. Table 9 gives a description of the pins on the
96-way connector that are used to interface the EVAL-CED1Z
to the EVAL-AD7265/AD7266.
Figure 2. Pin Configuration for the 96-Way Connector, J1
Table 9. The 96-Way Connector Pin Description
Signal
DR1PRI
DR0SEC
RSCLK0
TFS0
RFS0
VDD
VDRIVE
−5 V
DGND
AGND
+12 V
−12 V
FL0
GPIO3
Description
Data receive primary. This input is connected to the
DOUTA pin of the AD7265/AD7266.
Data receive secondary. This input is connected to the
DOUTB pin of the AD7265/AD7266.
Receive clock. This continuous clock is connected to
the SCLK pin of the AD7265/AD7266 via LK27.
Transmit frame sync. This output is connected to the
CS pin of the AD7265/AD7266 via LK25 to frame the
serial data transfer.
Receive frame sync. This input is connected to the TFS
pin on the EVAL-CED1Z to frame the serial data read.
Analog +5 V supply. These lines are connected to the
VDD line on the board via LK15.
Digital +3.3 V supply. This is used to provide the VDRIVE
supply to the board via LK17 for the digital logic.
Analog −5 V supply. This supply is not used on the
EVAL-AD7265/AD7266.
Digital ground. These lines are connected to the
digital ground plane on the evaluation board.
Analog ground. These lines are connected to the
analog ground plane on the evaluation board.
+12 V supply (VCC). This line is connected to the +12 V
supply line on the board via LK57.
−12 V supply (VSS). This line is connected to the −12 V
supply line on the board via LK56.
Flag zero. This output is connected to the A0 pin of
the AD7265/AD7266 via LK22.
General-purpose input/output. This input is connected
to the A1 pin of the AD7265/AD7266 via LK23.
Table 10. 96-Way Connector Pin Functions1
Pin
1
2
3
4
Row A
DT1PRI
TFS1
TSCLK1
DGND
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
DGND
Row C
DR1PRI
RFS1
RSCLK1
DGND
DT0PRI
TFS0
TSCLK0
VDRIVE (+3.3 V)
VDRIVE (+3.3 V)
DR0PRI
RFS0
RSCLK0
VDRIVE (+3.3 V)
DT0SEC
DGND
DGND
GPIO5
GPIO0
DGND
FL0
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
−12 V
−5 V
VDD (+5 V)
Row B
GPIO3
DGND
GPIO1
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
−5 V
VDD (+5 V)
GPIO6
DGND
DR0SEC
GPIO7
GPIO4
DGND
GPIO2
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
+12 V
−5 V
VDD (+5 V)
The unused pins of the 96-way connector are not shown.
TEST POINTS
There are two test points on the inputs to the AD7265/AD7266
on the evaluation board. Test points enable the user to have easy
access to various signals on the EVAl-AD7265/AD7266, facilitating probing, evaluation, and debugging.
Rev. 0 | Page 12 of 24
EVAL-AD7265/AD7266
OPERATING WITH THE EVAL-CED1Z
The evaluation board can be operated in a standalone mode or
it can be operated in conjunction with the EVAL-CED1Z. This
evaluation board controller is available from Analog Devices
under the order entry, EVAL-CED1Z.
When interfacing the EVAL-AD7265/AD7266 directly to the
EVAL-CED1Z board, all supplies and control signals to operate
the AD7265/AD7266 board are provided by the EVAL-CED1Z.
The AD7266 can operate at 2 MSPS with SCLK frequencies up
to 32 MHz, and the AD7265 can operate with a 16 MHz SCLK
to give a 1 MSPS throughput. The SCLK frequency supplied by
the EVAL-CED1Z is fixed at 32 MHz for the AD7266. The software allows the user to change the throughput rate by effectively
modifying the CS high time.
Software to communicate with the EVAL-CED1Z and
AD7265/AD7266 is provided with the AD7266/AD7266
evaluation board package.
The 96-way connector on the EVAL-AD7265/AD7266 plugs
directly into the 96-way connector on the EVAL-CED1Z. The
evaluation board is powered from a 7 V, 15 W power supply
that accepts input voltages from 100 V to 240 V ac, and contains
the relevant adaptors for worldwide use.
Connection between the EVAL-CED1Z and the USB port of a
PC is via a standard USB 2.0 connection cable that is provided
as part of the EVAL-CED1Z package.
Rev. 0 | Page 13 of 24
EVAL-AD7265/AD7266
EVALUATION BOARD SOFTWARE
INSTALLING THE SOFTWARE
SETTING UP THE EVAL-CED1Z
The EVAL-AD7265/AD7266 evaluation kit includes self-installing
software on a CD-ROM for controlling and evaluating the
performance of the AD7265/AD7266 when it is operated with
the EVAL-CED1Z board. The software is compatible with
Windows® 2000/XP®. If the setup file does not run automatically, setup.exe can be run from the CD-ROM.
This section describes how the evaluation board, the
EVAL-CED1Z, and the software should be set up to begin
using the complete system.
When the CD is inserted into the PC, an installation program
automatically begins. This program installs the evaluation
software. The user interface on the PC is a dedicated program
written especially for the AD7265/AD7266 when operating
with the EVAL-CED1Z board.
Install the software before the USB cable is connected between
the EVAL-CED1Z and the PC. This ensures that the appropriate
USB driver files have been properly installed before the EVALCED1Z is connected to the PC.
When the software is run for the first time with the EVAL-CED1Z
connected to the PC, the PC automatically finds the new device
and identifies it. Follow the onscreen instructions that appear
automatically. This installs the drivers for the EVAL-CED1Z on
the PC. If an error appears onscreen when the software is first
opened, then the PC is not recognizing the USB device. To
correct this error,
1.
2.
3.
4.
5.
1.
2.
3.
4.
5.
Install the AD7265/AD7266 evaluation board software.
Connect the EVAL-CED1Z and the evaluation board
together via the 96-way connector. Apply power to the
EVAL-CED1Z via the provided 7 V, 15 W power supply.
At this stage, the green LED labeled Power on the
EVAL-CED1Z should light up, which indicates that
the EVAL-CED1Z is receiving power.
Connect the USB cable between the PC and the
EVAL-CED1Z. A green LED positioned beside the USB
connector on the EVAL-CED1Z lights up, indicating that
the USB connection has been established.
The EVAL-AD7265/AD7266 are detected. Proceed through
any dialog boxes that may appear (use the recommended
options) to finalize the installation.
Start the EVAL-AD7265/AD7266 software.
The FPGA on the EVAL-CED1Z is automatically programmed
when the software is opened. The two red LEDs (D14 and D15)
on the EVAL-CED1Z now light up. This indicates that the
EVAL-CED1Z is functional and ready to receive instructions.
Right-click the My Computer icon, then select Properties.
When the System Properties window opens, select the
Hardware tab.
Click Device Manager in the Hardware Tab of the System
Properties window.
Examine the devices listed under the Universal Serial Bus
Controller heading.
If an unknown device is listed, right-click this option and
select Update Driver.
The New Hardware Wizard runs twice. Under ADI
Development Tools, the hardware is listed as ADI Converter
Evaluation and Development Board (WF).
Reboot your PC.
Rev. 0 | Page 14 of 24
EVAL-AD7265/AD7266
SOFTWARE OPERATION
With the hardware set up, you can now use the software to
control the EVAL-CED1Z and the AD7266 or AD7265
evaluation board. To launch the software, from the Analog
Devices menu, select the AD7266/AD7265 submenu, and then
click the AD7266/AD7265 icon.
Figure 3 shows the window that appears when the software is
run. The main function of this window is to allow you to read a
predetermined number of samples from the evaluation board and
display them in both the time and frequency domain. The window
can be divided into three main sections: Part Information,
Data Capture, and Linearity. The menu bar is located at the top
portion of the window, with the Part Information panel on the
left-hand side of the window. The Data Capture and Linearity
tabs are in the center. The Data Capture tab consists of four
subtabs: Waveform, Histogram, FFT, and Summary. The
Linearity tab, which enables you to generate a linearity plot for
the device, consists of three subtabs: Histogram, INL, and DNL.
07921-003
Figure 3 displays the main window that is opened. If an error
message appears, click OK and restart the application after
checking the connection between the adapter board and the
USB port on the PC. Also check that the USB device is
identified by the Device Manager as detailed in the Installing
the Software Section.
The software that controls the EVAL-CED1Z and, therefore, the
AD7265/AD7266 evaluation board, has two main windows.
Figure 3. AD7266 Main Window
Rev. 0 | Page 15 of 24
EVAL-AD7265/AD7266
USING THE SOFTWARE
samples taken, for example, the minimum/maximum position
or velocity, the spread, the standard deviation, and the mean.
Menu Bar
The menu bar consists of the following menus: File, Edit,
Operate, Tools, Window, and Help.
Part Information Panel
The Part Information panel allows you to select the following
configuration options:
•
•
•
•
•
The part number box allows you to select the part being
tested by typing in the appropriate part number, either
AD7265 or AD7266.
Sampling Rate allows you to set the sampling frequency.
The maximum sampling frequency supported by the
EVAL-AD7265/AD7266 is 1.4 MSPS for the AD7266 and
1 MSPS for the AD7265.
Input Mode allows you to select from single-ended,
differential, or pseudodifferential mode.
Input Channel Selection allows you to select the pair of
channels for conversion. This channel selection option
must be used in conjunction with LK24 on the board.
Alternatively, LK22, LK23, and LK24 can be used instead
to select the channels for conversion in the hardware, in
which case this option is not used.
Voltage Span allows you to select between 0 V to VREF and
0 V to 2 VREF mode of operation.
•
Histogram Tab
The Histogram tab displays a histogram of the captured ADC
codes. It can be used to give an indication of the ADC’s performance in response to dc inputs. The Histogram Analysis
section contains information about the samples taken, for
example, maximum and minimum codes captured.
FFT Tab
This tab displays a fast Fourier transform (FFT) plot. The FFT
is typically used for examining the ADC’s performance in the
frequency domain. The Spectrum Analysis section contains
information about the samples taken, for example, ac specifications. You can choose whether to display the information for
ADC A, or ADC B, or both in the window using the ADC A
ON/OFF and ADC B ON/OFF buttons, as explained in the
Waveform Tab section.
Summary Tab
The Part Information tab also provides the following
information:
•
The waveform graph displays the information for both ADC A
and ADC B, or either ADC as desired. Two buttons located on
the bottom right-hand side of the graph, labeled ADC A
ON/OFF and ADC B ON/OFF are used to select which ADC’s
data is displayed. An indicator, located on the top right-hand
corner of the graph, shows what color graph represents each
ADC when the data from both ADCs is displayed.
Resolution. The software automatically sets the resolution
at 12 bits.
Data Format. The software automatically sets the data
output format to straight binary or twos complement.
The Part Information tab also includes a Busy status indicator
that lights when the evaluation board is busy, and an Exit
button that allows you to quit the program.
Data Capture Tab
In the Data Capture tab, you can select the number of samples
to be captured from the # Samples drop-down box. The default
number of samples is 4096; you are free to change this as
required. The desired display option is selected by clicking one
of the Waveform, Histogram, or FFT tabs.
Waveform Tab
The Waveform subtab displays a digital storage oscilloscope
(DSO) that allows you to display a waveform. When samples are
uploaded from the EVAL-CED1Z board, they are displayed
here. The samples are displayed as integer code values.
At the bottom left of the graph are the zoom options. These
allow you to zoom in and out for a closer look at a sample, if
required. The Waveform Analysis section, which is located
beneath the waveform graph, contains information about the
This tab shows a summary of the information displayed in each
of the discrete tabs; that is, the waveform, histogram and FFT plots.
Linearity Tab
In the Linearity tab, you can select the number of hits per code
to be captured for the linearity analysis. The desired display option
is selected by clicking the Histogram, INL, DNL, or Summary
tabs. To initiate the data collection, click the Get Linearity Data
button. The data collection and analysis takes a few seconds to
complete. The greater the number of hits per code selected, the
longer the analysis takes.
Histogram Tab
The Histogram tab displays a histogram of the captured ADC
codes. It can be used to give an indication of the ADC’s performance in response to dc inputs. The Histogram Analysis
section contains information about the samples taken, for
example, maximum and minimum codes captured.
INL Tab
The INL tab displays an INL plot for the AD7266 or AD7265.
This plot can be used to examine the dc performance of the
ADC. The Linearity Analysis section contains information
on the maximum and minimum INL error and the code at
which this error occurred. It also shows the total number of
hits per code and the number of samples taken.
Rev. 0 | Page 16 of 24
EVAL-AD7265/AD7266
DNL Tab
The DNL tab displays a DNL plot for the AD7266 or AD7265.
This plot can be used to examine the dc performance of the
ADC in conjunction with the INL plot. The Linearity Analysis
section contains information on the maximum and minimum
DNL error and the code at which this error occurred.
TAKING SAMPLES
To initiate a conversion and capture the sample data, you must
click the Sample button or the Continuous button. Both the
Sample and the Continuous buttons are located on the top
right-hand corner of the Data Capture tab. When you click the
Sample button, the software instructs the EVAL-CED1Z to take
the required number of samples at the required frequency from
the evaluation board. The AD7266 evaluation board runs with a
sampling speed less than or equal to 2 MSPS, and the AD7265
evaluation board runs with a sampling speed less than 1 MSPS.
You can choose the sampling frequency up to this rate and the
number of samples to be taken.
The samples taken are then uploaded and displayed. An FFT
and/or histogram can be calculated and displayed. If you click
the Continuous button, the software repeats the process
indefinitely until you click Stop. (The Continuous button
switches to Stop when clicked). You can switch between
displaying data from ADC A, ADC B, or both while the
software is running continuously.
Rev. 0 | Page 17 of 24
EVAL-AD7265/AD7266
EVALUATION BOARD SCHEMATICS AND ARTWORK
07921-004
EVAL-AD7265/AD7266 schematics, silkscreen, and layout can be found in Figure 4 to Figure 9.
Figure 4. AD7265/AD7266 Evaluation Board Circuit Diagram 1
Rev. 0 | Page 18 of 24
07921-005
EVAL-AD7265/AD7266
Figure 5. AD7265/AD7266 Evaluation Board Circuit Diagram 2
Rev. 0 | Page 19 of 24
07921-006
EVAL-AD7265/AD7266
Figure 6. AD7265/AD7266 Evaluation Board Circuit Diagram 3
Rev. 0 | Page 20 of 24
07921-007
EVAL-AD7265/AD7266
07921-008
Figure 7. AD7265/AD7266 Evaluation Board PCB Layout—Component Side
Figure 8. AD7265/AD7266 Evaluation Board PCB Layout—Solder Side
Rev. 0 | Page 21 of 24
07921-009
EVAL-AD7265/AD7266
Figure 9. AD7265/AD7266 Evaluation Board PCB Layout—Silkscreen
Rev. 0 | Page 22 of 24
EVAL-AD7265/AD7266
ORDERING INFORMATION
BILL OF MATERIALS
Table 11.
Qty
6
12
16
1
Reference Designator
R17, R25, R33, R41, R47, R54
R1 to R12
R14 to R16, R18, R22 to R24, R26, R30 to R32, R34, R38 to
R40, R42
R13, R21, R29, R37
R45, R46, R48, R50 to R53, R55, R57 to R60
R49, R56
R20, R28, R36, R44
R19, R27, R35, R43
C33 to C36
C1 to C12
C13, C14
C16, C17, C20, C21, C23, C26, C30, C37, C44 to C50, C53,
C54, C59, C60, C63 to C67, C72, C74, C76, C78, C80
C15, C18, C19, C22, C27, C31, C38 to C43, C51, C52, C55 to
C58, C61, C62, C68 to C71, C73, C75, C77, C79
U1
1
9
1
57
1
2
U2
U3 to U8 and U10 to U12
D1
LK1 to LK57
J1
J2, J3
1
J30
25
J5 (EXT COM2), J6 (A0), J7 (A1), J8 (A2), J9 (CS), J10 (SCLK),
J11 (DOUTA), J12 (DOUTB), J13 (SVIN1), J14 (SVIN2),
J15 (SVIN3), J16 (SVIN4), J17 (V1 DIFF), J18 (EXT-COM1),
J19 (V2 DIFF), J20 (V3 DIFF), J21 (EXT COM3), J22 (V4 DIFF),
J23 (EXT COM4), J24 (DCAPA), J25 (DCAPB), J26 (VIN A),
J27 (VIN B), J28 (VBIASED-A), J29 (VBIASED-B)
T1, T4
4
12
2
4
4
4
12
2
29
28
2
1
Supplier/Number 1
FEC 9331336
FEC 9331433
FEC 9330801
390 Ω resistor
1 kΩ resistor
3 kΩ resistor
10 kΩ resistor
20 Ω resistor
68 pF capacitor
1 nF capacitor
470 nF capacitor
0.1 µF capacitor
FEC 9331131
FEC 9330380
FEC 9330976
FEC 9330399
FEC 9330771
FEC 722-066
FEC 722-170
FEC 318-8851
FEC 432-210
10 µF, 10 V capacitor
FEC 197-130
AD7266 or AD7265 ADC
Analog Devices AD7266BSUZ,
AD7265BSUZ
Analog Devices AD780ARZ
Analog Devices AD8022ARZ
Digi-Key SD103CTPMSCT-ND
FEC 1022244
FEC 1096832
FEC 3041359
AD780 reference
AD8022 op amp
20 V Schottky diode
Jumper
96-way connecter, CON\41612\96
Terminal block, 2-way power
connector
Terminal block, 3-way power
connector
SMB connector
FEC 1111349
Test points
FEC 8731144
FEC refers to Farnell Electronics.
ESD CAUTION
ORDERING GUIDE
Model
EVAL-AD7265EDZ1
EVAL-AD7266EDZ1
EVAL-CED1Z1
1
Description
51 Ω resistor
62 Ω resistor
220 Ω resistor
Description
Evaluation Board for AD7265
Evaluation Board for AD7266
Controller Board
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
FEC 3041360
EVAL-AD7265/AD7266
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
EB07921-0-4/09(0)
Rev. 0 | Page 24 of 24
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