EVAL-AD974CB

a Evaluation Board AD974 4-Channel, 16-Bit, 200 kSPS ADC EVAL-AD974CB The EVAL-AD974CB is ideal for use as either a stand-alone evaluation board to interface with customer application, or with the EVAL-CONTROL BOARD, also available from Analog Devices. The design offers the flexibility of applying external control signals and is capable of generating 16-bit conversion results as both serial and parallel buffered outputs. FEATURES Versatile Analog Signal Conditioning Circuitry Jumper Selectable Analog Input Ranges Analog and Digital Prototyping Area Flexible Power and Grounding Schemes On-Board Reference and Buffers 16-Bit Serial and Parallel Buffered Outputs Ideal For DSP and Data Acquisition Card Interfaces EVAL-CONTROL BOARD Compatibility PC Software for Control and Data Analysis GENERAL DESCRIPTION The EVAL-AD974CB is an evaluation board for the AD974 four-channel, 16-bit data-acquisition system. The AD974 is capable of a 200 kSPS throughput rate, operates from a single +5 V supply and uses a flexible serial interface. The AD974 evaluation board is designed to demonstrate the ADC’s performances and to provide an easy to understand interface for a variety of system applications. A full description of the AD974 is available in the AD974 data sheet and should be consulted when using this evaluation board. On-board components include an AD780, a +2.5 V ultrahigh precision bandgap reference, an AD845 signal conditioning op amp, and digital buffers. The board interfaces with a 96-pin connector for the EVAL-CONTROL BOARD, a 20-pin IDC connector for both externally applied control signals and serial output interfaces, and a 40-pin IDC connector for parallel output data. SMB connectors are provided for the low noise analog signal source and BNC connectors are provided for an external data clock and an external read/convert input. FUNCTIONAL BLOCK DIAGRAM AIN1 VA1 VB1 SIGNAL CONDITIONING AD845 SELECTABLE INPUT RANGE SELECTABLE SUPPLY PWRD VA2 VB2 VA3 VB3 DATA SHIFT REG AD974 BIP AIN3 ⴞ12V VCC VA4 VB4 AIN2 ⴞ5V EXT/INT 40-PIN CONNECTOR DATA DATACLK 96-PIN CONNECTOR BUSY REF 2.5V AD780 R/C REF AIN4 A0 A1 WR2 WR1 SYNC B U F F E R S 20-PIN CONNECTOR CS REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 EVAL-AD974CB OPERATING THE EVAL-AD974CB Analog Input Ranges The AD974-CB is a four-layer board carefully laid out and tested to demonstrate the specific high accuracy performance of the device. Figure 2 shows the schematics of the evaluation board. Figure 3 shows the component side silkscreen. The layouts of the board are given in: The AD974-CB provides the flexibility of operating the AD974 in each of its specified analog input ranges. Through easy to follow jumper selections, the four channels of the AD974 can be operated independently in the bipolar input range ± 10 V, or in all two unipolar input ranges of 0 V to +4 V, and 0 V to +5 V. Table I through Table III list the jumper configurations for each input range. Component Layer – Figure 4 Power Layer – Figure 5 Ground Layer – Figure 6 Circuit Side Layer – Figure 7. Table I. ⴞ10 V Analog Input Range The AD974-CB is a flexible design that enables the user to choose among many different board configurations. The available test points are listed in Table IV and a description of each selectable jumper is listed in Table V. The evaluation board schematic shows the factory installed jumper selections. The AD974 is configured for ± 10 V input range on each channel, powered through the EVAL-CONTROL BOARD, the AD780 external reference applied to the REF pin and on-board R/C generation used. The serial interface is configured to operate with its internal data clock, DCLK. Conversion data is available at the outputs of two 8-bit shift registers, U4 and U5, for parallel transfer via the 40-pin IDC connector, J4, or the 96-pin DIN connector, P5. Additionally, conversion results are available in serial format from the 20-pin connector, P4. The AD974 conversion control inputs, R/C and CS, are configured to provide continuous conversions with the CS input set low and the R/C input connected to the output of the counter, U6. Jumper Designation Header Shunt Position JP12, JP27, JP23, JP25 JP11, JP26, JP22, JP24 B B Table II. 0 V to +4 V Analog Input Range Jumper Designation Header Shunt Position JP12, JP27, JP23, JP25 JP11, JP26, JP22, JP24 A B Table III. 0 V to +5 V Analog Input Range Jumper Designation Header Shunt Position JP12, JP27, JP23, JP25 JP11, JP26, JP22, JP24 A A Table IV. EVAL-AD974CB Test Points Power Supplies and Grounding The AD974-CB power supply connectors and ground planes are configured to provide the multiple power and grounding configurations used in most system applications. The evaluation board ground plane is separated into two sections: a plane for the digital interface circuitry and an analog plane for the AD974 and its analog input and external reference circuitry. To attain high resolution performance the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths. The EVAL-AD974CB has three power supply blocks: a single +5 V supply for the AD974 VANA and VDIG power pins (P1), a +5 V supply for the digital interface circuitry (P2), and a ± 12 V supply for the analog signal conditioning circuitry (P3). All supplies are decoupled to ground with 10 µF tantalum and 0.1 µF ceramic capacitors. Figure 1 shows the recommended power connection diagram. ANALOG POWER SUPPLIES +15V GND –15V +VCC AGND –VEE P3 P4 DIGITAL SYSTEM POWER +5V GND Test Point Available Signal TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 AIN1 (BUFFERED) BUSY R/C DGND VDIG AGND1 SYNC DCLK DATA CAP AGND AIN1 (SMB) –VCC +VCC VANA AGND R/C (BNC) +5V GND VANA AGND P1 P2 VDIG DGND Figure 1. Power Connection Diagram –2– REV. A EVAL-AD974CB EVAL-CONTROL BOARD Interface Software Installation The EVAL-AD974CB interfaces to the EVAL-CONTROL BOARD through the 96-pin connector. The AD974-CB software runs under DOS 4.0 or higher. It requires a minimum of 386-based machine, with 500 kB of base RAM and 500 kB of free hard disk space. It may be necessary to disable some TSRs (network TSRs for example) or load them into high memory, to ensure that adequate base memory is available. Operation under Windows® 3.x is not recommended since the Windows COM interrupt can interfere with communication between the PC and the EVAL-CONTROL BOARD. For PC running under Windows 95, it is recommended to shut it down using the option restart with the computer in MS-DOS mode. RUNNING THE EVAL-AD974CB SOFTWARE Software Description The EVAL-AD974CB comes with software for analyzing the AD974. Through the EVAL-CONTROL BOARD one can perform a histogram to determine code transition noise, and Fast Fourier Transforms (FFT’s) to determine the Signal to Noise Ratio (SNR), Signal to Noise plus Distortion (SNRD) and Total Harmonic Distortion (THD). The front-end PC software has three screens as shown in Figures 8, 9 and 10. Figure 8 is the Setup Screen where channel selection, input voltage range, sample rate, number of samples are selected. Figure 9 is the Histogram Screen, which allows the code distribution for dc input and computes the mean and standard deviation. Figure 10 is the FFT Screen, which performs an FFT on the captured data, computes the Signal-to-Noise Ratio (SNR), Signal to Noise plus Distortion (SNRD) and Total Harmonic Distortion (THD). The AD974-CB software installation process is: – Create a new directory on the main PC drive and label this “AD974.” – Copy into this directory all files contained in the disk that accompanies the EVAL-AD974CB. – The software can be started by typing “AD974.” Note that the Mouse Driver on the PC should be enabled before running the software. If this has not been loaded, the program will not run. Table V. Jumper Description Jumper Designation JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP11, JP12 JP13 Function JP1 controls the state of the AD974 power-down pin, PWRD. With JP1 in Position B, conversions are inhibited and the AD974 power consumption is significantly reduced. For normal operation of the AD974, JP1 should be in Position A. JP2 selects the EXT/INT input to the AD974. Set JP2 to Position B and the AD974 requires an external data clock to transmit data. Position A chooses the internal clock mode. JP3 allows use of an external DCLK. When J2 is in Position A, internal clock mode is used and JP3 should be removed. When J2 is in Position B, external clock mode is used and the signal EXT DCLK from BNC connector, J2 is applied to the DCLK input of the AD974. With JP5 set to Position A, JP4 selects the signal source for the R/C input to the AD974. Set JP4 to Position A to use the on-board 200 kHz signal from the 74HC190. Select Position B to use the external R/C signal from the BNC connector, J1. With JP5 in Position A, the R/C input to the AD974 is applied from either the 74HC190 or the external source, J1. With JP5 in Position B, the R/C input is a buffered signal (FL0) from the EVAL-CONTROL BOARD and an input from the 20-pin IDC connector. JP6 selects the WR2 input to the AD974. With shunt header in JP6, the AD974 WR2 input is tied to a logic low. When shunt header in JP6 is removed, the AD974 WR2 input comes from the 20-pin IDC connector. JP7 selects the WR1 input to the AD974. With shunt header in JP7, the AD974 WR1 input is tied to a logic low. When shunt header in JP7 is removed, the AD974 WR1 input comes from the 20-pin IDC connector. JP8 selects the CS input to the AD974. With shunt header in JP8, the AD974 CS input is tied to a logic low. When shunt header in JP8 is removed, the AD974 CS input comes from the 20-pin IDC connector. JP3 allows use of an external read clock, EXT RCLK. With shunt header in JP9, the AD974 BUSY signal enables the data reading. When shunt header in JP9 is removed, the signal EXT RCLK from BNC connector, J5 enables the data reading. With JP10 set to Position A, gain adjustment for the AD974 is possible. Position B selects the AD780 for use as an external reference. Remove the shunt header of JP10 to use the AD974 internal reference without gain adjustment. These TWO jumpers set the analog input ranges for Channel 1 according to Table I through Table III. With JP13 tied to Position A, the analog Channel 1 input comes from either the analog signal source (AIN1) from J3, or the output of the op amp, U3. Set to Position B, the analog input is tied to analog ground. Windows is a registered trademark of the Microsoft Corporation. REV. A –3– EVAL-AD974CB Jumper Designation JP14 JP15, JP16 JP17 JP18 JP19 JP20 JP21 JP22, JP23 JP24, JP25 JP26, JP27 JP28 Function JP14 determines the source of the analog Channel 1 input of the AD974. To supply the AD974 analog Channel 1 input signal directly from the SMB connector, J3, set JP14 to Position B. Set JP14 to Position A to select the op amp output. These two jumpers are used to select the configuration of the op amp, U3. To configure the op amp as an inverter, install the header shunt of JP15 to Position A and JP16 to Position B. To configure the op amp as a noninverter, install the header shunt of JP15 to Position B and JP16 to Position A. JP17 selects the digital power source for the AD974-CB digital interface circuitry. Install the jumper to provide a single +5 V supply to all of the on-board components. Remove this header shunt to separate the analog supply for the AD974 from the supply for the digital interface circuitry. When used in conjunction with the EVALCONTROL BOARD, VANA and VDIG are respectively the +5 V and VDD from the 96-pin connector. When this header shunt is installed, JP28 must also be installed. With JP19 in Position B, the header shunt for JP18 allows the positive supply voltage of op amp, U3, to come from either connector P3 (Position A), or the +12 V supply from the EVAL-CONTROL BOARD (Position B). With JP19 set to Position A, the positive supply for the op amp, U3, is connected to VANA. When JP19 is set to Position B, U3’s positive supply voltage is connected to either the +12 V from the EVAL-CONTROL BOARD (JP18 Position B), or the external supply (+VCC) from connector P3 (JP18 Position A). With JP21 in Position A, the header shunt for JP20 allows the negative supply voltage of op amp, U3, to come from either connector P3 (Position B), or the –12 V supply from the EVAL-CONTROL BOARD (Position A). With JP21 set to Position B, the negative supply for the op amp, U3, is connected to analog ground (AGND). When JP21 is set to Position A, U3’s negative supply voltage comes from either the –12 V from the EVAL-CONTROL BOARD (JP20 Position A) or the external supply (–VCC) from connector P3 (JP20 Position B). These TWO jumpers set the analog input ranges for Channel 3 according to Tables I through Table III. These TWO jumpers set the analog input ranges for Channel 4 according to Tables I through Table III. These TWO jumpers set the analog input ranges for Channel 2 according to Tables I through Table III. Install JP28 when using a single +5 V supply for the EVAL-CONTROL BOARD. Thus, install JP28 when JP17 is connected. –4– REV. A REV. A –5– Figure 2. Schematic A 15 CLK 14 RCO 13 MX/MN 12 LOAD 11 C 10 D 9 QB QA CTEN D/U QC QD GND 2 3 4 5 6 7 8 U6 74HC190 VCC 16 B U2 TRIM 5 VANA C20 0.1␮F VANA B A A B VANA R5 1M⍀ 2.000MHz X1 GND TP11 TP10 TP6 B JP12 DCLK 16 SYNC 15 13 EXT/INT 14 DGND DATA 17 WR2 18 WR1 19 CS 20 BUSY 21 A1 22 12 PWRD 11 VDIG 10 R/C 9 AGND2 8 REF U1 AD974 A0 23 VA1 25 VB1 26 VA2 27 VB2 28 6 BIP 7 CAP TP7 3 TP9 JP9 U9 C22 0.1␮F 1,4–10,19 74HC541 20 VANA 24 B U9 VDIG 1,8,12,14,15 74HC366 16 5 VB4 4 VA4 3 VB3 2 VA3 1 AGND1 A A JP11 1,10,19 74HC541 B U8 20 C21 0.1␮F U7 C16 0.1␮F B –VCC A JP21 –12V 17 R/C TP8 18 U9 2 JP3 3 J2 U7 J5 14 16 5 SER U8 U8 EXT RCLK 4 14 U7 20 19 6 4 6 QH QG QF QE QD QC QB QA QH 74HC595 SER 16 V CC 8 GND 13 U5 G 12 RCLK 10 SRCLR 11 SRCLK VDIG 14 QH QG QF QE QD QC QB QA QH 74HC595 16 V CC 8 GND 13 U4 G 12 RCLK 10 SRCLR 11 SRCLK VDIG C7 0.1␮F VANA U7 TP2 2 C19 0.1␮F R9 49.9k⍀ C18 0.1␮F EXT DCLK JP5 A B 13 18 A JP4 VDIG VDIG U8 U8 B 7 2 TP17 A A J1 B B R6 R10 JP2 R8 R7 JP1 49.9⍀ 49.9k⍀ 49.9⍀ 49.9k⍀ C21 0.1␮F VR1 50k⍀ C5 0.1␮F TP3 C6 2.2␮F C8 10␮F TP1 VDIG VDIG A TP13 B P3 JP20 +VCC AGND –VCC JP18 B A JP19 B A TP14 +V CC +12V VANA A JP13 JP14 A B +VCC –VCC C11 10␮F VANA C4 2.2␮F C1 330␮F +V OUT B C10 0.1␮F JP23 C9 0.1␮F JP22 A JP10 VOUT 6 C17 2nF TP4 VDIG DGND P2 C15 0.1␮F R3 2k⍀ VDD C14 10␮F VDIG U3 AD845 JP17 O/P SELECT 8 NC 7 AD780 1 TEMP 3 GND +VIN 2 4 NC A R4 576k⍀ JP24 B JP25 A B JP27 JP26 B R2 499⍀ B R1 1k⍀ 1 B A B A C2 0.1␮F C3 1␮F VANA A JP16 A JP28 TP15 TP5 VANA C13 10␮F +5V JP15 C12 0.1␮F VANA TP12 VR2 50k⍀ J7 AIN4 J6 AIN3 J8 AIN2 J3 AIN1 TP16 P1 AGND VANA 9 7 7 6 5 4 3 2 1 15 9 7 6 5 4 3 2 1 15 5 9 8 8 U8 U8 U8 NC 15 11 12 U7 9 2 JP7 JP6 JP8 U8 3 A1 DCLK DATA BUSY R/C A0 BUSY VDD –12V +12V –5V +5V P5 96-PIN DIN CONNECTOR (A,B,C-21,22,23,24, 25,26,29 B-27,28,30) AGND DGND (A,B,C-4,12,16,20) F0 (A-1) SCLK1 (A,C-3) SCLK0 (A,C-7) DR0 (C-5) RFS0 (C-6) FL0 (A-17) FL1 (B-1) IRQ2 (C-17) VCC (A,B,C-8) –12V (A-30) +12V (C-30) AVSS (A,B,C-31) AVDD (A,B,C-32) D15 (C-19) D14 (C-18) D13 (B-18) D12 (A-18) D11 (B-17) D10 (B-15) D9 (B-14) D8 (B-13) D7 (B-11) D6 (B-10) D5 (B-9) D4 (B-7) D3 (B-6) D2 (B-5) D1 (B-3) D0 (B-2) CS (C-10) 1 P4 2 20-PIN IDC CONNECTOR 17 39 40 J4 40-PIN IDC CONNECTOR BUSY D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 1 EVAL-AD974CB EVAL-AD974CB Figure 3. Component Side Silkscreen (Not to Scale) Figure 4. Component Side (Not to Scale) Figure 6. Power Layer (Not to Scale) Figure 5. Ground Layer (Not to Scale) Figure 7. Circuit Side (Not to Scale) –6– REV. A EVAL-AD974CB Figure 8. Setup Screen Figure 9. Histogram Screen REV. A –7– C00910–0–7/00 (rev. A) EVAL-AD974CB PRINTED IN U.S.A. Figure 10. FFT Screen –8– REV. A