EVAL-ADCMP606BKSZ

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators ADCMP606/ADCMP607 Data Sheet FEATURES GENERAL DESCRIPTION Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V CML-compatible output stage 1.25 ns propagation delay 50 mW at 2.5 V power supply Shutdown pin Single-pin control for programmable hysteresis and latch (ADCMP607 only) Power supply rejection > 60 dB −40°C to +125°C operation The ADCMP606 and ADCMP607 are very fast comparators fabricated on XFCB2, an Analog Devices, Inc., proprietary process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE − 0.5 V to VCCI + 0.2 V, low noise, CML-compatible output drivers, and TTL-/CMOS-compatible latch inputs with adjustable hysteresis and/or shutdown inputs. APPLICATIONS A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a −0.5 V to +2.7 V input signal range up to a +5.5 V positive supply with a −0.5 V to +5.7 V input signal range. The ADCMP607 features split input/output supplies with no sequencing restrictions to support a wide input signal range with independent output swing control and power savings. The devices offer 1.25 ns propagation delay with 2.5 ps rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 50 ps. High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) The CML-compatible output stage is fully back-matched for superior performance. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. On the ADCMP607, latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP606 is available in a 6-lead SC70 package and the ADCMP607 is available in a 12-lead LFCSP package. FUNCTIONAL BLOCK DIAGRAM VCCI VCCO (ADCMP607 ONLY) VP NONINVERTING INPUT Q OUTPUT ADCMP606/ ADCMP607 CML LE/HYS INPUT (ADCMP607 ONLY) SDN INPUT (ADCMP607 ONLY) 05917-001 Q OUTPUT VN INVERTING INPUT Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADCMP606/ADCMP607 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 10 Applications ....................................................................................... 1 Power/Ground Layout and Bypassing ..................................... 10 General Description ......................................................................... 1 CML-Compatible Output Stage ............................................... 10 Functional Block Diagram .............................................................. 1 Using/Disabling the Latch Feature........................................... 10 Revision History ............................................................................... 2 Optimizing Performance ........................................................... 10 Specifications..................................................................................... 3 Comparator Propagation Delay Dispersion ............................... 11 Electrical Characteristics ............................................................. 3 Comparator Hysteresis .............................................................. 11 Timing Information ..................................................................... 5 Crossover Bias Points ................................................................. 12 Absolute Maximum Ratings ............................................................ 6 Minimum Input Slew Rate Requirement ................................ 12 Thermal Resistance ...................................................................... 6 Typical Application Circuits ......................................................... 13 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 14 Pin Configurations and Function Descriptions ........................... 7 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 4/16—Rev. B to Rev. C Changes to Figure 4 and Table 6 ..................................................... 7 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 11/14—Rev. A to Rev. B Changes to Figure 4 and Table 6 ..................................................... 7 Changes to Figure 12 and Figure 13............................................... 9 Changes to Comparator Hysteresis Section ................................ 11 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 8/07—Rev. 0 to Rev. A Changes to Specifications Section .................................................. 3 Changes to Table 3 ............................................................................ 6 Changes to Ordering Guide .......................................................... 14 10/06—Revision 0: Initial Version Rev. C | Page 2 of 14 Data Sheet ADCMP606/ADCMP607 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = −40°C to +125°C, typical at TA = 25°C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE PIN CHARACTERISTICS (ADCMP607 Only) VIH VIL IIH IIL HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS (ADCMP607 Only) VIH VIL IIH IIL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage Differential Symbol Test Conditions/Comments Min VP, VN VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V −0.5 −0.2 VOS IP, IN −5.0 −5.0 −2.0 ±2 −0.1 V to VCCI −0.5 V to VCCI + 0.5 V 200 100 1 700 350 85 VCCI = 2.5 V, VCCO = 2.5 V, VCM = −0.2 V to +2.7 V VCCI = 2..5 V, VCCO = 5.5 V RHYS = ∞ 50 CP, CN AV CMRR tS tH tPLOH, tPLOL tPL tSD tH VOH VOL Typ Unit VCCI + 0.2 VCCI + 0.2 VCCI +5.0 +5.0 2.0 V V V mV µA µA pF kΩ kΩ dB dB 50 dB mV