EVAL-ADE7878AEBZ

EVAL-ADE7878AEBZ User Guide UG-545 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the ADE7854A/ADE7858A/ADE7868A/ADE7878A Energy Metering ICs FEATURES Evaluation board designed to be used with accompanying software to implement a fully functional 3-phase energy meter Easy connection of external transducers via screw terminals Easy modification of signal conditioning components using PCB sockets LED indicators on the CF1, CF2, CF3, IRQ0, and IRQ1 logic outputs Digitally isolated metering components and USB-based communication with a PC External voltage reference option available for on-chip reference evaluation PC COM port-based firmware updates EVALUATION KIT CONTENTS EVAL-ADE7878AEBZ evaluation board USB cable converters (ADCs), a digital integrator, reference circuitry, and all of the signal processing required to perform the total (fundamental and harmonic) active and apparent energy measurements, rms calculations, and fundamental-only active and reactive energy measurements. This user guide describes the evaluation kit hardware, firmware, and software functionality. The evaluation board contains an IC and an LPC2368 microcontroller from NXP Semiconductors. The energy metering IC and its associated metering components are digitally isolated from the microcontroller. The microcontroller communicates with the PC using a USB interface. The EVAL-ADE7878AEBZ and this user guide, together with the ADE7854A/ADE7858A/ADE7868A/ADE7878A data sheet, provide a complete evaluation platform for the ADE7854A/ ADE7858A/ADE7868A/ADE7878A. GENERAL DESCRIPTION The evaluation board has been designed so that the ADE7854A/ ADE7858A/ADE7868A/ADE7878A can be evaluated as an energy meter. Using appropriate current transducers, the evaluation board can be connected to a test bench or high voltage (240 V rms) test circuit. On-board resistor divider networks provide the attenuation for the line voltages. The ADE7854A/ADE7858A/ADE7868A/ADE7878A are high accuracy, 3-phase electrical energy measurement ICs with serial interfaces and three flexible pulse outputs. These ICs incorporate second-order sigma-delta (Σ-∆) analog-to-digital This user guide describes how to connect the current transducers for the best performance. The evaluation board requires one external power supply of 3.3 V applied to the P9 connector. Appropriate current transducers are also required. ONLINE RESOURCES ADE7854A/ADE7858A/ADE7868A/ADE7878A data sheet EVAL-ADE7878AEBZ user guide PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 56 UG-545 EVAL-ADE7878AEBZ User Guide TABLE OF CONTENTS Features .............................................................................................. 1 PSM3 Mode ................................................................................. 23 Evaluation Kit Contents ................................................................... 1 Managing the Communication Protocol .................................... 24 Online Resources .............................................................................. 1 Acquiring HSDC Data Continuously ...................................... 27 General Description ......................................................................... 1 Starting the ADE7854A/ADE7858A/ADE7868A/ ADE7878A DSP.......................................................................... 29 Revision History ............................................................................... 2 Evaluation Board Connection Diagram ........................................ 3 Evaluation Board Hardware ............................................................ 4 Power Supplies .............................................................................. 4 Analog Inputs (P1 to P4 and P5 to P8)...................................... 4 Setting Up the Evaluation Board as an Energy Meter ............. 9 Installing and Uninstalling the ADE7854A/ADE7858A/ ADE7868A/ADE7878A Software ............................................ 12 Stopping the ADE7854A/ADE7858A/ADE7868A/ ADE7878A DSP.......................................................................... 29 Upgrading Microcontroller Firmware ......................................... 30 Control Registers Data File ....................................................... 30 Troubleshooting .............................................................................. 33 Evaluation Board Schematics and Layout ................................... 34 Schematics ................................................................................... 34 Evaluation Board Software ............................................................ 12 Layout .......................................................................................... 49 Front Panel .................................................................................. 12 Ordering Information .................................................................... 52 PSM0 Mode—Normal Power Mode ........................................ 13 Bill of Materials ........................................................................... 52 PSM1 Mode ................................................................................. 21 PSM2 Mode ................................................................................. 22 REVISION HISTORY 7/14—Revision 0: Initial Version Rev. 0 | Page 2 of 56 EVAL-ADE7878AEBZ User Guide UG-545 EVALUATION BOARD CONNECTION DIAGRAM VDD P9 GND IBN IBP IAN IAP P2 VDD2 GND2 P1 P10 MCU_VDD MCU_GND P12 P3 ICP ICN ADE7854A/ ADE7858A/ ADE7868A/ ADE7878A FILTER NETWORK INP USB PORT LPC2368 DIGITAL ISOLATORS INN P13 P4 P15 OPTIONAL EXTERNAL CLOCK INPUT OPTIONAL EXTERNAL ADR280 1.2V REFERENCE CONNECTOR TO PC COM PORT FILTER NETWORK AND ATTENUATION P6 VN GND VCP P7 GND VBP J2 P8 GND VAP GND Figure 1. Rev. 0 | Page 3 of 56 J3 CF3 J4 CF2 CF1 11403-001 P5 JTAG INTERFACE UG-545 EVAL-ADE7878AEBZ User Guide EVALUATION BOARD HARDWARE POWER SUPPLIES ANALOG INPUTS (P1 TO P4 AND P5 TO P8) Current and voltage signals are connected at the screw terminals, P1 to P4 and P5 to P8, respectively. All analog input signals are filtered using the on-board antialiasing filters before the signals are connected to the ADE7854A/ADE7858A/ ADE7868A/ADE7878A. The components used on the board are the recommended values to be used with the ADE7854A/ ADE7858A/ADE7868A/ADE7878A. Current Sense Inputs (P1, P2, P3, and P4) The ADE7854A/ADE7858A/ADE7868A/ADE7878A measures 3-phase currents and the neutral current. Current trans-formers or Rogowski coils can be used to sense the currents. These sensors cannot be mixed together for the phase currents sensing, but the neutral current may be sensed using a different sensor. The IC contains different internal PGA gains on phase currents and on the neutral current; therefore, sensors with different ratios can be used. The only requirement is to have the same scale signals at the PGA outputs; otherwise, the mismatch functionality of the IC is compromised (see the ADE7854A/ ADE7858A/ADE7868A/ADE7878A data sheet for more details about neutral current mismatch). Figure 2 shows the structure used for the Phase A current; the sensor outputs are connected to the P1 connector. R17 1kΩ JP1A R1 C9 22nF C17 22nF JP2A R2 C10 22nF C18 22nF IAP IAP IAN R10 R18 100Ω 1kΩ JP4A JP6A IAN 11403-002 The microcontroller 3.3 V supply is provided by the PC through the USB cable. Alternatively, if Jumper JP24 is connected between Pin 1 and Pin 2, the 3.3 V supply can be provided at the P12 connector. The ADE7854A/ADE7858A/ADE7868A/ ADE7878A 3.3 V supply is provided at the P9 connector. Ensure that Jumper JP11 is connected between Pin 1 and Pin 2 to ensure the same 3.3 V supply from the ADE7854A/ ADE7858A/ADE7868A/ADE7878A is also provided at the iCouplers. P1 R9 100Ω Figure 2. Phase A Current Input Structure on the Evaluation Board The R1 and R2 resistors are the burden resistors and, by default, they are not populated. They can also be disabled using the JP1A and JP2A jumpers. The R9/C9 and R10/C10 RC networks are used in conjunction with Rogowski coils. They can be disabled using the JP3A and JP4A jumpers. The R17/C17 and R18/C18 RC networks are the antialiasing filters. The default corner frequency of these low-pass filters is 7.2 kHz (1 kΩ/22 nF). These filters can easily be adjusted by replacing the components on the evaluation board. All the other current channels (that is, Phase B, Phase C, and the neutral current) have an identical input structure. Using a Current Transformer as the Current Sensor Figure 3 shows how a current transformer can be used as a current sensor in one phase of a 3-phase, 4-wire distribution system (Phase A). The other two phases and the neutral current require similar connections. JP3A IMAX = 6 ARMS CT 1:2000 P1 Rev. 0 | Page 4 of 56 ADE7854A/ ADE7858A/ ADE7868A/ ADE7878A JP5A R9 R17 100Ω 1kΩ JP1A R1 50Ω C9 22nF C17 22nF JP2A R2 50Ω C10 22nF C18 22nF R10 R18 100Ω 1kΩ JP4A JP6A IAP IAN Figure 3. Example of a Current Transformer Connection 11403-003 The evaluation board has two power domains: one domain supplies the microcontroller and one side of the iCoupler®, and one domain supplies the other side of the iCoupler and the ADE7854A/ADE7858A/ADE7868A/ADE7878A. The ground of the microcontroller’s power domain is connected to the ground of the PC through the USB cable. The ground of the ADE7854A/ADE7858A/ADE7868A/ADE7878A power domain is determined by the ground of the phase voltages, VAP, VBP, VCP, and VN, and must be different from the ground of the microcontroller’s power domain. ADE7854A/ ADE7858A/ ADE7868A/ ADE7878A JP5A JP3A EVAL-ADE7878AEBZ User Guide UG-545 in the current channel inputs. This prevents the occurrence of large energy errors at low power factors. R1 = R2 = 1/2 × 0.5/√2 × N/IFS JP3A ROGOWSKI COIL P1 The JP1A and JP2A jumpers should be opened if R1 and R2 are used. The antialiasing filters should be enabled by opening the J5A and J6A jumpers (see Figure 3). The secondary current of the transformer is converted to a voltage by using a burden resistor across the secondary winding outputs. Care should be taken when using a current transformer as the current sensor. If the secondary is left open (that is, no burden is connected), a large voltage may be present at the secondary outputs. This can cause an electric shock hazard and potentially damage electronic components. For this particular example, burden resistors of 50 Ω signify an input current of 7.05 A rms at the ADE7854A/ADE7858A/ ADE7868A/ADE7878A ADC full-scale input (0.5 V). In addition, the PGA gains for the current channel must be set to 1. For more information about setting PGA gains, see the ADE7854A/ADE7858A/ADE7868A/ADE7878A data sheet. The evaluation software allows the user to configure the current channel gain. R9 R17 100Ω 1kΩ IAP JP1A R1 C9 22nF C17 22nF JP2A R2 C10 22nF C18 22nF R10 R18 100Ω 1kΩ JP4A JP6A IAN 11403-004 where: 0.5/√2 is the rms value of the full-scale voltage accepted at the ADC input. N is the input-to-output ratio of the current transformer. Figure 3 shows an example for N = 2000. IFS is the maximum rms current to be measured. ADE7854A/ ADE7858A/ ADE7868A/ ADE7878A JP5A Figure 4. Example of a Rogowski Coil Connection Figure 5 shows a typical connection of the Phase A voltage input; the resistor divider is enabled by opening the JP7A jumper, closing JP9A and connecting JP8A to AGND (Pin 1). The antialiasing filter on the VN datapath is enabled by opening the JP7N jumper. The VN analog input is connected to AGND via the R25/C25 antialiasing filter using the P5 connector. The neutral can be tied to ground by inserting the neutral into the P5 connector and connecting the two terminals together. The attenuation networks can be easily modified by the user to accommodate any input level. However, the value of R32 (1 kΩ), should be modified only together with the corresponding resistors in the current channel (R17 and R18 on the Phase A current datapath). Using a Rogowski Coil as the Current Sensor Voltage Sense Inputs (P5, P6, P7, and P8 Connectors) The voltage input connections on the EVAL-ADE7878AEBZ can be directly connected to the line voltage sources. The line voltages are attenuated using a simple resistor divider network before they are supplied to the IC. The attenuation network on the voltage channels is designed so that the 3 dB corner frequency of the network matches that of the antialiasing filters 1MΩ P8 R29 VAP JP9A A COM B PHASE A 1kΩ C28 22nF R32 1kΩ JP7A VN JP8A VN P5 A COM B VAP NEUTRAL R25 1kΩ VN C25 22nF A COM B Figure 4 shows how a Rogowski coil can be used as a current sensor in one phase of a 3-phase, 4-wire distribution system (Phase A). The other two phases and the neutral current require identical connections. The Rogowski coil does not require any burden resistors; therefore, R1 and R2 should not be populated. The antialiasing filters should be enabled by opening the JP5A and JP6A jumpers. To account for the high frequency noise introduced by the coil, an additional antialiasing filter must be introduced by opening the JP3A and JP4A jumpers. Then, to compensate for the 20 dB/dec gain introduced by the di/dt sensor, the integrator of the IC must be enabled by setting Bit 0 (INTEN) of the CONFIG register. The integrator has a −20 dB/dec attenuation and a phase shift of approximately −90° and, when combined with the di/dt sensor, results in a magnitude and phase response with a flat gain over the frequency band of interest. ADE7854A/ ADE7858A/ ADE7868A/ ADE7878A R26 JP7N Figure 5. Phase A Voltage Input Structure on the Evaluation Board The maximum signal level permissible at the VAP, VBP, and VCP pins of the ADE7854A/ADE7858A/ADE7868A/ ADE7878A is 0.5 V peak. Although the IC analog inputs can withstand ±2 V without risk of permanent damage, the signal range should not exceed ±0.5 V with respect to AGND for a specified operation. Rev. 0 | Page 5 of 56 11403-005 The R1 and R2 burden resistors must be defined as functions of the current transformer ratio and the maximum current of the system, using the following formula: UG-545 EVAL-ADE7878AEBZ User Guide Table 1. Recommended Settings for Evaluation Board Connectors Jumper JP1A Option Closed Open (default) JP1B Closed Open (default) JP1C Closed Open (default) JP1N Closed Open (default) JP2A Closed Open (default) JP2B Closed Open (default) JP2C Closed Open (default) JP2N Closed Open (default) JP3A JP3B JP3C JP3N JP4A JP4B JP4C JP4N JP5A JP5B Closed (default) Open Closed (default) Open Closed (default) Open Closed (default) Open Closed (default) Open Closed (default) Open Closed (default) Open Closed (default) Open Closed Open (default) Closed Open (default) Description Connects Pin 1 of the Channel IA pin connector, P1, to AGND. Use this configuration in conjunction with JP3A and JP5A to short the IAP pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Pin 1 of the Channel IA pin connector, P1, is left floating. Use this configuration in normal operation to drive IAP with analog signal. Connects Pin 1 of the Channel IB pin connector, P2, to AGND. Use this configuration in conjunction with JP3B and JP5B to short the IBP pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Pin 1 of the Channel IB pin connector, P2, is left floating. Use this configuration in normal operation to drive IBP with analog signal. Connects Pin 1 of the Channel IC pin connector, P3, to AGND. Use this configuration in conjunction with JP3C and JP5C to short the ICP pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Pin 1 of the Channel IC pin connector, P3, is left floating. Use this configuration in normal operation to drive ICP with analog signal. Connects Pin 1 of the Channel IN pin connector, P4, to AGND. Use this configuration in conjunction with JP3N and JP5N to short the INP pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Pin 1 of the Channel IN pin connector, P4, is left floating. Use this configuration in normal operation to drive INP with analog signal. Connects Pin 2 of the Channel IA pin connector, P1, to AGND. Use this configuration in conjunction with JP4A and JP6A to short the IAN pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Pin 2 of the Channel IA pin connector, P1, is left floating. Use this configuration in normal operation when driving a differential input to IAN. Connects Pin 2 of the Channel IB pin connector, P2, to AGND. Use this configuration in conjunction with JP4B and JP6B to short the IBN pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Pin 2 of the Channel IB pin connector, P2, is left floating. Use this configuration in normal operation when driving a differential input to IBN. Connects Pin 2 of the Channel IC pin connector, P3, to AGND. Use this configuration in conjunction with JP4C and JP6C to short the ICN pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Pin 2 of the Channel IC pin connector, P3, is left floating. Use this configuration in normal operation when driving a differential input to ICN. Connects Pin 2 of the Channel IN pin connector, P4, to AGND. Use this configuration in conjunction with JP4N and JP6N to short the INN pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Pin 2 of the Channel IBN pin connector, P2, is left floating. Use this configuration in normal operation when driving a differential input to IBN. Disables the phase compensation network (composed by R9 and C9) in the IAP datapath. Enables the phase compensation network (composed by R9 and C9) in the IAP datapath. Disables the phase compensation network (composed by R11 and C11) in the IBP datapath. Enables the phase compensation network (composed by R11 and C11) in the IBP datapath. Disables the phase compensation network (composed by R13 and C13) in the ICP datapath. Enables the phase compensation network (composed by R13 and C13) in the ICP datapath. Disables the phase compensation network (composed by R15 and C15) in the INP datapath. Enables the phase compensation network (composed by R15 and C15) in the INP datapath. Disables the phase compensation network (composed by R10 and C10) in the IAN datapath. Enables the phase compensation network (composed by R10 and C10) in the IAN datapath. Disables the phase compensation network (composed by R12 and C12) in the IBN datapath. Enables the phase compensation network (composed by R12 and C12) in the IBN datapath. Disables the phase compensation network (composed by R14 and C14) in the ICN datapath. Enables the phase compensation network (composed by R14 and C14) in the ICN datapath. Disables the phase compensation network (composed by R16 and C16) in the INN datapath. Enables the phase compensation network (composed by R16 and C16) in the INN datapath. Disables the phase antialiasing filter (composed by R17 and C17) in the IAP datapath. Enables the phase antialiasing filter (composed by R17 and C17) in the IAP datapath. Disables the phase antialiasing filter (composed by R19 and C19) in the IBP datapath. Enables the phase antialiasing filter (composed by R19 and C19) in the IBP datapath. Rev. 0 | Page 6 of 56 EVAL-ADE7878AEBZ User Guide Jumper JP5C JP5N JP6A JP6B JP6C JP6N JP7A JP7B Option Closed Open (default) Closed Open (default) Closed Open (default) Closed Open (default) Closed Open (default) Closed Open (default) Closed between Pin 2 and Pin 1 Closed between Pin 2 and Pin 3 Unconnected (default) Closed between Pin 2 and Pin 1 Closed between Pin 2 and Pin 3 Unconnected (default) JP7C Closed between Pin 2 and Pin 1 Closed between Pin 2 and Pin 3 Unconnected (default) JP7N Closed between Pin 2 and Pin 1 Closed between Pin 2 and Pin 3 Unconnected (default) JP8A JP8B Soldered between Pin 2 and Pin 1 (default) Soldered between Pin 2 and Pin 3 Soldered between Pin 2 and Pin 1 (default) Soldered between Pin 2 and Pin 3 UG-545 Description Disables the phase antialiasing filter (composed by R21 and C21) in the ICP datapath. Enables the phase antialiasing filter (composed by R21 and C21) in the ICP datapath. Disables the phase antialiasing filter (composed by R23 and C23) in the INP datapath. Enables the phase antialiasing filter (composed by R23 and C23) in the INP datapath. Disables the phase antialiasing filter (composed by R18 and C18) in the IAN datapath. Enables the phase antialiasing filter (composed by R18 and C18) in the IAN datapath. Disables the phase antialiasing filter (composed by R20 and C20) in the IBN datapath. Enables the phase antialiasing filter (composed by R20 and C20) in the IBN datapath. Disables the phase antialiasing filter (composed by R22 and C22) in the ICN datapath. Enables the phase antialiasing filter (composed by R22 and C22) in the ICN datapath. Disables the phase antialiasing filter (composed by R24 and C24) in the INN datapath. Enables the phase antialiasing filter (composed by R24 and C24) in the INN datapath. Disables the resistor divider (composed by R26, R29, and R32) when JP9A is open. Use this configuration when using a low voltage signal source in the VAP datapath. Connects the VAP pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Use this configuration when no signal source is desired in the VAP datapath. Enables the resistor divider (composed by R26, R29, and R32) when JP9A is closed. Use this configuration when using a high voltage signal source in the VAP datapath in 3-phase, 4-wire and 3-phase, 3-wire configurations. Disables the resistor divider (composed by R27, R30, and R33) when JP9B is open. Use this configuration when using a low voltage signal source in the VBP datapath. Connects the VBP pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Use this configuration when no signal source is desired in the VBP datapath, such as 3-phase, 3-wire configuration. Enables the resistor divider (composed by R27, R30, and R33) when JP9B is closed. Use this configuration when using a high voltage signal source in the VBP datapath in 3-phase, 4-wire configuration. Disables the resistor divider (composed by R28, R31, and R34) when JP9C is open. Use this configuration when using a low voltage signal source in the VCP datapath. Connects the VCP pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Use this configuration when no signal source is desired in the VCP datapath. Enables the resistor divider (composed by R28, R31, and R34) when JP9C is closed. Use this configuration when using a high voltage signal source in the VCP datapath in 3-phase, 4-wire and 3-phase, 3-wire configurations. Disables the antialiasing filter (composed by R25 and C25) in the VN datapath. Use this configuration when normal single ended signals are connected to the ADE7854A/ADE7858A/ADE7868A/ADE7878A voltage channels. Connects the VN pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to AGND. Use this configuration when the ADE7854A/ADE7858A/ADE7868A/ADE7878A voltage channels are connected to AGND. Enables the antialiasing filter in the VN datapath. Use this configuration when the ADE7854A/ ADE7858A/ADE7868A/ADE7878A voltage channels are differential, in 3-phase, 4-wire and 3-phase, 3-wire configurations. Connects C28 to AGND. Use this configuration when the ADE7854A/ADE7858A/ADE7868A/ADE7878A voltage channels are differential, in 3-phase, 4-wire and 3-phase, 3-wire configurations. Connects C28 to VN. Use this configuration, with JP7N connected between Pin 2 and Pin 3, when the ADE7854A/ADE7858A/ADE7868A/ADE7878A voltage channels are single-ended. Connects C27 to AGND. Use this configuration when the ADE7854A/ADE7858A/ADE7868A/ADE7878A voltage channels are differential, in 3-phase, 4-wire and 3-phase, 3-wire configurations. Connects C27 to VN. Use this configuration, with JP7N connected between Pin 2 and Pin 3, when the ADE7854A/ADE7858A/ADE7868A/ADE7878A voltage channels are single-ended. Rev. 0 | Page 7 of 56 UG-545 Jumper JP8C JP9A EVAL-ADE7878AEBZ User Guide Option Soldered between Pin 2 and Pin 1 (default) Soldered between Pin 2 and Pin 3 Closed (default) Open JP9B Closed (default) Open JP9C Closed (default) Open JP10 Soldered between Pin 2 and Pin 1 (default) Soldered between Pin 2 and Pin 3 JP11 Closed between Pin 2 and Pin 1 (default) Closed between Pin 2 and Pin 3 Closed JP12 Open (default) JP21 Closed Open (default) JP24 Closed between Pin 2 and Pin 1 Closed between Pin 2 and Pin 3 (default) JP31, JP32, JP33, JP34 Closed between Pin 2 and Pin 1 Closed between Pin 2 and Pin 3 (default) Description Connects C25 to AGND. Use this configuration when ADE7854A/ADE7858A/ADE7868A/ADE7878A voltage channels are differential, in 3-phase, 4-wire and 3-phase, 3-wire configurations. Connects C25 to VN. Use this configuration, with JP7N connected between Pin 2 and Pin 3, when the ADE7854A/ADE7858A/ADE7868A/ADE7878A voltage channels are single-ended. Enables the resistor divider (composed by R26, R29, and R32) when JP7A is unconnected. Use this configuration when using a high voltage signal source in the VAP datapath, in 3-phase, 4-wire and 3-phase, 3-wire configurations. Disables the resistor divider (composed by R26, R29, and R32) when JP7A is closed between Pin 1 and Pin 2. Use this configuration when using a low voltage signal source in the VAP datapath. Enables the resistor divider (composed by R27, R30, and R33) when JP7B is unconnected. Use this configuration when using a high voltage signal source in the VBP datapath in 3-phase, 4-wire and 3-phase, 3-wire configurations. Disables the resistor divider (composed by R27, R30, and R33) when JP7B is closed between Pin 1 and Pin 2. Use this configuration when using a low voltage signal source in the VBP datapath. Enables the resistor divider (composed by R28, R31, and R34) when JP7C is unconnected. Use this configuration when using a high voltage signal source in the VCP datapath in 3 phase, 4 wire and 3-phase, 3-wire configurations. Disables the resistor divider (composed by R28, R31, and R34) when JP7C is closed between Pin 1 and Pin 2. Use this configuration when using a low voltage signal source in the VCP datapath. Connects the on-board 16.384 MHz crystal, Y1, to the CLKIN pin of the ADE7854A/ADE7858A/ ADE7868A/ADE7878A. Use this configuration when Crystal Y1 is used as the clock source for the ADE7854A/ADE7858A/ADE7868A/ADE7878A. Disconnects the on-board 16.384 MHz crystal, Y1, from the CLKIN pin of the ADE7854A/ADE7858A/ ADE7868A/ADE7878A. Use this configuration when an external clock is used. This clock can be connected to the EXT_CLKIN connector. Connects the supply of the secondary side of the iCouplers (VDD2) to VDD, the supply of the ADE7854A/ADE7858A/ADE7868A/ADE7878A. Connects the supply of the secondary side of the iCouplers (VDD2) to a 3.3 V supply provided at the P10 connector. Connects the ADR280 voltage reference to the REFIN/OUT pin of the ADE7854A/ADE7858A/ ADE7868A/ADE7878A. Use this configuration when the ADE7854A/ADE7858A/ADE7868A/ ADE7878A are configured to use an external reference. Disconnects the ADR280 voltage reference from the REFIN/OUT pin of the ADE7854A/ADE7858A/ ADE7868A/ADE7878A. Use this configuration in normal operation when the ADE7854A/ADE7858A/ADE7868A/ADE7878A are configured to use the internal reference. Signals the NXP LPC2368 microcontroller to declare all I/O pins as outputs. Use this configuration when another microcontroller manages the ADE7854A/ADE7858A/ADE7868A/ADE7878A through the P17 socket. Disables the option to use another microcontroller to manage the ADE7854A/ADE7858A/ ADE7868A/ADE7878A through the P17 socket. Use this configuration in normal operation to allow the NXP LPC2368 microcontroller to manage the ADE7854A/ADE7858A/ADE7868A/ADE7878A. Selects an external 3.3 V power supply provided at P12 connector to power the domain that includes the NXP LPC2368 and one side of the iCouplers. Use this configuration if USB provided power supply is not desired. Selects the USB provided power supply to power the domain that includes the NXP LPC2368 and one side of the iCouplers. Use this configuration in normal operation to provide power to the NXP LPC2368 and one side of the iCouplers from the PC. When I2C communication between the NXP LPC2368 and the ADE7854A/ADE7858A/ ADE7868A/ADE7878A is used, the HSDC port of the IC is also enabled and the SPI ports of the IC are disabled. Use this configuration when I2C communication is selected. When SPI communication between the NXP LPC2368 and the ADE7854A/ADE7858A/ADE7868A/ ADE7878A is used, the I2C and HSDC ports of the IC are disabled. Use this configuration when SPI communication is selected. Rev. 0 | Page 8 of 56 EVAL-ADE7878AEBZ User Guide UG-545 SETTING UP THE EVALUATION BOARD AS AN ENERGY METER SPI port should be chosen as the active port in the ADE7854A/ ADE7858A/ADE7868A/ADE7878A Control Panel. Figure 6 shows a typical setup for the EVAL-ADE7878AEBZ board. In this example, an energy meter for a 3-phase, 4-wire, wye distribution system is shown. Current transformers are used to sense the phase and neutral currents and are connected as shown in Figure 6. The line voltages are connected directly to the evaluation board as shown. Note that the state of all jumpers must match the states shown in Figure 6, equal to the default states in Table 1. Communication between the ADE7854A/ADE7858A/ ADE7868A/ADE7878Aand the NXP LPC2368 is also possible using the I2C ports. To accomplish this, the JP31, JP32, JP33, and JP34 jumpers should be closed between Pin 2 and Pin 1. In this case, the I2C port should be chosen as the active port in the Control Panel (see Table 2). Note that the HSDC port of the ADE7854A/ADE7858A/ADE7868A/ADE7878A also becomes available to communicate with the NXP LPC2368 in this case. The board is supplied from two different power supplies. One is supplied by the PC through the USB cable and is used for the NXP LPC2368 and for one side of the iCouplers. The other is an external 3.3 V supply used for theADE7854A/ADE7858A/ ADE7868A/ADE7878A domain and the other side of the iCouplers. Because the two domains are isolated to ensure that there is no electrical connection between the high voltage test circuit and the control circuit, the external power supply should have floating voltage outputs. Table 2. Jumper State to Activate SPI or I2C Communication Figure 7 shows a setup for the evaluation board as an energy meter for a 3-phase, 3-wire, delta distribution system. The Phase B voltage is used as a ground reference, and the VN pin of the ADE7854A/ADE7858A/ADE7868A/ADE7878A IC is connected to it. The evaluation board is connected to the PC using a USB cable supplied with the board. When the evaluation board is connected to the PC, the enumeration process begins. The PC recognizes new hardware and asks to install the appropriate driver. The driver can be found in the VirCOM_Driver_XP folder in the evaluation software, downloadable from the product website, for a Windows® XP PC or in VirCom_Driver_W7_64bit for a Windows 7 64-bit PC. After the driver is installed, the supplied evaluation software can be started. The Evaluation Board Software section describes the evaluation software in detail and how it can be installed and uninstalled. Activating Serial Communication Between the IC and the NXP LPC2368 The EVAL-ADE7878AEBZ provides communication between the ADE7854A/ADE7858A/ADE7868A/ADE7878A and the NXP LPC2368 that is set through the SPI ports. The JP31, JP32, JP33, and JP34 jumpers are closed between Pin 2 and Pin 3. The Active Communication SPI (Default) I2 C JP31, JP32, JP33, JP34 Jumpers Closed between Pin 2 and Pin 3 Closed between Pin 2 and Pin 1 Using the Evaluation Board with Another Microcontroller It is possible to manage the ADE7854A/ADE7858A/ ADE7868A/ADE7878A mounted on the evaluation board with a different microcontroller mounted on another board. The IC can be connected to this second board through one of two connectors: P11 or P17. P11 is placed on the same power domain as the ADE7854A/ADE7858A/ADE7868A/ADE7878A. P17 is placed on the power domain of the NXP LPC2368 and communicates with the ADE7854A/ADE7858A/ADE7868A/ ADE7878A through the iCouplers. If P11 is used, the USB cable should not be connected to the P14 connector to avoid supplying the power domain of the NXP LPC2368. In addition, it is recommended to remove the iCouplers from the board in these instances. If P17 is used, a conflict may arise with the NXP LPC2368 I/O ports. To avoid this conflict, close the JP21 jumper. This tells the NXP LPC2368 to set all of its I/O ports to a high impedance state to allow the other microcontroller to communicate with the ADE7854A/ ADE7858A/ADE7868A/ADE7878A. After JP21 is closed, press the S2 reset button low to reset the NXP LPC2368. This is necessary because the state of JP21 is checked inside the NXP LPC2368 program only once after reset. Based on the communication port used, solder jumpers JP71, JP72, JP73, and JP74 appropriately. In the case of SPI, solder jumpers between Pin 2 (middle) and Pin 3 (top); in the case of I2C, solder jumpers between Pin 1(bottom) and Pin 2 (middle). Rev. 0 | Page 9 of 56 UG-545 EVAL-ADE7878AEBZ User Guide JP24 CLOSED BETWEEN PIN 2 AND PIN 3 JP11 CLOSED BETWEEN PIN 2 AND PIN 1 USB CABLE CONNECTED BETWEEN THE BOARD AND PC VDD GND VOLTAGE SOURCE PHASE C P9 PHASE B NEUTRAL PHASE A P1 IAP R1 IAP JP1A, JP2A = OPEN JP3A, JP4A = CLOSED R2 IAN IAN JP5A, JP6A = OPEN IBP JP1B, JP2B = OPEN P2 R3 IBP JP3B, JP4B = CLOSED R4 IBN IBN JP5B, JP6B = OPEN ICP JP1C, JP2C = OPEN P3 R5 ICP JP3C, JP4C = CLOSED R6 ICN ICN JP5C, JP6C = OPEN INP JP1N, JP2N = OPEN P4 R7 INP JP3N, JP4N = CLOSED R8 INN INN JP5N, JP6N = OPEN VAP JP7A = UNCONNECTED P8 R26 VAP BETWEEN PIN 2 AND PIN 1 C28 R32 JP8A = SOLDERED JP9A = CLOSED P7 R27 VBP VBP JP7B = UNCONNECTED BETWEEN PIN 2 AND PIN 1 C27 R33 JP8B = SOLDERED JP9B = CLOSED P6 R28 VCP VCP JP7C = UNCONNECTED LOAD BETWEEN PIN 2 AND PIN 1 C26 R34 JP8C = SOLDERED JP9C = CLOSED P5 VN JP7N = UNCONNECTED NEUTRAL Figure 6. Typical Setup for the ADE7854A/ADE7858A/ADE7868A/ADE7878A Evaluation Board for 3-Phase, 4-Wire, Wye Distribution Systems Rev. 0 | Page 10 of 56 10385-006 R25 C25 VN EVAL-ADE7878AEBZ User Guide UG-545 JP24 CLOSED BETWEEN PIN 2 AND PIN 3 JP11 CLOSED BETWEEN PIN 2 AND PIN 1 USB CABLE CONNECTED BETWEEN THE BOARD AND PC VDD GND VOLTAGE SOURCE PHASE C P9 PHASE B PHASE A P1 IAP R1 IAP JP1A, JP2A = OPEN JP3A, JP4A = CLOSED R2 IAN IAN JP5A, JP6A = OPEN IBP JP1B, JP2B = CLOSED P2 IBP JP3B, JP4B = CLOSED IBN IBN JP5B, JP6B = CLOSED ICP JP1C, JP2C = OPEN P3 R5 ICP JP3C, JP4C = CLOSED R6 ICN ICN JP5C, JP6C = OPEN INP JP1N, JP2N = CLOSED P4 INP JP3N, JP4N = CLOSED INN INN JP5N, JP6N = CLOSED VAP JP7A = UNCONNECTED P8 R26 VAP BETWEEN PIN 2 AND PIN 1 C28 R32 JP8A = SOLDERED JP9A = CLOSED P7 * JP7B = CONNECTED VBP VBP BETWEEN PIN 2 AND PIN 3 JP8B = SOLDERED BETWEEN PIN 2 AND PIN 1 JP9B = CLOSED P6 R28 VCP VCP JP7C = UNCONNECTED LOAD BETWEEN PIN 2 AND PIN 1 C26 R34 JP8C = SOLDERED JP9C = CLOSED P5 VN JP7N = UNCONNECTED *PHASE B IS TIED TO GROUND. Figure 7. Typical Setup for the ADE7854A/ADE7858A/ADE7868A/ADE7878A Evaluation Board for 3-Phase, 3-Wire, Delta Distribution Systems Rev. 0 | Page 11 of 56 10385-007 R25 C25 VN UG-545 EVAL-ADE7878AEBZ User Guide EVALUATION BOARD SOFTWARE The EVAL-ADE7878AEBZ is supported by Windows based software that allows the user to access all the functionality of the IC. The software communicates with the NXP LPC2368 microcontroller using the USB as a virtual COM port. The NXP LPC2368 communicates with the ADE7854A/ADE7858A/ ADE7868A/ADE7878A to process the requests that are sent from the PC. INSTALLING AND UNINSTALLING THE ADE7854A/ADE7858A/ADE7868A/ADE7878A SOFTWARE Serial communication between the microcontroller and the ADE7854A/ADE7858A/ADE7868A/ADE7878A is then introduced using a switch. By default, the SPI port is used. Note that the active serial port must first be set in the hardware. See the Activating Serial Communication Between the IC and the NXP LPC2368 section for details on how to set it up. Once this is set up, the indicator box showing the IC on board is populated. The ADE7854A/ADE7858A/ADE7868A/ADE7878A software, downloadable from the product website, includes two projects: one that represents the NXP LPC2368 project and a LabVIEW™ based program that runs on the PC. The NXP LPC2368 project is already loaded into the processor, but the LabVIEW based program must be installed. 2. To install the software, open LabView_project\installation_files\setup.exe. This launches the setup program that automatically installs all the software components, including the uninstall program, and creates the required directories. To launch the software, go to the Start/Programs/ ADE7854A/ADE7858A/ADE7868A/ADE7878A Eval Software menu and click ADE7854A/ADE7858A/ADE7868A/ADE7878A Eval Software. 11403-008 1. Figure 8. Front Panel of Software When the chip is detected, the next main menu options are enabled. These options allow you to command the ADE7854A/ ADE7858A/ADE7868A/ADE7878A in either PSM0 or PSM3 power mode. The other power modes, PSM1 and PSM2, are not available because initializations have to be made in PSM0 before the device can be used in one of these other modes. Both the evaluation software program and the NI run-time engine are easily uninstalled by using the Add/Remove Programs option in the Control Panel. 1. 2. 3. Before installing a new version of the evaluation software, first uninstall the previous version. Select the Add/Remove Programs option in the Windows Control Panel. Select the program to uninstall and click the Add/Remove button. Once the power mode main menu option is selected, the corresponding selectable options are enabled in the submenu category on the right pane. FRONT PANEL When the software is launched, the Front Panel is opened. This panel contains two panes. The left pane shows the communication selector and the main menu options. The right pane shows all the submenu options along with the indicators that show the COM port, the firmware version downloaded to the microcontroller, and the IC on the board (see Figure 8). 11403-009 When you run the software, the COM port and the firmware version indicators are populated first. The COM port box displays the port that matches the echo function communication protocol (see the Managing the Communication Protocol section)and then sets it to 115,200 baud, eight data bits, no parity, no flow control, one stop bit. Figure 9. Front Panel After PSMO Mode is Selected Rev. 0 | Page 12 of 56 EVAL-ADE7878AEBZ User Guide UG-545 PSM0 MODE—NORMAL POWER MODE Reset the ADE7854A/ADE7858A/ADE7868A/ADE7878A Enter PSM0 Mode When Reset ADE78xxA is selected on the Front Panel, the RESET pin of the ADE7854A/ADE7858A/ADE7868A/ ADE7878A is kept low for 20 ms and then is set high. If the operation is correctly executed, the message ADE7854A/ ADE7858A/ADE7868A/ADE7878A was reset successfully is displayed, and you must click OK to continue. The only error that may occur during this operation is communication related; if this happens, the following message is displayed: The communication between PC and ADE7854A/ADE7858A/ ADE7868A/ADE7878A evaluation board or between LPC2368 and ADE78xxA did not function correctly. There is no guarantee the reset of ADE7854A/ADE7858A/ ADE7868A/ADE7878A has been performed. When the evaluation board is powered up, the device is in PSM3 sleep mode. When Enter PSM0 mode is selected, the microcontroller manipulates the PM0 and PM1 pins of the ADE7854A/ADE7858A/ADE7868A/ADE7878A to switch it into PSM0 mode and the Front Panel windows appears (see Figure 9). It waits 50 ms for the circuit to power up, and, if SPI communication is activated on the board, it executes three SPI write operations to Address 0xEBFF of the ADE7854A/ ADE7858A/ADE7868A/ADE7878A to activate the SPI port. If the operation has been correctly executed or I2C communication is used, the message Configuring LPC2368— ADE7854A/ADE7858A/ADE7868A/ADE7878A communication was successful is displayed, and you must click OK to continue. The only error that may occur during this operation is communication related; if this happens, the following message is displayed: Configuring LPC2368— ADE7854A/ADE7858A/ADE7868A/ADE7878A communication was not successful. Please check the communication between the PC and ADE7854A/ADE7858A/ ADE7868A/ADE7878A evaluation board and between LPC2368 and ADE78xxA. Bit 1 (I2C_LOCK) of the CONFIG2[7:0] register is now set to 1 to lock in the serial port choice. Then, the DICOEFF register is initialized with 0xFF8000, and the DSP of the ADE7854A/ ADE7858A/ADE7868A/ADE7878A is started when the software program writes RUN = 0x1. At the end of this process, the entire main menu is grayed out, and the submenu is enabled. You can now manage all functionality of the IC in PSM0 mode. When Configure Communication is selected on the Front Panel, the panel shown in Figure 11 opens. This panel is useful if an ADE7854A/ADE7858A/ADE7868A/ADE7878A reset has been performed and the SPI is no longer the active serial port. Select the SPI port by clicking the I2C/SPI Selector and then click OK to update the selection and lock the port. This submenu is also useful to switch the active communication port from SPI to I2C. If the port selection is successful, the message Configuring LPC2368—ADE7854A/ADE7858A/ADE7868A/ADE7878A communication was successful is displayed, and you must click OK to continue. If a communication error occurs, the message, Configuring LPC2368—ADE7854A/ADE7858A/ADE7868A/ADE7878A communication was not successful. Please check the communication between the PC and ADE7854A/ADE7858A/ ADE7868A/ADE7878A evaluation board is displayed. 11403-011 11403-010 To switch the ADE7854A/ADE7858A/ADE7868A/ADE7878A to another power mode, click Exit on the submenu. The state of the Front Panel is shown in Figure 10. Configure Communication Figure 10. Front Panel Showing All Mode Selection Options Figure 11. Configure Communication Panel The CONFIG2[7:0] register is written with Bit 1 (I2C_LOCK) set to 1 so that you do not need to remember to set it once the Rev. 0 | Page 13 of 56 UG-545 EVAL-ADE7878AEBZ User Guide communication is set. The contents of CONFIG2[7:0] are then read back and displayed with Bit 1 (I2C_LOCK). To close the panel, click Exit; the cursor is now at Please select from the following options in the submenu of the Front Panel. Total Active Power 1403-013 When Total Active Power is selected on the Front Panel, the panel shown in Figure 12 is opened. The screen has an upper half and a lower half: the lower half shows the total active power datapath of one phase, and the upper half shows bits, registers, and commands necessary to power management. Figure 12. Total Active Power Panel Active Data Path manages which datapath is shown in the bottom half. Some registers or bits, like the WTHR0[23:0] register or Bit 0 (INTEN) of the CONFIG[15:0] register, are common to all datapaths, independent of the phase shown. When these registers are updated, all the values in all datapaths are updated. The HPFDIS[23:0] register is included twice in the datapath, but only the register value from the current datapath is written into the device. All the other instances take this value directly. 1. 2. 3. Click Read Configuration to read and display all registers that manage the total active power. Registers from the inactive datapaths are also read and updated. Click Write Configuration to write all registers that manage the total active power into the ADE7854A/ ADE7858A/ADE7868A/ADE7878A. Registers from the inactive datapaths are also written. The ADE78xxA status box shows which power mode the IC is in (it should always be PSM0 in this window), the active serial port (it should always be SPI), and the CHECKSUM[31:0] register. After every read and write operation, the CHECKSUM[31:0] register is read and its contents displayed. Click CFx Configuration to open a new panel (see Figure 13). This panel gives access to all bits and registers that configure the CF1, CF2, and CF3 outputs of the ADE7854A/ADE7858A/ADE7868A/ADE7878A. Read Setup and Write Setup update and display the CF1, CF2, and CF3 output values. Like the Total Active Power panel, the CHECKSUM[31:0] register is read back whenever a read or write operation is executed in the CFx Configuration panel. To select more than one option for a TERMSELx bit in the COMPMODE [15:0] register, press the CTRL key while clicking the options you want. Note that a special select bit, the LPFSEL bit of the CONFIG_A register, is made available for ICs datapath; when set, this bit enables a stronger filter for power calculations. Clicking EXIT closes the panel and redisplays the Total Active Power panel. When the Read Energy Registers button in the Total Active Power panel is clicked, a new panel is opened (see Figure 14). This panel gives access to bits and registers that configure the energy accumulation. The Read Setup and Write Setup buttons update and display the bit and register values. The CHECKSUM[31:0] register is read back whenever a read or write operation is executed in the Read Energy Registers panel. Clicking Read all energy registers causes all energy registers to be read immediately, without regard to the modes in which they function. Rev. 0 | Page 14 of 56 11403-014 11403-012 Figure 13. CFx Configuration Panel Figure 14. Read Energy Registers Panel EVAL-ADE7878AEBZ User Guide UG-545 1. 2. 3. 4. 5. The STATUS0[31:0] register is read and then written back so that all nonzero interrupt flag bits are cancelled. Bit 14 (CF1) in the MASK0[31:0] register is set to 1, and the interrupt protocol is started (see the Managing the Communication Protocol section for protocol details). The microcontroller then waits until the IRQ0 pin goes low. If the wait is longer than the timeout indicated in 3 sec increments, the following error message is displayed: No CF1 pulse was generated. Verify all the settings before attempting to read energy registers in this mode! When the IRQ0 pin goes low, the STATUS0[31:0] register is read and written back to cancel Bit 14 (CF1); then the energy registers involved in the CF1 signal are read and their contents are displayed. A timer in 10 ms increments can be used to measure the reaction time after the IRQ0 pin goes low. The operation is repeated until the button is clicked again. 11403-015 The panel also gives the choice of reading the energy registers synchronous to CFx interrupts (pulses) or using line cycle accumulation mode. When Read energy registers synchronous with CF1 pulses is clicked, the following sequence occurs: Figure 15. Total Reactive Power Panel The process is similar when the other CF2, CF3, and line accumulation (Read Energy Registers panel) buttons are clicked. Figure 16. Fundamental Active Power Panel 11403-017 When clicking on the Front Panel, the Total Reactive Power, Fundamental Active Power, and Fundamental Reactive Power buttons open panels that are very similar to the Total Active Power panel. These panels are shown in Figure 15, Figure 16, and Figure 17. 1403-016 It is recommended to always use a timeout when dealing with interrupts. By default, the timeout is set to 10 (indicating a 30 sec timeout), and the timer is set to 0 (indicating that the STATUSx[31:0] and energy registers are read immediately after the IRQ0 pin goes low). Figure 17. Fundamental Reactive Power Panel Rev. 0 | Page 15 of 56 UG-545 EVAL-ADE7878AEBZ User Guide Apparent Power 1403-019 1 When Apparent Power is selected on the Front Panel, a new panel opens (see Figure 18). Similar to the other panels that deal with power measurement, this panel is divided into two parts: the lower half shows the apparent power datapath of one phase and the ADE7854A/ADE7858A/ADE7868A/ADE7878A status; the upper half shows the bits, registers, and commands necessary to power management. Figure 19. Current RMS Panel 11403-018 Clicking the Read Setup button causes a read of all registers shown in the panel. Clicking the Write Setup button causes writes to the xIRMSOS[23:0] registers. Figure 18. Apparent Power Panel Current RMS When RMS Current is selected on the Front Panel, a new panel is opened (see Figure 19). All datapaths of all phases are available. There is a special select bit that is made available for ADE7868A/ADE7878A parts called the INSEL bit of the CONFIG_A register. Setting this bit calculates and routes the sum value of all phase currents to the NIRMS register, which would otherwise be displaying the neutral channel current. You can use the Start Digital Signal Processor and Stop Digital Signal Processor buttons to manage the Run[15:0] register. You can use and the Read xIRMS registers button, which uses the ZXIA, ZXIB, and ZXIC interrupts at the IRQ1 pin, to read the xIRMS[23:0] registers 500 consecutive times and then computes and displays their average. If no interrupt occurs for the time indicated by the timeout (in 3 sec increments), the following message is displayed: No ZXIA, ZXIB or ZXIC interrupt was generated. Verify at least one sinusoidal signal is provided between IAP-IAN, IBP-IBN or ICP-ICN pins. A delay can be introduced (in 10 ms increments) between the time the IRQ1 pin goes low and the moment the xIRMS registers are read. The operation is repeated until the button is clicked again. The Low ripple RMS current submenu is also quite similar to the regular RMS current, in terms of window display. These low ripple registers update every 1.024 second and contain an averaged version of the regular current RMS data. Internally, 8192 averages are performed to get a single low ripple RMS measurement. Rev. 0 | Page 16 of 56 EVAL-ADE7878AEBZ User Guide UG-545 Mean Absolute Value Current 8192 averages are performed to get a single low ripple rms measurement. 11403-021 When Mean Absolute Value Current is selected on the Front Panel, a new panel is opened (see Figure 20). When the Read xIMAV registers button is clicked, the xIMAV[19:0] registers are read 10 consecutive times, and their average is computed and displayed. After this operation, the button is returned to high automatically. The ADE7854A/ADE7858A/ADE7868A/ ADE7878A status is also displayed. Figure 21. Voltage RMS Panel 11403-020 Power Quality Figure 20. Mean Absolute Value Current Panel Voltage RMS When RMS Voltage is selected on the Front Panel, the Voltage RMS panel is opened (see Figure 21). This panel is very similar to the Current RMS panel. Clicking the Read Setup button executes a read of the xVRMSOS[23:0] and xVRMS[23:0] registers. Clicking Write Setup writes the xVRMSOS[23:0] registers into the ADE7854A/ADE7858A/ADE7868A/ADE7878A. The Start Digital Signal Processor and Stop Digital Signal Processor buttons manage the Run[15:0] register. When the Read xVRMS registers button is clicked, the xVRMS[23:0] registers are read 500 consecutive times and the average is displayed. The operation is repeated until the button is clicked again. Note that the ZXVA, ZXVB, and ZXVC zerocrossing interrupts are not used in this case because they are disabled when the voltages go below 10% of full scale. This allows rms voltage registers to be read even when the phase voltages are very low. The Power Quality panel is accessible from the Front Panel and is divided into two parts (see Figure 22). The lower part displays registers that manage the power quality measurement functions for the Active Measurement button in the upper part of the panel. The upper part also displays the ADE7854A/ADE7858A/ ADE7868A/ADE7878A status and the buttons that manage the measurements. When the READ CONFIGURATION button is clicked, all power quality registers (MASK1[31:0], STATUS1[31:0], PERIOD[15:0], MMODE[7:0], ISUM[27:0], OVLVL[23:0], OILVL[23:0], PHSTATUS[15:0], IPEAK[31:0], VPEAK[31:0], SAGLVL[23:0], SAGCYC[7:0], ANGLE0[15:0], ANGLE1[15:0], ANGLE2[15:0], COMPMODE[15:0], CHECKSUM[31:0], and PEAKCYC[7:0]) are read, and the ones belonging to the active panel are displayed. Based on the PERIOD[15:0] register, the line frequency is computed and displayed in the lower part of the panel, in Zero Crossing Measurements. Based on the ANGLEx[15:0] registers, cos(ANGLEx) is computed and displayed in the Time Intervals Between Phases panel that is accessible from the Active Measurement Zero Crossing drop-down box (see Figure 22). When the WRITE CONFIGURATION button is clicked, MMODE[7:0], OVLVL[23:0], OILVL[23:0], SAGLVL[23:0], SAGCYC[7:0], COMPMODE[15:0], and PEAKCYC[7:0] are written into the ADE7854A/ADE7858A/ADE7868A/ ADE7878A, and CHECKSUM[31:0] is read back and displayed in the CHECKSUM[31:0] box at the top of the upper part of the panel. The Low ripple RMS voltage submenu is also quite similar to the regular rms voltage, in terms of window display. These low ripple registers update every 1.024 second and contain an averaged version of the regular voltage rms data. Internally, Rev. 0 | Page 17 of 56 EVAL-ADE7878AEBZ User Guide 11403-022 UG-545 Figure 22. Power Quality Zero-Crossing Measurements Panel 11403-024 When the WAIT FOR INTERRUPTS button is clicked, the interrupts that you have enabled in the MASK1[31:0] register are monitored. When the IRQ1 pin goes low, the STATUS1[31:0] register is read and its bits are displayed. The ISUM[27:0], PHSTATUS[15:0], IPEAK[31:0], VPEAK[31:0], ANGLE0[15:0], ANGLE1[15:0], and ANGLE2[15:0] registers are also read and displayed. A timeout should be introduced in 3 sec increments to ensure that the program does not wait indefinitely for interrupts. A timer (in 10 ms increments) is provided to allow reading of the registers with a delay from the moment the interrupt is triggered. Figure 24. Overvoltage and Overcurrent Measurements Panel The Active Measurement Zero Crossing button gives access to the Zero Crossing, Neutral Current Mismatch, Overvoltage and Overcurrent Measurement, Peak Detection, and Time Intervals Between Phases panels (see Figure 22 through Figure 26). f = 11403-025 The line frequency is computed using the PERIOD[15:0] register, based on the following formula: 256,000 [ Hz ] Period Figure 25. Peak Detection Panel The cosine of the ANGLE0[15:0], ANGLE1[15:0], and ANGLE2[15:0] measurements is computed using the following formula: 11403-026  ANGLEx × 360 × f  cos( ANGLEx) = cos  256,000   11403-023 Figure 26. Time Intervals Between Phases Panel Figure 23. Neutral Current Mismatch Panel Rev. 0 | Page 18 of 56 EVAL-ADE7878AEBZ User Guide UG-545 Waveform Sampling • The Waveform Sampling panel (see Figure 27) is accessible from the Front Panel and uses the HSDC port to acquire data from the ADE7854A/ADE7858A/ADE7868A/ADE7878A and display it. The HSDC port can be accessed only if the communication between the ADE7854A/ADE7858A/ADE7868A/ADE7878A and the NXP LPC2368 is through the I2C. See the Activating Serial Communication Between the IC and the NXP LPC2368 section for details on how to set I2C communication on the evaluation board. The acquisition time should also be set before an acquisition is ordered. By default, this time is 150 ms. It is unlimited for phase currents and voltages and for phase powers. The NXP LPC2368 executes in real time three tasks using the ping-pong buffer method: continuously receiving data from HSDC, storing the data into its USB memory, and sending the data to the PC. Transmitting seven phase currents and voltages at 4 MHz takes 103.25 µs (which is less than 125 µs); therefore, the HSDC update rate is 8 kHz (HSDC_CFG = 0x0F). Transmitting nine phase powers takes 72 µs (again, less than 125 µs); therefore, the HSDC update rate is also 8 kHz (HSDC_CGF = 0x11). To start the acquisition, click the ACQUIRE DATA button. The data is displayed on one plot. If you click the Write waveforms to file?/No writing to files switch to enable the writing of waveforms to a file, the program asks for the name and location of the files before storing the waveform. Checksum Register 11403-027 The Checksum Register panel is accessible from the Front Panel and gives access to all ADE7854A/ADE7858A/ ADE7868A/ADE7878A registers used to compute the CHECKSUM[31:0] register (see Figure 28). You can read/write the values of these registers by clicking the Read and Write buttons. The LabView program estimates the value of the CHECKSUM[31:0] register and displays it whenever one of the registers is changed. When the Read button is pressed, the registers are read and the CHECKSUM[31:0] register is read and its values displayed. This allows you to compare the value of the CHECKSUM[31:0] register estimated by LabView with the value read from the parts. The values should always be identical, after the setup is read. Figure 27. Waveform Sampling Panel The HSDC transmits data to the NXP LPC2368 at 4 MHz because this is the maximum speed at which the slave SPI of the NXP LPC2368 can receive data. The panel contains some switches that must be set before acquiring data. • One switch chooses the quantities that are displayed: phase currents and voltages or phase powers. For every set of quantities, only one can be acquired at a time. This choice is made using the Select Waveform button. A second switch allows acquired data to be stored in files for further use. This switch is set with the ACQUIRE DATA button. 11403-028 • Figure 28. Checksum Register Panel Rev. 0 | Page 19 of 56 UG-545 EVAL-ADE7878AEBZ User Guide All Registers Access Quick Startup The All Registers Access panel provides access to the ADE7854A/ADE7858A/ADE7868A/ADE7878A registers. Because there are many, the panel can be scrolled up and down and has multiple read, write, and exit buttons (see Figure 29 and Figure 30). The Quick Startup panel, accessible from the Front Panel, can be used to rapidly initialize a 3-phase meter (see Figure 31). The registers are listed in columns in alphabetical order, starting at the upper left, except for the new registers, which are displayed at the end. 11403-031 The panel also allows you to save all control registers into a data file by clicking the Save All Regs into a file button. By clicking the Load All Regs from a file button, you can load all control registers from a data file. Then, by clicking the Write All Regs button, you can load these values into the IC. The order in which the registers are stored into a file is shown in the Control Registers Data File section. Figure 31. Panel Used to Quickly Set Up the 3-Phase Meter 11403-029 The meter constant (MC, in impulses/kWh), the nominal voltage (Un, in V rms units), the nominal current (In, in A rms units), and the nominal line frequency (fn, in either 50 Hz or 60 Hz) must be introduced in the panel controls. Then phase voltages and phase currents must be provided through the relative sensors. Figure 29. Panel Giving Access to All Registers (1) Clicking the Begin Computations button starts the program that reads rms voltages and currents and calculates the fullscale voltage and currents used to further initialize the meter. This process takes 7 seconds as the program reads the rms voltages 100 times and the rms currents 100 times, and then averages them (this is because the PC reads the rms values directly and cannot synchronize the readings with the zero crossings). 11403-030 The program then computes the full-scale voltages and currents and the constants that are important for setting up the ADE7854A/ADE7858A/ADE7868A/ADE7878A: nominal values (n), CFDEN, WTHR1, VARTHR1, VATHR1, WTHR0, VARTHR0, and VATHR0. Figure 30. Panel Giving Access to All Registers (2) Rev. 0 | Page 20 of 56 EVAL-ADE7878AEBZ User Guide UG-545 At this point, you can overwrite these values. You can also click the Update Registers button to cause the program to do the following: • • Initialize the CFxDEN and xTHR registers Enable the CF1 pin to provide a signal proportional to the total active power, enable the CF2 pin to provide a signal proportional to the total reactive power, and enable the CF3 pin to provide a signal proportional to the apparent power. Throughout the program, it is assumed that PGA gains are 1 (for simplicity) and that the Rogowski coil integrators are disabled. You can enter and modify the PGAs and enable the integrators before executing this quick startup, if necessary. After the board is powered down and then powered up again, the registers can be loaded into the ADE7854A/ADE7858A/ ADE7868A/ADE7878A by simply loading back the content of the data file. To do this, click the Load All Regs from a file button in the All Registers Access panel. PSM2 Settings The PSM2 Settings panel, which is accessible from the Front Panel, gives access to the LPOILVL[7:0] register that is used to access PSM2 low power mode (see Figure 32). You can manipulate its LPOIL[2:0] and LPLINE[4:0] bits. The value shown in the LPOILVL[7:0] register is composed from these bits and then displayed. Note that you cannot write a value into the register by writing a value in the LPOILVL[7:0] register box. 11403-032 At this point, the evaluation board is set up as a 3-phase meter, and calibration can be executed. To store the register initializations, click the Save All Regs into a file button in the All Registers Access panel. Figure 32. PSM2 Settings Panel PSM1 MODE Enter PSM1 Mode When Enter PSM1 mode is selected on the Front Panel, the microcontroller manipulates the PM0 and PM1 pins of the ADE7868A/ADE7878A to switch the ADE7868A/ADE7878A into PSM1 reduced power mode. Then, the submenu allows access only to the Mean Absolute Value Current function because this is the only ADE7868A/ADE7878A functionality available in this reduced power mode (see Figure 33). 11403-033 You can select the PSM2 IRQ1 only mode by selecting the appropriate control available. Doing so pulls IRQ0 to high always and IRQ1 alone would determine if a tamper condition occurs. Figure 33. Front Panel After the IC Enters PSM1 Mode Rev. 0 | Page 21 of 56 UG-545 EVAL-ADE7878AEBZ User Guide Mean Absolute Value Current in PSM1 Mode 11403-035 The Mean Absolute Value Current panel, which is accessible from the Front Panel when Enter PSM1 mode is selected, is very similar to the panel accessible in PSM0 mode (see the Mean Absolute Value Current section for details). The only difference is that ADE7868A/ADE7878A status does not show the CHECKSUM[31:0] register because it is not available in PSM1 mode (see Figure 34). Figure 35. Front Panel After the IC Enters PSM2 Mode 11403-034 Phase Current Monitoring Figure 34. Mean Absolute Value Currents Panel in PSM1 Mode PSM2 MODE Enter PSM2 Mode When Enter PSM2 mode is selected on the Front Panel, the microcontroller manipulates the PM0 and PM1 pins of the ADE7868A/ADE7878A to switch the ADE7868A/ADE7878A into PSM2 low power mode. Then, the submenu allows access only to the Phase Current Monitoring function because this is the only ADE7868A/ADE7878A functionality available in this low power mode (see Figure 35). The Phase Current Monitoring panel is accessible from the Front Panel when Enter PSM2 mode is selected; it allows you to display the state of the IRQ0 and IRQ1 pins because, in PSM2 low power mode, the ADE7868A/ADE7878A compares the phase currents against a threshold determined by the LPOILVL[7:0] register (see Figure 36). Clicking the READ STATUS OF IRQ0 AND IRQ1 PINS button reads the status of these pins and displays and interprets the status. You can select the PSM2 IRQ1 only mode by selecting the appropriate control from the window. Doing so keeps IRQ0 at high always; IRQ1 alone determines if a tamper condition occurs. This Phase Current Monitoring operation is managed by the LPOILVL[7:0] register and can be modified only in PSM0 mode. The panel offers this option by switching the ADE7868A/ADE7878A into PSM0 mode and then back to PSM2 mode when one of the READ LPOILVL/WRITE LPOILVL buttons is clicked. To avoid toggling both the PM0 and PM1 pins at the same time during this switch, the ADE7868A/ADE7878A is set to PSM3 when changing modes. Rev. 0 | Page 22 of 56 EVAL-ADE7878AEBZ User Guide UG-545 PSM3 MODE Enter PSM3 Mode 11403-036 In PSM3 sleep mode, most of the internal circuits of the ADE7854A/ADE7858A/ADE7868A/ADE7878A are turned off. Therefore, no submenu is activated while in this mode. You can select the Enter PSM0 mode, Enter PSM1 mode, or Enter PSM2 mode menu options to set the IC to one of these power modes. Figure 36. Panel Managing Current Monitoring in PSM2 Mode Rev. 0 | Page 23 of 56 UG-545 EVAL-ADE7878AEBZ User Guide MANAGING THE COMMUNICATION PROTOCOL This sections lists the protocol commands implemented to manage the ADE7854A/ADE7858A/ADE7868A/ADE7878A from the PC using the microcontroller. The microcontroller is a pure slave during the communication process. It receives a command from the PC, executes the command, and sends an answer to the PC. The PC waits for the answer before sending a new command to the microcontroller. There are two versions of microcontroller codes for ADE7854A/ADE7858A/ADE7868A/ADE7878A parts: Version 0.0 and Version 0.1. Version 0.0 is the microcontroller code originally written for ADE7854A/ADE7858A/ADE7868A/ ADE7878A parts. It can be used with ADE7854A/ADE7858A/ ADE7868A/ADE7878A parts as well. Version 0.1, the latest version, reads rms values at zero-crossings thus improving the accuracy of the readings. The evaluation software detects the version of the microcontroller code programmed in the board and makes internal changes accordingly. Table 3. Echo Command—Message from the PC to the Microcontroller Byte 0 1 2 3 4 … N N+1 Description A = 0x41 N = number of bytes transmitted after this byte Data Byte N − 1 (MSB) Data Byte N − 2 Data Byte N − 3 … Data Byte 1 Data Byte 0 (LSB) Table 4. Echo Command—Answer from the Microcontroller to the PC Byte 0 1 2 3 4 … N+1 N+2 Description R = 0x52 A = 0x41 N = number of bytes transmitted after this byte Data byte N − 1 (MSB) Data byte N − 2 … Data Byte 1 Data Byte 0 (LB) Table 5. Power Mode Select—Message from the PC to the Microcontroller Byte 0 1 2 Description B = 0x42, change PSM mode N=1 Data Byte 0: 0x00 = PSM0 0x01 = PSM1 0x02 = PSM2 0x03 = PSM3 Table 6. Power Mode Select—Answer from the Microcontroller to the PC Byte 0 1 Description R = 0x52 ~ = 0x7E, to acknowledge that the operation was successful Table 7. Reset—Message from the PC to the Microcontroller Byte 0 1 2 Description C = 0x43, toggle the RESET pin and keep it low for at least 10 ms N=1 Data Byte 0: this byte can have any value Rev. 0 | Page 24 of 56 EVAL-ADE7878AEBZ User Guide UG-545 Table 8. Reset—Answer from the Microcontroller to the PC Byte 0 1 Description R = 0x52 ~ = 0x7E, to acknowledge that the operation was successful Table 9. I2C/SPI Select (Configure Communication)—Message from the PC to the Microcontroller Byte 0 1 2 Description D = 0x44, select I2C and SPI and initialize them; then set CONFIG2[7:0] = 0x2 to lock in the port choice. When I2C is selected, also enable SSP0 of the LPC2368 (used for HSDC). N = 1. Data Byte 0: 0x00 = I2C, 0x01 = SPI. Table 10. I2C/SPI Select (Configure Communication)—Answer from the Microcontroller to the PC Byte 0 1 Description R = 0x52 ~ = 0x7E, to acknowledge that the operation was successful Table 11. Data Write—Message from the PC to the Microcontroller Byte 0 1 2 3 4 5 6 … N+2 N+3 Description E = 0x45 N = number of bytes transmitted after this byte. N can be 1 + 2, 2 + 2, 4 + 2, or 6 + 2 MSB of the address LSB of the address Data Byte N − 3 (MSN) Data Byte N − 4 Data Byte N − 5 … Data Byte 1 Data Byte 0 (LSB) Table 12. Data Write—Answer from the Microcontroller to the PC Byte 0 1 Description R = 0x52 ~ = 0x7E, to acknowledge that the operation was successful Rev. 0 | Page 25 of 56 UG-545 EVAL-ADE7878AEBZ User Guide Table 13. Data Read—Message from the PC to the Microcontroller Byte 0 1 2 3 4 Description F = 0x46. N = number of bytes transmitted after this byte; N = 3. MSB of the address. LSB of the address. M = number of bytes to be read from the address above. M can be 1, 2, 4, or 6. Table 14. Data Read—Answer from the Microcontroller to the PC Byte 0 1 2 3 4 5 6 7 8 Description R = 0x52. MSB of the address. LSB of the address. Byte 5, Byte 3, Byte 1, or Byte 0 (MSB) read at the location indicated by the address. The location may contain 6, 4, 2, or 1 byte. The content is transmitted MSB first. Byte 4, Byte 2, or Byte 0. Byte 3, Byte 1. Byte 2, Byte 0. Byte 1. Byte 0. Table 15. Interrupt Setup—Message from the PC to the Microcontroller Byte 0 1 2 3 4 5 6 7 8 9 Description J = 0x4A. N = 8, number of bytes transmitted after this byte. MSB of the MASK1[31:0] or MASK0[31:0] register. LSB of the MASK1[31:0] or MASK0[31:0] register. Byte 3 of the desired value of the MASK0[31:0] or MASK1[31:0] register. Byte 2. Byte 1. Byte 0. Time out byte: time the MCU must wait for the interrupt to be triggered. It is measured in 3 sec increments. Time out byte (TOB) = 0 means that timeout is disabled. IRQ timer: time the MCU leaves the IRQx pin low before writing back to clear the interrupt flag. It is measured in 10 ms increments. Timer = 0 means that timeout is disabled. Table 16. Interrupt Setup—Message from the Microcontroller to the PC Byte 0 1 2 3 4 Description R = 0x52. Byte 3 of the STATUS0[31:0] or STATUS1[31:0] register. If the program waited for TOB × 3 sec and the interrupt was not triggered, then Byte 3 = Byte 2 = Byte 1 = Byte 0 = 0xFF. Byte 2 of the STATUS0[31:0] or STATUS1[31:0] register. Byte 1 of the STATUS0[31:0] or STATUS1[31:0] register. Byte 0 of the STATUS0[31:0] or STATUS1[31:0] register. The microcontroller executes the following operations once the interrupt setup command is received: 1. 2. 3. 4. 5. Reads the STATUS0[31:0] or STATUS1[31:0] register (depending on the address received from the PC) and, if it shows an interrupt already triggered (one of its bits is equal to 1), it erases the interrupt by writing it back. Writes to the MASK0[31:0] or MASK1[31:0] register with the value received from the PC. Waits for the interrupt to be triggered. If the wait is more than the timeout specified in the command, 0xFFFFFFFF is sent back. If the interrupt is triggered, the STATUS0[31:0] or STATUS1[31:0] register is read and then written back to clear it. The value read at this point is the value sent back to the PC so that you can see the source of the interrupts. Sends back the answer. Rev. 0 | Page 26 of 56 EVAL-ADE7878AEBZ User Guide UG-545 Table 17. Interrupt Pins Status—Message from the PC to the Microcontroller Byte 0 1 2 Description H = 0x48. N = 1, number of bytes transmitted after this byte. Any byte. This value is not used by the program, but it is used in the communication because N must not be equal to 0. Table 18. Interrupt Pins Status—Answer from the Microcontroller to the PC Byte 0 1 Description R = 0x52. A number representing the status of the IRQ0 and IRQ1 pins. 0: IRQ0 = low, IRQ1 = low. 1: IRQ0 = low, IRQ1 = high. 2: IRQ0 = high, IRQ1 = low. 3: IRQ0 = high, IRQ1 = high. The reason for the IRQ0 and IRQ1 order is that on the microcontroller IO port, IRQ0 = P0.1 and IRQ1 = P0.0. ACQUIRING HSDC DATA CONTINUOUSLY This function acquires data from the HSDC continuously for a defined time period and for up to two variables. The microcontroller sends data in packages of 4 kB. Table 19 describes the protocol when two instantaneous phase currents or voltages are acquired. Table 19. Acquire HSDC Data Continuously—Message from the PC to the Microcontroller if Phase Currents and Voltages are Acquired Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description G = 0x47. N = number of bytes transmitted after this byte. N = 32. 0: corresponds to Byte 3 of IA. Because this byte is only a sign extension of Byte 2, it is not sent back by the microcontroller. Increment_IA_Byte2. If IA is to be acquired, Byte 3, Byte 4, and Byte 5 are 1. Otherwise, they are 0. Increment_IA_Byte1. Increment_IA_Byte2. 0. Increment_VA_Byte2. If VA is to be acquired, Byte 7, Byte 8, and Byte 9 are 1. Otherwise, they are 0. Increment_VA_Byte1. Increment_VA_Byte0. 0. Increment_IB_Byte2. If IB is to be acquired, Byte 11, Byte 12, and Byte 13 are 1. Otherwise, they are 0. Increment_IB_Byte1. Increment_IB_Byte0. 0. Increment_VB_Byte2. If VB is to be acquired, Byte 15, Byte 16, and Byte 17 are 1. Otherwise, they are 0. Increment_VB_Byte1. Increment_VB_Byte0. 0. Increment_IC_Byte2. If IC is to be acquired, Byte 19, Byte 20, and Byte 21 are 1. Otherwise, they are 0. Increment_IC_Byte1. Increment_IC_Byte0. 0. Increment_VC_Byte2. If VC is to be acquired, Byte 23, Byte 24, and Byte 25 are 1. Otherwise, they are 0. Increment_VC_Byte1. Increment_VC_Byte0. 0. Increment_IN_Byte2. If IN is to be acquired, Byte 27, Byte 28, and Byte 29 are 1. Otherwise, they are 0. Increment_IN_Byte1. Increment_IN_Byte0. Rev. 0 | Page 27 of 56 UG-545 Byte 30 31 EVAL-ADE7878AEBZ User Guide Description Byte 1 of M. M is a 16-bit number. The number of 32-bit samples acquired by the microcontroller is (2 × M + 1) × 67 per channel. Byte 0 of M. If two of the phase powers are to be acquired, the protocol changes (see Table 20). Table 20. Acquire HSDC Data Continuously—Message from the PC to the Microcontroller if Phase Powers are Acquired Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Description G = 0x47. N = number of bytes transmitted after this byte. N = 38. 0: corresponds to Byte 3 of AVA. Because this byte is only a sign extension of Byte 2, it is not sent back by the microcontroller. Increment_AVA_Byte2. If AVA is to be acquired, Byte 3, Byte 4, and Byte 5 are 1. Otherwise, they are 0. Increment_AVA_Byte1. Increment_AVA_Byte2. 0. Increment_BVA_Byte2. If BVA is to be acquired, Byte 7, Byte 8, and Byte 9 are 1. Otherwise, they are 0. Increment_BVA_Byte1. Increment_BVA_Byte0. 0. Increment_CVA_Byte2. If CVA is to be acquired, Byte 11, Byte 12, and Byte 13 are 1. Otherwise, they are 0. Increment_CVA_Byte1. Increment_CVA_Byte0. 0. Increment_AWATT_Byte2. If AWATT is to be acquired, Byte 15, Byte 16, and Byte 17 are 1. Otherwise, they are 0. Increment_AWATT_Byte1. Increment_AWATT_Byte0. 0. Increment_BWATT_Byte2. If BWATT is to be acquired, then Byte 19, Byte 20, and Byte 21 are 1. Otherwise, they are 0. Increment_BWATT_Byte1. Increment_BWATT_Byte0. 0. Increment_CWATT_Byte2. If CWATT is to be acquired, Byte 23, Byte 24, and Byte 25 are 1. Otherwise, they are 0. Increment_CWATT_Byte1. Increment_CWATT_Byte0. 0. Increment_AVAR_Byte2. If AVAR is to be acquired, Byte 27, Byte 28, and Byte 29 are 1. Otherwise, they are 0. Increment_AVAR_Byte1. Increment_AVAR_Byte0. 0. Increment_BVAR_Byte2. If BVAR is to be acquired, then Byte 31, Byte 32, and Byte 33 are 1. Otherwise, they are 0. Increment_BVAR_Byte1. Increment_BVAR_Byte0. 0. Increment_CVAR_Byte2. If CVAR is to be acquired, Byte 35, Byte 36, and Byte 37 are 1. Otherwise, they are 0. Increment_CVAR_Byte1. Increment_CVAR_Byte0. Byte 1 of M. M is a 16-bit number. The number of 32-bit samples acquired by the microcontroller is (2 × M + 1) × 67 per channel. Byte 0 of M. Rev. 0 | Page 28 of 56 EVAL-ADE7878AEBZ User Guide UG-545 After receiving the command, the microcontroller enables the HSDC port and acquires 67 × 7 × 4 = 1876 bytes into BUFFER0. As soon as BUFFER0 is filled, data is acquired in BUFFER1 (equal in size to BUFFER0), while 2 × 3 × 67 = 402 bytes (134 24-bit words) from BUFFER0 are transmitted to the PC. As soon as BUFFER1 is filled, data is acquired into BUFFER0 while 402 bytes from BUFFER1 are transmitted to the PC. Only the less significant 24 bits of every 32-bit instantaneous value are sent to the PC to decrease the size of the buffer sent to the PC. The most significant eight bits are only an extension of a 24-bit signed word; therefore, no information is lost. The protocol used by the microcontroller to send data to the PC is shown in Table 21. Table 21. Acquire HSDC Data Continuously—Answer from the Microcontroller to the PC Byte 0 1 2 3 4 5 … 402 Description R = 0x52 Byte 2 (MSB) of Word 1 Byte 1 of Word 1 Byte 0 (LSB) of Word 1 Byte 2 (MSB) of Word 2 Byte 1 (MSB) of Word 2 … Byte 0 (LSB) of Word 134 STARTING THE ADE7854A/ADE7858A/ADE7868A/ADE7878A DSP This function orders the microcontroller to start the DSP. The microcontroller writes to the run register with 0x1. Table 22. Start ADE7854A/ADE7858A/ADE7868A/ADE7878A DSP—Message from the PC to the Microcontroller Byte 0 1 2 Description N = 0x4E N = number of bytes transmitted after this byte; N = 1 Any byte Table 23. Start ADE7854A/ADE7858A/ADE7868A/ADE7878A DSP—Answer from the Microcontroller to the PC Byte 0 1 Description R = 0x52 ~ = 0x7E, to acknowledge that the operation was successful STOPPING THE ADE7854A/ADE7858A/ADE7868A/ADE7878A DSP This function orders the microcontroller to stop the DSP. The microcontroller writes to the run register with 0x0. Table 24. Stop ADE7854A/ADE7858A/ADE7868A/ADE7878A DSP—Message from the PC to the Microcontroller Byte 0 1 2 Description O = 0x4F N = number of bytes transmitted after this byte; N = 1 Any byte Table 25. Stop ADE7854A/ADE7858A/ADE7868A/ADE7878A DSP—Answer from the Microcontroller to the PC Byte 0 1 Description R = 0x52 ~ = 0x7E to acknowledge that the operation was successful Rev. 0 | Page 29 of 56 UG-545 EVAL-ADE7878AEBZ User Guide UPGRADING MICROCONTROLLER FIRMWARE The Flash Magic settings are shown in Figure 37. Although the evaluation board is supplied with the microcontroller firmware already installed, the ADE7854A/ ADE7858A/ADE7868A/ADE7878A evaluation software, downloadable from the product website, provides the NXP LPC2368 microcontroller project developed under the IAR embedded workbench environment for ARM. Users in possession of this tool can modify the project at will and can download it using an IAR J-link debugger. As an alternative, the executable can be downloaded using the Flash Magic program available on the Flash Magic website. 1. 2. 3. 4. 5. 6. Plug a serial cable into the P15 connector of the evaluation board and into a PC COM port. As an alternative, use a USB-to-UART board together with a USB cable. If doing so, plug the USB-to-UART board into the P15 connector of the evaluation board with the VDD pin of the USB-toUART board aligned at Pin 1 of P15. Launch the Device Manager under Windows XP by writing devmgmt.msc into the Start/Run box. This helps to identify which COM port is used by the serial cable. Connect Jumper JP8. The P2.10/EINT0 pin of the microcontroller is now connected to ground. Supply the board with two 3.3 V supplies at the P10 and P12 connectors. Press and release the reset button, S2, on the evaluation board. Launch Flash Magic and complete the following: a. Select a COM port (COMx as seen in the Device Manager). b. Set the baud rate to 115,200. c. Select the NXP LPC2368 device. d. Set the interface to none (ISP). e. Set the oscillator frequency (MHz) to 12.0. f. Select Erase all Flash + Code Rd Block. g. Choose ADE7854A/ADE7858A/ADE7868A/ADE7878A_Ev al_Board.hex from the \Debug\Exe project folder. h. Select Verify after programming. 09078-036 Flash Magic uses the PC COM port to download the microcontroller firmware. The procedure for using Flash Magic is as follows: Figure 37. Flash Magic Settings 7. 8. 9. Click Start to begin the download process. After the process finishes, extract the JP8 jumper. Reset the evaluation board by pressing and releasing the S2 reset button. At this point, the program should be functional, and a USB cable can be connected to the board. When the PC recognizes the evaluation board and asks for a driver, indicate the \VirCOM_Driver_XP folder for a Windows XP PC or to the \VirCOM_Driver_W7_64bit folder for a Windows 7 PC. CONTROL REGISTERS DATA FILE Table 26 shows the order in which the control registers of the IC are stored into a data file when you click the Save All Regs into a file button in the All Registers Access panel. Rev. 0 | Page 30 of 56 EVAL-ADE7878AEBZ User Guide UG-545 Table 26. Control Register Data File Content Line Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Register AIGAIN AVGAIN BIGAIN BVGAIN CIGAIN CVGAIN NIGAIN AIRMSOS AVRMSOS BIRMSOS BVRMSOS CIRMSOS CVRMSOS NIRMSOS AVAGAIN BVAGAIN CVAGAIN AWGAIN AWATTOS BWGAIN BWATTOS CWGAIN CWATTOS AVARGAIN AVAROS BVARGAIN BVAROS CVARGAIN CVAROS AFWGAIN AFWATTOS BFWGAIN BFWATTOS CFWGAIN CFWATTOS AFVARGAIN AFVAROS BFVARGAIN BFVAROS CFVARGAIN CFVAROS VATHR1 VATHR0 WTHR1 WTHR0 VARTHR1 VARTHR0 VANOLOAD APNOLOAD VARNOLOAD VLEVEL DICOEFF Rev. 0 | Page 31 of 56 UG-545 Line Number 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 EVAL-ADE7878AEBZ User Guide Register HPFDIS ISUMLVL RUN OILVL OVLVL SAGLVL MASK0 MASK1 VNOM LINECYC ZXTOUT COMPMODE GAIN CFMODE CF1DEN CF2DEN CF3DEN APHCAL BPHCAL CPHCAL CONFIG MMODE ACCMODE LCYCMODE PEAKCYC SAGCYC CFCYC HSDC_CFG CONFIG_A LPOILVL CONFIG2 Rev. 0 | Page 32 of 56 EVAL-ADE7878AEBZ User Guide UG-545 TROUBLESHOOTING • This section provides troubleshooting tips for resolving the most commonly encountered difficulties. While executing the evaluation software, if the power supply to the board is not connected, the name of the IC displayed on the main screen of the front panel will be faulty. In addition, you will not be able to communicate with the IC correctly. If this occurs, provide power to the evaluation board and restart the execution of the evaluation software. If the registers read all FFs or 00s, then • • Check the power supply to the board. If there is no power, power up the board and restart the software. Check if the jumper connections made on the evaluation board match the communication protocol selected. If not, reconfigure the jumpers properly and restart the software. Check if the DSP is running: Write 0x01 to the Run register and verify if the registers can be accessed properly. Note that if a reset has been performed, set the Run register to 0x01 before accessing other registers. If the USB connection to the evaluation board was terminated while the software execution was taking place, then an error will be reported while re-executing the software. When encountering this problem, remove the USB cable from the evaluation board and press the S2 (MRESET) button once. Now, connect the USB cable to the board and restart the evaluation software. Rev. 0 | Page 33 of 56 UG-545 EVAL-ADE7878AEBZ User Guide EVALUATION BOARD SCHEMATICS AND LAYOUT SCHEMATICS ADE7878A DUT 1 MOSI/SD A 1 MISO/HS D 1 SSB/HSA SSB/HS A SCLK/SC L 1 CF3/HSCL K 1 CF2/HREA D 1 Y CF 1 1 GRY RESE TB 1 IRQ1 B PAD 40 39 38 37 36 35 34 33 32 31 GRY PM1 GRY PM0 PM1 RESETB DVDD 30 29 28 27 26 25 24 23 22 21 1 IRQ0B GRY IRQ0 B CLKOU T CLKI N VDD AVD D VAP VBP 10-0016A 11403-038 1 JP1 2 IBN ICP ICN INP INN REF VN VCP 11 12 13 14 15 16 17 18 19 20 IAP IAN IBP 1 2 3 4 5 6 7 8 9 10 JPR0402 PM0 GRY U1 MOSI/S DA GRY MISO/ HSD GRY SCLK/S CL GRY CF3/HSCLK GRY CF2/HR EA DY GRY CF1 GRY IRQ1B GRY Figure 38. ADE7854A/ADE7858A/ADE7868A/ADE7878A Schematic ISOLATED CONNECTIONS OF CF PINS 5227699-2 MGND CF2_ISO CF2_HREADY_ISO 5227699-2 MGN D Figure 39. Isolated Connections of CF Pins Rev. 0 | Page 34 of 56 CF3_ISO CF3_HSCLK_ISO 5227699-2 MGN D 11403-039 CF1_ISO CF1_ISO EVAL-ADE7878AEBZ User Guide UG-545 DUT COMM. PROTOCOL SELECT MISO_HSD _ISO 1 2 3 HSD C MISO_ISO SCL I2C SPI JP31 22-03-2031 SDA ALIGN JP32, JP3 3 AND JP34 AS CLOSE TO ISOLATO RS AS POSSIBLE. SPI JP33 22-03-2031 PUT JP31 ON MCU SIDE OF ISOLATIO N MOSI/SDA MOSI SCLK/SCL SCLK 1 2 3 HSDATA_I SO SSB/HS A HSACTIVE SSB HSDC 1 2 3 INDICATI NG PROTOCOL ON SILKSCRE EN ON EITH ER SIDE OF JUMPERS. JP34 22-03-2031 Figure 40. Communication Protocol Selection EXTRA GROUND TP FOR PROBING AGND2 AGND3 AGND4 AGND5 AGND1 1 BLK 1 BLK 1 BLK 1 BLK 1 BLK AGND6 AGND7 AGND8 AGND9 AGND10 1 BLK 1 BLK 1 BLK 1 BLK 1 BLK Figure 41. Ground Connections Rev. 0 | Page 35 of 56 SPI 11403-040 JP32 22-03-2031 SPI 11403-041 1 2 3 PLACE LABELS I2C UG-545 EVAL-ADE7878AEBZ User Guide MOSI/SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCLK/SCL SSB/HSA MISO/HSD CF3/HSCLK CF2/HREADY CF1 IRQ1B IRQ0B RESETB PM1 PM0 EXT_CLKIN CLKOU T TSW-116-0 8-G-D 11403-042 DEVICE INTERFACE HEADER P11 Figure 42. Device Interface Header Rev. 0 | Page 36 of 56 EVAL-ADE7878AEBZ User Guide UG-545 XTAL CKT CLKOUT GRY C29 1 18PF Y1 1 2 16.384 MEGH Z CLKOUT C30 18PF CLKIN GRY CLKIN 1 2 3 1 EXT_CLKIN JP10 A COM B 3PIN_SOLDER_JUMPER 131-3701-301 1 DN I TBD0805 R35 2 3 4 5 TBD0805 EXT_CLKIN C31 11403-043 DN I Figure 43. ADE7854A/ADE7858A/ADE7868A/ADE7878A Clock Circuitry EXT. I/O SELECT SCLK_ SCL_EXT I2C CF2_HREADY_EX T EXT JP75 3PIN_SOLDER_JUMPER DUT SPI 1 2 3 CF3_H SCLK_IS O CF3_H SCLK_EX T 1 EXT JP76 3PIN_SOLDER_JUMPER Figure 44. I/O Selection Rev. 0 | Page 37 of 56 O JP74 3PIN_SOLDER_JUMPER CF3_HSCLK_DU T 1 A 2 COM 3 B DUT HSD C CF2_H READY_I SO CF2_H READY_D UT 1 A 2 COM 3 B CF1_E XT SPI JP73 3PIN_SOLDER_JUMPER CF1_ISO CF1_D UT SSB_I S DUT EXT JP77 3PIN_SOLDER_JUMPER 11403-044 SPI JP72 3PIN_SOLDER_JUMPER JP71 3PIN_SOLDER_JUMPER HSA_I SO A 2 COM 3 B I2C O SSB_H SA_EXT MOSI_ ISO 1 2 3 1 2 3 SPI A COM B A COM B HSDC MOSI_ SDA_EX T SDA_ISO SCLK_ IS A COM B SCL_I SO 1 2 3 MISO_ ISO A COM B MISO_ HSD_EX T HSDATA_IS O UG-545 EVAL-ADE7878AEBZ User Guide VDD2 MCU_VDD C45 RESB_CTRL PM0_CTRL PM1_CTRL HSA_ISO 0.1U F 10K 1 VDD2 VDD1 2 GND2 GND1 3 VIA VOA 4 VIB VOB 5 VIC VOC 6 VID VOD 7 VE2 VE1 8 GND2 GND1 JP51 2 0 RESETB PM0 PM1 HSACTIVE 16 15 14 13 12 11 10 9 MCU -> 1 3.3V ADP1713AUJZ-3.3-R7 1 IN 5 3 OUT EN 4 U9 11403-054 .01UF C63 330K USB_VDD GND 2 R58 JP23 2 0 10UF BYP 1 C64 220K SMAJ4735A-TP D1 A R57 JP22 2 0 C 1 10UF Figure 54. MCU Power Supply Regulator TOGGLE SWITCHES R73 3 4 1 2 10K C67 S3 MCU_VDD R59 3 4 10K C68 B3S1000 B3S1000 1UF 1UF SERIAL DOWNLOAD ENABLE MRESET Figure 55. MCU Reset and Boot Switches XTAL CIRCUIT Y2 1 2 12.000MEGHZ MCU_XT2 11403-056 20PF MCU_XT1 20PF S2 C66 1 2 SDENB Figure 56. MCU Clock Circuit Rev. 0 | Page 42 of 56 11403-055 MCU_VDD MCU_RST C65 C62 VBU S EVAL-ADE7878AEBZ User Guide UG-545 DNI 2 R16 1500 OHMS 100 JP4N 1K JP6N 69157-102HLF 69157-102HLF 1 INN_IN R24 INN 1 GRY INN 11403-057 DNI INP 22NF 1K 22NF R23 100 C23 R15 INP 1 GRY C24 E2N 69157-102HLF 22NF R7 R8 69157-102HLF 69157-102HLF 25.161.0253 JP1N P4 1 2 JP2N 1500 OHMS 69157-102HLF 22NF 2 TBD1206 1 TBD1206 INP_IN JP5N C15 E1N JP3N C16 NEUTRAL CURRENT Figure 57. Neutral Current Circuit NEUTRAL VOLTAGE VN GRY 1 2 R25 VN 1K 22NF 1500 OHMS C25 JP7N 22-03-2031 11403-058 25.161.0253 VN_IN 1 2 3 P5 1 2 E3N Figure 58. VN Circuit Rev. 0 | Page 43 of 56 UG-545 EVAL-ADE7878AEBZ User Guide OUTPUT LED CIRCUIT VDD 2 R69 10K 10K FDV302P 1 Q2 Q3 499 R40 D CF3 A CF2 3 CR3 499 R39 D G C C 3 CR2 A CF1 CR1 1 D 499 R38 3 G FDV302P FDV302P 1 S CF3/HSCLK CMD2 8-21VGCT R8T1 CF2/HREADY G 2 S CMD2 8-21VGCT R8T1 CF1 10K 2 Q1 A S C 2 R60 CMD2 8-21VGCT R8T1 R67 VDD 2 R68 R61 10K 10K 2 2 S S FDV302P A (SEE JP66 CONFIG ) 11403-059 CR5 Q5 499 R42 LED_OUT_2: IRQ1B/MOSI/SDA D C 499 CMD2 8-21VGCT R8T1 3 CMD2 8-21VGCT R8T1 LED_OUT_2 1 Q4 C CR4 CONFIG ) D A R41 3 LED_OUT_1: IRQ0B/MISO/HSDA TA (SEE JP65 G FDV302P G LED_OUT _1 1 Figure 59. Output LED Circuit DNI C18 DNI 2 R10 1500 OHM S 100 JP4A 1K JP6A 69157-102HLF 69157-102HLF 1 IAN_ IN Figure 60. Phase A Current Rev. 0 | Page 44 of 56 IAP R18 IAN 1 GRY IAN 11403-060 1K C17 R17 22NF R9 100 IAP 1 GRY 22NF 69157-102HLF 22NF 69157-102HLF 22NF E2A TBD1 206 1500 OHM S TBD1 206 2 R1 JP1A 69157-102HLF JP2A 25.161.025 3 69157-102HLF P1 1 2 1 R2 IAP_IN JP5A C9 E1A JP3A C10 PHA SE A CURRENT EVAL-ADE7878AEBZ User Guide UG-545 R26 VAP GRY 1MEG PHASE A VOLTAG E E3A P8 VAP_I N 1 1 2 R29 2 VAP 1K R32 JP7A 22-03-2031 22NF 1 2 3 25.161.0253 C28 JP9A 1500 OHMS 6915 7-102HL F 1K 11403-061 B A COM 1 2 3 VN JP8A 3PIN_SOLDER_JUMPE R Figure 61. Phase A Voltage PHASE B CURREN T JP3B JP5B 6915 7-10 2HL F 6915 7-10 2HL F IBP 100 JP4B 1500 OHM S 22NF R20 IBN 1 GRY IBN 1K JP6B 69157-102HLF 11403-062 IBN_I N 22NF DNI R12 2 IBP C20 DNI 1 GRY C19 1K 22NF R19 100 22NF E2B 1 R11 C11 R3 1500 OHMS R4 6915 7-10 2HL F 6915 7-10 2HL F 25.161.0253 2 TBD120 6 JP1B JP2B P2 1 2 1 TBD120 6 IBP_I N C12 E1B 6915 7-10 2HL F Figure 62. Phase B Current R27 1MEG PHASE B VOLTAGE VBP GRY E3B R30 1 2 3 R33 JP7B 22-03-2031 22N F 1500 OHMS 25.161.0253 C27 VBP 1K 6915 7-102HL F 1 VN JP8B 3PIN_SOLDER_JUMPER Figure 63. Phase B Voltage Rev. 0 | Page 45 of 56 11403-063 2 1K 1 JP9B VBP_IN 1 2 A 2 COM 3 B P7 UG-545 EVAL-ADE7878AEBZ User Guide PHA SE C CURREN T 691 5 7- 10 2 HL F 1500 OHM S 100 JP4C ICN 1 GRY ICN 1K JP6C 69157-102HLF 22NF R22 11403-064 R14 ICN_I N 22NF DNI 2 1 ICP C22 DNI 1 GRY C21 1K 22NF 100 22NF R21 C13 TBD120 6 R13 C14 E2C TBD120 6 R5 1500 OHM S R6 691 5 7- 10 2 HL F 691 5 7- 10 2 HL F 2 1 691 5 7- 10 2 HL F JP1C 25.161.0253 JP2C P3 1 2 JP5C ICP E1C ICP_I N JP3C 691 5 7- 10 2 HL F Figure 64. Phase C Current R28 1MEG PHASE C VOLT AGE VCP GRY E3C 2 R31 VCP 1 2 3 JP7C 22-03-2031 22NF JP9C 1500 OHMS 25.161.0253 69157-102HLF 1K C26 A COM B 1 2 3 VN Figure 65. Phase C Voltage Rev. 0 | Page 46 of 56 JP8C 3PIN_SOLDER_JUMPE R 11403-065 1 2 1 1K VCP _IN R34 P6 EVAL-ADE7878AEBZ User Guide UG-545 PS CONNECTIONS DUT VDD VDD 1 RED P9 1 2 0.1UF C2 C1 10UF VDD 25.161.0253 DIGITAL SUPPLY ANALOG SUPPLY DVDD 1 GRY AVDD 1 GRY DVDD 0.22U F C4 4.7UF C3 0.22U F C6 C5 4.7UF AVDD ISO SUPPLY (DUT SIDE) 10UF 25.161.0253 11403-066 1 2 3 C7 1 2 P10 VDD 0.1UF C8 ISO_VDD_EX T VDD2 JP11 22-03-2031 Figure 66. Power Supply Connections REFERENCE DECOUPLING AND EXTERNAL REF XREF JP12 REF REF 1 GRY Figure 67. Reference Voltage Circuit Rev. 0 | Page 47 of 56 4.7UF 11403-067 PLACE C35, C36 AS CLOSE TO DUT PIN 17 AS POSSIBLE C36 C35 69157-102HLF 0.1UF VO 0.1UF V- 3 C34 0.1UF V+ XREF 1 GRY A1 2 ADR280ARTZ 1 C33 VDD UG-545 EVAL-ADE7878AEBZ User Guide 1 2 1UF 10K C32 1 2 R37 VDD 3 4 RESETB 11403-068 B3S1000 Figure 68. ADE7854A/ADE7858A/ADE7868A/ADE7878A Reset Circuit P15 R81 MCU_VDD RXD 10K TXD 1 2 3 4 11403-069 TSW-104-08-G-S UART Figure 69. UART Circuit USB INTERFACE D-_MCU R78 D- P14 D+ 2 3 6 27 D+_M CU R79 1 4 5 USB_UP C A 4-173437 6 -8 R76 680 MCU_VDD VBUS(5V) D- 27 CR6 VBU S R66 1.5K D+ NC GND SHIELD D+, D-, VREF_MCU WITH GND FROM CONN TO MCU Figure 70. USB Interface Rev. 0 | Page 48 of 56 11403-070 SML-LXT0805G W-TR EVAL-ADE7878AEBZ User Guide UG-545 11403-071 LAYOUT Figure 71. Layer Top Layer Rev. 0 | Page 49 of 56 EVAL-ADE7878AEBZ User Guide 11403-072 UG-545 11403-073 Figure 72. Layer 2 Figure 73. Layer 3 Rev. 0 | Page 50 of 56 UG-545 11403-074 EVAL-ADE7878AEBZ User Guide Figure 74. Bottom Layer Rev. 0 | Page 51 of 56 UG-545 EVAL-ADE7878AEBZ User Guide ORDERING INFORMATION BILL OF MATERIALS Table 27. Qty 1 Designator A1 1 10 30 A2 AGND1 to AGND10 VN, CF1, IAN, IAP, IBN, IBP, ICN, ICP, INN, INP, PM0, PM1, REF, VAP, VBP, VCP, AVDD, DVDD, XREF, CLKIN, IRQ0, IRQ1, CLKOUT, RESET, SS/HSA, MISO/HSD, MOSI/SDA, SCLK/SCL, CF3/HSCLK, CF2/HREADY C1, C8, C61, C62, C64 C9 to C28 C2, C7, C33 to C35, C37, C38, C40 to C46, C48 to C60 C29, C30, C65, C66 5 20 27 4 3 3 2 1 3 5 2 1 12 1 13 10 29 2 2 2 3 11 C3, C5, C36 C32, C67, C68 C4, C6 C63 CF1_ISO to CF3_ISO CR1 to CR5 CR6, CR7 D1 E1A to E3A, E1B to E3B, E1C to E3C, E1N to E3N EXT_CLKIN HSA_ISO, SCL_ISO, SDA_ISO, SSB_ISO, MISO_ISO, MOSI_ISO, PM0_CTRL, PM1_CTRL, SCLK_ISO, IRQ0B_ISO, IRQ1B_ISO, RESB_CTRL, HSDATA_ISO JP11, JP24, JP31 to JP34, JP7A, JP7B, JP7C, JP7N JP12, JP1A to JP6A, JP1B to JP6B, JP1C to JP6C, JP1N to JP6N, JP21, JP9A, JP9B, JP9C JP22, JP23 JP61, JP62 VDD, MCU_VDD MGND1 to MGND3 P1 to P10, P12 Description IC, 1.2 V ultralow power high PSRR voltage reference IC, swappable dual isolator Connector, PCB, test point, black Connector, PCB, test point, grey Manufacturer/Part Number Analog Devices/ADR280ARTZ Analog Devices/ADuM1250ARZ Components Corporation/TP-104-01-00 Components Corporation/TP-104-01-08 Capacitor, monolithic, ceramic, 10 µF Capacitor, ceramic chip, C0G, 0603, 22 nF Capacitor, X7R, 0805, 100 nF Murata/GRM21BR61C106KE15L Digi-Key/0603YC223KAT2A Murata/GRM21BR71H104KA01L Capacitor, monolithic, ceramic, C0G, 0402, 20 pF Capacitor, ceramic, 0805, X5R, 4.7 µF Capacitor, ceramic, 1206, X7R, 1 µF Capacitor, ceramic, X7R, 0.22 µF Capacitor, ceramic, X7R, 0.01 µF Connector, PCB coax, vertical, BNC, 50 Ω Diode, LED, green, SMD LED, green, surface mount Diode, 6.2 V, Zener, SMA Inductor, chip, ferrite bead, 0805, 1500 Ω Connector, PCB coax, SMB, RA Connector, PCB, test point, white Murata/GRM1555C1H200JZ01D Taiyo Yuden/EMK212BJ475KG-T Taiyo Yuden/GMK316B7105KL-T Phycomp (Yageo)/2222 780 15654 AVX/0306ZC103KAT2A Tyco Electronics/5227699-2 Chicago Mini Lamp/CMD28-21VGCTR8T1 Lumex/SML-LXT0805GW-TR Micro Commercial Co./SMAJ4735A-TP Murata/BLM21BD152SN1D Johnson/131-3701-301 Components Corporation/TP-104-01-09 3-pin jumper N/A Connector, PCB Berg jumper, ST, male 2-pin BERG/69157-102 Resistor jumper, SMD 1206 (short) Resistor jumper, SMD 0805 (open) Connector, PCB, test point, red Connector, PCB, test point, green Connector, PCB term, black, 2-pin, ST Panasonic/ERJ-8GEYJ0.0 Panasonic/ERJ-6GEYJ0.0 Components Corporation/TP-104-01-02 Components Corporation/TP-104-01-05 Weiland/25.161.0253 Rev. 0 | Page 52 of 56 EVAL-ADE7878AEBZ User Guide Qty 2 Designator P11, P17 1 1 P13 P14 1 1 5 8 P15 P16 Q1 to Q5 R9 to R16 15 R17 to R25, R29 to R34 3 R26 to R28 37 5 R37, R43 to R56, R59 to R65, R67 to R75, R77, R81 to R85 R38 to R42 1 1 1 R57 R58 R66 2 2 3 4 1 1 R76, R80 R78, R79 S1 to S3 U3, U4, U6, U7 U8 U9 1 Y1 1 Y2 UG-545 Description Connector, PCB, header, SHRD, ST, male 32-pin Connector, PCB, header, ST, male 20-pin Connector, PCB, USB, Type B, R/A, through hole Connector, PCB, header, ST, male 4-pin Connector, PCB, straight header 3-pin Trans digital FET P channel Resistor, precision thick film, chip R1206, 100 Ω Resistor, precision thick film, chip R0805, 1 kΩ Resistor, precision thick film, chip R0805, 1 MΩ Resistor, precision thick film, chip R0805, 10 kΩ Resistor, precision thick film, chip R1206, 499 Ω Resistor, film, SMD 0805, 220 kΩ Resistor, film, SMD 0805, 330 kΩ Resistor, PREC, thick film chip, R1206, 1.5 kΩ Resistor, film, SMD 0805, 680 Ω Resistor, film, SMD 1206, 27 Ω SW SM mechanical key switch IC quad channel digital isolator IC ARM7, MCU, flash, 512K 100 LQFP IC 300mA low dropout CMOS linear regulator IC crystal, 16.384 MHz maximum drive level: 500 µW maximum ESR: 40 Ω IC crystal quartz, 12.0 MHz Rev. 0 | Page 53 of 56 Manufacturer/Part Number Samtec/TSW-1-30-08-G-D Samtec/TSW-110-08-G-D AMP/4-1734376-8 Samtec/TSW-104-08-G-S Molex/22-03-2031 Fairchild/FDV302P Panasonic/ERJ-8ENF1000V Panasonic/ERJ-6ENF1001V Panasonic/ERJ-6ENF1004V Panasonic/ERJ-6ENF1002V Panasonic/ERJ-8ENF4990V Multicomp/MC 0.1W 0805 1% 220K Panasonic/ERJ-6GEYJ334V Panasonic/ERJ-8ENF1501V Multicomp/MC 0.1W 0805 1% 680R Phycomp (Yageo)/9C12063A27R0FKHFT Omron/B3S1000 Analog Devices/ADuM3401CRWZ NXP/LPC2368FBD100 Analog Devices/ADP1713AUJZ-3.3-R7 ECS/ECS-163.8-18-4XEN ECS/ECS-120-20-4X UG-545 EVAL-ADE7878AEBZ User Guide NOTES Rev. 0 | Page 54 of 56 EVAL-ADE7878AEBZ User Guide UG-545 NOTES Rev. 0 | Page 55 of 56 UG-545 EVAL-ADE7878AEBZ User Guide NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11403-0-7/14(0) Rev. 0 | Page 56 of 56