Evaluation Board User Guide
UG-146
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADE7878 Energy Metering IC
FEATURES
This user guide describes the ADE7878 evaluation kit hardware,
firmware, and software functionality. The evaluation board
contains an ADE7878 and a LPC2368 microcontroller (from
NXP Semiconductors). The ADE7878 and its associated
metering components are optically isolated from the
microcontroller. The microcontroller communicates with the
PC using a USB interface. Firmware updates can be loaded
using one PC com port and a regular serial cable.
Evaluation board designed to be used with accompanying
software to implement a fully functional 3-phase energy
meter
Easy connection of external transducers via screw terminals
Easy modification of signal conditioning components using
PCB sockets
LED indicators on the CF1, CF2, CF3, IRQ0, and IRQ1 logic
outputs
Optically isolated metering components and USB-based
communication with a PC
External voltage reference option available for on-chip
reference evaluation
PC COM port-based firmware updates
The ADE7878 evaluation board and this user guide, together
with the ADE7878 data sheet, provide a complete evaluation
platform for the ADE7878.
The evaluation board has been designed so that the ADE7878
can be evaluated in an energy meter. Using appropriate current
transducers, the evaluation board can be connected to a test
bench or high voltage (240 V rms) test circuit. On-board
resistor divider networks provide the attenuation for the line
voltages. This user guide describes how the current transducers
should be connected for the best performance. The evaluation
board requires two external 3.3 V power supplies and the
appropriate current transducers.
GENERAL DESCRIPTION
The ADE7878 is a high accuracy, 3-phase electrical energy
measurement IC with serial interfaces and three flexible pulse
outputs. The ADE7878 incorporates seven ADCs, reference
circuitry, and all signal processing required to perform total
(fundamental and harmonic) active, reactive, and apparent
energy measurement, fundamental active and reactive energy
measurement, and rms calculations.
EVALUATION BOARD CONNECTION DIAGRAM
IBN IBP
IAN IAP
P2
VDD2 GND2
P1
MCU_VDD MCU_GND
P10
P12
P3
ICP
ICN
LPC2368
FILTER
NETWORK
USB PORT
ADE78xx
DIGITAL
ISOLATORS
INP
INN
P13
P4
P15
OPTIONAL
EXTERNAL
CLOCK IN
OPTIONAL EXTERNAL ADR280
1.2V REFERENCE
CONNECTOR TO
PC COM PORT
FILTER NETWORK
AND ATTENUATION
P6
VN GND
VCP GND
P7
VBP GND
P8
P9
VAP GND
VDD GND
Figure 1.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 36
J2
J3
CF3
J4
CF2
CF1
09078-001
P5
JTAG
INTERFACE
UG-146
Evaluation Board User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
PSM3 Mode ................................................................................. 18
General Description ......................................................................... 1
Evaluation Board Connection Diagram ........................................ 1
Managing the Communication Protocol Between the
Microcontroller and the ADE7878 .............................................. 19
Revision History ............................................................................... 2
Acquiring HSDC Data Continuously ...................................... 21
Evaluation Board Hardware ............................................................ 3
Starting the ADE7878 DSP ....................................................... 22
Power Supplies .............................................................................. 3
Stopping the ADE7878 DSP ..................................................... 22
Analog Inputs (P1 to P4 and P5 to P8)...................................... 3
Upgrading Microcontroller Firmware ......................................... 23
Setting Up the Evaluation Board as an Energy Meter ............. 6
Control Registers Data File ....................................................... 23
Evaluation Board Software .............................................................. 8
Evaluation Board Schematics and Layout ................................... 25
Installing and Uninstalling the ADE7878 Software ................. 8
Schematic..................................................................................... 25
Front Panel .................................................................................... 8
Layout .......................................................................................... 32
PSM0 Mode—Normal Power Mode .......................................... 9
Ordering Information .................................................................... 34
PSM1 Mode ................................................................................. 17
Bill of Materials ........................................................................... 34
PSM2 Mode ................................................................................. 17
REVISION HISTORY
8/10—Revision 0: Initial Version
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Evaluation Board User Guide
UG-146
EVALUATION BOARD HARDWARE
POWER SUPPLIES
JP3A
JP5A
R9
R17
TP1
The evaluation board has three power domains: one that
supplies the microcontroller and one side of the isocouplers,
one that supplies the other side of the optocouplers, and one
that supplies the ADE7878. The ground of the microcontroller’s
power domain is connected to the ground of the PC through
the USB cable. The ground of the ADE7878 power domain is
determined by the ground of the phase voltages, VAP, VBP, VCP,
and VN, and must be different from the ground of the microcontroller’s power domain.
The microcontroller 3.3 V supply is provided at the P12
connector. The ADE7878 3.3 V supply is provided at the P9
connector. Close jumper JP2 to ensure that the same 3.3 V
supply from ADE7878 is also provided at the isocouplers.
P1
IAP
JP1A
R1
100Ω
C9
22,000pF
1kΩ
C17
22,000pF
JP2A
R2
C10
22,000pF
C18
22,000pF
ADE78xx
IAP
IAN
R18
1kΩ
JP4A
JP6A
IAN
09078-002
R10
100Ω
TP2
Figure 2. Phase A Current Input Structure on the Evaluation Board
JP5A
R9
R17
TP1
ANALOG INPUTS (P1 TO P4 AND P5 TO P8)
Current and voltage signals are connected at the screw terminal,
P1 to P4 and P5 to P8, respectively. All analog input signals are
filtered using the on-board antialiasing filters before the signals
are connected to the ADE7878. The components used on the
board are the recommended values to be used with the
ADE7878.
IMAX = 6A rms
CT
P1
1:2000
JP1A
R1
50Ω
100Ω
C9
22,000pF
1kΩ
C17
22,000pF
JP2A
R2
50Ω
C10
22,000pF
C18
22,000pF
R10
R18
100Ω
1kΩ
JP4A
JP6A
IAP
ADE78xx
IAN
TP2
Current Sense Inputs (P1, P2, P3, and P4)
09078-003
JP3A
Figure 3. Example of a Current Transformer Connection
The ADE7878 measures three phase currents and the neutral
current. Current transformers or Rogowski coils can be used
to sense the current but should not be mixed together. The
ADE7878 contains different internal PGA gains on phase
currents and on the neutral current; therefore, sensors with
different ratios can be used. The only requirement is to have the
same scale signals at the PGA outputs; otherwise, the mismatch
functionality of the ADE7878 is compromised (see the
ADE7878 data sheet for more details about neutral current
mismatch). Figure 2 shows the structure used for the Phase A
current; the sensor outputs are connected to the P1 connector.
The R1 and R2 resistors are the burden resistors and, by default,
they are not populated. They can also be disabled using the JP1A
and JP2A jumpers. The R9/C9 and R10/C10 RC networks are
used in conjunction with Rogowski coils. They can be disabled
using the JP3A and JP4A jumpers. The R17/C17 and R18/C18
RC networks are the antialiasing filters. The default corner
frequency of these low pass filters is 7.2 kHz (1 kΩ/22 nF).
These filters can easily be adjusted by replacing the components
on the evaluation board.
All the other current channels (that is, Phase B, Phase C, and
the neutral current) have a similar input structure.
Using a Current Transformer as the Current Sensor
Figure 3 shows how a current transformer can be used as a
current sensor in one phase of a 3-phase, 4-wire distribution
system (Phase A). The other two phases and the neutral current
require similar connections.
The R1 and R2 burden resistors must be defined as functions of
the current transformer ratio and maximum current of the
system, using the following formula:
R1 = R2 = 1/2 × 0.5/sqrt(2) × N/IFS
where:
0.5/sqrt(2) is the rms value of the full-scale voltage accepted at
the ADC input.
N is the input-to-output ratio of the current transformer.
IFS is the maximum rms current to be measured.
The JP1A and JP2A jumpers should be opened if R1 and R2 are
used. The antialiasing filters should be enabled by opening the
J5A and J6A jumpers (see Figure 3).
The secondary current of the transformer is converted to a
voltage by using a burden resistor across the secondary winding
outputs. Care should be taken when using a current transformer
as the current sensor. If the secondary is left open (that is, no
burden is connected), a large voltage may be present at the
secondary outputs. This can cause an electric shock hazard and
potentially damage electronic components.
Most current transformers introduce a phase shift that the
manufacturer indicates in the data sheet. This phase shift can
lead to significant energy measurement errors, especially at low
power factors. The ADE7878 can correct the phase error using
the APHCAL[9:0], BPHCAL[9:0], and CPHCAL[9:0] phase
calibration registers as long as the error stays between −6.732°
and +1.107° at 50 Hz (see the ADE7878 data sheet for more
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Evaluation Board User Guide
Voltage Sense Inputs (P5, P6, P7, and P8 Connectors)
Using a Rogowski Coil as the Current Sensor
JP3A
JP5A
R9
R17
100Ω
C9
22,000pF
1kΩ
C17
22,000pF
TP1
ROGOWSKI P1
COIL
JP1A
R1
IAP
Figure 5 shows a typical connection of the Phase A voltage
inputs; the resistor divider is enabled by opening the JP7A
jumper. The antialiasing filter on the VN data path is enabled
by opening the JP7N jumper. JP8A and JP8N are also opened.
The VN analog input is connected to AGND via the R25/C25
antialiasing filter using the JP8N connector.
The attenuation networks can be easily modified by the user to
accommodate any input level. However, the value of R32 (1 kΩ),
should be modified only together with the corresponding
resistors in the current channel (R17 and R18 on the Phase A
current data path).
JP7A
ADE78xx
TP12
P8
VAP
R26
R29
1MΩ
100kΩ
JP9A
R18
1kΩ
IAN
TP2
JP4A
VN
C25
22,000pF
09078-005
R10
100Ω
1kΩ
JP8N
C18
22,000pF
JP6A
Figure 4. Example of a Rogowski Coil Connection
09078-004
C10
22,000pF
VN
TP9
R25
VN
R2
C32
22,000pF
JP7N
P5
JP2A
ADE78xx
VAP
R32
1kΩ
JP8A
NEUTRAL
Figure 4 shows how a Rogowski coil can be used as a current
sensor in one phase of a 3-phase, 4-wire distribution system
(Phase A). The other two phases and the neutral current require
similar connections. The Rogowski coil does not require any
burden resistors; therefore, R1 and R2 should not be populated.
The antialiasing filters should be enabled by opening the J5A
and J6A jumpers. To account for the high frequency noise
introduced by the coil, an additional antialiasing filter must be
introduced by opening the JP3A and JP4A jumpers. Then, to
compensate for the 20 dB/dec gain introduced by the di/dt
sensor, the integrator of the ADE7878 must be enabled by
setting Bit 0 (INTEN) of the CONFIG register. The integrator
has a −20 dB/dec attenuation and an approximately −90° phase
shift and, when combined with the di/dt sensor, results in a
magnitude and phase response with a flat gain over the
frequency band of interest.
The voltage input connections on the ADE7878 evaluation
board can be directly connected to the line voltage sources.
The line voltages are attenuated using a simple resistor divider
network before they are supplied to the ADE7878. The
attenuation network on the voltage channels is designed so that
the corner frequency (3 dB frequency) of the network matches
that of the antialiasing filters in the current channel inputs. This
prevents the occurrence of large energy errors at low power
factors.
1
A
2
COM
3
B
For this particular example, burden resistors of 50 Ω signify an
input current of 7.05 A rms at the ADE7878 ADC full-scale
input (0.5 V). In addition, the PGA gains for the current
channel must be set at 1. For more information about setting
PGA gains, see the ADE7878 data sheet. The evaluation
software allows the user to configure the current channel gain.
PHASE A
details). The software supplied with the ADE7878 evaluation
board allows user adjustment of phase calibration registers.
Figure 5. Phase A Voltage Input Structure on the Evaluation Board
The maximum signal level permissible at the VAP, VBP, and
VCP pins of the ADE7878 is 0.5 V peak. Although the
ADE7878 analog inputs can withstand ±2 V without risk of
permanent damage, the signal range should not exceed ±0.5 V
with respect to AGND for a specified operation.
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Evaluation Board User Guide
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Table 1. Recommended Settings for Evaluation Board Connectors
Jumper
JP1
JP1A, JP1B,
JP1C, JP1N,
JP2
Option
Soldered
Open
Description
Connects AGND to ground. By default, it is soldered.
Connect IAP, IBP, IC, and INP to AGND. By default, they are open.
Closed
JP2A, JP2B,
JP2C, JP2N
JP3
JP3A, JP3B,
JP3C, JP3N
JP4
JP4A, JP4B,
JP4C, JP4N
JP5
JP5A, JP5B,
JP5C, JP5N
JP6
JP6A, JP6B,
JP6C, JP6N
JP7
Open
Connects the ADE7878 VDD power supply (VDD_F at the P9 connector) to the power supply of the
isocouplers (VDD2 at the P10 connector). By default, it is closed.
Connect IAN, IBN, ICN, and INN to AGND. By default, they are open.
JP7A, JP7B,
JP7C
JP7N
JP8
JP8A, JP8B,
JP8C
JP8N
JP9
JP9A, JP9B,
JP9C
JP10
JP11
Unsoldered
Closed
Soldered
Open
Connects the pad metal below the ADE7878 to AGND. By default, it is unsoldered.
Disable the phase compensation network in the IAP, IBP, ICP, and INP data path. By default, they are
closed.
Connects C3 to DVDD. By default, it is soldered.
Disable the phase compensation network in the IAN, IBN, ICN, and INN data path. By default, they are
closed.
Connects C5 to AVDD. By default, it is soldered.
Disable the phase antialiasing filter in the IAP, IBP, ICP, and INP data path. By default, they are open.
Soldered
Open
Connects C41 to the REF pin of the ADE7878. By default, it is soldered.
Disable the phase antialiasing filter in the IAN, IBN, ICN, and INN data path. By default, they are open.
Closed
Open
Enables the supply to the microcontroller. When open, takes out the supply to the microcontroller. By
default, it is closed.
Disable the resistor divider in the VAP, VBP, and VCP data path. By default, they are open.
Open
Open
Open
Disables the antialiasing filter in the VN data path. By default, it is open.
Sets the microcontroller in flash memory programming mode. By default, it is open.
Connect VAP, VBP, and VCP to AGND. By default, they are open.
Closed
Open
Connects VN to AGND. By default, it is closed.
When closed, signals the microcontroller to declare all I/O pins as outputs. It is used when another
microcontroller is used to manage the ADE7878 through the P38 socket. By default, it is open.
Connect the ground of antialiasing filters in the VAP, VB, and VCP data path to AGND or VN. By default,
they are soldered to AGND.
Connects the external voltage reference to ADE7878. By default, it is open.
Connects the CLKIN pin of the ADE7878 to a 16,384 MHz crystal (Pin 1 of JP11) or to an external clock
input provided at J1. By default, it is soldered to Pin 1.
Connects DGND (Pin 2 of JP12) of the ADE7878 to ground (Pin 1 of JP12) or to AGND (Pin 3 of JP12).
Soldered
Closed
JP35, JP33
Soldered to Pin
1 (AGND)
Open
Soldered to Pin
1
Soldered to Pin
3 (AGND)
Open
JP31, JP37
Open
JP36, JP34,
JP32, JP38
Closed with
0 Ω resistors
JP12
If I2C communication between the NXP LPC2368 and the ADE7878 is used, these connectors should be
closed with 0 Ω resistors, and the JP36 and JP34 connectors should be opened. By default, the SPI is the
communication used between the NXP LPC2368 and the ADE7878; therefore, these connectors are open.
If HSDC communication is used, these connectors should be closed with 0 Ω resistors, and the JP35 and
JP33 connectors should also be closed. By default, the SPI is the communication used between the NXP
LPC2368 and the ADE7878; therefore, these connectors are open.
If SPI communication is used between the NXP LPC2368 and the ADE7878, these connectors should be
closed and JP35, JP33, JP31, and JP37 should be opened. By default, the SPI is the communication used
between the NXP LPC2368 and the ADE7878; therefore, these connectors are closed.
Rev. 0 | Page 5 of 36
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Evaluation Board User Guide
SETTING UP THE EVALUATION BOARD AS AN
ENERGY METER
Figure 6 shows a typical setup for the ADE7878 evaluation
board. In this example, an energy meter for a 4-wire, 3-phase
distribution system is shown. Current transformers are used to
sense the phase and neutral currents and are connected as
shown in Figure 6. The line voltages are connected directly to
the evaluation board as shown. Note that the state of all jumpers
must match the states shown in Figure 6, keeping in mind that
the board is supplied from two different 3.3 V power supplies,
one for the ADE7878 domain, VDD, and one for the NXP
LPC2368 domain, MCU_VDD. Because the two domains are
isolated to ensure that there is no electrical connection between
the high voltage test circuit and the control circuit, the power
supplies should have floating voltage outputs.
The evaluation board is connected to the PC using a regular
USB cable supplied with the board. When the evaluation board
is powered up and connected to the PC, the enumeration process
begins and the PC recognizes new hardware and asks to install
the appropriate driver. The drive can be found in the VirCOM_
Driver_XP folder of the CD. After the driver is installed, the
supplied evaluation software can be launched. The next section
describes the ADE7878 evaluation software in detail and how it
can be installed and uninstalled.
Activating Serial Communication Between the ADE7878
and the NXP LPC2368
The ADE7878 evaluation board is supplied with communication between the ADE7878 and the NXP LPC2368 that is set
through the SPI ports. The JP32, JP34, JP36, and JP38 jumpers
are closed using 0 Ω resistors, and the JP31, JP33, JP35, and
JP37 jumpers are open. The SPI port should be chosen as the
active port in the ADE7878 control panel.
JP33, JP35, and JP37 jumpers should be closed using 0 Ω
resistors, and the JP32, JP34, JP36, and JP38 jumpers should be
open. In this case, the I2C port should be chosen as the active
port in the ADE7878 control panel (see Table 2).
Table 2. Jumper State to Activate SPI or I2C Communication
Active
Communication
SPI (Default)
I2C
Jumpers Closed
with 0 Ω Resistors
JP32, JP34, JP36,
JP38
JP31, JP33, JP35,
JP37
Jumpers Open
JP31, JP33, JP35,
JP37
JP32, JP34, JP36,
JP38
Using the Evaluation Board with Another Microcontroller
It is possible to manage the ADE7878 mounted on the evaluation board with a different microcontroller mounted on another
board. The ADE7878 can be connected to this second board
through one of two connectors: P11 or P38. P11 is placed on the
same power domain as the ADE7878. P38 is placed on the
power domain of the NXP LPC2368 and communicates with
the ADE7878 through the isocouplers. If P11 is used, the power
domain of the NXP LPC2368 should not be supplied at P12. If
P38 is used, a conflict may arise with the NXP LPC2368 I/O
ports. The following two options are provided to deal with this
situation:
•
•
Communication between the ADE7878 and the NXP LPC2368
is also possible using the I2C ports. To accomplish this, the JP31,
Rev. 0 | Page 6 of 36
One option is to keep the NXP LPC2368 running and close
JP9. This tells the NXP LPC2368 to set all of its I/Os high
to allow the other microcontroller to communicate with
the ADE7878. After JP9 is closed, the S2 reset button
should be pressed low to force the NXP LPC2368 to reset.
This is necessary because the state of JP9 is checked inside
the NXP LPC2368 program only once after reset.
The other option is to cut the power supply of the NXP
LPC2368 by disconnecting JP7.
Evaluation Board User Guide
UG-146
VOLTAGE SOURCE
VOLTAGE SOURCE
GND
VDD
MCU_GND
P9
MCU_VDD
P12
PHASE C
JP1, JP2 = CLOSED
NEUTRAL
PHASE B
IAP
IAP
P1
JP1A, JP2A = OPEN
R1
JP3A, JP4A = CLOSED
IAN
R2
IBP
P2
IAN
JP5A, JP6A = OPEN
IBP
JP1B, JP2B = OPEN
R3
JP3B, JP4B = CLOSED
IBN
R4
ICP
P3
IBN
JP5B, JP6B = OPEN
ICP
JP1C, JP2C = OPEN
R5
JP3C, JP4C = CLOSED
ICN
R6
INP
P4
ICN
JP5C, JP6C = OPEN
INP
JP1N, JP2N = OPEN
R7
JP3N, JP4N = CLOSED
INN
R8
INN
VAP
P8
R26
VAP
R32
VBP
P7
R27
C32
JP7A, JP8A = OPEN
R30
VBP
R33
VCP
JP5N, JP6N = OPEN
R29
P6
R28
C33
JP7B, JP8B = OPEN
R31
VCP
R34
C34
JP7C, JP8C = OPEN
LOAD
NEUTRAL
P5
R25
VN
C34
JP7N = OPEN
JP8N = CLOSED
Figure 6. Typical Setup for the ADE7878 Evaluation Board
Rev. 0 | Page 7 of 36
09078-006
VN
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Evaluation Board User Guide
EVALUATION BOARD SOFTWARE
The ADE7878 evaluation board is supported by Windows®
based software that allows the user to access all the functionality
of the ADE7878. The software communicates with the NXP
LPC2368 microcontroller using the USB as a virtual COM port.
The NXP LPC2368 communicates with the ADE7878 to
process the requests that are sent from the PC.
Serial communication between the microcontroller and the
ADE7878 is introduced using a switch. By default, the SPI port
is used. Note that the active serial port must first be set in the
hardware. See the Activating Serial Communication Between
the ADE7878 and the NXP LPC2368 section for details on how
to set it up.
INSTALLING AND UNINSTALLING THE ADE7878
SOFTWARE
The main menu has only one choice, other than Exit, enabled,
Find COM Port. Clicking it starts a process in which the PC
tries to connect to the evaluation board using the port indicated
in the Start menu. It uses the echo function of the communication protocol (see the Managing the Communication Protocol
Between the Microcontroller and the ADE7878 section). It
displays the port that matches the protocol and then sets it to
115,200 baud, eight data bits, no parity, no flow control, one
stop bit.
The ADE7878 software is supplied on one CD-ROM. It
contains two projects: one that represents the NXP LPC2368
project and one LabVIEW™ based program that runs on the PC.
The NXP LPC2368 project is already loaded into the processor,
but the LabVIEW based program must be installed.
1.
2.
To install the ADE7878 software, place the
CD-ROM in the CD-ROM reader and double-click
LabView_project\installation_files\setup.exe. This
launches the setup program that automatically installs
all the software components, including the uninstall
program, and creates the required directories.
To launch the software, go to the Start/Programs/
ADE7878 Eval Software menu and click ADE7878
Eval Software.
1.
2.
3.
Before installing a new version of the ADE7878 evaluation
software, first uninstall the previous version.
Select the Add/Remove Programs option in the Windows
control panel.
Select the program to uninstall and click the Add/Remove
button.
FRONT PANEL
When the software is launched, the Front Panel is opened. This
panel contains three areas: the main menu at the left, the submenu at the right, and a box that displays the name of the
communication port used by the PC to connect to the
evaluation port, also at the right (see Figure 7).
The COM port used to connect the PC with the evaluation
board must be selected first. The program displays a list of the
active COM ports, allowing you to select the right one. To learn
what COM port is used by the evaluation board, launch the
Windows Device Manager (the devmgmt.msc file) in the Run
window on the Windows Start menu. By default, the program
offers the option of searching for the COM port.
09078-007
Both the ADE7878 evaluation software program and the NI
run-time engine are easily uninstalled by using the Add/
Remove Programs option in the control panel.
Figure 7. Front Panel of ADE7878 Software
If the evaluation board is not connected, the port is displayed as
XXXXX. In this case, the evaluation software is still accessible,
but no communication can be executed. In both cases, whether
the search for the COM port is successful or not, the cursor is
positioned back at Please select from the following options in
the main menu, Find COM Port is grayed out, and the next main
menu options are enabled (see Figure 8). These options allow
you to command the ADE7878 in either the PSM0 or PSM3
power mode. The other power modes, PSM1 and PSM2, are not
available because initializations have to be made in PSM0 before
the ADE7878 can be used in one of these other modes.
Rev. 0 | Page 8 of 36
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09078-009
09078-008
Evaluation Board User Guide
Figure 8. Front Panel After the COM Port Is Identified
Figure 9. Front Panel After the ADE7878 Enters PSM0 Mode
PSM0 MODE—NORMAL POWER MODE
Reset ADE7878
Enter PSM0 Mode
When Reset ADE78xx is selected on the Front Panel, the
RESET pin of the ADE7878 is kept low for 20 ms and then is
set high. If the operation is correctly executed, the message
ADE7878 was reset successfully is displayed, and you must
click OK to continue. The only error that may occur during this
operation is communication related; if this happens, the
following message is displayed: The communication between
PC and ADE7878 evaluation board or between LPC2368 and
ADE78xx did not function correctly. There is no guarantee
the reset of ADE7878 has been performed.
When the evaluation board is powered up, the ADE7878 is in
PSM3 sleep mode. When Enter PSM0 mode is selected, the
microcontroller manipulates the PM0 and PM1 pins of the
ADE7878 to switch it into PSM0 mode. It waits 50 ms for the
circuit to power up and, if SPI communication is activated on
the board, it executes three SPI write operations to Address
0xEBFF of the ADE7878 to activate the SPI port.
If the operation has been correctly executed or I2C communication is used, the message Configuring LPC2368 – ADE7878
communication was successful is displayed, and you must click
OK to continue. The only error that may occur during this
operation is communication related; if this happens, the
following message is displayed: Configuring LPC2368 –
ADE7878 communication was not successful. Please check
the communication between the PC and ADE7878 evaluation
board and between LPC2368 and ADE78xx.
Bit 1 (I2C_LOCK) of the CONFIG2[7:0] register is now set to 1
to lock in the serial port choice. Then the DICOEFF register is
initialized with 0xFF8000, and the DSP of the ADE7878 is
started when the software program writes RUN = 0x1. At the
end of this process, the entire main menu is grayed out, and the
submenu is enabled. You can now manage all functionality of
the ADE7878 in PSM0 mode. To switch the ADE7878 to another
power mode, click the Exit button on the submenu. The state of
the Front Panel is shown in Figure 9.
Configure Communication
When Configure Communication is selected on the Front
Panel, the panel shown in Figure 10 is opened. This panel is
useful if an ADE7878 reset has been performed and the SPI is
no longer the active serial port. Select the SPI port by clicking
the I2C/SPI Selector button and then click OK to update the
selection and lock the port. If the port selection is successful,
the message, Configuring LPC2368 – ADE7878 communication was successful, is displayed, and you must click OK to
continue. If a communication error occurs, the message,
Configuring LPC2368 – ADE7878 communication was not
successful. Please check the communication between the PC
and ADE7878 evaluation board, is displayed.
Rev. 0 | Page 9 of 36
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Evaluation Board User Guide
current data path is written into the ADE7878. All the other
instances take this value directly.
1.
09078-010
2.
3.
Figure 10. Configure Communication Panel
The CONFIG2[7:0] register is written with Bit 1 (I2C_LOCK) set
to 1 so that you do not need to remember to set it once the
communication is set. The contents of CONFIG2[7:0] are then
read back and displayed with Bit 1 (I2C_LOCK).
Click the Read Configuration button to cause all registers
that manage the total active power to be read and
displayed. Registers from the inactive data paths are also
read and updated.
Click the Write Configuration button to cause all registers
that manage the total active power to be written into the
ADE7878. Registers from the inactive data paths are also
written. The ADE78xx status box shows the power mode
that the ADE7878 is in (it should always be PSM0 in this
window), the active serial port (it should always be SPI),
and the CHECKSUM[31:0] register. After every read and
write operation, the CHECKSUM[31:0] register is read and
its contents displayed.
Click the CFx Configuration button to open a new panel
(see Figure 12). This panel gives access to all bits and
registers that configure the CF1, CF2, and CF3 outputs of
the ADE7878. The Read Setup and Write Setup buttons
update and display the CF1, CF2, and CF3 output values.
To close the panel, click the Exit button; the cursor is positioned
at Please select from the following options in the submenu of
the Front Panel.
Total Active Power
09078-012
When Total Active Power is selected on the Front Panel, the
panel shown in Figure 11 is opened. The screen has an upper
half and a lower half: the lower half shows the total active power
data path of one phase, and the upper half shows bits, registers,
and commands necessary to power management.
09078-011
Figure 12. CFx Configuration Panel
Figure 11. Total Active Power Panel
The Active Data Path button manages which data path is
shown in the bottom half. Some registers or bits, like the
WTHR0[23:0] register or Bit 0 (INTEN) of the CONFIG[15:0]
register, are common to all data paths, independent of the phase
shown. When these registers are updated, all the values in all
data paths are updated. The HPFDIS[23:0] register is included
twice in the data path, but only the register value from the
Like the Total Active Power panel, the CHECKSUM[31:0]
register is read back whenever a read or write operation is
executed in the CFx Configuration panel. To select more
than one option for a TERMSELx bit in the COMPMODE
[15:0] register, press the CTRL key while clicking the options
you want.
Clicking the Exit button closes the panel and redisplays the
Total Active Power panel. When the Read Energy Registers
button in the Total Active Power panel is clicked, a new panel is
opened (see Figure 13). This panel gives access to bits and
registers that configure the energy accumulation. The Read
Setup and Write Setup buttons update and display the bit and
register values.
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09078-014
When clicked on the Front Panel, the Total Reactive Power,
Fundamental Active Power, and Fundamental Reactive
Power buttons open panels that are very similar to the Total
Active Power panel. These panels are shown in Figure 14,
Figure 15, and Figure 16.
09078-013
The CHECKSUM[31:0] register is read back whenever a read or
write operation is executed in the Read Energy Registers panel.
Clicking the Read all energy registers button causes all energy
registers to be read immediately, without regard to the modes in
which they function.
Figure 14. Total Reactive Power Panel
Figure 13. Read Energy Registers Panel
1.
2.
3.
4.
5.
The STATUS0[31:0] register is read and then written back
to so that all nonzero interrupt flag bits are cancelled.
Bit 14 (CF1) in the MASK0[31:0] register is set to 1, and
the interrupt protocol is started (see the Managing the
Communication Protocol Between the Microcontroller
and the ADE7878 section for protocol details).
The microcontroller then waits until the IRQ0 pin goes
low. If the wait is longer than the timeout you indicate in
3 sec increments, the following error message is displayed:
No CF1 pulse was generated. Verify all the settings
before attempting to read energy registers in this mode!
When the IRQ0 pin goes low, the STATUS0[31:0] register
is read and written back to cancel Bit 14 (CF1); then the
energy registers involved in the CF1 signal are read and
their contents are displayed. A timer in 10 ms increments
can be used to measure the reaction time after the IRQ0
pin goes low.
The operation is repeated until the button is clicked again.
09078-015
The panel also gives the choice of reading the energy registers
synchronous to CFx interrupts (pulses) or using line cycle
accumulation mode. When the Read energy registers
synchronous with CF1 pulses button is clicked, the following
happens:
Figure 15. Fundamental Active Power Panel
It is recommended to always use a timeout when dealing with
interrupts. By default, the timeout is set to 10 (indicating a
30 sec timeout), and the timer is set to 0 (indicating that the
STATUSx[31:0] and energy registers are read immediately after
the IRQ0 pin goes low).
Rev. 0 | Page 11 of 36
09078-016
The process is similar when the other CF2, CF3, and line accumulation (Read Energy Registers panel) buttons are clicked.
Figure 16. Fundamental Reactive Power Panel
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Evaluation Board User Guide
Apparent Power
When Apparent Power is selected on the Front Panel, a new
panel is opened (see Figure 17). Similar to the other panels that
deal with power measurement, this panel is divided into two
parts: the lower half shows the apparent power data path of one
phase and the ADE7878 status; the upper half shows the bits,
registers, and commands necessary to power management.
indicated by the timeout (in 3 sec increments), the following
message is displayed: No ZXIA, ZXIB or ZXIC interrupt was
generated. Verify at least one sinusoidal signal is provided
between IAP-IAN, IBP-IBN or ICP-ICN pins. A delay can be
introduced (in 10 ms increments) between the time the IRQ1 pin
goes low and the moment the xIRMS registers are read. The
operation is repeated until the button is clicked again.
Mean Absolute Value Current
09078-017
When Mean Absolute Value Current is selected on the Front
Panel, a new panel is opened (see Figure 19). When the Read
xIMAV registers button is clicked, the xIMAV[19:0] registers
are read 10 consecutive times, and their average is computed
and displayed. After this operation, the button is returned to
high automatically. The ADE7878 status is also displayed.
Figure 17. Apparent Power Panel
Current RMS
09078-019
When RMS Current is selected on the Front Panel, a new
panel is opened (see Figure 18). All data paths of all phases
are available.
Figure 19. Mean Absolute Value Current Panel
09078-018
Voltage RMS
Figure 18. Current RMS panel
Clicking the Read Setup button causes a read of all registers
shown in the panel. Clicking the Write Setup button causes
writes to the xIRMSOS[23:0] registers.
You can use the Start Digital Signal Processor and Stop
Digital Signal Processor buttons to manage the Run[15:0]
register and the Read xIRMS registers button, which uses the
ZXIA, ZXIB, and ZXIC interrupts at the IRQ1 pin, to read the
xIRMS[23:0]registers 500 consecutive times and then compute
and display their average. If no interrupt occurs for the time
When RMS Voltage is selected on the Front Panel, the Voltage
RMS panel is opened (see Figure 20). This panel is very similar
to the Current RMS panel. Clicking the Read Setup button
executes a read of the xVRMSOS[23:0] and xVRMS[23:0]
registers.
Clicking Write Setup writes the xVRMSOS[23:0] registers into
the ADE7878. The Start Digital Signal Processor and Stop
Digital Signal Processor buttons manage the Run[15:0]
register.
When the Read xVRMS registers button is clicked, the
xVRMS[23:0] registers are read 500 consecutive times and the
average is displayed. The operation is repeated until the button
is clicked again. Note that the ZXVA, ZXVB, and ZXVC zerocrossing interrupts are not used in this case because they are
disabled when the voltages go below 10% of full scale. This
allows rms voltage registers to be read even when the phase
voltages are very low.
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Evaluation Board User Guide
Figure 20. Voltage RMS Panel
Figure 21. Power Quality Zero-Crossing Measurements Panel
Power Quality
The Power Quality panel is accessible from the Front Panel
and is divided into two parts (see Figure 21). The lower part
displays registers that manage the power quality measurement
functions for the Active Measurement button in the upper part
of the panel. The upper part also displays the ADE7878 status
and the buttons that manage the measurements.
When the READ CONFIGURATION button is clicked, all
power quality registers (MASK1[31:0], STATUS1[31:0],
PERIOD[15:0], MMODE[7:0], ISUM[27:0], OVLVL[23:0],
OILVL[23:0], PHSTATUS[15:0], IPEAK[31:0], VPEAK[31:0],
SAGLVL[23:0], SAGCYC[7:0], ANGLE0[15:0], ANGLE1[15:0],
ANGLE2[15:0], COMPMODE[15:0], CHECKSUM[31:0], and
PEAKCYC[7:0]) are read, and the ones belonging to the active
panel are displayed. Based on the PERIOD[15:0] register, the
line frequency is computed and displayed in the lower part of
the panel, in Zero Crossing Measurements. Based on the
ANGLEx[15:0] registers, cos(ANGLEx) is computed and
displayed in the Time Intervals Between Phases panel that is
accessible from the Active Measurement Zero Crossing
dropdown box (see Figure 21).
When the WRITE CONFIGURATION button is clicked,
MMODE[7:0], OVLVL[23:0], OILVL[23:0], SAGLVL[23:0],
SAGCYC[7:0], COMPMODE[15:0], and PEAKCYC[7:0] are
written into the ADE7878, and CHECKSUM[31:0] is read back
and displayed in the CHECKSUM[31:0] box at the top of the
upper part of the panel.
When the WAIT FOR INTERRUPTS button is clicked, the
interrupts that you have enabled in the MASK1[31:0] register
are monitored. When the IRQ1 pin goes low, the STATUS1[31:0]
register is read and its bits are displayed. The ISUM[27:0],
PHSTATUS[15:0], IPEAK[31:0], VPEAK[31:0], ANGLE0[15:0],
ANGLE1[15:0], and ANGLE2[15:0] registers are also read and
displayed. A timeout should be introduced in 3 sec increments
to ensure that the program does not wait indefinitely for
interrupts. A timer (in 10 ms increments) is provided to allow
reading of the registers with a delay from the moment the
interrupt is triggered.
The Active Measurement Zero Crossing button gives access to
the Zero Crossing, Neutral Current Mismatch, Overvoltage
and Overcurrent Measurement, Peak Detection, and Time
Intervals Between Phases panels (see Figure 21 through
Figure 25).
The line frequency is computed using the PERIOD[15:0] register,
based on the following formula:
f =
256,000
[ Hz ]
Period
The cosine of the ANGLE0[15:0], ANGLE1[15:0], and
ANGLE2[15:0] measurements is computed using the following
formula:
Rev. 0 | Page 13 of 36
ANGLEx × 360 × f
cos( ANGLEx) = cos
256,000
Evaluation Board User Guide
09078-022
09078-025
UG-146
Figure 25. Time Intervals Between Phases Panel
Figure 22. Neutral Current Mismatch Panel
Waveform Sampling
09078-023
The Waveform Sampling panel (see Figure 26) is accessible
from the Front Panel and uses the HSDC port to acquire data
from the ADE7878 and display it. It can be accessed only if the
communication between the ADE7878 and the NXP LPC2368
is through the I2C. See the Activating Serial Communication
Between the ADE7878 and the NXP LPC2368 section for
details on how to set I2C communication on the ADE7878
evaluation board.
Figure 24. Peak Detection Panel
Rev. 0 | Page 14 of 36
09078-026
09078-024
Figure 23. Overvoltage and Overcurrent Measurements Panel
Figure 26. Waveform Sampling Panel
Evaluation Board User Guide
UG-146
•
•
•
One switch chooses the quantities that are displayed: phase
currents and voltages or phase powers. For every set of
quantities, only one can be acquired at a time. This choice
is made using the Select Waveform button.
A second switch allows acquired data to be stored in files
for further use. This switch is set with the ACQUIRE
DATA button.
The acquisition time should also be set before an acquisition is ordered. By default, this time is 150 ms. It is
unlimited for phase currents and voltages and for phase
powers. The NXP LPC2368 executes in real time three
tasks using the ping pong buffer method: continuously
receiving data from HSDC, storing the data into its USB
memory, and sending the data to the PC. Transmitting
seven phase currents and voltages at 4 MHz takes 103.25 µs
(which is less than 125 µs); therefore, the HSDC update
rate is 8 kHz (HSDC_CFG = 0x0F). Transmitting nine phase
powers takes 72 µs (again, less than 125 µs); therefore, the
HSDC update rate is also 8 kHz (HSDC_CGF = 0x11).
To start the acquisition, click the ACQUIRE DATA button. The
data is displayed on one plot. If you click the Write waveforms
to file?/No writing to files switch to enable the writing of
waveforms to a file, the program asks for the name and location
of the files before storing the waveform.
Checksum Register
Figure 27. Checksum Register Panel
All Registers Access
The All Registers Access panel is accessible from the Front
Panel and gives read/write access to all ADE7878 registers.
Because there are many, the panel can scroll up and down and
has multiple read, write, and exit buttons (see Figure 28 and
Figure 29). The registers are listed in columns in alphabetical
order, starting at the upper left. The panel also allows you to
save all control registers into a data file by clicking the Save All
Regs into a file button. By clicking the Load All Regs from a
file button, you can load all control registers from a data file.
Then, by clicking the Write All Regs button, you can load these
values into the ADE7878. The order in which the registers are
stored into a file is shown in the Control Registers Data File
section.
09078-028
The Checksum Register panel is accessible from the Front
Panel and gives access to all ADE7878 registers that are used to
compute the CHECKSUM[31:0] register (see Figure 27). You
can read/write the values of these registers by clicking the Read
and Write buttons. The LabView program estimates the value of
the CHECKSUM[31:0] register and displays it whenever one of
the registers is changed. When the Read button is pressed, the
registers are read and the CHECKSUM[31:0] register is read
and its values displayed. This allows you to compare the value of
the CHECKSUM[31:0] register estimated by LabView with the
value read from the ADE7878. The values should always be
identical.
09078-027
The HSDC transmits data to the NXP LPC2368 at 4 MHz
because this is the maximum speed at which the slave SPI of the
NXP LPC2368 can receive data. The panel contains some
switches that must be set before acquiring data.
Figure 28. Panel Giving Access to All ADE7878 Registers (1)
Rev. 0 | Page 15 of 36
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Evaluation Board User Guide
Clicking the Begin Computations button starts the program
that reads rms voltages and currents and calculates the full-scale
voltage and currents used to further initialize the meter. This
process takes 7 sec as the program reads the rms voltages 100
times and the rms currents 100 times and then averages them
(this is because the PC reads the rms values directly and cannot
synchronize the readings with the zero crossings).
The program then computes the full-scale voltages and currents
and the constants that are important for setting up the
ADE7878: nominal values (n), CFDEN, WTHR1, VARTHR1,
VATHR1 and WTHR0, VARTHR0, and VATHR0.
09078-029
At this point, you can overwrite these values. You can also click
the Update Registers button to cause the program to do the
following:
Figure 29. Panel Giving Access to All ADE7878 Registers (2)
•
•
Quick Startup
The Quick Startup panel is accessible from the Front Panel
and can be used to rapidly initialize a 3-phase meter (see
Figure 30).
Initialize the CFxDEN and xTHR registers
Enable the CF1 pin to provide a signal proportional to the
total active power, the CF2 pin to provide a signal
proportional to the total reactive power, and the CF3 pin to
provide a signal proportional to the apparent power.
Throughout the program, it is assumed that PGA gains are 1
(for simplicity) and that the Rogowski coil integrators are
disabled. You can enter and modify the PGAs and enable the
integrators before executing this quick startup if necessary.
At this point, the evaluation board is set up as a 3-phase meter,
and calibration can be executed. To store the register initializations, click the Save All Regs into a file button in the All
Registers Access panel. After the board is powered down and
then powered up again, the registers can be loaded into the
ADE7878 by simply loading back the content of the data file. To
do this, click the Load All Regs from a file button in the All
Registers Access panel.
PSM2 Settings
09078-030
The PSM2 Settings panel, which is accessible from the Front
Panel, gives access to the LPOILVL[7:0] register that is used to
access PSM2 low power mode (see Figure 31). You can
manipulate its LPOIL[2:0] and LPLINE[4:0] bits. The value
shown in the LPOILVL[7:0] register is composed from these
bits and then displayed. Note that you cannot write a value into
the register by writing a value in the LPOILVL[7:0] register box.
Figure 30. Panel Used to Quickly Set Up the 3-Phase Meter
The meter constant (MC, in impulses/kWh), the nominal
voltage (Un, in V rms units), the nominal current (In, in A rms
units), and the nominal line frequency (fn, in either 50 Hz or
60 Hz) must be introduced in the panel controls. Then phase
voltages and phase currents must be provided through the
relative sensors.
Rev. 0 | Page 16 of 36
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09078-033
09078-031
Evaluation Board User Guide
Figure 31. PSM2 Settings Panel
Figure 33. Mean Absolute Value Currents Panel in PSM1 Mode
PSM1 MODE
Enter PSM1 Mode
PSM2 MODE
When Enter PSM1 mode is selected on the Front Panel, the
microcontroller manipulates the PM0 and PM1 pins of the
ADE7878 to switch the ADE7878 into PSM1 reduced power
mode. Then, the submenu allows access only to the Mean
Absolute Value Current function because this is the only
ADE7878 functionality available in this reduced power mode
(see Figure 32).
Enter PSM2 Mode
Figure 32. Front Panel After the ADE7878 Enters PSM1 Mode
09078-034
09078-032
When Enter PSM2 mode is selected on the Front Panel, the
microcontroller manipulates the PM0 and PM1 pins of the
ADE7878 to switch the ADE7878 into PSM2 low power mode.
Then the submenu allows access only to the Phase Current
Monitoring function because this is the only ADE7878
functionality available in this low power mode.
Figure 34. Front Panel After the ADE7878 Enters PSM2 Mode
Mean Absolute Value Current in PSM1 Mode
The Mean Absolute Value Current panel, which is accessible
from the Front Panel when Enter PSM1 mode is selected, is
very similar to the panel accessible in PSM0 mode (see the
Mean Absolute Value Current section for details). The only
difference is that ADE7878 status does not show the
CHECKSUM[31:0] register because it is not available in
PSM1 mode (see Figure 33)
Rev. 0 | Page 17 of 36
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Evaluation Board User Guide
Phase Current Monitoring
The Phase Current Monitoring panel is accessible from the
Front Panel when Enter PSM2 mode is selected; it allows you
to display the state of the IRQ0and IRQ1 pins because, in PSM2
low power mode, the ADE7878 compares the phase currents
against a threshold determined by the LPOILVL[7:0] register
(see Figure 35). Clicking the READ STATUS OF IRQ0 AND
IRQ1 PINS button reads the status of these pins and displays
and interprets the status.
09078-035
This operation is managed by the LPOILVL[7:0] register and
can be modified only in PSM0 mode. The panel offers this
option by switching the ADE7878 into PSM0 mode and then
back to PSM2 mode when one of the READ LPOILVL/WRITE
LPOILVL buttons is clicked. To avoid toggling both the PM0
and PM1 pins at the same time during this switch, the
ADE7878 is set to PSM3 when changing modes.
Figure 35. Panel Managing Current Monitoring in PSM2 Mode
PSM3 MODE
Enter PSM3 Mode
In PSM3 sleep mode, most of the internal circuits of the
ADE7878 are turned off. Therefore, no submenu is activated
while in this mode. You can click the Enter PSM0 mode, Enter
PSM1 mode, or Enter PSM2 mode button to set the ADE7878
to one of these power modes.
Rev. 0 | Page 18 of 36
Evaluation Board User Guide
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MANAGING THE COMMUNICATION PROTOCOL BETWEEN THE MICROCONTROLLER AND
THE ADE7878
In this section, the protocol commands are listed that have been
implemented to manage the ADE7878 from the PC using the
microcontroller.
The microcontroller is a pure slave during the communication
process. It receives a command from the PC, executes the
command, and sends an answer to the PC. The PC should wait
for the answer before sending a new command to the microcontroller.
Table 3. Echo Command—Message from the PC to the Microcontroller
Byte
0
1
2
3
4
…
N
N+1
Description
A = 0x41
N = number of bytes transmitted after this byte
Data Byte N − 1 (MSB)
Data Byte N − 2
Data Byte N − 3
…
Data Byte 1
Data Byte 0 (LSB)
Description
R = 0x52
A = 0x41
N = number of bytes transmitted after this byte
Data byte N − 1 (MSB)
Data byte N − 2
…
Data Byte 1
Data Byte 0 (LB)
Table 5. Power Mode Select—Message from the PC to the
Microcontroller
Byte
0
1
2
Description
B = 0x42, change PSM mode
N=1
Data Byte 0:
0x00 = PSM0
0x01 = PSM1
0x02 = PSM2
0x03 = PSM3
Byte
0
1
2
Description
C = 0x43, toggle the RESET pin and keep it low for at
least 10 ms
N=1
Data Byte 0: this byte can have any value
Table 8. Reset—Answer from the Microcontroller to the PC
Byte
0
1
Description
R = 0x52
~ = 0x7E, to acknowledge that the operation was
successful
Table 9. I2C/SPI Select (Configure Communication)—
Message from the PC to the Microcontroller
Byte
0
Table 4. Echo Command—Answer from the Microcontroller to
the PC
Byte
0
1
2
3
4
…
N+1
N+2
Table 7. Reset—Message from the PC to the Microcontroller
1
2
Description
D = 0x44, select I2C and SPI and initialize them; then set
CONFIG2[7:0] = 0x2 to lock in the port choice. When I2C
is selected, also enable SSP0 of the LPC2368 (used for
HSDC).
N = 1.
Data Byte 0: 0x00 = I2C, 0x01 = SPI.
Table 10. I2C/SPI Select (Configure Communication)—
Answer from the Microcontroller to the PC
Byte
0
1
Description
R = 0x52
~ = 0x7E, to acknowledge that the operation was
successful
Table 11. Data Write—Message from the PC to the Microcontroller
Byte
0
1
2
3
4
5
6
…
N+2
N+3
Description
E = 0x45.
N = number of bytes transmitted after this byte. N can
be 1 + 2, 2 + 2, 4 + 2, or 6 + 2.
MSB of the address.
LSB of the address.
Data Byte N − 3 (MSN).
Data Byte N − 4.
Data Byte N − 5.
…
Data Byte 1.
Data Byte 0 (LSB).
Table 6. Power Mode Select—Answer from the Microcontroller to the PC
Table 12. Data Write—Answer from the Microcontroller to
the PC
Byte
0
1
Byte
0
1
Description
R = 0x52
~ = 0x7E, to acknowledge that the operation was
successful
Rev. 0 | Page 19 of 36
Description
R = 0x52
~ = 0x7E, to acknowledge that the operation was
successful
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Evaluation Board User Guide
Table 13. Data Read—Message from the PC to the Microcontroller
Table 16. Interrupt Setup—Message from the Microcontroller to the PC
Byte
0
1
2
3
4
Byte
0
1
Description
F = 0x46.
N = number of bytes transmitted after this byte; N = 3.
MSB of the address.
LSB of the address.
M = number of bytes to be read from the address above.
M can be 1, 2, 4, or 6.
Table 14. Data Read—Answer from the Microcontroller to
the PC
Byte
0
1
2
3
4
5
6
7
8
Description
R = 0x52.
MSB of the address.
LSB of the address.
Byte 5, Byte 3, Byte 1, or Byte 0 (MSB) read at the location
indicated by the address. The location may contain 6, 4,
2, or 1 byte. The content is transmitted MSB first.
Byte 4, Byte 2, or Byte 0.
Byte 3, Byte 1.
Byte 2, Byte 0.
Byte 1.
Byte 0.
2
3
4
The microcontroller executes the following operations once the
interrupt setup command is received:
1.
2.
3.
4.
Table 15. Interrupt Setup—Message from the PC to the
Microcontroller
Byte
0
1
2
3
4
5
6
7
8
9
Description
J = 0x4A.
N = 8, number of bytes transmitted after this byte.
MSB of the MASK1[31:0] or MASK0[31:0] register.
LSB of the MASK1[31:0] or MASK0[31:0] register.
Byte 3 of the desired value of the MASK0[31:0] or
MASK1[31:0] register.
Byte 2.
Byte 1.
Byte 0.
Time out byte: time the MCU must wait for the interrupt
to be triggered. It is measured in 3 sec increments.
Time out byte (TOB) = 0 means that timeout is disabled.
IRQ timer: time the MCU leaves the IRQx pin low before
writing back to clear the interrupt flag. It is measured in
10 ms increments.
Timer = 0 means that timeout is disabled.
Description
R = 0x52.
Byte 3 of the STATUS0[31:0] or STATUS1[31:0] register.
If the program waited for TOB × 3 sec and the interrupt
was not triggered, then Byte 3 = Byte 2 = Byte 1 = Byte 0
= 0xFF.
Byte 2 of the STATUS0[31:0] or STATUS1[31:0] register.
Byte 1 of the STATUS0[31:0] or STATUS1[31:0] register.
Byte 0 of the STATUS0[31:0] or STATUS1[31:0] register.
5.
Reads the STATUS0[31:0] or STATUS1[31:0] register
(depending on the address received from the PC) and, if it
shows an interrupt already triggered (one of its bits is equal
to 1), it erases the interrupt by writing it back.
Writes to the MASK0[31:0] or MASK1[31:0] register with
the value received from the PC.
Waits for the interrupt to be triggered. If the wait is more
than the timeout specified in the command, 0xFFFFFFFF
is sent back.
If the interrupt is triggered, the STATUS0[31:0] or
STATUS1[31:0] register is read and then written back to
clear it. The value read at this point is the value sent back
to the PC so that you can see the source of the interrupts.
Sends back the answer.
Table 17. Interrupt Pins Status—Message from the PC to the
Microcontroller
Byte
0
1
2
Description
H = 0x48.
N = 1, number of bytes transmitted after this byte.
Any byte. This value is not used by the program but it is
used in the communication because N must not be equal
to 0.
Table 18. Interrupt Pins Status—Answer from the Microcontroller to the PC
Byte
0
1
Rev. 0 | Page 20 of 36
Description
R = 0x52.
A number representing the status of the IRQ0 and IRQ1
pins.
0: IRQ0 = low, IRQ1 = low
1: IRQ0 = low, IRQ1 = high.
2: IRQ0 = high, IRQ1 = low.
3: IRQ0 = high, IRQ1 = high.
The reason for the IRQ0 and IRQ1 order is that on the
microcontroller IO port, IRQ0= P0.1 and IRQ1 = P0.0.
Evaluation Board User Guide
UG-146
ACQUIRING HSDC DATA CONTINUOUSLY
This function acquires data from the HSDC continuously for a
defined time period and for up to two variables. The microcontroller sends data in packages of 4 kB.
Table 19 describes the protocol when two instantaneous phase
currents or voltages are acquired.
Table 19. Acquire HSDC Data Continuously—Message from
the PC to the Microcontroller If Phase Currents and Voltages
Are Acquired
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Description
G = 0x47.
N = number of bytes transmitted after this byte. N = 32.
0: corresponds to Byte 3 of IA. Because this byte is only a
sign extension of Byte 2, it is not sent back by the
microcontroller.
Increment_IA_Byte2. If IA is to be acquired, Byte 3, Byte 4,
and Byte 5 are 1. Otherwise, they are 0.
Increment_IA_Byte1.
Increment_IA_Byte2.
0.
Increment_VA_Byte2. If VA is to be acquired, Byte 7,
Byte 8, and Byte 9 are 1. Otherwise, they are 0.
Increment_VA_Byte1.
Increment_VA_Byte0.
0.
Increment_IB_Byte2. If IB is to be acquired, Byte 11,
Byte 12, and Byte 13 are 1. Otherwise, they are 0.
Increment_IB_Byte1.
Increment_IB_Byte0.
0.
Increment_VB_Byte2. If VB is to be acquired, Byte 15,
Byte 16, and Byte 17 are 1. Otherwise, they are 0.
Increment_VB_Byte1.
Increment_VB_Byte0.
0.
Increment_IC_Byte2. If IC is to be acquired, Byte 19,
Byte 20, and Byte 21 are 1. Otherwise, they are 0.
Increment_IC_Byte1.
Increment_IC_Byte0.
0.
Increment_VC_Byte2. If VC is to be acquired, Byte 23,
Byte 24, and Byte 25 are 1. Otherwise, they are 0.
Increment_VC_Byte1.
Increment_VC_Byte0.
0.
Increment_IN_Byte2. If IN is to be acquired, Byte 27,
Byte 28, and Byte 29 are 1. Otherwise, they are 0.
Increment_IN_Byte1.
Increment_IN_Byte0.
Byte 1 of M. M is a 16-bit number. The number of 32-bit
samples acquired by the microcontroller is (2 × M + 1) ×
67 per channel.
Byte 0 of M.
If two of the phase powers are to be acquired, the protocol
changes (see Table 20).
Table 20. Acquire HSDC Data Continuously—Message from
the PC to the Microcontroller If Phase Powers Are Acquired
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Rev. 0 | Page 21 of 36
Description
G = 0x47
N = number of bytes transmitted after this byte. N = 38.
0: corresponds to Byte 3 of AVA. Because this byte is only
a sign extension of Byte 2, it is not sent back by the
microcontroller.
Increment_AVA_Byte2. If AVA is to be acquired, Byte 3,
Byte 4, and Byte 5 are 1. Otherwise, they are 0.
Increment_AVA_Byte1.
Increment_AVA_Byte2.
0.
Increment_BVA_Byte2. If BVA is to be acquired, Byte 7,
Byte 8, and Byte 9 are 1. Otherwise, they are 0.
Increment_BVA_Byte1.
Increment_BVA_Byte0.
0.
Increment_CVA_Byte2. If CVA is to be acquired, Byte 11,
Byte 12, and Byte 13 are 1. Otherwise, they are 0.
Increment_CVA_Byte1.
Increment_CVA_Byte0.
0.
Increment_AWATT_Byte2. If AWATT is to be acquired,
Byte 15, Byte 16, and Byte 17 are 1. Otherwise, they are 0.
Increment_AWATT_Byte1.
Increment_AWATT_Byte0.
0.
Increment_BWATT_Byte2. If BWATT is to be acquired,
then Byte 19, Byte 20, and Byte 21 are 1. Otherwise, they
are 0.
Increment_BWATT_Byte1.
Increment_BWATT_Byte0.
0.
Increment_CWATT_Byte2. If CWATT is to be acquired,
Byte 23, Byte 24, and Byte 25 are 1. Otherwise, they are 0.
Increment_CWATT_Byte1.
Increment_CWATT_Byte0.
0.
Increment_AVAR_Byte2. If AVAR is to be acquired,
Byte 27, Byte 28, and Byte 29 are 1. Otherwise, they are 0.
Increment_AVAR_Byte1.
Increment_AVAR_Byte0.
0.
Increment_BVAR_Byte2. If BVAR is to be acquired, then
Byte 31, Byte 32, and Byte 33 are 1. Otherwise, they are 0.
Increment_BVAR_Byte1.
Increment_BVAR_Byte0.
0.
Increment_CVAR_Byte2. If CVAR is to be acquired,
Byte 35, Byte 36, and Byte 37 are 1. Otherwise, they are 0.
UG-146
Byte
36
37
38
39
Evaluation Board User Guide
Description
Increment_CVAR_Byte1.
Increment_CVAR_Byte0.
Byte 1 of M. M is a 16-bit number. The number of 32-bit
samples acquired by the microcontroller is (2 × M + 1) ×
67 per channel.
Byte 0 of M.
After receiving the command, the microcontroller enables the
HSDC port and acquires 67 × 7 × 4 = 1876 bytes into
BUFFER0. As soon as BUFFER0 is filled, data is acquired in
BUFFER1 (equal in size to BUFFER0), while 2 × 3 × 67 = 402
bytes (134 24-bit words) from BUFFER0 are transmitted to the
PC. As soon as BUFFER1 is filled, data is acquired into
BUFFER0 while 402 bytes from BUFFER1 are transmitted to
the PC. Only the less significant 24 bits of every 32-bit
instantaneous value are sent to the PC to decrease the size of the
buffer sent to the PC. The most significant eight bits are only an
extension of a 24-bit signed word; therefore, no information is
lost. The protocol used by the microcontroller to send data to
the PC is shown in Table 21.
Table 21. Acquire HSDC Data Continuously—Answer from
the Microcontroller to the PC
Byte
0
1
2
3
4
5
…
402
Description
R = 0x52
Byte 2 (MSB) of Word 1
Byte 1 of Word 1
Byte 0 (LSB) of Word 1
Byte 2 (MSB) of Word 2
Byte 1 (MSB) of Word 2
…
Byte 0 (LSB) of Word 134
STARTING THE ADE7878 DSP
This function orders the microcontroller to start the DSP. The
microcontroller writes to the run register with 0x1.
Table 22. Start ADE7878 DSP—Message from the PC to the
Microcontroller
Byte
0
1
2
Description
N = 0x4E
N = number of bytes transmitted after this byte; N = 1
Any byte
Table 23. Start ADE7878 DSP—Answer from the Microcontroller to the PC
Byte
0
1
Description
R = 0x52
~ = 0x7E, to acknowledge that the operation was
successful
STOPPING THE ADE7878 DSP
This function orders the microcontroller to stop the DSP. The
microcontroller writes to the run register with 0x0.
Table 24. Stop ADE7878 DSP—Message from the PC to the
Microcontroller
Byte
0
1
2
Description
O = 0x4F
N = number of bytes transmitted after this byte; N = 1
Any byte
Table 25. Stop ADE7878 DSP—Answer from the Microcontroller to the PC
Byte
0
1
Rev. 0 | Page 22 of 36
Description
R = 0x52
~ = 0x7E to acknowledge that the operation was
successful
Evaluation Board User Guide
UG-146
UPGRADING MICROCONTROLLER FIRMWARE
Although the evaluation board is supplied with the
microcontroller firmware already installed, the ADE7878
evaluation software CD provides the NXP LPC2368
microcontroller project developed under the IAR embedded
workbench environment for ARM. Users in possession of this
tool can modify the project at will and can download it using an
IAR J-link debugger. As an alternative, the executable can be
downloaded using a program called Flash Magic, available on
the evaluation software CD or at the following website:
http://www.flashmagictool.com/.
1.
2.
3.
4.
5.
6.
7.
Plug a serial cable into connector P15 of the ADE7878
evaluation board and into a PC COM port. As an
alternative, use the ADE8052Z-DWDL1 ADE downloader
from Analog Devices, Inc., together with a USB cable.
Launch the Device Manager under Windows XP by
writing devmgmt.msc into the Start/Run box. This helps
to identify which COM port is used by the serial cable.
Plug the USB2UART board into the P15 connector of the
ADE7878 evaluation board with the VDD pin of the
USB2UART aligned at Pin 1 of P15.
Connect Jumper JP8. The P2.10/EINT0 pin of the
microcontroller is now connected to ground.
Supply the board with two 3.3 V supplies at the P10 and
P12 connectors.
Press and release the reset button, S2, on the ADE7878
evaluation board.
Launch Flash Magic and do the following:
a. Select a COM port (COMx as seen in the Device
Manager).
b. Set the baud rate to 115,200.
c. Select the NXP LPC2368 device.
d. Set the interface to none (ISP).
e. Set the DOscillator frequency (MHz) to 12.0.
f. Select Erase all Flash + Code Rd Block.
g. Choose ADE7878_Eval_Board.hex from the
\Debug\Exe project folder.
h. Select Verify after programming.
09078-036
Flash Magic uses the PC COM port to download the microcontroller firmware. The procedure for using Flash Magic is as
follows:
Figure 36. Flash Magic Settings
8. Click Start to begin the download process.
9. After the process finishes, extract the JP8 jumper.
10. Reset the ADE7878 evaluation board by pressing and
releasing the S2 reset button.
At this point, the program should be functional, and a USB
cable can be connected to the board. When the PC recognizes
the evaluation board and asks for a driver, point it to the project
\VirCOM_Driver_XP folder. The ADE7878_eval_board_
vircomport.inf file is the driver.
CONTROL REGISTERS DATA FILE
Table 26 shows the order in which the control registers of the
ADE7878 are stored into a data file when you click the Save All
Regs into a file button in the All Registers Access panel.
The Flash Magic settings are shown in Figure 36.
Rev. 0 | Page 23 of 36
UG-146
Evaluation Board User Guide
Table 26. Control Register Data File Content
Line Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Register
AIGAIN
AVGAIN
BIGAIN
BVGAIN
CIGAIN
CVGAIN
NIGAIN
AIRMSOS
AVRMSOS
BIRMSOS
BVRMSOS
CIRMSOS
CVRMSOS
NIRMSOS
AVAGAIN
BVAGAIN
CVAGAIN
AWGAIN
AWATTOS
BWGAIN
BWATTOS
CWGAIN
CWATTOS
AVARGAIN
AVAROS
BVARGAIN
BVAROS
CVARGAIN
CVAROS
AFWGAIN
AFWATTOS
BFWGAIN
BFWATTOS
CFWGAIN
CFWATTOS
AFVARGAIN
AFVAROS
BFVARGAIN
BFVAROS
CFVARGAIN
CFVAROS
Line Number
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Rev. 0 | Page 24 of 36
Register
VATHR1
VATHR0
WTHR1
WTHR0
VARTHR1
VARTHR0
VANOLOAD
APNOLOAD
VARNOLOAD
VLEVEL
DICOEFF
HPFDIS
ISUMLVL
RUN
OILVL
OVLVL
SAGLVL
MASK0
MASK1
VNOM
LINECYC
ZXTOUT
COMPMODE
Gain
CFMODE
CF1DEN
CF2DEN
CF3DEN
APHCAL
BPHCAL
CPHCAL
CONFIG
MMODE
ACCMODE
LCYCMODE
PEAKCYC
SAGCYC
CFCYC
HSDC_CFG
LPOILVL
CONFIG2
WEILAND25.161.0253
1
2
P5
AGND
VN_IN
1
2
1500 OHMS
E8N
C44
1
2
JP8N
JP7N
1
1
B3S1000
S1
3
4
1
2
VDD_F
2
1
TP9
BLK
AGND
V+ VO
V3
1
VN
C42
JP1
2
VDD_F
JPR0402
1
1
1
DGND_D
TP25
BLK
1
PAD_CN
1
TP26
BLK
TP13
BLK
2
BERG69157-102
TP23
BLK
DGND
0
3PIN_SOLDER_JUMPER
1
A
2
COM
3
B
JP12
1
JP10
2
REF
BERG69157-102
XREF
1
1
TP34
1
BLK
1
TP36
1
BLK
TP35
1
BLK
DGND
TP38
BLK
TP37
1
BLK
EXTRA GROUND TP FOR PROBING
TP49
BLK
TP29
BLK
AGND
TP39
BLK
1
JP6
DGND
PM0
PM1
RESETB
IAP
IAN
IBP
IBN
ICP
ICN
INP
INN
VN
VCP
VBP
VAP
CLKIN
SCLK/SCL
MOSI/SDA
TP22
BLK
VDD2
R37
2
VDD
AGND
C3
1
JP4
JPR0402
U1
DGND_D
2
1
AGND
JPR0402
JP3
1
2
JP5
JPR0402
CLKOUT
BLK
CLKIN
AGND
5 4 3 2
1
JP11
AMP227699-2
3PIN_SOLDER_JUMPER
20PF
1
A
2
COM
3
B
EXT_CLKIN
BLK
TP14
CLKIN 1
C27
C26
20PF
1
TP15
XTAL CKT
R36
10K
AVDD
TP51
BLK
VDD
AGND
1
R35
10K
AGND
TP32
BLK
2
C6
NOTE:
MOUNT JP? DIRECTLY BELOW
PAD METAL. CONNECT TO PAD
WITH MULTIPLE VIAS.
REPEAT VIA GRID TO AGND PLANE
1
1
C5
REF
CLKOUT
IRQ0B
IRQ1B
CF1
CF2
CF3/HSCLK
MISO/HSD
SSB/HSA
DVDD
TP50
BLK
PAD_CN
ADE7858CPZ
PM0
PM1
RESET_N
17
REFIN_OUT
IAP
28
CLKOUT
IAN
29
IRQ0_N_SBSCL
IBP
32
IRQ1_N_SBSDA
IBN
33
CF1
ICP
34
CF2
ICN
35
CF3_HSCLK
INP
37
MISO_HSD
INN
39
SS_N_HSA
VN
VCP
VBP
VAP
CLKIN
SCLK_SCL
MOSI_SDA
JPR0402
2
3
4
7
8
9
12
13
14
15
16
18
19
22
23
27
36
38
10UF
P9
1
2
1
R38
AGND
WEILAND25.161.0253
0.1UF
P
N
RSB 1
C40
A1
ADR280ARTZ
AGND
1K
R25
BERG69157-102
2
10UF
1.0UF
REFERENCE DECOUPLING AND EXTERNAL REF
AGND
0.1UF
22NF
P
N
10K
C38
1 2
C1
0.1UF
P
N
2
C2
4.7UF
4.7UF
VDD_F
C41
0.1UF
PAD
PAD
25
AGND
6
DGND
CF1
R68
10K
1
C7
1
TP33
BLK
TP30
BLK
G
VDD2
3
2
1
CF1
P
D
S
1
R70
10K
G
3
IRQ0B
1
2
1
D
S
1
G
Q4
3
2
D
S
TP24
BLK
CF2
1
TP27
BLK
DGND
DGND
IRQ1B
R84
10K
VDD2
DGND
Q2
R85
10K
G
3
2
IRQ1B
1
D
S
CF3/HSCLK
CF1
IRQ1B
IRQ0B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P11
Q5
DGND
1
CF3
G
DGND
3
2
D
S
SAMTSW-1-30-08-GD
CF3/HSCLK
SCLK/SCL
MISO/HSD
MOSI/SDA
SSB/HSA
PM0
PM1
RESETB
CF2
CLKOUT
EXT_CLKIN
OUTPUT LED CIRCUIT
IRQ0B
R69
10K
DGND
P10
TP28
BLK
VDD2
CF2
VDD2
1
TP31
BLK
10UF
Q1
DGND
N
JP2
16.384MHZ
P
N
P
N
AVDD
DVDD
VDD
4.7UF
AVDD 24
5
DVDD
26
VDD
C4
Y1
0.22UF
BY DEFAULT SELECT OPTION A TO COMPLETE PARALLEL
RESONANT CIRCUIT. THIS OPTION SHOULD BE PLACED AS
CLOSE TO DEVICE AS POSSIBLE.
FDV302P
C
A
499
CMD28-21VGCTR8T1
FDV302P
WEILAND25.161.0253
FDV302P
0.22UF
2
1
VDD_F
BERG69157-102
AGND
AGND
C43
C25
FDV302P
0.1UF
C8
R39
CR1
R40
CR2
C
A
499
CMD28-21VGCTR8T1
C
A
499
CMD28-21VGCTR8T1
Q3
FDV302P
1
2
R42
CR4
R43
CR5
R41
CR3
Rev. 0 | Page 25 of 36
C
A
499
CMD28-21VGCTR8T1
Figure 37.
DEVICE INTERFACE HEADER
DGND
C
A
499
CMD28-21VGCTR8T1
VDD_F
Evaluation Board User Guide
UG-146
EVALUATION BOARD SCHEMATICS AND LAYOUT
SCHEMATIC
09078-037
WEILAND25.161.0253
P2
1
2
WEILAND25.161.0253
IBP_IN
IBN_IN
2
1
E2A
2
2
E2B
2
1500 OHMS
1
1500 OHMS
1
E1B
1500 OHMS
IAN_IN
BERG69157-102
BERG69157-102
P1
1
2
1
1500 OHMS
BERG69157-102
BERG69157-102
IAP_IN
E1A
R1
R2
TBD1206
R3
R4
TBD1206
TBD1206
TBD1206
JP3A
2
2
JP3B
2
2
BERG69157-102
1
100
JP4B
R12
AGND
100
R11
BERG69157-102
1
BERG69157-102
1
100
JP4A
R10
AGND
100
R9
BERG69157-102
1
C9
C10
C11
22NF
C12
JP5A
2
2
JP5B
2
2
BERG69157-102
1
1K
JP6B
R20
AGND
1K
R19
BERG69157-102
1
BERG69157-102
1
1K
JP6A
R18
AGND
1K
R17
BERG69157-102
1
TP1
1 BLK
TP3
1 BLK
1 BLK
TP2
C17
C18
1 BLK
TP4
C19
22NF
22NF
22NF
22NF
C20
IAN
P4
1
2
WEILAND25.161.0253
IBN
AGND
P3
1
2
WEILAND25.161.0253
IBP
AGND
IAP
ICP_IN
2
E2C
2
INP_IN
2
E2N
2
1500 OHMS
INN_IN
1
1500 OHMS
1
E1N
1500 OHMS
ICN_IN
1
1500 OHMS
1
E1C
TBD1206
INPUT ANTI-ALIAS AND DEVICE CONNECTION
2
21
1 JP2A 2 1 JP1A 2
JP1B
JP2B
2
2 1
1
BERG69157-102
BERG69157-102
22NF
22NF
22NF
BERG69157-102
BERG69157-102
2
21
1
JP1C
JP2C
JP1N
JP2N
R5
R6
R7
R8
TBD1206
TBD1206
TBD1206
100
JP4C
R14
AGND
100
R13
JP3N
2
2
2
BERG69157-102
100
JP4N
R16
AGND
100
R15
BERG69157-102
1
2
BERG69157-102
1
1
JP3C
BERG69157-102
1
C13
C14
C15
22NF
C16
JP5C
2
2
JP5N
2
2
BERG69157-102
1
1K
JP6N
R24
AGND
1K
R23
BERG69157-102
1
BERG69157-102
1
1K
JP6C
R22
AGND
1K
R21
BERG69157-102
1
TP5
1 BLK
TP7
1 BLK
1 BLK
TP6
C21
C22
1 BLK
TP8
C23
C24
22NF
22NF
22NF
22NF
22NF
22NF
Rev. 0 | Page 26 of 36
22NF
Figure 38.
1
INN
AGND
INP
ICN
AGND
ICP
UG-146
Evaluation Board User Guide
09078-043
Evaluation Board User Guide
UG-146
BERG69157-102
JP7A
2
R29
1M
100K
1
VAP
JP8A
1500 OHMS
TP12
BLK
22NF
R26
1K
C32
2
VN
2
AGND
COM
B
AGND
A
WEILAND25.161.0253
1
AGND
BERG69157-102
1
2
1
R32
VAP_IN
1
2
3
P8
PHASE A VOLTAGE
1
E8A
JP9A
3PIN_SOLDER_JUMPER
BERG69157-102
JP7B
2
1500 OHMS
TP11
BLK
VBP
22NF
100K
JP8B
1
1M
1
VN
B
A
AGND
COM
AGND
1
2
3
2
BERG69157-102
AGND
WEILAND25.161.0253
2
R30
1K
C33
1
R27
R33
VBP_IN
1
2
PHASE B VOLTAGE
1
E8B
P7
JP9B
3PIN_SOLDER_JUMPER
BERG69157-102
JP7C
1
R31
1M
100K
1K
C34
1500 OHMS
TP10
BLK
VCP
R34
R28
JP8C
VN
B
1
2
3
AGND
A
AGND
JP9C
3PIN_SOLDER_JUMPER
Figure 39.
Rev. 0 | Page 27 of 36
09078-044
1
AGND
1
2
2
WEILAND25.161.0253
1
2
1
BERG69157-102
PHASE C VOLTAGE
VCP_IN
COM
P6
22NF
2
E8C
P
C78
MCU_VDD
WEILAND25.161.0253
10UF
C79
JP7
2
MRESET
1UF
C74
10K
R74
MCU_VDD
TP40
BLK
TP48
TP47
BLK
BLK
1
BLK
BLK
BLK
BLK
BLK
BLK
BLK
TP55
TP53
TP54
TP44
TP45
TP52
TP46
10K
0.1UF
28 54 71 96
13 42 84
2
Y2
12.000MHZ
1
C71
20PF
MCU_XT2
VBAT
19
R76
GND
2 3 4 5
TP18
TP16
TP17
1 BLK 1 BLK 1 BLK
CF1_ISO
IRQ1B_ISO
IRQ0B_ISO
SCLK_ISO
SCL_ISO
CF3_HSCLK_ISO
10K
R78
CF2_ISO
CF2
TDO
10K
RSTOUT_N
MCU_XT2
RTCX2
P1_0
P1_1
P1_4
P1_8
P1_9
P1_10
P1_14
P1_15
CR6
P1_16
R77
P1_17
C
A
680
USB_UP
SML-LXT0805GW-TR
P1_19
BLK
TP41
CF3_HSCLK_ISO
HSA_ISO
TP42
P1_22
BLK
P1_23
HSDATA_ISO
TP43
P1_25
P1_26
P1_27
P1_28
P1_29
VBUS
P1_31
MCU_RST
P2_0
P2_1
P2_2
CF2_ISO
P2_3
P2_4
RESB_CTRL
P2_5
P2_6
PM1_CTRL
P2_7
P2_8
PM0_CTRL
P2_9
P2_10
P2_11
SSB_ISO
P2_12
HSA_ISO
MOSI_ISO
LPC2368FBD100
SDA_ISO
MISO_HSD_ISO
U8
P13
1
TP FOR EVAL PROBE - DISTRIBUTE AROUND ISOLATED CIRCUITS
11
VSSA
VREF
12
VDDA
10
AMP227699-2
1
TDO
14
RSTOUT_N
23
XTAL2
18
RTCX2
P1_0_ENET_TXD0 95
P1_1_ENET_TXD1 94
P1_4_ENET_TX_EN 93
P1_8_ENET_CRS 92
P1_9_ENET_RXD0 91
P1_10_ENET_RXD1 90
P1_14_ENET_RX_ER 89
P1_15_ENET_REF_CLK 88
P1_16_ENET_MDC 87
P1_17_ENET_MDIO 86
P1_18_USB_UP_LED_PWM1_1 32
P1_19_CAP1_1 33
P1_20_PWM1_2_SCK0 34
P1_21_PWM1_3_SSEL0 35
P1_22_MAT1_0 36
P1_23_PWM1_4_MISO0 37
P1_24_PWM1_5_MOSI0 38
P1_25_MAT1_1 39
P1_26_PWM1_6_CAP0_0 40
P1_27_CAP0_1 43
P1_28_PCAP1_0_MAT0_0 44
P1_29_PCAP1_1_MAT0_1 45
P1_30_VBUS_AD0_4 21
P1_31_SCK1_AD0_5 20
P2_0_PWM1_1_TXD1_TRACECLK 75
P2_1_PWM1_2_RXD1_PIPESTAT0 74
P2_2_PWM1_3_CTS1_PIPESTAT1 73
P2_3_PWM1_4_DCD1_PIPESTAT2 70
P2_4_PWM1_5_DSR1_TRACESYNC 69
P2_5_PWM1_6_DTR1_TRACEPKT0 68
P2_6_PCAP1_0_RI1_TRACEPKT1 67
P2_7_RD2_RTS1_TRACEPKT2 66
P2_8_TD2_TXD2_TRACEPKT3 65
P2_9_USB_CONNECT_RXD2_EXTIN0 64
P2_10_EINT0 53
P2_11_EINT1_MCIDAT1_I2STX_CLK52
P2_12_EINT2_MCIDAT2_I2STX_WS 51
15 31 41 55 72 83 97
VSS
2 TDI
3 TMS
4 TRST_N
5 TCK
22 XTAL1
16 RTCX1
17 RESET_N
30 P0_30_USB_DN
24 P0_28_SCL0
6 P0_26_AD0_3_AOUT_RXD3
8 P0_24_AD0_1_I2SRX_WS_CAP3_1
56 P0_22_RTS1_MCIDAT0_TD1
58 P0_20_DTR1_MCICMD_SCL1
60 P0_18_DCD1_MOSI0_MOSI
63 P0_16_RXD1_SSEL0_SSEL
49 P0_11_RXD2_SCL2_MAT3_1
76 P0_9_I2STX_SDA_MOSI1_MAT2_3
78 P0_7_I2STX_CLK_SCK1_MAT2_1
46 P0_0_RD1_TXD3_SDA1
47 P0_1_TD1_RXD3_SCL1
98 P0_2_TXD0
99 P0_3_RXD0
81 P0_4_I2SRX_CLK_RD2_CAP2_0
80 P0_5_I2SRX_WS_TD2_CAP2_1
79 P0_6_I2SRX_SDA_SSEL1_MAT2_0
77 P0_8_I2STX_WS_MISO1_MAT2_2
48 P0_10_TXD2_SDA2_MAT3_0
62 P0_15_TXD1_SCK0_SCK
61 P0_17_CTS1_MISO0_MISO
59 P0_19_DSR1_MCICLK_SDA1
57 P0_21_RI1_MCIPWR_RD1
9 P0_23_AD0_0_I2SRX_CLK_CAP3_0
7 P0_25_AD0_2_I2SRX_SDA_TXD3
25 P0_27_SDA0
29 P0_29_USB_DP
27 P3_25_MAT0_0_PWM1_2
26 P3_26_MAT0_1_PWM1_3
82 P4_28_MAT2_0_TXD3
85 P4_29_MAT2_1_RXD3
50 P2_13_EINT3_MCIDAT3_I2STX_SDA
100 RTCK
MCU_XT1
C70
20PF
MCU_RST
D-_MCU
SCL_ISO
P0_26
P0_24
P0_22
P0_20
MOSI_ISO
SSB_ISO
SBENB_ISO
P0_9
PM1_CTRL
IRQ1B_ISO
IRQ0B_ISO
TXD
RXD
P0_4
P0_5
PM0_CTRL
RESB_CTRL
WP
SCLK_ISO
MISO_ISO
P0_19
P0_21
IRQ_IN_EN
IRQ_OUT_EN_ISO
SDA_ISO
D+_MCU
P3_25
P3_26
P4_28
P4_29
P2_13
RTCK
TDI
TMS
TRST_N
TCLK
MCU_XT1
MCU_VDD_ISO
GND
2 3 4 5
CF1
1 CF1_ISO
1 BLK
3
4
MCU_RST
BERG69157-102
1
MCU CIRCUIT
AMP227699-2
1
B3S1000
1
2
S2
MCU_VDD
ISOLATED PSU CONNECTIONS
N
P12
VDD_3V3_1
10K
10K
0.1UF
C73
VDD_3V3_2
R72
R71
0.1UF
C72
0.1UF
C75
VDD_3V3_3
0.1UF
C77
1
2
VDD_DCDC_3V3_3
0.1UF
C83
VDD_DCDC_3V3_1
C76
VDD_3V3_4
0.1UF
C84
VDD_DCDC_3V3_2
0.1UF
C80
0.1UF
C81
0.1UF
C82
0.1UF
R73
1
1
1
1
MCU_VDD
10K
1
R75
1
1
1
1
1
Rev. 0 | Page 28 of 36
10K
Figure 40.
R83
AMP227699-2
MCU_VDD
D+_MCU
D-_MCU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D+
D-
MCU_VDD
4-1734376-8
P14
2
3
6
1
4
5
USB IF
1
2
3
4
UART
BYPASSING CONTROLLER
SAMTSW-1-30-08-GD
P15
SAMTECTSW10608GS4PIN
MCU_VDD
RXD
TXD
(OPTIONAL; CUSTOMER SUPPLIED)
P38
10K
R82
VBUS
VBUS(5V)
DD+
NC
GND
R44
10K
R45
10K
MCU_RST
TDO
RTCK
TCLK
TMS
TDI
TRST_N
SAMTECTSW11008GD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SHIELD D+, D-, VREF_MCU WITH GND
FROM CONN TO MCU
1.5K
R81
27
R80
27
R79
CF3_HSCLK_ISO
CF3
GND
2 3 4 5
1
UG-146
Evaluation Board User Guide
09078-038
Evaluation Board User Guide
UG-146
MCU_VDD
ISOLATION CIRCUIT
VDD2
R48
VE2_U3
R49
U3
1
16
10K
10K
C49
VE1
10 IRQ_OUT_EN
VE2
3 IRQ0B_ISO
VIA
4 IRQ1B_ISO
VIB
5 WP
VIC
11
VID
GND1
C55
MISO_HSD_ISO
CF3_HSCLK_ISO
HSA_ISO
IRQ_OUT_EN
1
VDD2 VDD1
C57
0.1UF
SSB_ISO
MOSI_ISO
SCLK_ISO
C59
VE1
10
VE2
3
VIA
4
VIB
5
VIC
11
VID
GND1
0.1UF
VOA
VOB
VOC
VOD
GND2
R47
10K
10K
15
9
8
2
0.1UF
C56
7
14
13
12
6
ADUM1401BRWZ
SSB
MOSI
SCLK
10K
ADUM1401BRWZ
R57
2
8
9
15
16
14
13
12
6
0.1UF
VE2_U6
VOA
VOB
VOC
VOD
GND1 GND2
U7
10K
R55
16
1
R54
U6
VDD1 VDD2
7 VE1
10 VE2
VE2_U6
3 VIA
MISO/HSD
4 VIB
CF3/HSCLK
5 VIC
HSACTIVE
IRQ_OUT_EN_ISO 11 VID
0.1UF
C54
10K
15
9
8
2
ADUM1401BRWZ
VOA
VOB
VOC
VOD
GND2
C53
0.1UF
C52
7
14
13
12
6
0.1UF
ADUM1401BRWZ
VDD2 VDD1
IRQ0B
IRQ1B
WP_UX
0.1UF
R46
IRQ_IN_EN
IRQ0B_ISO
IRQ1B_ISO
CF2_ISO
SB_ENB
14
13
12
6
1
U5
16
2
8
9
15
VOA
VOB
VOC
VOD
GND1 GND2
C51
U4
R53
IRQ_IN_EN
IRQ0B
IRQ1B
CF2
SBENB_ISO
MCU ->
ADUM1401BRWZ
VDD1 VDD2
7 VE1
10 VE2
3 VIA
4 VIB
5 VIC
11 VID
VE2_U3
RESB_CTRL
PM0_CTRL
PM1_CTRL
CF1
0.1UF
16
1
10K
R50
0.1UF
C50
7
10
3
4
5
11
10K
VE1
VE2
VIA
VIB
VIC
VID
GND1
15
9
8
2
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