3.3 V, 100 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
ADN4690E/ADN4692E/ADN4694E/ADN4695E
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 100 Mbps (50 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
Type 1 (ADN4690E/ADN4692E): hysteresis of 25 mV
Type 2 (ADN4694E/ADN4695E): threshold offset of 100 mV
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch-free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4690E/ADN4694E) and 14-lead
(ADN4692E/ADN4695E) SOIC packages
VCC
ADN4690E/
ADN4694E
RO
R
RE
A
B
DE
D
10471-001
DI
GND
Figure 1.
VCC
ADN4692E/
ADN4695E
R
RO
A
B
RE
DE
DI
D
GND
Z
Y
10471-102
Data Sheet
Figure 2.
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
GENERAL DESCRIPTION
The ADN4690E/ADN4692E/ADN4694E/ADN4695E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up
to 100 Mbps (50 MHz). Slew rate control is implemented on the
driver outputs. The receivers detect the bus state with a differential
input of as little as 50 mV over a common-mode voltage range of
−1 V to +3.4 V. ESD protection of up to ±15 kV is implemented
on the bus pins. The parts adhere to the TIA/EIA-899 standard for
M-LVDS and complement TIA/EIA-644 LVDS devices with
additional multipoint capabilities.
The ADN4690E/ADN4692E are Type 1 receivers with 25 mV of
hysteresis, so that slow-changing signals or loss of input does
not lead to output oscillations. The ADN4694E/ADN4695E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the
inputs are open (open-circuit fail-safe).
Rev. B
The parts are available as half-duplex in an 8-lead SOIC package
(the ADN4690E/ADN4694E) or as full-duplex in a 14-lead
SOIC package (the ADN4692E/ADN4695E). A selection table
for the ADN469xE parts is shown in Table 1.
Table 1. High Speed M-LVDS Transceiver Selection Table
Part No.
ADN4690E
ADN4691E
ADN4692E
ADN4693E
ADN4694E
ADN4695E
ADN4696E
ADN4697E
Receiver
Type 1
Type 1
Type 1
Type 1
Type 2
Type 2
Type 2
Type 2
Data Rate
100 Mbps
200 Mbps
100 Mbps
200 Mbps
100 Mbps
100 Mbps
200 Mbps
200 Mbps
SOIC
8-lead
8-lead
14-lead
14-lead
8-lead
14-lead
8-lead
14-lead
Duplex
Half
Half
Full
Full
Half
Full
Half
Full
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ADN4690E/ADN4692E/ADN4694E/ADN4695E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Voltage and Current Measurements............................ 11
Applications ....................................................................................... 1
Driver Timing Measurements .................................................. 12
Functional Block Diagrams ............................................................. 1
Receiver Timing Measurements ............................................... 13
General Description ......................................................................... 1
Theory of Operation ...................................................................... 14
Revision History ............................................................................... 2
Half-Duplex/Full-Duplex Operation ....................................... 14
Specifications..................................................................................... 3
Three-State Bus Connection ..................................................... 14
Receiver Input Threshold Test Voltages .................................... 4
Truth Tables................................................................................. 14
Timing Specifications .................................................................. 5
Glitch-Free Power-Up/Power-Down ....................................... 15
Absolute Maximum Ratings ............................................................ 6
Fault Conditions ......................................................................... 15
Thermal Resistance ...................................................................... 6
Receiver Input Thresholds/Fail-Safe ........................................ 15
ESD Caution .................................................................................. 6
Applications Information .............................................................. 16
Pin Configurations and Function Descriptions ........................... 7
Outline Dimensions ....................................................................... 17
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 17
Test Circuits and Switching Characteristics ................................ 11
REVISION HISTORY
1/16—Rev. A to Rev. B
Changed NC to DNC .................................................... Throughout
Changes to Table 1 Title ................................................................... 1
Changes to Table 6 ............................................................................ 6
3/12—Rev. 0 to Rev. A
Added ADN4694E and ADN4695E................................. Universal
Change to Features Section, General Description Section,
and Table 1 ......................................................................................... 1
Added Type 2 Receiver Parameters, Table 2 ................................. 3
Added Table 4, Renumbered Sequentially .....................................5
Added Type 2 Receiver Parameters, Table 5 ..................................5
Changes to Table 8.............................................................................7
Added Table 13 ............................................................................... 14
Changes to Receiver Input Thresholds/Fail-Safe Section
and Figure 35................................................................................... 15
Changes to Figure 36 and Figure 37 and Their Captions ......... 16
Changes to Ordering Guide .......................................................... 18
1/12—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 50 Ω; TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
DRIVER
Differential Outputs
Differential Output Voltage Magnitude
∆|VOD| for Complementary Output States
Common-Mode Output Voltage (Steady State)
ΔVOC(SS) for Complementary Output States
Peak-to-Peak VOC
Maximum Steady-State Open-Circuit Output
Voltage
Voltage Overshoot
Low to High
High to Low
Output Current
Short Circuit
High Impedance State, Driver Only
Power Off
Output Capacitance
Differential Output Capacitance
Output Capacitance Balance (CY/CZ)
Logic Inputs (DI, DE)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Type 1 Receiver (ADN4690E, ADN4692E)
Type 2 Receiver (ADN4694E, ADN4695E)
Input Hysteresis
Type 1 Receiver (ADN4690E, ADN4692E)
Type 2 Receiver (ADN4694E, ADN4695E)
Differential Input Voltage Magnitude
Input Capacitance
Differential Input Capacitance
Input Capacitance Balance (CA/CB)
Logic Output RO
Output High Voltage
Output Low Voltage
High Impedance Output Current
Logic Input RE
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Symbol
Min
|VOD|
∆|VOD|
VOC(SS)
ΔVOC(SS)
VOC(PP)
VA(O), VB(O),
VY(O), or VZ(O)
480
−50
0.8
−50
Typ
0
Max
Unit
Test Conditions/Comments
650
+50
1.2
+50
150
2.4
mV
mV
V
mV
mV
V
See Figure 18
See Figure 18
See Figure 19, Figure 22
See Figure 19, Figure 22
See Figure 19, Figure 22
See Figure 20
1.2VSS
V
V
See Figure 23, Figure 26
See Figure 23, Figure 26
VPH
VPL
−0.2VSS
|IOS|
IOZ
−15
24
+10
mA
µA
IO(OFF)
−10
+10
µA
CYZ
CY/Z
pF
0.99
2.5
1.01
See Figure 21
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
other output = 1.2 V
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
other output = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
VI = 0.4 sin(30e6πt) V + 0.5 V,2
other output = 1.2 V, DE = 0 V
VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
VIH
VIL
IIH
IIL
2
GND
0
0
VCC
0.8
10
10
V
V
µA
µA
VIH = 2 V to VCC
VIL = GND to 0.8 V
VTH
VTH
−50
50
+50
150
mV
mV
See Table 3, Figure 35
See Table 4, Figure 35
CY or CZ
VHYS
VHYS
|VID|
CA or CB
CAB
CA/B
3
pF
25
0
0.05
VCC
3
0.99
2.5
1.01
VOH
VOL
IOZ
2.4
−10
0.4
+15
VIH
VIL
IIH
IIL
2
GND
−10
−10
VCC
0.8
0
0
Rev. B | Page 3 of 20
mV
mV
V
pF
pF
VI = 0.4 sin(30e6πt) V + 0.5 V,2
other input = 1.2 V
VAB = 0.4 sin(30e6πt) V2
V
V
µA
IOH = –8 mA
IOL = 8 mA
VO = 0 V or 3.6 V
V
V
µA
µA
VIH = 2 V to VCC
VIL = GND to 0.8 V
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Parameter
BUS INPUT/OUTPUT
Input Current
A (Receiver or Transceiver with Driver Disabled)
B (Receiver or Transceiver with Driver Disabled)
Differential (Receiver or Transceiver with Driver
Disabled)
Power-Off Input Current
A (Receiver or Transceiver)
B (Receiver or Transceiver)
Differential Input Capacitance (Transceiver with
Driver Disabled)
Input Capacitance Balance (CA/CB) (Transceiver
with Driver Disabled)
POWER SUPPLY
Supply Current
Only Driver Enabled
Both Driver and Receiver Disabled
Both Driver and Receiver Enabled
Only Receiver Enabled
Total Power Dissipation
2
Min
IA
IB
IAB
IA(OFF)
IB(OFF)
Differential (Receiver or Transceiver)
Input Capacitance (Transceiver with Driver Disabled)
1
Symbol
IAB(OFF)
CA or CB
Data Sheet
Typ
Max
Unit
Test Conditions/Comments
0
−20
−32
0
−20
−32
−4
32
+20
0
32
+20
0
+4
μA
μA
μA
μA
μA
μA
μA
VB = 1.2 V, VA = 3.8 V
VB = 1.2 V, VA = 0 V or 2.4 V
VB = 1.2 V, VA = −1.4 V
VA = 1.2 V, VB = 3.8 V
VA = 1.2 V, VB = 0 V or 2.4 V
VA = 1.2 V, VB = −1.4 V
VA = VB, 1.4 ≤ VA ≤ 3.8 V
0
−20
−32
0
−20
−32
−4
32
+20
0
32
+20
0
+4
μA
μA
μA
μA
μA
μA
μA
pF
3
pF
5
CAB
CA/B
0.99
1.01
0 V ≤ VCC ≤ 1.5 V
VB = 1.2 V, VA = 3.8 V
VB = 1.2 V, VA = 0 V or 2.4 V
VB = 1.2 V, VA = −1.4 V
VA = 1.2 V, VB = 3.8 V
VA = 1.2 V, VB = 0 V or 2.4 V
VA = 1.2 V, VB = −1.4 V
VA = VB, 1.4 V ≤ VA ≤ 3.8 V
VI = 0.4 sin(30e6πt) V + 0.5 V,2
other input = 1.2 V, DE = 0 V
VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
DE = 0 V
ICC
13
1
16
4
PD
22
4
24
13
94
mA
mA
mA
mA
mW
DE, RE = VCC, RL = 50 Ω
DE = 0 V, RE = VCC, RL = no load
DE = VCC, RE = 0 V, RL = 50 Ω
DE, RE = 0 V, RL = 50 Ω
RL = 50 Ω, input (DI) = 50 MHz,
50% duty cycle square wave;
DE = VCC; RE = 0 V; TA = 85°C
All typical values are given for VCC = 3.3 V and TA = 25°C.
HP4194A impedance analyzer (or equivalent).
RECEIVER INPUT THRESHOLD TEST VOLTAGES
RE = 0 V, H = high, L = low.
Table 3. Test Voltages for Type 1 Receiver
VA (V)
2.4
0
3.425
3.375
−0.975
−1.025
Applied Voltages
VB (V)
0
2.4
3.375
3.425
−1.025
−0.975
Input Voltage, Differential
VID (V)
2.4
−2.4
0.05
−0.05
0.05
−0.05
Rev. B | Page 4 of 20
Input Voltage, Common Mode
VIC (V)
1.2
1.2
3.4
3.4
−1
−1
Receiver Output
RO
H
L
H
L
H
L
Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Table 4. Test Voltages for Type 2 Receiver
VA (V)
2.4
0
3.475
3.425
−0.925
−0.975
Applied Voltages
VB (V)
0
2.4
3.325
3.375
−1.075
−1.025
Input Voltage, Differential
VID (V)
2.4
−2.4
0.15
0.05
0.15
0.05
Input Voltage, Common Mode
VIC (V)
1.2
1.2
3.4
3.4
−1
−1
Receiver Output
RO
H
L
H
L
H
L
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay
Differential Output Rise/Fall Time
Pulse Skew |tPHL − tPLH|
Part-to-Part Skew
Period Jitter, rms (One Standard Deviation)2
Peak-to-Peak Jitter2, 4
Disable Time from High Level
Disable Time from Low Level
Enable Time to High Level
Enable Time to Low Level
RECEIVER
Propagation Delay
Rise/Fall Time
Pulse Skew |tRPHL – tRPLH|
Type 1 Receiver (ADN4690E, ADN4692E)
Type 2 Receiver (ADN4694E, ADN4695E)
Part-to-Part Skew6
Period Jitter, RMS (One Standard Deviation)2
Peak-to-Peak Jitter2, 4
Type 1 Receiver (ADN4690E, ADN4692E)
Type 2 Receiver (ADN4694E, ADN4695E)
Disable Time from High Level
Disable Time from Low Level
Enable Time to High Level
Enable Time to Low Level
Symbol
tPLH, tPHL
tR, tF
tSK
tSK(PP)
tJ(PER)
tJ(PP)
tPHZ
tPLZ
tPZH
tPZL
tRPLH, tRPHL
tR, tF
Min
100
2
2
Typ
Max
Unit
Test Conditions/Comments
2.5
2.6
30
3.5
3.2
150
0.9
3
150
7
7
7
7
Mbps
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
See Figure 23, Figure 26
See Figure 23, Figure 26
See Figure 23, Figure 26
See Figure 23, Figure 26
50 MHz clock input3 (see Figure 25)
100 Mbps 215 − 1 PRBS input5 (see Figure 28)
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
6
2.3
ns
ns
ps
ps
ns
ps
ps
ps
ns
ns
ns
ns
2
4
4
4
4
2
1
tSK
tSK
tSK(PP)
tJ(PER)
100
300
4
300
500
1
7
tJ(PP)
tJ(PP)
tRPHZ
tRPLZ
tRPZH
tRPZL
200
225
6
6
10
10
700
800
10
10
15
15
1
All typical values are given for VCC = 3.3 V and TA = 25°C.
Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
3
tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
4
Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
5
tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
6
HP4194A impedance analyzer or equivalent.
2
Rev. B | Page 5 of 20
CL = 15 pF (see Figure 29, Figure 32)
CL = 15 pF (see Figure 29, Figure 32)
CL = 15 pF (see Figure 29, Figure 32)
CL = 15 pF (see Figure 29, Figure 32)
50 MHz clock input3 (see Figure 31)
100 Mbps 215 − 1 PRBS input5 (see Figure 34)
See Figure 30, Figure 33
See Figure 30, Figure 33
See Figure 30, Figure 33
See Figure 30, Figure 33
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, unless otherwise noted.
THERMAL RESISTANCE
Table 6.
Parameter
VCC
Digital Input Voltage (DE, RE, DI)
Receiver Input (A, B) Voltage
Half-Duplex (ADN4690E, ADN4694E)
Full Duplex (ADN4692E, ADN4695E)
Receiver Output Voltage (RO)
Driver Output (A, B, Y, Z) Voltage
ESD Rating (A, B, Y, Z Pins)
HBM (Human Body Model)
Air Discharge
Contact Discharge
IEC 61000-4-2
Air Discharge
Contact Discharge
ESD Rating (Other Pins, HBM)
ESD Rating (All Pins, FICDM)
Operating Temperature Range
Storage Temperature Range
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
–0.5 V to +4 V
–0.5 V to +4 V
Table 7. Thermal Resistance
Package Type
8-Lead SOIC
14-Lead SOIC
–1.8 V to +4 V
–4 V to +6 V
–0.3 V to +4 V
–1.8 V to +4 V
ESD CAUTION
±15 kV
±8 kV
±10 kV
±8 kV
±4 kV
±1.25 kV
−40°C to +85°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 6 of 20
θJA
121
86
Unit
°C/W
°C/W
Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
DNC 1
14
VCC
RO 2
13
VCC
12
A
11
B
10
Z
RE 3
DE 4
DI 5
RE 2
DE 3
DI 4
ADN4690E/
ADN4694E
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
8
VCC
GND 6
9
Y
7
B
GND 7
8
DNC
6
A
5
GND
10471-002
RO 1
ADN4692E/
ADN4695E
NOTES
1. DNC = DO NOT CONNECT.
10471-104
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADN4692E/ADN4695E Pin Configuration
Figure 3. ADN4690E/ADN4694E Pin Configuration
Table 8. Pin Function Descriptions
ADN4690E/
ADN4694E
Pin No.1
1
ADN4692E/
ADN4695E
Pin No.1
2
Mnemonic
RO
2
3
RE
3
4
DE
4
5
DI
5
N/A
N/A
6
N/A
7
N/A
8
N/A
6, 7
9
10
N/A
12
N/A
11
13, 14
1, 8
GND
Y
Z
A
A
B
B
VCC
DNC
1
Description
Receiver Output. Type 1 receiver (ADN4690E/ADN4692E), when enabled:
If A − B ≥ 50 mV, then RO = logic high. If A − B ≤ −50 mV, then RO = logic low.
Type 2 receiver (ADN4694E/ADN4695E), when enabled:
If A − B ≥ 150 mV, then RO = logic high. If A − B ≤ 50 mV, then RO = logic low.
Receiver output is undefined outside these conditions.
Receiver Output Enable. A logic low on this pin enables the receiver output, RO.
A logic high on this pin places RO in a high impedance state.
Driver Output Enable. A logic high on this pin enables the driver differential outputs.
A logic low on this pin places the driver differential outputs in a high impedance state.
Driver Input. Half-duplex (ADN4690E/ADN4694E), when enabled:
A logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low.
Full-duplex (ADN4692E/ADN4695E), when enabled:
A logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low.
Ground.
Noninverting Driver Output Y.
Inverting Driver Output Z.
Noninverting Receiver Input A and Noninverting Driver Output A.
Noninverting Receiver Input A.
Inverting Receiver Input B and Inverting Driver Output B.
Inverting Receiver Input B.
Power Supply (3.3 V ± 0.3 V).
Do Not Connect. Do not connect to these pins.
N/A means not applicable.
Rev. B | Page 7 of 20
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
16
14
12
10
8
6
4
0
10
15
25
20
30
35
45
40
50
FREQUENCY (MHz)
10471-003
2
–10
–15
–20
–25
–30
–35
–40
–45
–50
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
RECEIVER HIGH LEVEL OUTPUT VOLTAGE, VOH (V)
Figure 8. Receiver Output Current vs. Output Voltage (Output High)
(TA = 25°C)
3.4
30
tPLH
tPHL
25
20
15
10
5
0
20
40
80
60
TEMPERATURE (°C)
3.0
2.8
2.6
2.4
2.2
2.0
–40
6.0
RECEIVER PROPAGATION DELAY (ns)
VCC = 3V
VCC = 3.3V
VCC = 3.6V
30
25
20
15
10
5
1.0
1.5
2.0
2.5
3.0
3.5
RECEIVER LOW LEVEL OUTPUT VOLTAGE, VOL (V)
4.0
40
60
80
tRPLH
tRPHL
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
–40
10471-005
0
0.5
20
Figure 9. Driver Propagation Delay vs. Temperature
(Data Rate = 2 Mbps, VCC = 3.3 V, RL = 50 Ω)
40
0
0
TEMPERATURE (°C)
Figure 6. Power Supply Current vs. Temperature
(Data Rate = 100 Mbps, VCC = 3.3 V)
35
–20
–20
0
20
40
TEMPERATURE (°C)
Figure 7. Receiver Output Current vs. Output Voltage (Output Low)
(TA = 25°C)
60
80
10471-008
–20
10471-004
0
–40
3.2
10471-007
DRIVER PROPAGATION DELAY (ns)
DRIVER
RECEIVER (VID = 200mV, VIC = 1V)
RECEIVER LOW LEVEL OUTPUT CURRENT, IOL (mA)
VCC = 3.0V
VCC = 3.3V
VCC = 3.6V
–5
0
Figure 5. Power Supply Current vs. Frequency
(VCC = 3.3 V, TA = 25°C)
SUPPLY CURRENT, ICC (mA)
0
10471-006
DRIVER
RECEIVER (VID = 200mV, VIC = 1V)
18
SUPPLY CURRENT, ICC (mA)
RECEIVER HIGH LEVEL OUTPUT CURRENT (mA)
20
Figure 10. Receiver Propagation Delay vs. Temperature
(Data Rate = 2 Mbps, VCC = 3.3 V, VID = 200 mV, VIC = 1 V, CL = 15 pF)
Rev. B | Page 8 of 20
Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
2.5
2.0
1.5
1.0
0.5
0
20
40
60
80
100
FREQUENCY (MHz)
6
5
4
3
2
1
0
10
Figure 14. Receiver Jitter (Period) vs. Frequency
(VCC = 3.3 V, TA = 25°C, VIC = 1 V, Clock Input)
20
16
14
12
10
8
6
4
2
0
20
30
40
50
60
70
80
90
100
DATA RATE (Mbps)
80
70
60
50
40
30
20
20
40
60
80
10471-011
10
TEMPERATURE (°C)
300
200
100
–20
0
20
40
60
Figure 15. Receiver Jitter (Peak-to-Peak) vs. Temperature
(VCC = 3.3 V, VIC = 1 V, PRBS 215 − 1 NRZ Input)
90
0
400
TEMPERATURE (°C)
100
–20
500
0
–40
Figure 12. Driver Jitter (Peak-to-Peak) vs. Data Rate
(VCC = 3.3 V, TA = 25°C, PRBS 215 − 1 NRZ Input)
0
–40
600
Figure 13. Driver Jitter (Peak-to-Peak) vs. Temperature
(Data Rate = 100 Mbps, VCC = 3.3 V, TA = 25°C, PRBS 215 − 1 NRZ Input)
Rev. B | Page 9 of 20
80
10471-014
ADDED RECEIVER PEAK-TO-PEAK JITTER (ps)
700
18
10471-010
ADDED DRIVER PEAK-TO-PEAK JITTER (ps)
50
40
FREQUENCY (MHz)
Figure 11. Driver Jitter (Period) vs. Frequency
(VCC = 3.3 V, TA = 25°C, Clock Input)
ADDED DRIVER PEAK-TO-PEAK JITTER (ps)
30
20
10471-012
ADDED RECEIVER PERIOD JITTER (ps)
7
10471-009
ADDED DRIVER PERIOD JITTER (ps)
3.0
Data Sheet
2.5ns/DIV
Figure 16. ADN4690E Driver Output Eye Pattern
(Data Rate = 100 Mbps, PRBS 215 − 1 Input, RL = 50 Ω)
Figure 17. ADN4690E Receiver Output Eye Pattern
(Data Rate = 100 Mbps, PRBS 215 − 1, CL = 15 pF)
Rev. B | Page 10 of 20
10471-016
2ns/DIV
10471-015
400mV/DIV
200mV/DIV
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
DRIVER VOLTAGE AND CURRENT MEASUREMENTS
A/Y
3.32kΩ
VOD
DI
VTEST = –1V TO +3.4V
IOS
VCC
49.9Ω
A/Y
+
3.32kΩ
B/Z
VTEST
S1
DI
VTEST = –1V OR +3.4V
S2
–
Figure 18. Driver Voltage Measurement over Common-Mode Range
A/Y
C1
1pF
R1
24.9Ω
10471-020
10471-017
NOTES
1. 1% TOLERANCE FOR ALL RESISTORS.
VTEST
B/Z
Figure 21. Driver Short Circuit
A
≈ 1.3V
B
≈ 0.7V
DI
C3
2.5pF VOC
VOC
NOTES
1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
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