3.0 kV RMS, 6-Channel Digital Isolators
ADuM160N/ADuM161N/ADuM162N/ADuM163N
FUNCTIONAL BLOCK DIAGRAMS
High common-mode transient immunity: 100 kV/μs
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals (pending)
UL recognition: 3000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
CQC certification per GB4943.1-2011
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS-compliant, narrow-body SOIC package
VDD1 1
16 VDD2
ENCODE
DECODE
15 VOA
VIB 3
ENCODE
DECODE
14 VOB
VIC 4
ENCODE
DECODE
13 VOC
VID 5
ENCODE
DECODE
12 VOD
VIE 6
ENCODE
DECODE
11 VOE
VIF 7
ENCODE
DECODE
10 VOF
GND1 8
9
GND2
Figure 1. ADuM160N Functional Block Diagram
ADuM161N
ENCODE
DECODE
15 VOA
VIB 3
ENCODE
DECODE
14 VOB
VIC 4
ENCODE
DECODE
13 VOC
VID 5
ENCODE
DECODE
12 VOD
VIE 6
ENCODE
DECODE
11 VOE
VOF 7
DECODE
ENCODE
10 VIF
GND1 8
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
16 VDD2
VIA 2
9
GND2
14532-002
VDD1 1
APPLICATIONS
Figure 2. ADuM161N Functional Block Diagram
The ADuM160N/ADuM161N/ADuM162N/ADuM163N1 are
6-channel digital isolators based on Analog Devices, Inc., iCoupler®
technology. Combining high speed, complementary metal-oxide
semiconductor (CMOS) and monolithic air core transformer
technology, these isolation components provide outstanding
performance characteristics superior to alternatives such as
optocoupler devices and other integrated couplers. The maximum propagation delay is 13 ns with a pulse width distortion of
less than 4.5 ns at 5 V operation. Channel to channel matching
of propagation delay is tight at 4.0 ns maximum.
ADuM162N
16 VDD2
VIA 2
ENCODE
DECODE
15 VOA
VIB 3
ENCODE
DECODE
14 VOB
VIC 4
ENCODE
DECODE
13 VOC
VID 5
ENCODE
DECODE
12 VOD
VOE 6
DECODE
ENCODE
11 VIE
VOF 7
DECODE
ENCODE
10 VIF
GND1 8
9
GND2
14532-003
VDD1 1
GENERAL DESCRIPTION
Figure 3. ADuM162N Functional Block Diagram
VDD1 1
The ADuM160N/ADuM161N/ADuM162N/ADuM163N data
channels are independent and are available in a variety of
configurations with a withstand voltage rating of 3.0 kV rms
(see the Ordering Guide). The devices operate with the supply
voltage on either side ranging from 1.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling
voltage translation functionality across the isolation barrier.
ADuM163N
16 VDD2
VIA 2
ENCODE
DECODE
15 VOA
VIB 3
ENCODE
DECODE
14 VOB
VIC 4
ENCODE
DECODE
13 VOC
VOD 5
DECODE
ENCODE
12 VID
VOE 6
DECODE
ENCODE
11 VIE
VOF 7
DECODE
ENCODE
10 VIF
GND1 8
Unlike other optocoupler alternatives, dc correctness is ensured
in the absence of input logic transitions. Two different fail-safe
options are available by which the outputs transition to a predetermined state when the input power supply is not applied.
1
ADuM160N
VIA 2
14532-001
FEATURES
9
GND2
14532-004
Data Sheet
Figure 4. ADuM163N Functional Block Diagram
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. A
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ADuM160N/ADuM161N/ADuM162N/ADuM163N
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 12
Applications ....................................................................................... 1
Absolute Maximum Ratings ......................................................... 13
General Description ......................................................................... 1
ESD Caution................................................................................ 13
Functional Block Diagrams ............................................................. 1
Pin Configurations and Function Descriptions ......................... 14
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 18
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 20
Electrical Characteristics—5 V Operation................................ 3
Applications Information .............................................................. 21
Electrical Characteristics—3.3 V Operation ............................ 5
PCB Layout ................................................................................. 21
Electrical Characteristics—2.5 V Operation ............................ 7
Propagation Delay Related Parameters ................................... 21
Electrical Characteristics—1.8 V Operation ............................ 9
Jitter Measurement ..................................................................... 21
Insulation and Safety Related Specifications .......................... 11
Insulation Lifetime ..................................................................... 21
Package Characteristics ............................................................. 11
Outline Dimensions ....................................................................... 23
Regulatory Information ............................................................. 11
Ordering Guide .......................................................................... 23
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 12
REVISION HISTORY
6/2019—Rev. 0 to Rev. A
Changes to Table 11 ........................................................................ 11
Changes to Ordering Guide .......................................................... 23
7/2016—Revision 0: Initial Version
Rev. A | Page 2 of 23
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate 1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Symbol
Min
PW
6.6
150
4.8
tPHL, tPLH
PWD
7.2
0.5
1.5
tPSK
VIH
VIL
Output Voltage
Logic High
VOH
Logic Low
VOL
Max
Unit
Test Conditions/Comments
13
4.5
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
6.1
tPSKCD
tPSKOD
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM160N
Typ
0.5
0.5
490
70
4.0
4.5
0.7 ×
VDDx
See the Jitter Measurement section
See the Jitter Measurement section
V
0.3 ×
VDDx
VDDx
VDDx −
0.2
0.0
0.2
+0.01
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
V
V
V
IOx 2 = −20 µA, VIx = VIxH 3
IOx2 = −4 mA, VIx = VIxH3
0.1
0.4
+10
V
V
µA
IOx2 = 20 µA, VIx = VIxL 4
IOx2 = 4 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
2.3
3.3
19.3
3.5
3.5
4.52
30
4.82
mA
mA
mA
mA
VI 5 = 0 (N0), 1 (N1) 6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.5
3.2
16.0
7.2
3.8
4.22
24.8
11.2
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.8
3.0
14.1
10.5
4.0
4.2
22.5
16.7
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
II
VDDx − 0.1
VDDx − 0.4
ns
ns
ps p-p
ps rms
Between any two units at the
same temperature, voltage, and load
−10
ADuM161N
ADuM162N
Rev. A | Page 3 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
Parameter
ADuM163N
Symbol
Dynamic Supply Current
Dynamic Input
Dynamic Output
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 7
Min
Data Sheet
Typ
Max
Unit
Test Conditions/Comments
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
3.0
2.8
11.8
14.6
4.26
3.92
18.9
23
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDDI (D)
IDDO (D)
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
0.01
0.02
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
1.6
1.5
0.1
V
V
V
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
IOx is the Channel x output current, where x = A, B, C, D, E, or F.
3
VIxH is the input side logic high.
4
VIxL is the input side logic low.
5
VI is the voltage input.
6
N0 refers to the ADuM160N0/ADuM161N0/ADuM162N0/ADuM163N0 models. N1 refers to the ADuM160N1/ADuM161N1/ADuM162N1/ADuM163N1 models. See the
Ordering Guide section.
7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
1
2
Table 2. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM160N
Supply Current Side 1
Supply Current Side 2
ADuM161N
Supply Current Side 1
Supply Current Side 2
ADuM162N
Supply Current Side 1
Supply Current Side 2
ADuM163N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
10.8
3.6
15.8
5.5
12.3
5.63
19.2
9.0
18.3
12.8
26
20.9
mA
mA
IDD1
IDD2
9.27
5.33
14.5
9.0
10.9
7.39
17.2
12
17.3
14.5
25.6
22.2
mA
mA
IDD1
IDD2
8.53
6.83
13.0
10.5
10.2
8.64
15.6
13.1
16.4
14.6
25.5
22.3
mA
mA
IDD1
IDD2
7.47
8.75
12.3
14.0
9.35
10.5
14.5
16.0
15.9
17.0
23
23.3
mA
mA
Rev. A | Page 4 of 23
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate 1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM160N
Symbol
Min
PW
6.6
150
4.8
tPHL, tPLH
PWD
Typ
6.8
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
14
4.5
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
7.5
tPSKCD
tPSKOD
0.7
0.7
580
120
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
4.0
4.5
ns
ns
ps p-p
ps rms
Between any two units at the same
temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx 2 = −20 µA, VIx = VIxH 3
IOx2 = −2 mA, VIx = VIxH3
IOx2 = 20 µA, VIx = VIxL 4
IOx2 = 2 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.2
3.1
19
3.4
3.4
4.1
27.7
4.7
mA
mA
mA
mA
VI 5 = 0 (N0), 1 (N1) 6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.3
3.0
15.8
7.0
3.6
4.0
24.6
11
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.6
2.8
13.9
10.3
3.8
4.0
22.2
16.5
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.8
2.6
11.5
14.3
4.16
3.82
18.5
22.5
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
VOL
II
−10
ADuM161N
ADuM162N
ADuM163N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Rev. A | Page 5 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
Parameter
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity 7
Symbol
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
Min
Data Sheet
Typ
Max
Unit
1.6
1.5
0.1
V
V
V
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
Test Conditions/Comments
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
IOx is the Channel x output current, where x = A, B, C, D, E, or F.
3
VIxH is the input side logic high.
4
VIxL is the input side logic low.
5
VI is the voltage input.
6
N0 refers to the ADuM160N0/ADuM161N0/ADuM162N0/ADuM163N0 models. N1 refers to the ADuM160N1/ADuM161N1/ADuM162N1/ADuM163N1 models. See the
Ordering Guide section.
7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
1
2
Table 4. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM160N
Supply Current Side 1
Supply Current Side 2
ADuM161N
Supply Current Side 1
Supply Current Side 2
ADuM162N
Supply Current Side 1
Supply Current Side 2
ADuM163N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
10.5
3.4
15.5
5.4
11.7
5.4
18.6
7.8
16.6
11.8
24.6
19.9
mA
mA
IDD1
IDD2
9.0
5.1
14.2
8.8
10.4
7.0
16.6
11.6
15.7
13.1
24.1
20.8
mA
mA
IDD1
IDD2
8.3
6.6
12.8
10.3
9.8
8.3
14.8
12.6
15.2
13.8
24.3
21.5
mA
mA
IDD1
IDD2
7.3
8.5
12
13.7
8.9
9.9
14.2
15.6
14.9
16
22
22.3
mA
mA
Rev. A | Page 6 of 23
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate 1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM160N
Symbol
Min
PW
6.6
150
5.0
tPHL, tPLH
PWD
Typ
7.0
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
14
5.0
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
6.8
tPSKCD
tPSKOD
0.7
0.7
800
190
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
5.0
5.0
ns
ns
ps p-p
ps rms
Between any two units at the
same temperature, voltage, load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx 2 = −20 µA, VIx = VIxH 3
IOx2 = −2 mA, VIx = VIxH3
IOx2 = 20 µA, VIx = VIxL 4
IOx2 = 2 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.1
3.1
19
3.3
3.3
4.1
27.7
4.6
mA
mA
mA
mA
VI 5 = 0 (N0), 1 (N1) 6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.2
2.9
15.7
6.9
3.5
3.9
24.5
10.9
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.5
2.7
13.8
10.2
3.7
3.9
22.1
16.4
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.7
2.55
11.5
14.3
4.08
3.72
18.4
22.3
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
VOL
II
−10
ADuM161N
ADuM162N
ADuM163N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Rev. A | Page 7 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
Parameter
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity 7
Symbol
Min
VDDxUV+
VDDxUV−
VDDxUVH
Data Sheet
Typ
Max
Unit
1.6
1.5
0.1
V
V
V
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
Test Conditions/Comments
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
IOx is the Channel x output current, where x = A, B, C, D, E, or F.
3
VIxH is the input side logic high.
4
VIxL is the input side logic low.
5
VI is the voltage input.
6
N0 refers to the ADuM160N0/ADuM161N0/ADuM162N0/ADuM163N0 models. N1 refers to the ADuM160N1/ADuM161N1/ADuM162N1/ADuM163N1 models. See the
Ordering Guide section.
7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
1
2
Table 6. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM160N
Supply Current Side 1
Supply Current Side 2
ADuM161N
Supply Current Side 1
Supply Current Side 2
ADuM162N
Supply Current Side 1
Supply Current Side 2
ADuM163N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
10.4
3.3
15.4
5.3
11.2
4.8
18.4
7.2
16
9.8
24
17.9
mA
mA
IDD1
IDD2
8.9
5.0
14.1
8.7
10.1
6.5
16.3
11.1
14.8
11.4
23.6
20.1
mA
mA
IDD1
IDD2
8.1
6.5
12.6
10.2
9.4
7.8
14.4
12.1
14.1
12.4
23.2
20.1
mA
mA
IDD1
IDD2
7.1
8.3
11.9
13.4
8.5
9.7
13.9
15.2
13.6
14.8
21
21.3
mA
mA
Rev. A | Page 8 of 23
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate 1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM160N
Symbol
Min
PW
6.6
150
5.8
tPHL, tPLH
PWD
Typ
8.7
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
15
5.0
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
7.0
tPSKCD
tPSKOD
0.7
0.7
470
70
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
5.0
5.0
ns
ns
ps p-p
ps rms
Between any two units at the same
temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx 2 = −20 µA, VIx = VIxH 3
IOx2 = −2 mA, VIx = VIxH3
IOx2 = 20 µA, VIx = VIxL 4
IOx2 = 2 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.0
3.0
18.7
3.3
3.2
4.0
27.4
4.6
mA
mA
mA
mA
VI 5 = 0 (N0), 1 (N1) 6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.1
2.9
15.5
6.8
3.4
3.9
24.3
10.8
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.4
2.7
13.7
10.1
3.6
3.9
22
16.3
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.6
2.5
11.3
14
4.03
3.72
18.3
22
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
VOL
II
−10
ADuM161N
ADuM162N
ADuM163N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Rev. A | Page 9 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
Parameter
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity 7
Symbol
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
Min
Typ
Data Sheet
Max
Unit
1.6
1.5
0.1
V
V
V
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
Test Conditions/Comments
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
IOx is the Channel x output current, where x = A, B, C, D, E, or F.
3
VIxH is the input side logic high.
4
VIxL is the input side logic low.
5
VI is the voltage input.
6
N0 refers to the ADuM160N0/ADuM161N0/ADuM162N0/ADuM163N0 models. N1 refers to the ADuM160N1/ADuM161N1/ADuM162N1/ADuM163N1 models. See the
Ordering Guide section.
7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
1
2
Table 8. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM160N
Supply Current Side 1
Supply Current Side 2
ADuM161N
Supply Current Side 1
Supply Current Side 2
ADuM162N
Supply Current Side 1
Supply Current Side 2
ADuM163N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
10.2
3.3
15.2
5.3
11.3
4.8
18.2
7.2
15.9
9.8
23.9
17.9
mA
mA
IDD1
IDD2
8.7
4.9
13.9
8.6
10
6.4
16.2
11
14.6
11.4
23.4
20.1
mA
mA
IDD1
IDD2
8.0
6.4
12.5
10.1
9.2
7.7
14.2
12
13.9
12.4
23
20.1
mA
mA
IDD1
IDD2
7.0
8.2
11.8
13.3
8.3
9.5
13.7
15
13.3
14.5
20.7
21
mA
mA
Rev. A | Page 10 of 23
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see http://www.analog.com/icouplersafety.
Table 9.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L (I01)
Value
3000
4.0
Unit
V rms
mm min
Minimum External Tracking (Creepage)
L (I02)
4.0
mm min
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB)
4.5
mm min
CTI
25.5
>400
II
μm min
V
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 10.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction to Ambient Thermal Resistance
1
2
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1013
2.2
4.0
75
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside
The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 15 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 11.
UL (Pending)
Recognized Under UL 1577
Component Recognition Program1
CSA (Pending)
Approved under CSA Component
Acceptance Notice 5A
Single Protection, 3000 V rms Isolation
Voltage
Double Protection, 3000 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC
60950-1, second edition, +A1+A2:
Basic insulation at 400 V rms
(565 V peak)
Reinforced insulation at 200 V rms
(283 V peak)
IEC 60601-1 Edition 3.1: basic
insulation (one means of patient
protection (1 MOPP)), 250 V rms
(354 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains,
400 V rms secondary (565 V peak)
Reinforced insulation at 300 V rms
mains, 200 V secondary (282 V peak)
File 205078
File E214100
1
VDE (Pending)
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Reinforced insulation, VIORM =
565 V peak, VIOSM = 6000 V peak
Basic insulation, VIORM =
565 V peak, VIOSM = 10,000 V peak
CQC (Pending)
Certified under
CQC11-471543-2015,
GB4943.1-2011:
Basic insulation at
400 V rms (565 V peak)
File 2471900-4880-0001
File (CQC18001196412)
In accordance with UL 1577, each ADuM160N/ADuM161N/ADuM162N/ADuM163N in the R-16, narrow-body (SOIC_N) package is proof tested by applying an insulation
test voltage ≥ 3600 V rms for 1 sec.
2
In accordance with DIN V VDE V 0884-10, each ADuM160N/ADuM161N/ADuM162N/ADuM163N in the R-16, narrow-body (SOIC_N) package is proof tested by applying
an insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10
approval.
Rev. A | Page 11 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 12.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
Surge Isolation Voltage Reinforced
Safety Limiting Values
Unit
VIORM
Vpd (m)
I to IV
I to IV
I to III
40/125/21
2
565
1059
V peak
V peak
848
V peak
678
V peak
VIOTM
VIOSM
4200
10000
V peak
V peak
VIOSM
6000
V peak
TS
PS
RS
150
1.64
>109
°C
W
Ω
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VPEAK = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
VPEAK = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
Maximum value allowed in the event of a
failure (see Figure 5)
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
RECOMMENDED OPERATING CONDITIONS
1.8
1.6
SAFE LIMITING POWER (W)
Characteristic
Vpd (m)
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage Basic
Table 13.
1.4
Parameter
Operating Temperature
Supply Voltages
Input Signal Rise and Fall Times
1.2
1.0
0.8
0.6
0.4
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
14532-005
0.2
0
Symbol
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
Rev. A | Page 12 of 23
Symbol
TA
VDD1, VDD2
Rating
−40°C to +125°C
1.7 V to 5.5 V
1.0 ms
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 14.
Parameter
Storage Temperature (TST) Range
Ambient Operating Temperature
(TA) Range
Supply Voltages (VDD1, VDD2)
Input Voltages (VIA, VIB, VIC, VID, VIE,
VIF)
Output Voltages (VOA, VOB, VOC, VOD, VOE,
VOF)
Average Output Current per Pin3
Side 1 Output Current (IO1)
Side 2 Output Current (IO2)
Common-Mode Transients4
Rating
−65°C to +150°C
−40°C to +125°C
−0.5 V to +7.0 V
−0.5 V to VDDI1 + 0.5 V
ESD CAUTION
−0.5 V to VDDO2 + 0.5 V
−10 mA to +10 mA
−10 mA to +10 mA
−150 kV/μs to +150 kV/μs
VDDI is the input side supply voltage.
VDDO is the output side supply voltage.
3
See Figure 5 for the maximum rated current values for various temperatures.
4
Refers to the common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings may
cause latch-up or permanent damage.
1
2
Table 15. Maximum Continuous Working Voltage1
Parameter
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Rating
Constraint
789 V peak
403 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
909 V peak
469 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
558 V peak
285 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Truth Table
Table 16. ADuM160N/ADuM161N/ADuM162N/ADuM163N Truth Table (Positive Logic)
VIx Input 1, 2
L
H
L
X4
VDDI State2
Powered
Powered
Unpowered
Powered
VDDO State2
Powered
Powered
Powered
Unpowered
Default Low (N0),
VOx Output1, 2, 3
L
H
L
Indeterminate
Default High (N1),
VOx Output1, 2, 3
L
H
H
Indeterminate
Test Conditions/Comments
Normal operation
Normal operation
Fail-safe output
Output Unpowered
L means low, H means high, and X means don’t care.
VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, E or F). VDDI and VDDO refer to the supply voltages on the input and output sides of the
given channel, respectively.
3
N0 refers to the ADuM160N0/ADuM161N0/ADuM162N0/ADuM163N0 models. N1 refers to the ADuM160N1/ADuM161N1/ADuM162N1/ADuM163N1 models. See the
Ordering Guide section.
4
Input pins (VIx) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.
1
2
Rev. A | Page 13 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16 VDD2
VIB 3
VIC 4
15 VOA
ADuM160N
14 VOB
VIE 6
13 VOC
TOP VIEW
(Not to Scale) 12 VOD
11 VOE
VIF 7
10 VOF
VID 5
GND1 8
9
GND2
14532-006
VIA 2
Figure 6. ADuM160N Pin Configuration
Table 17. ADuM160N Pin Function Descriptions
Pin No.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Mnemonic
VDD1
VIA
VIB
VIC
VID
VIE
VIF
GND1
GND2
VOF
VOE
VOD
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Logic Input E.
Logic Input F.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Logic Output F.
Logic Output E.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2.
Reference the AN-1109 Application Note for specific layout guidelines.
Rev. A | Page 14 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
VDD1 1
16 VDD2
VIA 2
VIB 3
VIC 4
VID 5
VIE 6
VOF 7
GND1 8
15 VOA
ADuM161N
14 VOB
13 VOC
TOP VIEW
(Not to Scale) 12 VOD
11 VOE
10 VIF
9
GND2
14532-007
Data Sheet
Figure 7. ADuM161N Pin Configuration
Table 18. ADuM161N Pin Function Descriptions
Pin No.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Mnemonic
VDD1
VIA
VIB
VIC
VID
VIE
VOF
GND1
GND2
VIF
VOE
VOD
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Logic Input E.
Logic Output F.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Logic Input F.
Logic Output E.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2.
Reference the AN-1109 Application Note for specific layout guidelines.
Rev. A | Page 15 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
VDD1 1
16 VDD2
VIA 2
VIC 4
VID 5
VOE 6
VOF 7
GND1 8
15 VOA
ADuM162N
14 VOB
13 VOC
TOP VIEW
(Not to Scale) 12 VOD
11 VIE
10 VIF
9
GND2
14532-008
VIB 3
Data Sheet
Figure 8. ADuM162N Pin Configuration
Table 19. ADuM162N Pin Function Descriptions
Pin No.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Mnemonic
VDD1
VIA
VIB
VIC
VID
VOE
VOF
GND1
GND2
VIF
VIE
VOD
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Logic Output E.
Logic Output F.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Logic Input F.
Logic Input E.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2.
Reference the AN-1109 Application Note for specific layout guidelines.
Rev. A | Page 16 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
VDD1 1
16 VDD2
VIA 2
VIB 3
VIC 4
VOD 5
VOE 6
VOF 7
GND1 8
15 VOA
ADuM163N
14 VOB
13 VOC
TOP VIEW
(Not to Scale) 12 VID
11 VIE
10 VIF
9
GND2
14532-009
Data Sheet
Figure 9. ADuM163N Pin Configuration
Table 20. ADuM163N Pin Function Descriptions
Pin No.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Mnemonic
VDD1
VIA
VIB
VIC
VOD
VOE
VOF
GND1
GND2
VIF
VIE
VID
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Logic Output E.
Logic Output F.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Logic Input F.
Logic Input E.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2.
Reference the AN-1109 Application Note for specific layout guidelines.
Rev. A | Page 17 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
Data Sheet
25
20
20
5
5V
3.3V
2.5V
1.8V
0
0
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
IDD1 SUPPLY CURRENT (mA)
20
5
5V
3.3V
2.5V
1.8V
0
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
Figure 11. ADuM160N IDD2 Supply Current vs. Data Rate at Various Voltages
60
80
100
DATA RATE (Mbps)
120
140
160
Figure 12. ADuM161N IDD1 Supply Current vs. Data Rate at Various Voltages
20
40
60
80
100
120
140
160
Figure 14. ADuM162N IDD1 Supply Current vs. Data Rate at Various Voltages
IDD2 SUPPLY CURRENT (mA)
40
160
DATA RATE (Mbps)
15
10
5
5V
3.3V
2.5V
1.8V
0
14532-012
20
140
5V
3.3V
2.5V
1.8V
0
5V
3.3V
2.5V
1.8V
0
120
0
20
0
100
5
20
5
80
10
25
10
60
15
25
15
40
Figure 13. ADuM161N IDD2 Supply Current vs. Data Rate at Various Voltages
20
10
20
DATA RATE (Mbps)
25
15
5V
3.3V
2.5V
1.8V
0
25
0
IDD1 SUPPLY CURRENT (mA)
5
0
14532-011
IDD2 SUPPLY CURRENT (mA)
Figure 10. ADuM160N IDD1 Supply Current vs. Data Rate at Various Voltages
10
14532-014
10
15
0
20
40
60
80
100
DATA RATE (Mbps)
120
140
160
14532-015
15
14532-013
IDD2 SUPPLY CURRENT (mA)
25
14532-010
IDD1 SUPPLY CURRENT (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. ADuM162N IDD2 Supply Current vs. Data Rate at Various Voltages
Rev. A | Page 18 of 23
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
14
25
10
5
5V
3.3V
2.5V
1.8V
0
0
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
10
8
6
4
5V
3.3V
2.5V
1.8V
2
0
–40
Figure 16. ADuM163N IDD1 Supply Current vs. Data Rate at Various Voltages
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
14532-018
PROPAGATION DELAY tPLH (ns)
15
14532-016
IDD1 SUPPLY CURRENT (mA)
12
20
Figure 18. Propagation Delay, tPLH vs. Temperature at Various Voltages
25
14
10
5
5V
3.3V
2.5V
1.8V
0
0
20
40
60
80
100
DATA RATE (Mbps)
120
140
160
10
8
6
4
5V
3.3V
2.5V
1.8V
2
0
–40
Figure 17. ADuM163N IDD2 Supply Current vs. Data Rate at Various Voltages
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
14532-019
PROPAGATION DELAY tPHL (ns)
15
14532-017
IDD2 SUPPLY CURRENT (mA)
12
20
Figure 19. Propagation Delay, tPHL vs. Temperature at Various Voltages
Rev. A | Page 19 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
THEORY OF OPERATION
The ADuM160N/ADuM161N/ADuM162N/ADuM163N use
a high frequency carrier to transmit data across the isolation
barrier using iCoupler chip scale transformer coils separated by
layers of polyimide isolation. Using an on/off keying (OOK)
technique and the differential architecture shown in Figure 20
and Figure 21, the ADuM160N/ADuM161N/ADuM162N/
ADuM163N have very low propagation delay and high speed.
Internal regulators and input/output design techniques allow
logic and supply voltages over a wide range from 1.7 V to 5.5 V,
offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic.
The architecture is designed for high common-mode transient
immunity and high immunity to electrical noise and magnetic
interference. Radiated emissions are minimized with a spread
spectrum OOK carrier and other techniques.
Data Sheet
Figure 20 shows the waveforms for models of the ADuM160N0/
ADuM161N0/ADuM162N0/ADuM163N0 that have the condition
of the fail-safe output state equal to low, where the carrier waveform is off when the input state is low. If the input side is off or
not operating, the fail-safe output state of low sets the output to
low. For the ADuM160N1/ADuM161N1/ADuM162N1/
ADuM163N1 that have a fail-safe output state of high, Figure 21
illustrates the conditions where the carrier waveform is off
when the input state is high. When the input side is off or not
operating, the fail-safe output state of high sets the output to
high. See the Ordering Guide for the model numbers that have
the fail-safe output state of low or the fail-safe output state of high.
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
GND1
14532-020
VOUT
GND2
Figure 20. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
GND1
GND2
Figure 21. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
Rev. A | Page 20 of 23
14532-021
VOUT
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
APPLICATIONS INFORMATION
PCB LAYOUT
JITTER MEASUREMENT
The ADuM160N/ADuM161N/ADuM162N/ADuM163N digital
isolators require no external interface circuitry for the logic
interfaces. Power supply bypassing is strongly recommended at
the input and output supply pins (see Figure 22). Bypass
capacitors are connected between Pin 1 and Pin 8 for VDD1 and
between Pin 9 and Pin 16 for VDD2. The recommended bypass
capacitor value is between 0.01 μF and 0.1 μF. The total lead
length between both ends of the capacitor and the input power
supply pin must not exceed 10 mm.
Figure 24 illustrates the eye diagram for the ADuM160N/
ADuM161N/ADuM162N/ADuM163N. The measurement was
taken using an Agilent 81110A pulse pattern generator at 150 Mbps
with pseudorandom bit sequences (PRBS) 2(n − 1), n = 14, for 5 V
supplies. Jitter was measured with the Tektronix Model 5104B
oscilloscope, 1 GHz, 10 GSPS with the DPOJET jitter and eye
diagram analysis tools. The result shows a typical measurement
on the ADuM160N/ADuM161N/ADuM162N/ADuM163N
with 490 ps p-p jitter.
5
4
VOLTAGE (V)
Figure 22. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
0
–10
14532-023
tPHL
Figure 23. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation
delay differs between channels within a single ADuM160N/
ADuM161N/ADuM162N/ADuM163N component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM160N/ADuM161N/
ADuM162N/ADuM163N components operating under the
same conditions.
5
10
INSULATION LIFETIME
50%
50%
0
Figure 24. ADuM160N/ADuM161N/ADuM162N/ADuM163N Eye Diagram
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
OUTPUT (VOx)
–5
TIME (ns)
PROPAGATION DELAY RELATED PARAMETERS
tPLH
2
1
See the AN-1109 Application Note for board layout guidelines.
INPUT (VIx)
3
14532-024
VDD2
VOA
VOB
VOC
VID/VOD
VIE/VOE
VIF/VOF
GND2
14532-022
VDD1
VIA
VIB
VIC
VID/VOD
VIE/VOE
VIF/VOF
GND1
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking,
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation, pollution degree, and material group. The material
Rev. A | Page 21 of 23
ADuM160N/ADuM161N/ADuM162N/ADuM163N
Data Sheet
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
Testing and modeling have shown that the primary driver of longterm degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as:
dc stress, which causes very little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltages. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out,
Equation 1 can be rearranged to solve for the ac rms voltage, as
is shown in Equation 2. For insulation wear out with the polyimide
materials used in these products, the ac rms voltage determines
the product lifetime.
VRMS = VAC RMS 2 + VDC 2
VAC RMS
VRMS
VPEAK
VDC
TIME
14532-025
Insulation Wear Out
ISOLATION VOLTAGE
group and creepage for the ADuM160N/ADuM161N/
ADuM162N/ADuM163N isolators are presented in Table 9.
Figure 25. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
VRMS = VAC RMS 2 + VDC 2
VRMS = 2402 + 4002
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
VAC RMS = VRMS 2 − VDC 2
VAC RMS = 4662 − 4002
(1)
VAC RMS = 240 V rms
or
VAC RMS = VRMS 2 − VDC 2
(2)
where:
VAC RMS is the time varying portion of the working voltage.
VRMS is the total rms working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms, a 400 V dc bus voltage is present on
the other side of the isolation barrier, and the isolator material
is polyimide. To establish the critical voltages in determining
the creepage, clearance and lifetime of a device, see Figure 25
and the following equations.
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 15 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Note that the dc working voltage limit in Table 15 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.
Rev. A | Page 22 of 23
Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
8
1.27 (0.0500)
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
6.20 (0.2441)
5.80 (0.2283)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0197)
0.25 (0.0098)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1
ADuM160N1BRZ
ADuM160N1BRZ-RL7
ADuM160N0BRZ
ADuM160N0BRZ-RL7
ADuM161N1BRZ
ADuM161N1BRZ-RL7
ADuM161N0BRZ
ADuM161N0BRZ-RL7
ADuM162N1BRZ
ADuM162N1BRZ-RL7
ADuM162N0BRZ
ADuM162N0BRZ-RL7
ADuM163N1BRZ
ADuM163N1BRZ-RL7
ADuM163N0BRZ
ADuM163N0BRZ-RL7
EVAL-5CH6CHSOICEBZ
EVAL-ADuM163N0EBZ
1
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
No. of
Inputs,
VDD1
Side
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
No. of
Inputs,
VDD2
Side
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
Withstand
Voltage
Rating
(kV rms)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
Z = RoHS Compliant Part.
©2016–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14532-0-6/19(A)
Rev. A | Page 23 of 23
Fail-Safe
Output
State
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
Package Description
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
Unpopulated Evaluation Board
Populated Evaluation Board
Package
Option
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
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