EVAL-ADV7403EBZ

Data Sheet 12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer ADV7403 FEATURES GENERAL DESCRIPTION 4 Noise Shaped Video (NSV)® 12-bit analog-to-digital converters (ADCs) sampling up to 140 MHz (140 MHz speed grade only) Mux with 12 analog input channels SCART fast blank support Internal antialias filters NTSC/PAL/SECAM color standards support 525p/625p component progressive scan support 720p/1080i component HDTV support Digitizes RGB graphics up to 1280 × 1024 at 75 Hz (SXGA) (140 MHz speed grade only) 24-bit digital input port supports data from DVI/HDMI receiver IC Any-to-any, 3 × 3 color-space conversion matrix Industrial temperature range: −40°C to +85°C 12-bit 4:4:4 and 10-/8-bit 4:2:2 DDR pixel output interface Programmable interrupt request output pin Vertical blanking interval (VBI) data slicer, including teletext The ADV7403 is a high quality, single chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-Video into a digital ITU-R BT.656 format. The ADV7403 also supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, and many other HD and SMPTE standards. Graphic digitization is also supported by the ADV7403; it is capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ability of the ADV7403 to simultaneously process CVBS and standard definition RGB signals. The fast blank pin controls the mixing of these signals. APPLICATIONS LCD/DLP™ rear projection HDTVs PDP HDTVs CRT HDTVs LCD/DLP front projectors LCD TV (HDTV ready) HDTV STBs with PVR Hard-disk-based video recorders Multiformat scan converters DVD recorders with progressive scan input support AVR receivers Rev. B The ADV7403 contains two main processing sections. The first is the standard definition processor (SDP), which processes all PAL, NTSC, and SECAM signal types, and the second is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. For additional descriptions of the features of the ADV7403, see the Functional Overview and the Theory of Operation sections. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7403 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Standard Definition Processor (SDP) Pixel Data Output Modes........................................................................................... 12 General Description ......................................................................... 1 Component Processor (CP) Pixel Data Output Modes ........ 12 Revision History ............................................................................... 2 Composite and S-Video Processing ......................................... 12 Functional Block Diagram .............................................................. 3 Component Video Processing .................................................. 12 Specifications..................................................................................... 4 RGB Graphics Processing ......................................................... 13 Electrical Characteristics ............................................................. 4 Digital Video Input Port ............................................................ 13 Video Specifications ..................................................................... 5 General Features ......................................................................... 13 Timing Characteristics ................................................................ 6 Theory of Operation ...................................................................... 14 Analog Specifications ................................................................... 8 Analog Front End ....................................................................... 14 Absolute Maximum Ratings ............................................................ 9 Standard Definition Processor (SDP)...................................... 14 Package Thermal Performance ................................................... 9 Component Processor (CP) ...................................................... 14 Thermal Resistance ...................................................................... 9 Pixel Input/Output Formatting .................................................... 16 ESD Caution .................................................................................. 9 Recommended External Loop Filter Components .................... 18 Pin Configuration and Function Descriptions ........................... 10 Typical Connection Diagram........................................................ 19 Functional Overview ...................................................................... 12 Outline Dimensions ....................................................................... 20 Analog Front End ....................................................................... 12 Ordering Guide .......................................................................... 20 REVISION HISTORY 9/13—Revision B: Initial Version Rev. B | Page 2 of 20 Figure 1. Rev. B | Page 3 of 20 05431-001 P40 TO P31 24 P29 TO P20 P11 TO P10 P1 TO P0 SOG SOY DE_IN HS_IN/CS_IN VS_IN DCLK_IN SCLK1 SCLK2 SDA1 SDA2 ALSB FB CVBS S-VIDEO YPrPb SCART– (RGB + CVBS) GRAPHICS RGB AIN1 12 TO AIN12 A/D ANTIALIAS FILTER CLAMP STDI DVI or HDMI DIGITAL INPUT PORT XTAL XTAL1 SSPD SYNC PROCESSING AND CLOCK GENERATION 8 8 8 A/D CLAMP A/D A/D ANTIALIAS FILTER ANTIALIAS FILTER SERIAL INTERFACE CONTROL AND VBI DATA INPUT MUX CLAMP CLAMP ANTIALIAS FILTER ADV7403 12 12 12 12 COLORSPACE CONVERSION 12 12 12 DECIMATION AND DOWNSAMPLING 12 FILTERS DATA PREPROCESSOR 12 12 12 Cb Cr C CVBS DIGITAL FINE CLAMP ACTIVE PEAK AND AGC CHROMA DEMOD RECOVERY fSC CVBS/Y MACROVISION DETECTION CHROMA RESAMPLE RESAMPLE CONTROL LUMA RESAMPLE CHROMA 2D COMB (4H MAX) LUMA 2D COMB (5H MAX) GAIN CONTROL OFFSET CONTROL CGMS DATA EXTRACTION Cb Cr Y Cb Cr Y AV CODE INSERTION FAST BLANK OVERLAY CONTROL AND AV CODE INSERTION VBI DATA RECOVERY COMPONENT PROCESSOR MACROVISION DETECTION CHROMA FILTER SYNC EXTRACT LUMA FILTER STANDARD AUTODETECTION STANDARD DEFINITION PROCESSOR 30 20 8 8 8 INT SFL/ SYNCOUT LLC1 FIELD/DE VS CS/HS PIXEL DATA P29 TO P20 P19 TO P10 P9 TO P0 Data Sheet ADV7403 FUNCTIONAL BLOCK DIAGRAM OUTPUT FIFO AND FORMATTER ADV7403 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. Operating temperature range, unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). To obtain all specifications the following write sequence must be included in the programming scripts: Address 0x0E to Data 0x80, Address 0x54 to Data 0x00, and Address 0x0E to Data 0x00. Table 1. Parameter STATIC PERFORMANCE 1 Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage 4 Input Low Voltage 5 Input High Voltage Input Low Voltage Input Current Symbol N INL DNL VIH VIL VIH VIL IIN Input Capacitance 6 DIGITAL OUTPUTS Output High Voltage 7 Output Low Voltage7 High Impedance Leakage Current CIN Output Capacitance6 POWER REQUIREMENTS6 Digital Core Power Supply Digital Input/Output Power Supply PLL Power Supply Analog Power Supply Digital Core Supply Current COUT VOH VOL ILEAK DVDD DVDDIO PVDD AVDD IDVDD Digital Input/Output Supply Current IDVDDIO PLL Supply Current IPVDD Test Conditions/Comments Min Best straight line (BSL) at 27 MHz at a 12-bit level BSL at 54 MHz at a 12-bit level BSL at 74 MHz at a 10-bit level BSL at 110 MHz at a 10-bit level BSL at 135 MHz at an 8-bit level 3 At 27 MHz at a 12-bit level At 54 MHz at a 12-bit level At 74 MHz at a 10-bit level At 110 MHz at a 10-bit level At 135 MHz at an 8-bit level3 Typ Max Unit ±2.0 12 2 ±8.02 Bits LSB −0.99/+2.52 LSB LSB LSB LSB LSB LSB LSB LSB LSB −2.0/+2.5 ±1.0 −3.0/+3.0 ±1.3 −0.7/+0.85 −0.75/+0.9 ±0.75 −0.7/+5.0 −0.8/+2.5 2 0.3 +60 V V V V µA +10 10 µA pF 0.4 60 10 20 V V µA µA pF 0.8 HS_IN, VS_IN low trigger mode HS_IN, VS_IN low trigger mode P20 to P29, P31 to P40, SCLK2, SDA2, DCLK_IN, DE_IN, RESET All other input pins ISOURCE = 0.4 mA ISINK = 3.2 mA INT, P20 to P29, SDA2 All other output pins 0.7 −60 −10 2.4 1.65 3.0 1.71 3.15 CVBS input sampling at 54 MHz Graphics RGB sampling at 135 MHz SCART RGB FB sampling at 54 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at 135 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at135 MHz Rev. B | Page 4 of 20 1.8 3.3 1.8 3.3 105 137 106 4 19 11 12 2 3.6 1.89 3.45 V V V V mA mA mA mA mA mA mA Data Sheet Parameter Analog Supply Current 8 Power-Down Current Green Mode Power-Down Power-Up Time ADV7403 Symbol IAVDD IPWRDN IPWRDNG TPWRUP Test Conditions/Comments CVBS input sampling at 54 MHz Graphics RGB sampling at 135 MHz SCART RGB FB sampling at 54 MHz Min Typ 99 242 269 2.25 16 20 Sync bypass function Max Unit mA mA mA mA mA ms All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%. Maximum INL and DNL specifications obtained with device configured for component video input. This specification is for the ADV7403KSTZ-140 only. 4 To obtain specified VIH level on the XTAL pin (Pin 38), program Subaddress 0x13 (write only) with 0x04 value. When Subaddress 0x13 is set to 0x00 value, VIH level on the XTAL pin = 1.2 V. 5 To obtain specified VIL level on the XTAL pin (Pin 38), program Subaddress 0x13 (write only) with 0x04 value. When Subaddress 0x13 is set to 0x00 value, VIL level on the XTAL pin (Pin 38) = 0.4 V. 6 Guaranteed by characterization. 7 VOH and VOL levels obtained using default drive strength value (0xD5) in Subaddress 0xF4. 8 Analog current measurements for CVBS made with only ADC0 are powered up; for RGB, only ADC0, ADC1, and ADC2 are powered up; and for SCART FB, all ADCs powered up. 1 2 3 VIDEO SPECIFICATIONS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). Guaranteed by characterization. Table 2. Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range fSC Subcarrier Lock Range Color Lock in Time Sync Depth Range 1 Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Accuracy Brightness Contrast 1 Symbol Test Conditions/Comments DP DG LNL CVBS input, modulated 5 step CVBS input, modulated 5 step CVBS input, 5 step Luma ramp Luma flat field Min 61 64 Typ Max 0.4 0.4 0.4 Degrees % % 64 65 60 dB dB dB −5 40 +5 70 ±1.3 60 20 5 200 200 2 100 HUE CL_AC 1 1 Nominal sync depth is 300 mV at 100% sync depth range. Rev. B | Page 5 of 20 % Hz kHz Lines % % Fields Lines 0.4 0.3 0.1 Degrees % % % Degrees % 1 1 % % 5 CVBS, 1 V input CVBS, 1 V input Unit 400 ADV7403 Data Sheet TIMING CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). Guaranteed by characterization. Table 3. Parameter SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency LLC1 Frequency Range 1 I2C PORT 2 SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transition Time SDR (SDP) 3 Symbol Typ 14.8 12.825 Max Unit ±50 110 140 MHz ppm kHz MHz 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 300 300 0.6 5 t9:t10 t11 t13 t14 Data Output Transition Time DDR (CP)4, 5 Min 28.63636 t12 Data Output Transition Time SDR (CP) 4 Test Conditions/Comments t15 t16 t17 t18 DATA and CONTROL INPUTS2 Input Setup Time (Digital Input Port) t19 Input Hold Time (Digital Input Port) t20 45:55 Negative clock edge to start of valid data End of valid data to negative clock edge End of valid data to negative clock edge Negative clock edge to start of valid data Positive clock edge to end of valid data Positive clock edge to start of valid data Negative clock edge to end of valid data Negative clock edge to start of valid data HS_IN, VS_IN DE_IN, data inputs HS_IN, VS_IN DE_IN, data inputs Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110. TTL input values are 0 V to 3 V with rise/fall times ≥ 3 ns measured between the 10% and 90% points. 3 SDP timing figures obtained using default drive strength value (0xD5) in Subaddress 0xF4. 4 CP timing figures obtained using maximum drive strength value (0xFF) in Subaddress 0xF4. 5 DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz. 1 2 Rev. B | Page 6 of 20 kHz µs µs µs µs ns ns ns µs ms 55:45 % duty cycle 3.6 ns 2.4 ns 2.8 ns 0.1 ns −4 + TLLC1/4 ns 0.25 + TLLC1/4 ns −2.95 + TLLC1/4 ns −0.5 + TLLC1/4 ns 9 2.2 7 2 ns ns ns ns Data Sheet ADV7403 Timing Diagram t3 t3 t5 SDA1/SDA2 t1 t6 t2 t7 05431-003 SCLK1/SCLK2 t8 t4 Figure 2. I2C Timing t10 t9 LLC1 t11 t12 05431-004 P0 TO P29, VS, HS, FIELD/DE, SFL/SYNC_OUT Figure 3. Pixel Port and Control SDR Output Timing (SD Core) t9 t10 LLC1 t13 05431-005 t14 P0 TO P29, VS, HS, FIELD/DE Figure 4. Pixel Port and Control SDR Output Timing (CP Core) LLC1 t16 t17 P6 TO P9, P10 TO P19 05431-006 t18 t15 Figure 5. Pixel Port and Control DDR Output Timing (CP Core) DCLK_IN t9 t20 HS_IN VS_IN DE_IN P0 TO P1, P10 TO P11, P20 TO P21, P22 TO P29, P31 TO P32, P33 TO P40 t19 Figure 6. Digital Input Port and Control Input Timing Rev. B | Page 7 of 20 05431-007 CONTROL INPUTS t10 ADV7403 Data Sheet ANALOG SPECIFICATIONS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p. Guaranteed by characterization. Table 4. Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance (Except the FB Pin, Pin 51) Input Impedance of Pin 51 (FB) CML ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Large Clamp Source Current Sink Current Fine Clamp Source Current Sink Current Test Conditions/Comments Clamps switched off CVBS input SCART RGB input (R, G, B signals) S-Video input (Y signal) S-Video input (C signal) Component input (Y, Pr, Pb signals) PC RGB input (R, G, B signals) SDP only Min Typ Max Unit 0.1 10 20 1.86 CML + 0.8 CML − 0.8 1.6 CML − 0.292 CML − 0.4 CML − 0.292 CML − 0 CML − 0.3 CML − 0.3 µF MΩ kΩ V V V V V V V V V V 0.75 0.9 mA mA 17 17 µA µA SDP only Rev. B | Page 8 of 20 Data Sheet ADV7403 ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 5. Parameter AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO to PVDD DVDDIO to DVDD AVDD to PVDD AVDD to DVDD Digital Inputs Voltage to DGND Digital Outputs Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 2.2 V 2.2 V 4V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +2 V DGND − 0.3 V to DVDDIO + 0.3 V DGND − 0.3 V to DVDDIO + 0.3 V AGND − 0.3 V to AVDD + 0.3 V 125°C To reduce power consumption when using the device, the user is advised to turn off any unused ADCs. Keep the junction temperature less than the maximum junction temperature (TJ MAX) of 125°C. The junction temperature is calculated by TJ = TA MAX + (θJA × WMAX) where: TA MAX = 85°C. θJA = 30°C/W. WMAX = ((AVDD × IAVDD)+(DVDD × IDVDD)+ (DVDDIO × IDVDDIO) + (PVDD × IPVDD)). THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. −65°C to +150°C 260°C Package Type 100-Lead LQFP Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 2 θJA1 30 θJC2 7 Unit °C/W It is a 4-layer printed circuit board (PCB) with a solid ground plane (still air). It is a 4-layer PCB with a solid ground plane. ESD CAUTION Rev. B | Page 9 of 20 ADV7403 Data Sheet 1 P31 2 P39 P40 SCLK1 SDA1 ALSB 83 82 81 80 AIN6 VS_IN 84 SOY HS_IN/CS_IN 85 77 P38 86 76 P37 87 DE_IN DGND 88 RESET DVDD 89 78 P19 91 90 79 P17 P16 94 P18 P36 95 92 P35 96 93 FIELD/DE P34 97 VS 98 P33 100 P32 99 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 75 AIN12 74 AIN5 INT 3 73 AIN11 CS/HS 4 72 AIN4 DGND 5 71 AIN10 DVDDIO 6 70 TEST0 P15 7 69 CAPC2 P14 8 68 CAPC1 P13 9 P12 10 ADV7403 67 BIAS 66 AGND DGND 11 65 CML DVDD 12 64 REFOUT LQFP TOP VIEW (Not to Scale) AVDD CAPY2 15 61 CAPY1 SCLK2 16 60 AGND DGND 17 59 TEST1 DVDDIO 18 58 AIN3 SDA2 19 57 AIN9 P11 20 56 AIN2 13 P28 14 SFL/SYNC_OUT 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DCLK_IN LLC1 XTAL1 XTAL DVDD DGND P3 P2 P1 P0 P20 ELPF PVDD PVDD AGND AGND 34 P21 33 P22 32 FB P23 51 31 25 30 SOG P7 P25 52 P24 24 29 AIN7 P27 P26 53 28 23 P4 AIN1 P8 27 AIN8 54 26 55 22 P6 21 P9 P5 P10 05431-002 63 62 P29 Figure 7. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1, 2, 83, 84, 87, 88, 95 to 97, 100 3 Mnemonic P31 to P40 Type 1 I Description Video Pixel Input Port. INT O 4 CS/HS O 5, 11, 17, 40, 89 6, 18 7 to 10, 22, 23, 25 to 28, 41, 42, 91 to 94 12, 39, 90 13, 14, 20, 21, 24, 29 to 34, 43 to 45 DGND DVDDIO P2 to P9, P12 to P19 G P O Interrupt. This pin can be active low or active high. When SDP/CP status bits change, this pin triggers. The set of events that triggers an interrupt is under user control. Digital Composite Synchronization Signal (CS). The CS pin can be selected while in CP mode. Horizontal Synchronization Output Signal (HS). The HS pin can be selected while in SDP or CP modes. Digital Ground. Digital Input/Output Supply Voltage (3.3 V). Video Pixel Output Port. DVDD P0 to P1, P10 to P11, P20 to P29 P I/O Digital Core Supply Voltage (1.8 V). Video Pixel Input/Output Port. Rev. B | Page 10 of 20 Data Sheet ADV7403 Pin No. 15 Mnemonic SFL/SYNC_OUT Type 1 O 16, 82 SCLK1, SCLK2 I 19, 81 SDA1, SDA2 I/O 35 DCLK_IN I 36 LLC1 O 37 XTAL1 O 38 XTAL I 46 47, 48 49, 50, 60, 66 51 52 53 to 58, 71 to 76 59 61, 62 63 64 65 67 ELPF PVDD AGND FB SOG AIN1 to AIN12 TEST1 CAPY1, CAPY2 AVDD REFOUT CML BIAS O P G I I I O I P O O O 68, 69 70 77 78 CAPC1, CAPC2 TEST0 SOY RESET I NC I I 79 DE_IN I 80 ALSB I 85 86 VS_IN HS_IN/CS_IN I I 98 FIELD/DE O 99 VS O 1 Description Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be used to lock the subcarrier frequency when the decoder is connected to any Analog Devices, Inc., digital video encoder. Sliced Sync Output Signal (SYNC_OUT). This pin is only available in CP mode. I2C Port Serial Clock Input (Maximum Clock Rate of 400 kHz) Pins. SCLK1 is the clock line for the control port, and SCLK2 is the clock line for the VBI data readback port. I2C Port Serial Data Input/Output Pins. SDA1 is the data line for the control port, and SDA2 is the data line for the VBI readback port. Clock Input Signal. This pin is used in 24-bit digital input mode (for example, processing 24-bit RGB data from a DVI receiver IC) and also in digital CVBS input mode. Line-Locked Output Clock for Pixel Data. This pin range is 12.825 MHz to 140 MHz for the ADV7403KSTZ-140, and 12.825 MHz to 110 MHz for the ADV7403BSTZ-110. Connect this pin to the 28.63636 MHz crystal, or if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7403, leave this pin as no connect. In crystal mode, the crystal must be a fundamental crystal. Input Pin for 28.63636 MHz crystal. To clock the ADV7403, this pin can also be overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source. External Loop PLL Filter. Connect the recommend external loop filter to the ELPF pin. PLL Supply Voltage (1.8 V). Analog Ground. Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals. Sync on Green Input. This pin is used in embedded sync mode. Analog Video Input Channels. Leave this pin unconnected. ADC Capacitor Network. Analog Supply Voltage (3.3 V). Internal Voltage Reference Output. Common-Mode Level (CML) Pin for theInternal ADCs. External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ) between the BIAS pin and ground. ADC Capacitor Network. Leave this pin unconnected, or alternately, tie this pin to AGND. Sync on Luma Input. This pin is used in embedded sync mode. System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to reset the circuitry of the ADV7403. Data Enable Input Signal. This pin is used in 24-bit digital input port mode (for example, processing 24-bit RGB data from a DVI receiver IC). This pin selects the I2C device address for the control and VBI readback ports of the ADV7403. When ALSB is set to Logic 0, it sets the address for a write to the control port to Address 0x40 and the readback address for the VBI port to Address 0x21. When ALSB is set to Logic 1, it sets the address for a write to the control port to Address 0x42 and the readback address for the VBI port to Address 0x23. VS Input Signal. This pin is used in CP mode for 5-wire timing mode. Can be configured in CP mode to be either a digital HS input signal or a digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode. Field Synchronization Output Signal for All Interlaced Video Modes (FIELD). This is a multifunction pin. It can also be enabled as a data enable signal (DE) in CP mode to allow direct connection to a HDMI/DVI transmitter IC. Vertical Synchronization Output Signal (SDP and CP Modes). G = ground, P = power, I = input, O = output, I/O = input/output, and NC = no connect. Rev. B | Page 11 of 20 ADV7403 Data Sheet FUNCTIONAL OVERVIEW The following overview provides a brief description of the functionality of the ADV7403. More details are available in the Theory of Operation section. ANALOG FRONT END The analog front end of the ADV7403 provides four 140 MHz (ADV7403KSTZ-140), NSV, 12-bit ADCs to enable 10-bit video decoding, a multiplexer with 12 analog input channels to enable multisource connection without the requirement of an external multiplexer, and four current and voltage clamp control loops to ensure that dc offsets are removed from the video signal. SCART functionality and standard definition RGB overlay with CVBS are controlled by the fast blank input. This front end also features four antialias filters to remove out-of-band noise on standard definition input video signals. STANDARD DEFINITION PROCESSOR (SDP) PIXEL DATA OUTPUT MODES The ADV7403 features the following SDP output modes: The ADV7403 also features chroma transient improvement (CTI) and luminance digital noise reduction (DNR), as well as teletext, closed captioning (CC), extended data service (EDS), and wide-screen signaling (WSS). It offers certified Macrovision® copy protection detection on composite and S-Video for all worldwide formats (PAL/NTSC/SECAM), and a copy generation management system (CGMS). Other features include 4× oversampling (54 MHz) for CVBS, S-Video, and YUV modes; line-locked clock output (LLC); vertical interval time codes (VITC); support for letterbox detection; a free-run output mode for stable timing when no video input is present; clocking from a single 28.63636 MHz crystal; Gemstar™ 1×/2× electronic program guide compatible; and subcarrier frequency lock (SFL) output for downstream video encoders. In addition, the device has color controls for hue, brightness, saturation, and contrast and controls for Cr and Cb offsets. The ADV7403 also incorporates a vertical blanking interval data processor and a video programming system (VPS) on the device. • 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD The differential gain of the ADV7403 is 0.4% typical, and the differential phase is 0.4° typical. • 16-/20-bit YCrCb with embedded time codes and/or HS, VS, and FIELD COMPONENT VIDEO PROCESSING • 24-/30-bit YCrCb with embedded time codes and/or HS, VS, and FIELD COMPONENT PROCESSOR (CP) PIXEL DATA OUTPUT MODES The ADV7403 features two single data rate (SDR) outputs: 16-/20-bit 4:2:2 YCrCb for all standards, and 24-/30-bit 4:4:4 YCrCb/RGB for all standards. The ADV7403 also features two double data rate (DDR) outputs: 8-/10-bit 4:2:2 YCrCb for all standards, and 12-bit 4:4:4 YCrCb/RGB for all standards. The ADV7403 supports 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats. It provides automatic adjustments for gain (contrast) and offset (brightness), as well as manual adjustment controls. Furthermore, the ADV7403 not only supports analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, and CS, but also supports YCrCb-to-RGB and RGB-to-YCrCb conversions by any-to-any, 3 × 3 color-space conversion matrices. Standard identification (STDI) enables detection of the component format at the system level, and a synchronization source polarity detector (SSPD) determines the source and polarity of the synchronization signals that accompany the input video. COMPOSITE AND S-VIDEO PROCESSING The ADV7403 supports NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N, Nc, 60), and SECAM (B, D, G, K, L) standards for CVBS and S-Video formats. Superadaptive 2D, 5-line comb filters for NTSC and PAL provide superior chrominance and luminance separation for composite video. The composite and S-Video processing functionalities also include fully automatic detection of switching among worldwide standards (PAL/NTSC/SECAM); automatic gain control (AGC) with white peak mode to ensure that the video is processed without compromising the video processing range; adaptive digital line length tracking (ADLLT™); and proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners. The IF filter block compensates for high frequency luma attenuation due to the tuner SAW filter. Certified Macrovision copy protection detection is available on component formats (525i, 625i, 525p, and 625p). When no video input is present, free-run output mode provides stable timing. The ADV7403 also supports arbitrary pixel sampling for nonstandard video sources. Rev. B | Page 12 of 20 Data Sheet ADV7403 RGB GRAPHICS PROCESSING DIGITAL VIDEO INPUT PORT The ADV7403 provides 140 MSPS conversion rate support of RGB input resolutions up to 1280 × 1024 at 75 Hz (SXGA) and 110 MSPS conversion rate for the ADV7403BSTZ-110. It also provides automatic or manual clamp and gain controls for graphics modes. The ADV7403 supports raw 8-/10-bit CVBS data from a digital tuner and 24-bit RGB input data from a DVI receiver chip, output converted to YCrCb 4:2:2. It also supports 24-bit 4:4:4, 16-/20-bit 4:2:2 525i, 625i, 525p, 625p, 1080i, 720p, VGA to SXGA at 60 Hz input data from HDMI receiver chip, output converted to 16-bit 4:2:2 YCrCb. The RGB graphics processing functionality features contrast and brightness controls, automatic detection of synchronization source and polarity by the SSPD block, standard identification enabled by the STDI block, and arbitrary pixel sampling support for nonstandard video sources. Additional RGB graphics processing features of the ADV7403 include the following: • • • 32-phase DLL support of optimum pixel clock sampling. Color-space conversion of RGB to YCrCb and decimation to a 4:2:2 format for videocentric back-end IC interfacing. Data enable (DE) output signal supplied for direct connection to the HDMI/DVI transmitter IC. GENERAL FEATURES The ADV7403 features HS, VS, and FIELD output signals with programmable position, polarity, and width. It also includes a programmable interrupt request output pin (INT), signals SDP/CP status changes, and supports two I2C host port interfaces (control and VBI). The ADV7403 offers low power consumption: 1.8 V digital core, 3.3 V analog and digital input/output, low power powerdown mode, and green PC mode. The ADV7403BSTZ-110 operates over the industrial temperature range (−40°C to +85°C) and is available in a 100-lead, 14 mm × 14 mm, RoHS-compliant LQFP. It is also available in a 140 MHz speed grade (ADV7403KST-140). Rev. B | Page 13 of 20 ADV7403 Data Sheet THEORY OF OPERATION ANALOG FRONT END The ADV7403 analog front end comprises four noise shaped video (NSV®), 12-bit ADCs that digitize the analog video signal before applying it to the standard definition processor (SDP) or component processor (CP). See Table 8 for the maximum sampling rates. The analog front end uses differential channels to each ADC to ensure high performance in a mixed signal application. The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7403. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping either in the CP or SDP. Optional antialiasing filters are positioned in front of each ADC. These filters can be used to band-limit standard definition video signals, removing spurious, out-of-band noise. The ADCs are configured to run in 4× oversampling mode when decoding composite and S-Video inputs; 2× oversampling is performed for component 525i, 625i, 525p, and 625p sources. All other video standards are 1× oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing filters with the benefit of an increased signal-tonoise ratio (SNR). The ADV7403 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed and output under control of I2C registers and the fast blank pin. Table 8. Maximum ADC Sampling Rates Model ADV7403BSTZ-110 ADV7403KSTZ-140 Maximum ADC Sampling Rate (MHz) 110 140 STANDARD DEFINITION PROCESSOR (SDP) The SDP section is capable of decoding a large selection of baseband video signals in composite S-Video and YUV formats. The video standards supported by the SDP include PAL (B, D, I, G, H, M, N, Nc, 60), NTSC (J, M, 4.43), and SECAM (B, D, G, K, L). The ADV7403 can automatically detect the video standard and process it accordingly. The SDP has a super adaptive 2-D, 5-line comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. The SDP has an IF filter block that compensates for attenuation in the high frequency luma spectrum due to the tuner SAW filter. The SDP has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. The ADV7403 implements a patented adaptive digital line length tracking (ADLLT™) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7403 to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The SDP also contains a chroma transient improvement (CTI) processor. This processor increases the edge rate on chroma transitions, resulting in a sharper video image. The SDP can process a variety of VBI data services, such as TeleText, closed captioning (CC), wide screen signaling (WSS), video programming system (VPS), vertical interval time codes (VITC), copy generation management system (CGMS), Gemstar 1×/2×, and extended data service (XDS). The ADV7403 SDP section has a Macrovision 7.1 detection circuit that allows it to detect Types I, II, and III protection levels. The decoder is also fully robust to all Macrovision signal inputs. COMPONENT PROCESSOR (CP) The CP section is capable of decoding/digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, VGA up to SXGA at 75 Hz (ADV7403KSTZ-140 only), and many other standards not listed here. The CP section of the ADV7403 contains an AGC block. When no embedded sync is present, the video gain can be set manually. The AGC section is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness); manual adjustment controls are also supported. A fully programmable any-to-any, 3 × 3 color space conversion matrix is placed between the analog front end and the CP section. This enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color space converter. The output section of the CP is highly flexible. It can be configured in SDR with one data packet per clock cycle or in a DDR mode where data is presented on the rising and falling edges of the clock. In SDR mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. In these modes, HS, VS, and FIELD/DE (where applicable) timing reference signals are provided. In DDR mode, the ADV7403 can be configured in an 8-/10-bit 4:2:2 YcrCb or 12-bit 4:4:4 YcrCb/RGB pixel output interface with corresponding timing signals. Rev. B | Page 14 of 20 Data Sheet ADV7403 The ADV7403 is capable of supporting an external DVI/HDMI receiver. The digital interface expects 24-bit 4:4:4 or 16-/20-bit 4:2:2 bit data (either graphics RGB or component video YcrCb), accompanied by HS, VS, DE, and a fully synchronous clock signal. The data is processed in the CP and output as 16-bit 4:2:2 YcrCb data. VBI extraction of CGMS data is performed by the CP section of the ADV7403 for interlaced, progressive, and high definition scanning rates. The data extracted can be read back over the I2C interface. For more detailed product information, see the ADV7403 product page. The CP section contains circuitry to enable the detection of Macrovision encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals. Rev. B | Page 15 of 20 ADV7403 Data Sheet PIXEL INPUT/OUTPUT FORMATTING Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0) Processor Mode SDP SDP SDP SDP SDP SDP SM-SDP CP CP CP CP CP CP CP SM-CP SM-CP SM-CP Format Video out, 8-bit, 4:2:2 Video out, 10-bit, 4:2:2 Video out, 16-bit, 4:2:2 Video out, 20-bit, 4:2:2 Video out, 24-bit, 4:4:4 Video out, 30-bit, 4:4:4 Digital tuner input[1] 8-bit, 4:2:2, DDR 10-bit, 4:2:2, DDR 12-bit, 4:4:4, RGB DDR Video out, 16-bit, 4:2:2 Video out, 20-bit, 4:2:2 Video out, 24-bit, 4:4:4 Video out, 30-bit, 4:4:4 HDMI receiver support, 24-bit, 4:4:4 input HDMI receiver support 16-bit pass through HDMI receiver support, 20-bit, pass through Pixel Port Pins P[19:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 YcrCb[7:0]OUT YcrCb[9:0]OUT Y[7:0]OUT CrCb[7:0]OUT Y[9:0]OUT CrCb[9:0]OUT Y[7:0]OUT Cb[7:0]OUT Y[9:0]OUT Cb[9:0]OUT Output choices are the same as video out 16-/20-bit or pseudo 8-/10-bit DDR D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 CHA[7:0]OUT (for example, Y[7:0]) CHB/C[7:0]OUT (for example, Cr/Cb[7:0]) CHA[9:0]OUT (for example, Y[9:0]) CHB/C[9:0]OUT (for example, Cr/Cb[9:0]) CHA[7:0]OUT (for example, G[7:0]) CHB[7:0]OUT (for example, B[7:0]) CHA[9:0]OUT (for example, G[9:0]) CHB[9:0]OUT (for example, B[9:0]) CHA[7:0]OUT (for example, Y[7:0]) R[5:4]IN CHB/C[7:0]OUT (for example, Cr/Cb[7:0]) R[1:0]IN CHA[7:0]OUT (for example, Y[7:0]) CHA[9:0]OUT (for example, Y[9:0]) Rev. B | Page 16 of 20 CHB/C[7:0]OUT (for example, Cr/Cb[7:0]) CHB/C[9:0]OUT (for example, Cr/Cb[9:0]) Data Sheet ADV7403 Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20) Processor Mode SDP SDP SDP SDP SDP SDP SM-SDP CP Format Video out, 8-bit, 4:2:2 Video out, 10-bit, 4:2:2 Video out, 16-bit, 4:2:2 Video out, 20-bit, 4:2:2 Video out, 24-bit, 4:4:4 Video out, 30-bit, 4:4:4 Digital tuner input[1] 8-bit, 4:2:2, DDR CP 10-bit, 4:2:2, DDR CP CP CP CP 12-bit, 4:4:4, RGB DDR Video out, 16-bit, 4:2:2 Video out, 20-bit, 4:2:2 Video out, 24-bit, 4:4:4 input Video out, 30-bit, 4:4:4 input HDMI receiver support, 24-bit, 4:4:4 input HDMI receiver support, 16-bit, pass through HDMI receiver support, 20-bit, pass through CP SM-CP SM-CP SM-CP Pixel Port Pins P[40:31], P[29:20] 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 20 Cr[7:0]OUT Cr[9:0]OUT DCVBS[9:0]IN CHC[7:0]OUT (for example, R[7:0]) CHC[9:0]OUT (for example, R[9:0]) G[7:0]IN R[7:6]IN CHA[7:0]IN(for example, Y[7:0]) CHA[9:0]IN(for example, Y[9:0]) Rev. B | Page 17 of 20 B[7:0]IN R[3:2]IN CHB/C[7:0]IN(for example, Cr/Cb[7:0]) CHB/C[9:0]IN(for example, Cr/Cb[9:0]) ADV7403 Data Sheet RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS Place the external loop filter components for the ELPF pin as close as possible to the respective pins. Figure 8 shows the recommended component values. PIN 46–ELPF 1.69kΩ 10nF PVDD = 1.8V 05431-008 82nF Figure 8. ELPF Components Rev. B | Page 18 of 20 Rev. B | Page 19 of 20 05431-009 RGB GRAPHICS F_BLNK BLUE GREEN RED/C 3 1LOAD AGND 2 4 19Ω 75Ω AGND 10nF Y C AGND 19Ω AGND Y 0.1 µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 75Ω Pb/Pr 75Ω 0.1µF 75Ω Pr/Pb 56Ω CAP VALUES ARE DEPENDANT ON CRYSTAL ATTRIBUTES 56Ω 1 2 3 4 0.1µF MINI-DIN-4 1 P7 1 2 3 4 5 6 20 CVBS/Y 16 2 11 15 75Ω PHONO3 AGND RED S-VIDEO 19 17 15 13 11 9 7 5 3 1 75Ω GREEN BLUE CVBS 19Ω P9 P8 20 18 16 14 12 10 8 6 4 2 21 P4 SCART_21_PIN P5–14 P6–5 P6–6 P5–7 P5–8 P5–10 HS_IN VS_IN P5–13 P5–1 P5–3 P5–2 75Ω AGND 75Ω 0.1 µF 75Ω 0.1µF AGND 10nF AGND AGND 0.1 µF 0.1 µF 5.6kΩ Y2 SDA 10nF 47pF1 RESET SCLK 47pF1 1MΩ 0.1 µF 0.1 µF C22 1nF + 10 µF 1nF D1 BZX399-C3V3 100Ω 100Ω 1.69kΩ 82nF PVDD_1.8V AGND + 10 µF C94 10nF DGND 0.1 µF U1 BYPASS CAPACITORS 10nF DVDD_1.8V 0.1 µF 28.63636MHz 10nF 10nF DGND 0.1 µF DVDDIO 10 µF 10 µF 10nF 0.1 µF 0.1 µF DGND 0.1 µF 10nF U1 BYPASS CAPACITORS 2.7k Ω DVDDIO AIN4 AIN5 AIN6 SOY SOG AIN1 AIN2 AIN3 ELPF RESET 59 TEST1 51 FB 78 19 SDA2 16 SCLK2 80 ALSB 81 SDA 82 SCLK 46 38 XTAL 37 XTAL1 DVDD_1.8V AVDD_3.3V PVDD_1.8V 10nF 65 CML 64 REFOUT 67 BIAS 62 CAPY2 61 CAPY1 69 68 CAPC2 CAPC1 53 AIN7 55 AIN8 57 AIN9 71 AIN10 73 AIN11 75 AIN12 72 74 76 77 52 54 56 58 U1 0.1 µF AGND 100Ω 100Ω 100Ω 100Ω 100Ω 33Ω 15 LLC1 DGND BAT54C K2 VP19 VP18 VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10 VP09 VP08 VP07 VP06 VP05 VP04 VP03 VP02 VP01 VP00 VP29 VP28 VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20 10kΩ DVDDIO 100Ω 36 CS/HS 4 VS 99 FIELD 98 HS_IN/CS_IN 86 VS_IN85 K1 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 91 92 93 94 7 8 9 10 20 21 22 23 25 26 27 28 41 42 43 44 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 VP41 VP40 VP39 VP38 VP37 VP36 VP35 VP34 VP33 VP32 VP31 VP30 VP[00:41] SFL/SYNC_OUT HS VS FIELD HS_IN VS_IN LLC1 INT DCLCK_IN 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω 35 79 83 84 87 88 95 96 97 100 1 2 3 13 14 24 29 30 31 32 33 34 45 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 DCLK_IN DE_IN P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 INT DVDDIO SFL/SYNC_OUT ADV7403 AVDD 63 49 PVSS 50 PVSS PVDD_1.8V 2.7k Ω DVDD 12 DVDD 39 90 DVDD 5 DGND 17 DGND 6 DVDDIO 18 DVDDIO AVDD_3.3V 47 PVDD PVDD 48 70 TEST0 66 AGND 60 AGND Figure 9. ADV7403 Typical Connection Diagram 11 DGND 40 DGND 89 DGND U1 BYPASS CAPACITORS Data Sheet ADV7403 TYPICAL CONNECTION DIAGRAM ADV7403 Data Sheet OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 51 50 25 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BED 051706-A 1.45 1.40 1.35 Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADV7403BSTZ-110 ADV7403KSTZ-140 EVAL-ADV7403EBZ Temperature Range −40°C to +85°C 0°C to 70°C Package Description 100-Lead Low Profile Quad Flat Package [LQFP] 100-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Package Option ST-100 ST-100 The ADV7403 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and is able to withstand surface-mount soldering at up to 255°C (±5°C). In addition, it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220°C to 235°C. 2 Z = RoHS Compliant Part. 1 ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05431-0-9/13(B) Rev. B | Page 20 of 20