EVAL-ADV7613FEBZ

ADV7613 Reference Manual UG-907 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Low Power, HDMI to Dual Output LVDS Display Bridge SCOPE This reference manual provides a detailed description of the ADV7613 functionality and features. Full specifications on the ADV7613 are available in the product data sheet, available from Analog Devices, Inc. The data sheet must be consulted in conjunction with this reference manual when working with the ADV7613. FUNCTIONAL BLOCK DIAGRAM REFERENCE CLOCK DIGITAL CLOCK SYNTHESIS PACKET INFOFRAME MEMORY AUDIO PACKET PROCESSOR AUDIO INTERFACE AUDIO OUTPUT INT DDC CABLE EQUALIZER EDID CONTROL HDMI PROCESSOR HDCP KEYS HOST I/F CONFIGURATION AND CONTROL COMPONENT PROCESSOR OpenLDI ENCODER LVDS Tx LVDS Tx I2C SLAVE RESET Figure 1. Functional Block Diagram PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. DUAL LVDS Tx OUTPUT Rev. A | Page 1 of 168 13807-001 HDMI UG-907 ADV7613 Reference Manual TABLE OF CONTENTS Scope .................................................................................................. 1 Audio Control and Configuration ........................................... 41 Functional Block Diagram .............................................................. 1 Audio FIFO ................................................................................. 43 Revision History ............................................................................... 3 Audio Packet Type Flags ........................................................... 45 Using the ADV7613 Reference Manual......................................... 4 Audio Output Interface ............................................................. 47 Number Notations ........................................................................ 4 MCLKOUT Setting .................................................................... 54 Field Function Descriptions ........................................................ 4 Audio Channel Mode ................................................................ 55 References ...................................................................................... 4 Audio Muting.............................................................................. 55 Introduction to the ADV7613 ........................................................ 5 Audio Clock Regeneration Parameters ................................... 59 HDMI Receiver ............................................................................. 5 Channel Status ............................................................................ 61 Component Processor ................................................................. 5 Packets and InfoFrames Registers ............................................ 65 Main Features of the ADV7613 .................................................. 5 Packet Registers .......................................................................... 71 Functional Block Diagram .......................................................... 6 Customizing Packet/InfoFrame Storage Registers ................. 75 Pin Configuration and Function Descriptions......................... 7 Repeater Support ........................................................................ 77 Global Control Registers ................................................................. 9 Interface to DPP Section ........................................................... 83 ADV7613 Revision Identification .............................................. 9 Power-Down Controls ................................................................. 9 Color Space Information Sent to the DPP and CP Sections ................................................................................. 84 Global Pin Control ..................................................................... 11 Status Registers ........................................................................... 85 Primary Mode and Video Standard ............................................. 13 HDMI Section Reset Strategy ................................................... 88 Primary Mode and Video Standard Controls......................... 13 HDMI Packet Detection Flag Reset ......................................... 88 HDMI Decimation Modes ........................................................ 15 Data Preprocessor, Color Space Conversion, and Color Controls ................................................................................ 89 Primary Mode and Video Standard Configuration for HDMI Free Run .......................................................................... 15 Color Space Conversion Matrix ............................................... 89 Recommended Settings for HDMI Inputs .............................. 15 Color Controls ............................................................................ 98 HDMI Receiver ............................................................................... 17 Component Processor ................................................................. 100 +5 V Cable Detect ...................................................................... 17 Introduction to the Component Processor........................... 100 Hot Plug Assert ........................................................................... 18 Clamp Operation ...................................................................... 100 E-EDID/Repeater Controller .................................................... 20 CP Gain Operation .................................................................. 102 E-EDID Data Configuration ..................................................... 20 CP Offset Block ........................................................................ 106 Transitioning of Power Modes.................................................. 21 CP Data Path for HDMI Modes ............................................. 107 Structure of Internal E-EDID for Port A ................................. 21 Sync Processed by CP Section ................................................ 110 TMDS Equalization .................................................................... 22 Free Run Mode ......................................................................... 117 Port Selection .............................................................................. 22 CP Status .................................................................................... 121 TMDS Clock Activity Detection .............................................. 23 CP Core Bypassing ................................................................... 121 HDMI/DVI Status Bits .............................................................. 23 Consumer Electronics Control ................................................... 122 Video 3D Detection ................................................................... 24 Main Controls ........................................................................... 122 TMDS Measurement .................................................................. 24 CEC Transmit Section ............................................................. 123 Video FIFO .................................................................................. 27 CEC Receive Section ................................................................ 125 Pixel Repetition ........................................................................... 29 Antiglitch Filter Module .......................................................... 131 HDCP Support ........................................................................... 30 Typical Operation Flow ........................................................... 131 HDMI Synchronization Parameters ........................................ 34 Low Power CEC Message Monitoring ................................... 134 Rev. A | Page 2 of 168 ADV7613 Reference Manual UG-907 Interrupts ....................................................................................... 136 LVDS Output Modes ................................................................162 Interrupt Architecture Overview ........................................... 136 OpenLDI Bitmapping with 6-Bit Color Depth .....................162 Interrupt Pins ............................................................................ 140 OpenLDI Bitmapping with 8-Bit Color Depth .....................163 Description of Interrupt Bits .................................................. 141 Alternative Bitmapping (8-Bit Color Depth Only) ..............163 Additional Explanations .......................................................... 143 Polarity of Video Timing Control Bits ...................................164 Register Access and Serial Ports Description ........................... 157 Reserved Bit Control ................................................................164 Main I C Port ............................................................................ 157 LVDS Transmitter Readback Registers ..................................165 DDC Ports ................................................................................. 160 LVDS Output Formatter ..........................................................166 LVDS Transmitters ....................................................................... 161 PCB Layout Recommendations ..................................................167 Introduction .............................................................................. 161 Power Supply Bypassing ...........................................................167 Configuring the LVDS Transmitter ....................................... 161 Digital Outputs (Data and Clocks) .........................................167 Enabling the LVDS Transmitter ............................................. 161 Digital Inputs .............................................................................167 PLL Gear Selection................................................................... 161 XTAL and Load Cap Value Selection .....................................168 2 REVISION HISTORY 6/2017—Rev. 0 to Rev. A Changes to Figure 4.........................................................................17 Changes to Introduction Section ...............................................161 Changes to LVDS Output Formatter Section, TX_PIXEL_SWAP, OpenLDI Tx, Address 0x4E[4] Section, Table 443, and Table 444 ..............................................................166 3/2016—Revision 0: Initial Version Rev. A | Page 3 of 168 UG-907 ADV7613 Reference Manual USING THE ADV7613 REFERENCE MANUAL NUMBER NOTATIONS Table 1. Notation Bit N V[x:y] 0xNN 0bNN NN Description Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0. Bit field representation covering Bit x to Bit y of a value or a field (V). Hexadecimal (base 16) numbers are preceded by the prefix 0x. Binary (base 2) numbers are preceded by the prefix 0b. Decimal (base 10) are represented using no additional prefixes or suffixes. FIELD FUNCTION DESCRIPTIONS Throughout this reference manual, a series of function tables are provided. The function of a field is described in a table preceded by the bit name, a short function description, the I2C map, the register location within the I2C map, and a detailed description of the field. The detailed description consists of the following: • • The values that can be read back from the field (for a readable field) The values that the field can be set to (for a writable field) Example Field Function Description The following is an example of a field function table followed by a description of each part of the table. PRIM_MODE[3:0], IO Map, Address 0x01[3:0] This register is a control for selecting the primary mode of operation of the device. Table 2. PRIM_MODE Function Description PRIM_MODE[3:0] 0000 0001 0010 0011 0100 0101 0110 (default) 0111 to 1111 Description Reserved Reserved Reserved Reserved Reserved HDMI component HDMI graphics Reserved In this example, the name of the field is PRIM_MODE and it is four bits long. Address 0x01 is the I2C location of the field in big endian format (MSB first, LSB last). The address is followed by a detailed description of the field. The first column of the table lists values the field can take or can be set to. These values are in binary format if not preceded by 0x or in hexadecimal format if preceded by 0x. The second column describes the function of each field for each value the field can take or can be set to. Values are in binary format. REFERENCES CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006. Digital Content Protection (DCP) LLC, High-Bandwidth Digital Content Protection System, Revision 1.4, July 8, 2009. HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010. ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998. Rev. A | Page 4 of 168 ADV7613 Reference Manual UG-907 INTRODUCTION TO THE ADV7613 The ADV7613 is a high quality, low power, single-input, high-definition multimedia interface (HDMI) to LVDS display bridge. The ADV7613 incorporates a single-input HDMI receiver that supports high definition television (HDTV) formats up to 1080p, 8 bits per channel. The ADV7613 also integrates a consumer electronics control (CEC) controller that supports the capability discovery and control (CDC) feature. Each HDMI port has dedicated 5 V detect and hot plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures robust operation of the interface with long cables. Fabricated in an advanced CMOS process, the ADV7613 is provided in a 9 mm × 9 mm, 100-ball CSP_BGA, RoHS-compliant package and is specified over the −40°C to +85°C temperature range. HDMI RECEIVER The HDMI receiver on the ADV7613 supports 2.25 Gbps data bandwidth. The ADV7613 HDMI receiver incorporates active equalization of the HDMI data signals to compensate for the losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. The equalizer is highly effective and is capable of equalizing for long cables to achieve robust receiver performance. With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7613 allows a video receiver to authenticate, decrypt encoded data, and renew that authentication during transmission, as specified by the HDCP v1.4 protocol for both the active and background HDMI ports. The ADV7613 offers a flexible audio output port for audio data extraction from the HDMI stream. HDMI audio formats, including super audio CD (SACD) via Direct Stream Digital® (DSD) and high bit rate (HBR), are supported by the ADV7613. The HDMI receiver has advanced audio functionality, such as a mute controller, which prevents audible extraneous noise in the audio output. COMPONENT PROCESSOR The ADV7613 contains a component processor (CP), which processes the video data up to 1080p. The CP section provides color adjustment features, such as brightness, saturation, and hue. The color space conversion (CSC) matrix allows the color space to be changed as required. The standard detection and identification (STDI) block allows the detection of video timings. MAIN FEATURES OF THE ADV7613 HDMI Receiver The HDMI receiver supports the following features: • • • • • • • • • HDMI features supported • 148.5 MHz maximum transition minimized differential signaling (TMDS) clock frequency • Full colorimetry including sYCC601, Adobe RGB, Adobe YCC601, xvYCC extended gamut color • CEC 1.4 compatible HDCP 1.4 support Supports all display resolutions up to 1920 × 720 at 60 Hz, 8-bit Supports many audio formats including DSD, HBR, S/PDIF (IEC60958 compatible) with sampling frequency up to 192 kHz Programmable front-end equalization for long cable lengths Audio mute for removing extraneous noise Programmable interrupt generator to detect HDMI packets Internal extended display identification (EDID) support Repeater support, up to 127 key selection vectors (KSVs) Component Video Processing The ADV7613 supports the following component video processing features: • • • • An any-to-any 3 × 3 CSC matrix support YCrCb to RGB and RGB to YCrCb Provides color controls, such as saturation, brightness, hue, and contrast Standard detection and identification (STDI) block that enables format detection Free run output mode provides stable timing when no video input is present Video Output Formats The ADV7613 outputs the following LVDS video formats: VESA mapping and OpenLDI mapping. Rev. A | Page 5 of 168 UG-907 ADV7613 Reference Manual FUNCTIONAL BLOCK DIAGRAM ADV7613 DPLL RXA_5V  HPA_A A B C BACK‐END  COLOR SPACE  CONVERSION  CEC CONTROLLER DATA PREPROCESSOR AND COLOR SPACE CONVERSION 5V DETECT AND HPD CONTROLLER  HDMI PROCESSOR DDCA_SDA DDCA_SCL RXA_C± RXA_0± RXA_1± RXA_2± EDID REPEATER CONTROLLER LTX2_0+ LTX2_0– LTX2_1+ LTX2_1– LTX2_2+ LTX2_2– LTX2_3+ LTX2_3– LTX2_C+ LTX2_C– INT AP0 PACKET/INFOFRAME  MEMORY  HDCP KEYS PLL EQUALIZER INTERRUPT CONTROLLER SAMPLER HDCP ENGINE PACKET PROCESSOR Figure 2. Detailed Functional Block Diagram Rev. A | Page 6 of 168 AUDIO PROCESSOR AUDIO OUTPUT FORMATTER  CEC COMPONENT PROCESSOR CONTROL INTERFACE I2C CS LVDS FORMATTER  SCL SDA AP1 AP2 AP3 AP4 AP5 SCLK MCLKOUT 13807-002 XTALP XTALN LTX1_0+ LTX1_0– LTX1_1+ LTX1_1– LTX1_2+ LTX1_2– LTX1_3+ LTX1_3– LTX1_C+ LTX1_C– ADV7613 Reference Manual UG-907 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 A GND DDCA_SD A DDCA_SCL GND XTALP PVDD RESET SCL AP5 GND A B RXA_5V HPA_A CEC GND XTALN CS INT SDA AP4 AP3 B C RXA_C+ RXA_C– CVDD GND GND DVDD TEST0 TEST1 AP2 AP1 C D RXA_0+ RXA_0– CVDD GND GND DVDD TEST2 TEST3 MCLKOUT SCLK D E RXA_1+ RXA_1– CVDD GND GND DVDD DVDD TEST4 TEST5 AP0 E F RXA_2+ RXA_2– TVDD GND GND GND DVDDIO TEST6 TEST7 TEST8 F G CVDD CVDD TVDD GND GND GND DVDDIO TEST9 TEST10 TEST11 G H LTX2_3– LTX_VDD LTX_VDD GND GND LTX_VDD LTX_VDD TEST12 TEST13 LTX1_0– H J LTX2_3+ LTX2_C– LTX2_2– LTX2_1– LTX2_0– LTX1_3– LTX1_C– LTX1_2– LTX1_1– LTX1_0+ J K GND LTX2_C+ LTX2_2+ LTX2_1+ LTX2_0+ LTX1_3+ LTX1_C+ LTX1_2+ LTX1_1+ GND K 1 2 3 4 5 6 7 8 9 10 13807-003 DATA LINES (INPUT AND OUTPUT) POWER SUPPLIES GND TEST PINS Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No A1, A4, A10, B4, C4, C5, D4, D5, E4, E5, F4 to F6, G4 to G6, H4, H5, K1, K10 A2 A3 A5 Mnemonic GND Type Ground Description Ground. DDCA_SDA DDCA_SCL XTALP HDMI Rx DDC HDMI Rx DDC Miscellaneous analog A6 A7 PVDD RESET Power Miscellaneous digital A8 A9 SCL AP5 Miscellaneous digital Audio output B1 B2 RXA_5V HPA_A HDMI input Miscellaneous digital B3 CEC Digital input/output HDCP Slave Serial Data for HDMI Port A. HDCP Slave Serial Clock for HDMI Port A. Input for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator Source to Clock the ADV7613. Digital PLL Supply Voltage (1.8 V). System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7613 circuitry. I2C Port Serial Clock Input. SCL is the clock line for the control port. Audio Output Pin 5. This pin is configurable to output S/PDIF digital audio, HBR or DSD. The AP5 pin typically provides the LRCLK signal for the I2S modes. 5 V Detect Pin for HDMI Port A. Hot Plug Assert. This pin can be configured to output the hot plug assert signal for HDMI Port A. Consumer Electronics Control Channel. Rev. A | Page 7 of 168 UG-907 ADV7613 Reference Manual Pin No B5 B6 Mnemonic XTALN CS Type Miscellaneous analog Miscellaneous digital B7 INT Miscellaneous digital B8 B9 SDA AP4 Miscellaneous digital Audio output B10 AP3 Audio output C1 C2 C3, D3, E3, G1, G2 C6, D6, E6, E7 C7, C8, D7, D8, E8, E9, F8 to F10, G8 to G10, H8, H9 C9 RXA_C+ RXA_C− CVDD DVDD TEST0 to TEST13 AP2 HDMI input HDMI input Power Power Miscellaneous C10 AP1 Audio output D1 D2 D9 D10 E1 E2 E10 RXA_0+ RXA_0− MCLKOUT SCLK RXA_1+ RXA_1− AP0 HDMI input HDMI input Audio output Audio output HDMI input HDMI input Audio Output F1 F2 F3, G3 F7, G7 H1 H2, H3, H6, H7 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K2 K3 K4 K5 K6 K7 K8 K9 RXA_2+ RXA_2− TVDD DVDDIO LTX2_3− LTX_VDD LTX1_0− LTX2_3+ LTX2_C− LTX2_2− LTX2_1− LTX2_0− LTX1_3− LTX1_C− LTX1_2− LTX1_1− LTX1_0+ LTX2_C+ LTX2_2+ LTX2_1+ LTX2_0+ LTX1_3+ LTX1_C+ LTX1_2+ LTX1_1+ HDMI input HDMI input Power Power LVDS output Power LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output LVDS output Audio output Description Crystal Output. Chip Select. This pin must be set low for the ADV7613 to process I2C messages. Pulling this line up causes the I2C state machine to ignore I2C transmission. Interrupt. This pin can be active low or active high, open drain or transistor to transistor logic (TTL). The events that trigger an interrupt are under user configuration. I2C Port Serial Data Input/Output. SDA is the data line for the control port. Audio Output 4. This pin is configurable to output S/PDIF digital audio, HBR, or I2S. Audio Output 3. This pin is configurable to output S/PDIF digital audio, HBR, or I2S. Digital Input Clock True of HDMI Port A. Digital Input Clock Complement of HDMI Port A. HDMI Analog Block Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Test Pins. Connect these pins to ground via 1 kΩ resistors. Audio Output 2. This pin is configurable to output S/PDIF digital audio, HBR, DSD, or I2S mode. Audio Output 1. This pin is configurable to output S/PDIF digital audio, HBR, or DSD. Digital Input Channel 0 True of HDMI Port A. Digital Input Channel 0 Complement of HDMI Port A. Master Clock. This pin is configurable to output the audio master clock signal. Serial Clock. This pin is configurable to output the audio serial clock. Digital Input Channel 1 True of HDMI Port A. Digital Input Channel 1 Complement HDMI Port A. Audio Output 0. This pin is configurable to output S/PDIF digital audio, HBR, DSD, or I2S. Digital Input Channel 2 True of HDMI Port A. Digital Input Channel 2 Complement of HDMI Port A. Termination Supply Voltage (3.3 V). Digital I/O Supply Voltage (3.3 V). LVDS Output Channel 3 Complement of LVDS Output Port 2. LVDS Supply Voltage (1.8 V). LVDS Output Channel 0 Complement of LVDS Output Port 1. LVDS Output Channel 3 True of LVDS Output Port 2. LVDS Clock Complement of LVDS Output Port 2. LVDS Output Channel 2 Complement of LVDS Output Port 2. LVDS Output Channel 1 Complement of LVDS Output Port 2. LVDS Output Channel 0 Complement of LVDS Output Port 2. LVDS Output Channel 3 Complement of LVDS Output Port 1. LVDS Clock Complement of LVDS Output Port 1. LVDS Output Channel 2 Complement of LVDS Output Port 1. LVDS Output Channel 1 Complement of LVDS Output Port 1. LVDS Output Channel 0 True of LVDS Output Port 1. LVDS Clock True of LVDS Output Port 2. LVDS Output Channel 2 True of LVDS Output Port 2. LVDS Output Channel 1 True of LVDS Output Port 2. LVDS Output Channel 0 True of LVDS Output Port 2. LVDS Output Channel 3 True of LVDS Output Port 1. LVDS Clock True of LVDS Output Port 1. LVDS Output Channel 2 True of LVDS Output Port 1. LVDS Output Channel 1 True of LVDS Output Port 1. Rev. A | Page 8 of 168 ADV7613 Reference Manual UG-907 GLOBAL CONTROL REGISTERS The register control bits described in this section deal with the general control of the chip, and the CP and the HDMI receiver sections of the ADV7613. ADV7613 REVISION IDENTIFICATION RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0] (Read Only) This register contains the chip revision code. Table 4. RD_INFO[15:0] Function Description RD_INFO[15:0] 0x20C4 Description ADV7613 POWER-DOWN CONTROLS Primary Power-Down Controls POWER_DOWN is the main power-down control. It is the main control for Power-Down Mode 0 and Power-Down Mode 1. See the Power-Down Modes section for more details. POWER_DOWN, IO, Address 0x0C[5] This register is the control that enables power-down mode. This is the main I2C power-down control. Table 5. POWER_DOWN Function Description POWER_DOWN 0 1 (default) Description Chip operational Enables chip power down Secondary Power-Down Controls The following controls allow various sections of the ADV7613 to be powered down. It is possible to stop the clock to the CP to reduce power for a power sensitive application. The CP_PWRDN bit enables this power save mode. The HDMI block is not affected by this power save mode. The CP_PWRDN bit allows the use of limited HDMI, STDI monitoring features while reducing the power consumption. For full processing of the HDMI input, the CP core must be powered up. CP_PWRDN, IO, Address 0x0C[2] This bit is the power-down control for the CP core. Table 6. CP_PWRDN Function Description CP_PWRDN 0 (default) 1 Description Powers up clock to CP core. Powers down clock to CP core. HDMI block not affected by this bit. XTAL_PDN XTAL_PDN allows the user to power down the crystal oscillator (XTAL) clock in the following sections: • • • • STDI blocks Free run synchronization generation block I2C sequencer block, which is used for the configuration of the gain, clamp, and offset CP and HDMI section The XTAL clock is also provided to the HDCP engine, EDID, and the repeater controller within the HDMI receiver. The XTAL clock within these sections is not affected by XTAL_PDN. Rev. A | Page 9 of 168 UG-907 ADV7613 Reference Manual XTAL_PDN, IO, Address 0x0B[0] This bit is the power-down control for the XTAL in the digital blocks. Table 7. XTAL_PDN Function Description XTAL_PDN 0 (default) 1 Description Powers up XTAL buffer to digital core Powers down XTAL buffer to digital core CORE_PDN CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections: • • CP block Digital section of the HDMI block CORE_PDN, IO, Address 0x0B[1] A power-down control for the data preprocessor (DPP), component processor (CP) core, and digital sections of the HDMI core. Table 8. CORE_PDN Function Description CORE_PDN 0 (default) 1 Description Powers up CP and digital sections of HDMI block Powers down CP and digital section of HDMI block Power-Down Modes The ADV7613 supports the following power-down modes: • • Power-Down Mode 0 Power-Down Mode 1 Table 9 shows the power-down and normal modes of ADV7613. Table 9. Power-Down Modes POWER_DOWN Bit 1 1 0 0 1 CEC_POWER_UP Bit 0 1 0 1 CEC Disabled Enabled Disabled Enabled EDID Enabled Enabled Enabled1 Enabled1 Power-Down Mode Power-Down Mode 0 Power-Down Mode 1 Normal mode Normal mode Dependent on the values of EDID_A_ENABLE_CPU and EDID_A_ENABLE for the HDMI port. Power-Down Mode 0 In Power-Down Mode 0, selected sections and pads are kept active to provide EDID and 5 V antiglitch filter functionality. In Power-Down Mode 0, the sections of the ADV7613 are disabled except for the following blocks: • • • I2C slave section EDID/repeater controller EDID ring oscillator The ring oscillator provides a clock to the EDID/repeater controller (refer to the E-EDID/Repeater Controller section) and the 5 V power supply antiglitch filter. The clock output from the ring oscillator runs at approximately 50 MHz. The following pads only are enabled in Power-Down Mode 0: • • • • I2C pads: SDA, SCL 5 V pads: RXA_5V, HPA_A DDC pads: DDCA_SCL, DDCA_SDA Reset pad: RESET Power-Down Mode 0 is initiated through a software (I2C register) configuration. Rev. A | Page 10 of 168 ADV7613 Reference Manual UG-907 Entering Power-Down Mode 0 via Software The ADV7613 can be put into Power-Down Mode 0 by setting POWER_DOWN to 1 (default value) and CEC_POWER_UP to 0. This method allows an external processor to put the system in which the ADV7613 is integrated into standby mode. In this case, the CP and HDMI cores of the ADV7613 are kept powered up from the main power (for example, ac power) and set in or out of Power-Down Mode 0 through the POWER_DOWN bit. Power-Down Mode 1 Power-Down Mode 1 is enabled when the following conditions are met: • • POWER_DOWN bit is set to 1 CEC section is enabled by setting CEC_POWER_UP to 1 Power-Down Mode 1 provides the same functionality as Power-Down Mode 0, with the addition of the following sections: • • • XTAL clock CEC section Interrupt controller section The following pads are enabled in Power-Down Mode 1: • • • Same pads as enabled in Power-Down Mode 0 CEC pad INT The internal EDID is also accessible through the DDC bus for Port A and Port B in Power-Down Mode 0 and Power-Down Mode 1. GLOBAL PIN CONTROL RESET Pin The ADV7613 can be reset by a low reset pulse on the reset pin with a minimum width of 5 ms. It is recommended to wait 5 ms after the low pulse before performing an I2C write to the ADV7613. Reset Controls MAIN_RESET, IO, Address 0xFF[7] (Self Clearing) This bit controls the main reset where I2C registers are reset to their default values. Table 10. MAIN_RESET Function Description MAIN_RESET 0 (default) 1 Description Normal operation Applies main I2C reset Tristate Output Drivers PADS_PDN, IO, Address 0x0C[0] This bit is the power-down control for pads of the digital outputs. When enabled, the pads are tristated and the input path is disabled. This control applies to INT. Table 11. PDS_PDN Function Description PADS_PDN 0 (default) 1 Description Powers up pads of digital output pins Powers down pads of digital output pins Tristate Audio Output Drivers TRI_AUDIO allows the user to tristate the drivers of the following audio output signals: AP0, AP1, AP2, AP3, AP4, AP5, SCLK, and MCLKOUT. The drive strength for the output pins can be controlled by the DR_STR[1:0] bits. The ADV7613 does not support tristating via a dedicated pin. Rev. A | Page 11 of 168 UG-907 ADV7613 Reference Manual TRI_AUDIO, IO, Address 0x15[4] This bit is the control to tristate the audio output interface pins (AP0 to AP5). Table 12. TRI_AUDIO Function Description TRI_AUDIO 0 1 (default) Description Audio output pins active Tristates audio output pins Drive Strength Selection DR_STR It may be desirable to strengthen or weaken the drive strength of the output drivers for electromagnetic compatibility (EMC) and crosstalk reasons. This section describes the controls to adjust the output drivers used by the CP and HDMI modes. The DR_STR[1:0] drive strength bits affect output drivers for the following output pins: • • • • AP0 to AP5 SCLK SDA SCL Digital Synthesizer Controls The ADV7613 features two digital encoder synthesizers that generate the following clocks: • • Video DPLL: this clock synthesizer generates the pixel clock. It undoes the effect of deep color and pixel repetition that are inherent to HDMI streams. The output of the LLC pin is either this pixel clock or a divided down version, depending on the datapath configuration. It takes less than one video frame for this synthesizer to lock. Audio DPLL: this clock synthesizer generates the audio clock. As per HDMI specification, the incoming HDMI clock is divided down by CTS and then multiplied up by N. This audio clock is used as the main clock in the audio stream section. The output of MCLKOUT represents this clock. It takes less than 5 ms after a valid ACR packet for this synthesizer to lock. Crystal Frequency Selection The ADV7613 supports 28.63636 MHz frequency crystal. Following control allows selecting crystal frequency. XTAL_FREQ_SEL[1:0], IO, Address 0x04[2:1] These bits are the control to set the XTAL frequency used. Table 13. XTAL_FREQ_SEL[1:0] Function Description XTAL_FREQ_SEL[1:0] 00 01 (default) 10 11 Description Reserved 28.63636 MHz Reserved Reserved Rev. A | Page 12 of 168 ADV7613 Reference Manual UG-907 PRIMARY MODE AND VIDEO STANDARD Setting the primary mode and choosing a video standard are the most fundamental settings when configuring the ADV7613. There are two primary modes for the ADV7613: HDMI component and HDMI graphic modes. Set the appropriate mode using PRIM_MODE[3:0]. In HDMI modes, the ADV7613 can receive and decode HDMI or DVI data throughout the DVI/HDMI receiver front end. Video data from the HDMI receiver is routed to the CP block while audio data is available on the audio interface. One of these modes is enabled by selecting either the HDMI component or the HDMI graphics primary mode. Note that the HDMI receiver decodes and processes any applied HDMI stream irrespective of the video resolution. However, many primary mode and video standard combinations can be used to define how the decoded video data routed to the DPP and CP blocks is processed. This allows free run features and data decimation modes that some systems may require. If free run and decimation are not required, it is recommended to set the following configuration for HDMI mode: • • PRIM_MODE[3:0] = 0x06 VID_STD[5:0] = 0x02 PRIMARY MODE AND VIDEO STANDARD CONTROLS PRIM_MODE[3:0], IO, Address 0x01[3:0] A control to select the primary mode of operation of the decoder. Setting the appropriate HDMI mode is important for free run mode to work properly. This control is used with VID_STD[5:0]. Table 14. PRIM_MODE[3:0] Function Description PRIM_MODE[3:0] 0000 0001 0010 0011 0100 0101 0110 (default) 0111 to 1111 Description Reserved Reserved Reserved Reserved Reserved HDMI component HDMI graphics Reserved VID_STD[5:0], IO, Address 0x00[5:0] Sets the input video standard mode. Configuration is dependent on PRIM_MODE[3:0]. Setting the appropriate mode is important for free run mode to work properly. Table 15. VID_STD[5:0] Function Description VID_STD[5:0] 000010 Description Default value Use PRIM_MODE[3:0] with VID_STD[5:0] to select the required video mode. These controls are set according to Table 16. Table 16. Primary Mode and Video Standard Selection Code 0101 PRIM_MODE[3:0] Description HDMI Component (Component video) Processor CP CP CP CP CP Code 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 VID_STD[5:0] Input Video Output Resolution Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PR 1 × 1 525p 720 × 480 Rev. A | Page 13 of 168 Comments HDMI receiver support UG-907 Code PRIM_MODE[3:0] Description ADV7613 Reference Manual Processor CP CP CP CP CP CP CP 0110 HDMI Graphic (Graphics) CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP 1 Code 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 011000 011001 011010 011011 011100 011110 011111 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 01xxxx 10000 10001 10010 10011 10111 11000 11001 VID_STD[5:0] Input Video Output Resolution PR 1 × 1 625p 720 × 576 PR 2 × 1 525p 720 × 480 PR 2 × 1 625p 720 × 576 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved HD 1 × 1 1280 × 720 HD 1 × 1 1920 × 1080 HD 1 × 1 1920 × 1035 HD 1 × 1 1920 × 1080 Reserved Reserved HD 2 × 1 720p 1280 × 720 HD 2 × 1 1125 1920 × 1080 HD 2 × 1 1125 1920 × 1035 HD 2 × 1 1250 1920 × 1080 HD 1 × 1 1920 × 1080 HD 1 × 1 1920 × 1080 SVGA 800 × 600 at 56 Hz SVGA 800 × 600 at 60 Hz SVGA 800 × 600 at 72 Hz SVGA 800 × 600 at 75 Hz SVGA 800 × 600 at 85 Hz SXGA 1280 × 1024 at 60 Hz SXGA 1280 × 1024 at 75 Hz Reserved Reserved VGA 640 × 480 at 60 Hz VGA 640 × 480 at 72 Hz VGA 640 × 480 at 75 Hz VGA 640 × 480 at 85 Hz XGA 1024 × 768 at 60 Hz XGA 1024 × 768 at 70 Hz XGA 1024 × 768 at 75 Hz XGA 1024 × 768 at 85 Hz Reserved Reserved WXGA 1280 × 768 at 60 Hz WXGA-R 1 1280 × 768 at 60 Hz WXGA+ 1360 × 768 at 60 Hz WXGA 1366 × 768 at 60 Hz Reserved Reserved Reserved Reserved Reserved Reserved R means reduced blanking. Rev. A | Page 14 of 168 Comments HDMI receiver support ADV7613 Reference Manual UG-907 V_FREQ This control is set to allow free run to work correctly (see Table 18). V_FREQ[2:0], IO, Address 0x01[6:4] These bits are the control to set the vertical frequency. Table 17. V_FREQ[2:0] Function Description V_FREQ[2:0] 000 (default) 001 010 011 100 101 110 111 Description 60 Hz 50 Hz 30 Hz 25 Hz 24 Hz Reserved Reserved Reserved HDMI DECIMATION MODES Some of the modes defined by VID_STD have an inherent 2 × 1 decimation. For these modes, the main clock generator and the decimation filters in the DPP block are configured automatically, which ensures that the correct data rate at the input to the CP block. See the Data Preprocessor, Color Space Conversion, and Color Controls section for more information on the automatic configuration of the DPP block. The ADV7613 correctly decodes and processes any incoming HDMI stream with the required decimation, irrespective of its video resolution. In 1×1 mode (that is, without decimation), as long the PRIM_MODE and VID_STD registers are programmed for any HDMI mode without decimation. For example: • • • Set PRIM_MODE to 0x5 and VID_STD to 0x00 Set PRIM_MODE to 0x5 and VID_STD to 0x13 Set PRIM_MODE to 0x6 and VID_STD to 0x02 In 2 × 1 decimation mode, as long the PRIM_MODE and VID_STD registers are programmed for any HDMI mode with 2 × 1 decimation. For example: • • Set PRIM_MODE to 0x5 and VID_STD to 0x0C Set PRIM_MODE to 0x5 and VID_STD to 0x19 Note that decimating the video data from an HDMI stream is optional; decimate the video data from an HDMI stream only if it is required by the downstream devices connected to the ADV7613. PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN If free run is enabled in HDMI mode, PRIM_MODE[3:0] and VID_STD[5:0] specify the input resolution expected by the ADV7613 (for Free Run Mode 1) and/or the output resolution to which the ADV7613 free runs (for Free Run Mode 0 and Free Run Mode 1). See the Free Run Mode section for additional details on the free run feature for HDMI inputs. RECOMMENDED SETTINGS FOR HDMI INPUTS This section provides the recommended settings for an HDMI input encapsulating a video resolution corresponding to a selection video ID code described in the EIA/CEA-861 specification. Table 18 provides the recommended settings for the following registers: • • • PRIM_MODE VID_STD V_FREQ (do not set V_FREQ to 0x0 if not specified in Table 18) Rev. A | Page 15 of 168 UG-907 ADV7613 Reference Manual Table 18. Recommended Settings for HDMI Inputs Video ID Codes (861 Specification) 2, 3 Formats 720 × 480p at 60 Hz Pixel Repetition 0 4 1280 × 720p at 60 Hz 0 14, 15 1440 × 480p at 60 Hz 1 16 1920 × 1080p at 60 Hz 0 17, 18 720 × 576p at 60 Hz 0 19 1280 × 720p at 50 Hz 0 29, 30 144 0× 576p at 60 Hz 1 31 1920 × 1080p at 50 Hz 0 32 1920 × 1080p at 24 Hz 0 33 1920 × 1080p at 25 Hz 0 35, 36 2880 × 480p at 60 Hz 3 37, 38 2880 × 576p at 60 Hz 3 Not applicable SVGA 800 × 600p at 56 Hz 0 Not applicable SVGA 800 × 600p at 60 Hz 0 Not applicable SVGA 800 × 600p at 72 Hz 0 Not applicable SVGA 800 × 600p at 75 Hz 0 Not applicable SVGA 800 × 600p at 85 Hz 0 Not applicable SXGA 1280 × 1024p at 60 Hz 0 Not applicable SXGA 1280 × 1024p at 75 Hz 0 Not applicable VGA 640 × 480p at 60 Hz 0 Not applicable VGA 640 × 480p at 72 Hz 0 Not applicable VGA 640 × 480p at 75 Hz 0 Not applicable VGA 640 × 480p at 85 Hz 0 Not applicable VGA 1024 × 768p at 60 Hz 0 Not applicable VGA 1024 × 768p at 70 Hz 0 Not applicable VGA 1024 × 768p at 75 Hz 0 Not applicable VGA 1024 × 768p at 85 Hz 0 Recommended Settings if Free Run Used and DIS_AUTOPRAM_BUFFER = 0 PRIM_MODE = 0x5, VID_STD = 0xA PRIM_MODE = 0x5, VID_STD = 0x13 PRIM_MODE = 0x5, VID_STD = 0xA PRIM_MODE = 0x5, VID_STD = 0x1E PRIM_MODE = 0x5, VID_STD = 0xB PRIM_MODE = 0x5, VID_STD = 0xA3, V_FREQ = 0x1 PRIM_MODE = 0x5, VID_STD = 0xA PRIM_MODE = 0x5, VID_STD = 0x1E, V_FREQ = 0x1 PRIM_MODE = 0x5, VID_STD = 0x1E, V_FREQ = 0x4 PRIM_MODE = 0x5, VID_STD = 0x1E, V_FREQ = 0x3 PRIM_MODE = 0x5, VID_STD = 0xA PRIM_MODE = 0x5, VID_STD = 0xA PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x0 Rev. A | Page 16 of 168 Recommended Settings if Free Run Not Used or Free Run Used and DIS_AUTO_PARAM_BUFFER = 1 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x6, VID_STD = 0x2 PRIM_MODE = 0x06, VID_STD = 0x0 PRIM_MODE = 0x06, VID_STD = 0x1 PRIM_MODE = 0x06, VID_STD = 0x2 PRIM_MODE = 0x06, VID_STD = 0x3 PRIM_MODE = 0x06, VID_STD = 0x04 PRIM_MODE = 0x06, VID_STD = 0x05 PRIM_MODE = 0x06, VID_STD = 0x06 PRIM_MODE = 0x06, VID_STD = 0x08 PRIM_MODE = 0x06, VID_STD = 0x09 PRIM_MODE = 0x06, VID_STD = 0x0A PRIM_MODE = 0x06, VID_STD = 0x0B PRIM_MODE = 0x06, VID_STD = 0x0C PRIM_MODE = 0x06, VID_STD = 0x0D PRIM_MODE = 0x06, VID_STD = 0x0E PRIM_MODE = 0x06, VID_STD = 0x0F ADV7613 Reference Manual UG-907 HDMI RECEIVER HPA_A/INT2 RXA_5V 5V DETECT AND HPA CONTROLLER CEC CEC CONTROLLER DDCA_SDA/DDCA_SC L EDID/ REPEATER CONTROLLER TO INTERRUPT CONTROLLER DATA HS TO DATA PREPROCESSOR (2.25Gbps VIDEO PATH) VS DE PLL HDCP EEPROM FILTER HDCP BLOCK RXA_0± RXA_1± RXA_2± EQUALIZER PACKET/ INFOFRAME MEMORY SAMPLER PACKET PROCESSOR AUDIO PROCESSOR AUDIO OUTPUT FORMATTER RXA_C± AP0 AP1/I2S_TDM AP2 AP3 AP4 AP5 SCLK/INT2 MCLK/INT2 13807-004 4:2:2 TO 4:4:4 CONVERSION Figure 4. Functional Block Diagram of HDMI Core The ADV7613 features an HDMI 1.4a-compliant HDMI receiver capable of supporting an HDMI stream with bit rates of up to 2.25 Gbps data bandwidth. +5 V CABLE DETECT The HDMI receiver in the ADV7613 can monitor the level on the +5 V power signal pin of each connected HDMI port. The results of this detection can be read back from the following I2C registers. These readbacks are valid even when the part is not configured for HDMI mode. CABLE_DET_A_RAW, IO, Address 0x6F[0] (Read Only) This bit is the raw status of the Port A, +5 V cable detection signal. Table 19. CABLE_DET_A_RAW Function Description CABLE_DET_A_RAW 0 (default) 1 Description No cable detected on Port A Cable detected on Port A (high level on RXA_5V) The ADV7613 provides a digital glitch filter on the +5 V power signals from the HDMI port. The output of this filter is used to reset the HDMI block (see the HDMI Section Reset Strategy section). The +5 V power signal must be constantly high for the duration of the timer (controlled byFILT_5V_DET_TIMER[6:0]); otherwise, the output of the filter is low. The output of the filter returns low as soon as any change in the +5 V power signal is detected. FILT_5V_DET_DIS, Address 68 (HDMI), Address 0x56[7] Use this control to disable the digital glitch filter on the HDMI 5 V detect signals. The filtered signals are used as interrupt flags and used to reset the HDMI section. The filter works from an internal ring oscillator clock and, therefore, is available in power-down mode. The clock frequency of the ring oscillator is 42 MHz ± 10%. Table 20. FILT_5V_DET_DIS Function Description FILT_5V_DET_DIS 0 (default) 1 Description Enabled Disabled Note that if the +5 V pins are not used and are left unconnected, the +5 V detect circuitry must be disconnected from the HDMI reset signal by setting DIS_CABLE_DET_RST to 1 to avoid holding the HDMI section in reset. Rev. A | Page 17 of 168 UG-907 ADV7613 Reference Manual FILT_5V_DET_TIMER[6:0], Address 68 (HDMI), Address 0x56[6:0] Use this control to set the timer for the digital glitch filter on the HDMI +5 V detect inputs. The unit of this parameter is two clock cycles of the ring oscillator (approximately 47 ns). The input must be constantly high for the duration of the timer; otherwise, the filter output remains low. The output of the filter returns low as soon as any change in the +5 V power signal is detected. Table 21. FILT_5V_DET_TIMER[6:0] Function Description FILT_5V_DET_TIMER[6:0] 1011000 (default) xxxxxxx Description Approximately 4.2 µs. Time duration of +5 V deglitch filter. The unit of this parameter is 2 clock cycles of the ring oscillator (~47 ns) DIS_CABLE_DET_RST, Address 68 (HDMI), Address 0x48[6] This control disables the reset effects of cable detection. DIS_CABLE_DET_RST must be set to 1 if the +5 V pins are unused and left unconnected. Table 22. DIS_CABLE_DET_RST Function Description DIS_CABLE_DET_RST 0 (default) 1 Description Resets HDMI section if 5 V input pin corresponding to selected HDMI port (for example, RXA_5V for Port A) is inactive Does not use 5 V input pins as reset signal for HDMI section HOT PLUG ASSERT The ADV7613 features hot plug assert (HPA) control for its HDMI port. The purpose of the control and its corresponding output pin is to communicate to an HDMI transmitter that it is possible to access the enhanced-extended display identification (E-EDID) connected to the DDC bus. HPA_MANUAL, Address 68 (HDMI), Address 0x6C[0] This bit is the manual control enable for the HPA output pins. Automatic control of these pins is disabled by setting this bit. Manual control is determined by the HPA_MAN_VALUE_A. Table 23. HPA_MANUAL Function Description HPA_MANUAL 0 (default) 1 Description HPA takes its value based on HPA_AUTO_INT_EDID HPA takes its value from HPA_MAN_VALUE_A HPA_MAN_VALUE_A, IO, Address 0x20[7] A manual control for the value of HPA on Port A. Valid only if HPA_MANUAL is set to 1. Table 24. HPA_MAN_VALUE_A Function Description HPA_MAN_VALUE_A 0 1 (default) Description 0 V applied to HPA_A pin High level applied to HPA_A pin Note that the HPA_A pin is open drain. An external pull-up resistor is required to pull it high. HPA_AUTO_INT_EDID[1:0], Address 68 (HDMI), Address 0x6C[2:1] This control selects the type of automatic control on the HPA output pins. These bits have no effect when HPA_MANUAL is set to 1. Table 25. HPA_AUTO_INT_EDID[1:0] Function Description HPA_AUTO_INT_EDID[1:0] 00 01 (default) Description HPA of an HDMI port asserted high immediately after internal EDID activated for that port. HPA of a specific HDMI port deasserted low immediately after internal E-EDID is deactivated for that port. HPA of an HDMI port asserted high following a programmable delay after part detects an HDMI cable plug on that port. HPA of an HDMI port immediately deasserted after part detects a cable disconnect on that HDMI port. Rev. A | Page 18 of 168 ADV7613 Reference Manual HPA_AUTO_INT_EDID[1:0] 10 11 UG-907 Description HPA of an HDMI port asserted high after two conditions met. 1. Internal EDID is active for that port. 2. Delayed version of cable detect signal CABLE_DET_X_RAW for that port is high. HPA of an HDMI port immediately deasserted after either of these two conditions are met: 1. Internal EDID is de-activated for that port. 2. Cable detect signal CABLE_DET_X_RAW for that port is low. HPA of an HDMI port is asserted high after three conditions are met: 1. Internal EDID is active for that port. 2. Delayed version of cable detect signal CABLE_DET_X_RAW for that port is high. 3. User has set manual HPA control for that port to 1 via HPA_MAN_VALUE_X controls. HPA of an HDMI port immediately deasserted after any of these three conditions met: 1. Internal EDID de-activated for that port. 2. Cable detect signal CABLE_DET_X_RAW for that port is low. 3. User sets the manual hot plug detect (HPD) control for that port to 0 via HPA_MAN_VALUE_X controls. Note that the delay is programmable via HPA_DELAY_SEL[3:0]. See the EDID_A_ENABLE register (Table 31) for details on enabling the internal E-EDID for an HDMI port. In HPA_MAN_VALUE_x and CABLE_DET_x_RAW, x refers to A and B. HPA_DELAY_SEL[3:0], Address 68 (HDMI), Address 0x6C[7:4] HPA_DELAY_SEL[3:0] sets a delay between +5 V detection and hot plug assertion on the HPA output pins, in increments of 100 ms per bit. Table 26. HPA_DELAY_SEL[3:0] Function Description HPA_DELAY_SEL[3:0] 0000 0001 0010 1010 (default) 1111 Description No delay 100 ms delay 200 ms delay 1 sec delay 1.5 sec delay HPA_TRISTATE_A, IO, Address 0x20[3] This bit tristates the HPA output pin for Port A. Table 27. HPA_TRISTATE_A Function Description HPA_TRISTATE_A 0 (default) 1 Description HPA_A pin active Tristates HPA_A pin HPA_STATUS_PORT_A, IO, Address 0x21[3] (Read Only) This bit is the readback of the HPA status for Port A. Table 28. HPA_STATUS_PORT_A Function Description HPA_STATUS_PORT_A 0 (default) 1 Description +5 V not applied to HPA_A pin by chip +5 V applied to HPA_A pin by chip HPA_OVR_TERM, Address 68 (HDMI), Address 0x6C[3] This bit sets the termination control to be overridden by the HPA setting. When this bit is set, termination on a specific port is set according to the HPA status of that port. Table 29. HPA_OVR_TERM Function Description HPA_OVR_TERM 0 (default) 1 Description Automatic or manual I2C control of port termination Termination controls disabled and overridden by HPA controls Rev. A | Page 19 of 168 UG-907 ADV7613 Reference Manual E-EDID/REPEATER CONTROLLER The HDMI section incorporates an E-EDID/repeater controller, which performs the following tasks: • • Computes the E-EDID checksum for each port Performs the repeater routines described in the Repeater Support section The E-EDID/repeater controller is powered from the DVDD supply and clocked by an internal ring oscillator. The controller and the internal DDC bus arbiter are kept active in power-down Mode 0 and power-down Mode 1. This allows the internal E-EDID to be functional and accessible through the DDC port, even when the part is powered down (see the Power-Down Modes section). These HDMI transmitters can then read the capabilities of the powered-down application integrating the ADV7613 by accessing its internal E-EDID through the DDC ports. The E-EDID/repeater controller is reset when the DVDD supplies go low or when HDCP_REPT_EDID_RESET is set high. When the E-EDID/repeater controller reboots, it performs the following tasks: • • Clears the internal E-EDID and key selection vector (KSV) RAM (see the E-EDID Data Configuration section and the Internal HDCP Key OTP ROM section) Updates the source physical address (SPA) registers HDCP_REPT_EDID_RESET, Address 68 (HDMI), Address 0x5A[3] (Self Clearing) HDCP_REPT_EDID_RESET is a reset control for the E-EDID/repeater controller. When asserted, it resets the E-EDID/repeater controller. Table 30. HDCP_REPT_EDID_RESET Function Description HDCP_REPT_EDID_RESET 0 (default) 1 Description Normal operation Resets the E-EDID/repeater controller E-EDID DATA CONFIGURATION The ADV7613 features a RAM that can store an E-EDID. This internal E-EDID feature can be used for both HDMI ports A and B. The following controls are provided to enable the internal E-EDID for each of the two HDMI ports. EDID_A_ENABLE, Address 64 (Repeater), Address 0x74[0] This bit enables I2C access to the internal EDID RAM from DDC Port A. Table 31. EDID_A_ENABLE Function Description EDID_A_ENABLE 0 (default) 1 Description Disables E-EDID for Port A Enables E-EDID for Port A EDID_A_ENABLE_CPU, Address 64 (Repeater), Address 0x76[0] (Read Only) This bit flags internal EDID enabling on Port A. Table 32. EDID_A_ENABLE_CPU Function Description EDID_A_ENABLE_CPU 0 (default) 1 Description Disabled Enabled Note the following: • • • • • When the internal E-EDID is enabled, the corresponding enable control (such as EDID_A_ENABLE) must be set high in a single I2C write to ensure the fastest calculation of the checksums. If the internal E-EDID RAM is enabled for Port A, an external E-EDID storage device must not be connected on the DDC bus of that port. The internal E-EDID can be read by current address read sequences on the DDC port. The ADV7613 supports the segment pointer, which is set at Device Address 0x60 through the DDC bus, and used in combination with the internal E-EDID address (0xA0) to access the internal E-EDID. The contents of the EDID RAM are not to be trusted after power up or hardware reset. The user must write proper contents to the EDID RAM memory inside the ADV7613 via an external MCU. Rev. A | Page 20 of 168 ADV7613 Reference Manual UG-907 E-EDID Support for Power-Down Modes The ADV7613 supports E-EDID access in Power-Down Mode 0 and Power-Down Mode 1. Using this feature, an application that integrates the ADV7613 in standby can make its E-EDID available to the HDMI transmitter. This allows support of CEC and provides compatibility with HDMI transmitters that require the E-EDID to be available when the HDMI receiver is powered down. In Power-Down Mode 0, the device operates in a very low power state with only the minimum of internal circuitry enabled for the internal E-EDID. For more details on E-EDID accessibility in power-down modes, see the Power-Down Modes section. TRANSITIONING OF POWER MODES If the device starts in Power-Down Mode 0 and then transitions into a different power mode (that is, Power-Down Mode 1 or normal operation mode), the information in the internal E-EDID is not overwritten. The internal E-EDID remains active on the HDMI port for which the E-EDID has been accessed. This prevents disturbing E-EDID read requests from HDMI sources connected to the ADV7613 while it is being powered on, or while the power mode is transitioning. It is possible to disable the automatic enable of internal EDID on the HDMI ports when the device comes out of power-down mode, by setting the DISABLE_AUTO_EDID bit. DISABLE_AUTO_EDID, Address 64 (Repeater), Address 0x7A[1] This bit disables all automatic enables for internal E-EDID. Table 33. DISABLE_AUTO_EDID Function Description DISABLE_AUTO_EDID 0 (default) 1 Description Automatic enable of internal E-EDID on HDMI port when the part comes out of Power-Down Mode 0 Disable automatic enable of internal E-EDID on HDMI port when the part comes out of Power-Down Mode 0 Rev. A | Page 21 of 168 UG-907 ADV7613 Reference Manual STRUCTURE OF INTERNAL E-EDID FOR PORT A The internal E-EDID is enabled on Port A by setting EDID_A_ENABLE to 1 (see Table 31). The structure of the internal E-EDID that is accessible on the DDC line of Port A is shown in Figure 5. The image of the internal E-EDID that is accessed on the DDC bus of Port A corresponds to the data image contained in the internal E-EDID RAM. PORT A E-EDID STRUCTURE 0x1FF BLOCK 3 CHECKSUM 0x1FE BLOCK 3 0x180 0x17F BLOCK 2 CHECKSUM 0x17E BLOCK 2 0x100 0xFF BLOCK 1 CHECKSUM 0xFE BLOCK 1 0x80 0x7F BLOCK 0 CHECKSUM 0x7E 13807-005 BLOCK 0 0x00 Figure 5. Port A E-EDID Structure and Mapping Note the following: • • • • • After EDID_A_ENABLE is set to 1, the ADV7613 E-EDID/repeater controller calculates the four checksums of the E-EDID image for Port A and updates the 0x7F, 0xFF, 0x17F, and 0x1FF internal RAM address locations in the internal E-EDID RAM with the computed checksums. After power up, the ADV7613 E-EDID/repeater controller sets all bytes in the internal E-EDID RAM to 0, this operation takes less than 1 ms. It is recommended to wait for at least 1 ms before initializing the EDID map with an E-EDID image. When internal E-EDID is enabled on Port A, the hot plug must not be asserted until the EDID map has been completely initialized with E-EDID. The internal E-EDID can be accessed in read-only mode through the DDC interface at the I2C Address 0xA0. The internal E-EDID can be accessed in read/write mode through the general I2C interface at the EDID map I2C address. TMDS EQUALIZATION The ADV7613 incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at long lengths and higher frequencies. The ADV7613 is capable of equalizing for cable lengths up to 30 meters and for pixel clock frequencies up to 300 MHz. Note that transition minimized differential signaling (TMDS) equalization frequency of the active HDMI port can be read back in the TMDSFREQ[8:0] and TMDSFREQ_FRAC[6:0] registers. PORT SELECTION HDMI_PORT_SELECT allows the selection of the active HDMI port. This register must be set to activate HDMI Port A. HDMI_PORT_SELECT, Address 68 (HDMI), Address 0x00 [0] This control is used for HDMI primary port selection. Table 34. HDMI_PORT_SELECT Function Description HDMI_PORT_SELECT 000 (default) Description Port A Rev. A | Page 22 of 168 ADV7613 Reference Manual UG-907 TMDS CLOCK ACTIVITY DETECTION The ADV7613 provides circuitry to monitor TMDS clock activity on each of its HDMI ports. The firmware can poll the appropriate registers for TMDS clock activity detection and configure the ADV7613 as desired. TMDS clock detection control is active as soon as the ADV7613 detects activity above a 25 MHz on the TMDS clock input. TMDS_CLK_A_RAW, IO, Address 0x6A[4] (Read Only) TMDS_CLK_A_RAW is the raw status of the Port A TMDS clock detection signal. Table 35. TMDS_CLK_A_RAW Function Description TMDS_CLK_A_RAW 0 (default) 1 Description No TMDS clock detected on Port A TMDS clock detected on Port A It is important to note that the clock detection flag is valid if the device is powered up or in Power Down Mode 1 (see the Power-Down Mode 1 section). The clock detection flags is valid, irrespective of the mode the part is set into via the PRIM_MODE[3:0] register. Clock and Data Termination Control The ADV7613 provides controls for the TMDS clock and data termination on all HDMI ports. The ADV7613 also offers automatic manual termination closure of the selected port, and individual manual control over the HDMI ports. Note that the clock termination of the port by HDMI_PORT_SELECT must always be enabled. The device does not support HDMI streams with clock rates lower than 25 MHz. TERM_AUTO, Address 68 (HDMI), Address 0x01[0] This bit allows the user to select automatic or manual control of clock termination. If automatic mode termination is enabled, then the termination on the port selected via HDMI_PORT_SELECT[1:0] is enabled. The termination is disabled on all other ports Table 36. TERM_AUTO Function Description TERM_AUTO 0 (default) 1 Description Disable termination automatic control Enable termination automatic control Note that, to enable the fast switching feature, the termination must be set manually for each port. When manual mode is enabled, the termination for each port is set individually by the CLOCK_TERMx_DISABLE control bits (were x is A or B). CLOCK_TERMA_DISABLE, Address 68 (HDMI), Address 0x83[0] This bit disables the clock termination on Port A. It can be used when TERM_AUTO is set to 0. Table 37. CLOCK_TERMA_DISABLE Function Description CLOCK_TERMA_DISABLE 0 1 (default) Description Enable Termination Port A Disable Termination Port A HDMI/DVI STATUS BITS HDMI/DVI status mode is available through HDMI_MODE for active port and BG_HDMI_MODE for background port. HDMI_MODE, Address 68 (HDMI), Address 0x05[7] (Read Only) This bit is a readback to indicate whether the stream processed by the HDMI core is a DVI or an HDMI stream. Table 38. HDMI_MODE Function Description HDMI_MODE 0 (default) 1 Description DVI mode detected HDMI mode detected Rev. A | Page 23 of 168 UG-907 ADV7613 Reference Manual BG_HDMI_MODE, Address 68 (HDMI), Address 0xEB[0] (Read Only) This bit is a readback to indicate whether the stream processed by the HDMI core is a DVI or an HDMI stream. Table 39. BG_HDMI_MODE Function Description BG_HDMI_MODE 0 (default) 1 Description DVI mode detected HDMI mode detected VIDEO 3D DETECTION The status of 3D video is available through the VIDEO_3D_RAW bit. VIDEO_3D_RAW, IO, Address 0x6A[2] (Read Only) This bit is the raw status of the video 3D signal. Table 40. VIDEO_3D_RAW Function Description VIDEO_3D_RAW 0 1 Description Video 3D not detected Video 3D detected TMDS MEASUREMENT The ADV7613 contains logic that measures the frequency of the TMDS clock transmitted. The TMDS frequency can be read back via the TMDSFREQ[8:0] and TMDSFREQ_FRAC[6:0] registers. TMDS Measurement After TMDS PLL The TMDSFREQ measurement is provided by a clock measurement circuit located after the TMDS PLL. Therefore, TMDS PLL must be locked to the incoming TMDS clock for the TMDSFREQ and TMDSFREQ_FRAC registers to return a valid measurement. The TMDS frequency can be obtained using Equation 1, TMDS frequency in MHz (measured after TMDS PLL). fTMDS = TMDSFREQ + TMDSFREQ _ FRAC 128 (1) The TMDS PLL lock status can be monitored via TMDS_PLL_LOCKED. Figure 6 shows the algorithm that can be implemented on an external controller to monitor the TMDS clock frequency. The TMDS_PLL_LOCKED flag is considered valid if a TMDS clock is input on the HDMI port selected via HDMI_PORT_SELECT. The NEW_TMDS_FRQ_RAW flag can be used to monitor if the TMDS frequency on the selected HDMI port changes by a programmable threshold. The ADV7613 can be configured to trigger an interrupt when the NEW_TMDS_FRQ_RAW bit changes from 0 to 1. In that configuration, the NEW_TMDS_FRQ_ST interrupt status indicates that NEW_TMDS_FRQ_RAW has changed from 0 to 1. See the Interrupts section for additional information on the configuration of interrupts. TMDSFREQ[8:0], Address 68 (HDMI), Address 0x51[7:0]; Address 0x52[7] (Read Only) This register provides a full precision integer TMDS frequency measurement. Table 41. TMDSFREQ[8:0] Function Description TMDSFREQ[8:0] 000000000 (default) xxxxxxxxx Description Outputs 9-bit TMDS frequency measurement in MHz Outputs 9-bit TMDS frequency measurement in MHz TMDSFREQ_FRAC[6:0], Address 68 (HDMI), Address 0x52[6:0] (Read Only) This register is a readback to indicate the fractional bits of measured frequency of PLL recovered TMDS clock. The unit is 1/128 MHz. Table 42. TMDSFREQ_FRAC[6:0] Function Description TMDSFREQ_FRAC[6:0] 0000000 (default) xxxxxxx Description Outputs 7-bit TMDS fractional frequency measurement in 1/128 MHz Outputs 7-bit TMDS fractional frequency measurement in 1/128 MHz Rev. A | Page 24 of 168 ADV7613 Reference Manual UG-907 BG_TMDSFREQ[8:0], Address 68 (HDMI), Address 0xE0[7:0]; Address 0xE1[7] (Read Only) This register provides a precision integer TMDS frequency measurement on the background port selected by BG_MEAS_PORT_SEL[2:0]. The value provided is the result of a single measurement of the TMDS PLL frequency in MHz. This value is updated when an update request is made via the BG_MEAS_REQ control bit. This measurement is only valid when BG_PARAM_LOCK is set to 1. Table 43. BG_TMDSFREQ[8:0] Function Description BG_TMDSFREQ[8:0] xxxxxxxxx Description Outputs 9-bit TMDS frequency measurement in MHz BG_TMDSFREQ_FRAC[6:0], Address 68 (HDMI), Address 0xE1[6:0] (Read Only) This register provides a precision fractional measurement of the TMDS frequency on the background port selected by BG_MEAS_ PORT_SEL[2:0]. The unit is 1/128 MHz and the value is updated when an update request is made via the BG_MEAS_REQ control bit. This measurement is only valid when BG_PARAM_LOCK is set to 1. Table 44. BG_TMDSFREQ_FRAC[6:0] Function Description BG_TMDSFREQ_FRAC[6:0] xxxxxxx Description Outputs 7-bit TMDS fractional frequency measurement in 1/128 MHz TMDS_PLL_LOCKED, Address 68 (HDMI), Address 0x04[1] (Read Only) This bit is a readback to indicate if the TMDS PLL is locked to the TMDS clock input to the selected HDMI port. Table 45. TMDS_PLL_LOCKED Function Description TMDS_PLL_LOCKED 0 (default) 1 Description The TMDS PLL is not locked. The TMDS PLL is locked to the TMDS clock input to the selected HDMI port. TMDSPLL_LCK_A_RAW, IO, Address 0x6A[6] (Read Only) This bit is a readback to indicate the raw status of the Port A TMDS PLL lock signal. Table 46. TMDSPLL_LCK_A_RAW Function Description TMDSPLL_LCK_A_RAW 0 (default) 1 Description TMDS PLL on Port A is not locked. TMDS PLL on Port A is locked to the incoming clock. NEW_TMDS_FRQ_RAW, IO, Address 0x83[1] (Read Only) Status of new TMDS frequency interrupt signal. When set to 1, it indicates that the TMDS frequency has changed by more than the tolerance set in FREQTOLERANCE[3:0]. Once set, this bit remains high until it is cleared via NEW_TMDS_FREQ_CLR. Table 47. NEW_TMDS_FRQ_RAW Function Description NEW_TMDS_FRQ_RAW 0 (default) 1 Description TMDS frequency has not changed by more than tolerance set in FREQTOLERANCE[3:0] in the HDMI map. TMDS frequency has changed by more than tolerance set in FREQTOLERANCE[3:0] in the HDMI map. FREQTOLERANCE[3:0], Address 68 (HDMI), Address 0x0D[3:0] FREQTOLERANCE[3:0] sets the tolerance in MHz for new TMDS frequency detection. This tolerance is used for the audio mute mask MT_MSK_VCLK_CHNG and the HDMI status bit NEW_TMDS_FRQ_RAW. Table 48. FREQTOLERANCE[3:0] Function Description FREQTOLERANCE[3:0] 0100 (default) xxxx Description Default tolerance in MHz for new TMDS frequency detection Tolerance in MHz for new TMDS frequency detection Rev. A | Page 25 of 168 UG-907 ADV7613 Reference Manual START ENABLE TMDS_CLK_X_ST 1 INTERRUPT FOR THE HDMI PORTS THAT ARE USED ENABLE TMDS_PLL_LCK_ST INTERRUPT ENABLE NEW_TMDS_FRQ_ST INTERRUPT TMDS FREQUENCY READ BACK NOT VALID OR STABLE NO IS TMDS_CLK_X_RAW SET? YES NO IS TMDS_PLL_LCK_RAW SET? YES READ THE TMDS FREQUENCY TMDSFREQ IS TMDS_CLK_X_ST SET? YES CLEAR TMDS_CLK_X_ST BY SETTING TMDS_CLK_X_CLR TO 1 NO IS YES TMDS_PLL_LCK_ST SET? CLEAR TMDS_PLL_LCK_ST BY SETTING TMDS_PLL_LCK_S_CLR TO 1 NO IS YES NEW_TMDS_FRQ_ST SET? CLEAR TMDS_FRQ_ST BY SETTING NEW_TMDS_FRQ_ST_CLR TO 1 NO TMDS FREQUENCY READ BACK VALID AND STABLE 1THE 3) 2) 1) 0) 13807-006 TMDS_CLK_X_ST INTERRUPTS FOLLOW: TMDS_CLK_A_ST (IO MAP, REGISTER 0x6B BIT TMDS_CLK_B_ST (IO MAP, REGISTER 0x6B BIT TMDS_CLK_C_ST (IO MAP, REGISTER 0x6B BIT TMDS_CLK_D_ST (IO MAP, REGISTER 0x6B BIT Figure 6. Monitoring TMDS Clock Frequency Rev. A | Page 26 of 168 ADV7613 Reference Manual UG-907 VIDEO FIFO The ADV7613 contains a first in, first out (FIFO) located between the incoming TMDS data and the CP core (see Figure 7). Data arriving over the HDMI link is at 1× for non-deep color mode (8 bits per channel). The video FIFO also provides extreme robustness to jitter on the TMDS clock. The CP clock is generated by a DPLL running on the incoming TMDS clock, and the CP clock may contain less jitter than the incoming TMDS clock. The video FIFO provides immunity to the incoming jitter and the resultant clock phase mismatch between the CP clock and the TMDS clock. TMDS PLL DPLL DIVIDER R TMDS CHANNEL 1 R TMDS CHANNEL 0 TMDS CHANNEL 0 12 TMDS SAMPLING AND DATA RECOVERY B TMDS CHANNEL1 TMDS DECODING 10 TMDS CHANNEL 2 TMDS CHANNEL 2 12 G 10 10 G 12 12 HS B FIFO 12 12 HS VS VS DE DE 13807-007 TMDS CLOCK Figure 7. HDMI Video FIFO The video FIFO operates completely autonomously. It automatically resynchronizes the read and write pointers if they are about to point to the same location. However, it is also possible for the user to observe and control the FIFO operation with a number of FIFO status and control registers. DCFIFO_LEVEL[2:0], Address 68 (HDMI), Address 0x1C[2:0] (Read Only) DCFIFO_LEVEL[2:0] is a readback that indicates the distance between the read and write pointers. Overflow/underflow is read as Level 0. Ideal centered functionality is read as 0b100. Table 49. DCFIFO_LEVEL[2:0] Function Description DCFIFO_LEVEL[2:0] 000 (default) 001 010 011 100 101 110 111 Description FIFO has underflowed or overflowed. FIFO is about to overflow. FIFO has some margin. FIFO has some margin. FIFO perfectly balanced FIFO has some margin. FIFO has some margin. FIFO is about to underflow. DCFIFO_LOCKED, Address 68 (HDMI), Address 0x1C[3] (Read Only) A readback to indicate if video FIFO is locked. Table 50. DCFIFO_LOCKED Function Description DCFIFO_LOCKED 0 (default) 1 Description Video FIFO is not locked. Video FIFO had to resynchronize between previous two vertical synchronizations (VSYNCs). Video FIFO is locked. Video FIFO did not have to resynchronize between previous two VSYNCs. Rev. A | Page 27 of 168 UG-907 ADV7613 Reference Manual DCFIFO_RECENTER, Address 68 (HDMI), Address 0x5A[2] (Self Clearing) This bit is a reset to recenter the video FIFO. This is a self clearing bit. Table 51. DCFIFO_RECENTER Function Description DCFIFO_RECENTER 0 (default) 1 Description Video FIFO normal operation Video FIFO to recenter DCFIFO_KILL_DIS, Address 68 (HDMI), Address 0x1B[2] The video FIFO output is zeroed if there is more than one resynchronization of the pointers within two FIFO cycles. This behavior can be disabled with this bit. Table 52. DCFIFO_KILL_DIS Function Description DCFIFO_KILL_DIS 0 (default) 1 Description FIFO output set to zero if more than one resynchronization is necessary during two FIFO cycles FIFO output never set to zero regardless of how many resynchronizations occur DCFIFO_KILL_NOT_LOCKED, Address 68 (HDMI), Address 0x1B[3] DCFIFO_KILL_NOT_LOCKED controls whether or not the output of the Video FIFO is set to zero when the video PLL is unlocked. Table 53. DCFIFO_KILL_NOT_LOCKED Function Description DCFIFO_KILL_NOT_LOCKED 0 1 (default) Description FIFO data is output regardless of video PLL lock status. FIFO output is zeroed if video PLL is unlocked. The DCFIFO is programmed to reset itself automatically when the video PLL transitions from unlocked to locked. Note that the video PLL transition does not necessarily indicate that the overall system is stable. DCFIFO_RESET_ON_LOCK, Address 68 (HDMI), Address 0x1B[4] DCFIFO_RESET_ON_LOCK enables the reset/recentering of video FIFO on video PLL unlock. Table 54. DCFIFO_RESET_ON_LOCK Function Description DCFIFO_RESET_ON_LOCK 0 1 (default) Description Do not reset on video PLL lock. Reset FIFO on video PLL lock. Rev. A | Page 28 of 168 ADV7613 Reference Manual UG-907 PIXEL REPETITION In HDMI mode, video formats with TMDS rates below 25 M pixels/sec require pixel repetition to be transmitted over the TMDS link. When the ADV7613 receives this type of video format, it discards repeated pixel data automatically, based on the pixel repetition field available in the auxiliary video information (AVI) InfoFrame. When HDMI_PIXEL_REPETITION is nonzero, video pixel data is discarded and the pixel clock frequency is divided by (HDMI_PIXEL_REPETITION) + 1. HDMI_PIXEL_REPETITION[3:0], Address 68 (HDMI), Address 0x05[3:0] (Read Only) HDMI_PIXEL_REPETITION[3:0] is a readback to provide the current HDMI pixel repetition value decoded from the AVI InfoFrame received. The HDMI receiver automatically discards repeated pixel data and divides the pixel clock frequency appropriately as per the pixel repetition value. Table 55. HDMI_PIXEL_REPETITION[3:0] Function Description HDMI_PIXEL_REPETITION[3:0] 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 to 1111 Description 1× 2× 3× 4× 5× 6× 7× 8× 9× 10× Reserved DEREP_N_OVERRIDE, Address 68 (HDMI), Address 0x41[4] This control allows the user to override the pixel repetition factor. The ADV7613 then uses DEREP_N instead of HDMI_PIXEL_REPETITION[3:0] to discard video pixel data from the incoming HDMI stream. Table 56. DEREP_N_OVERRIDE Function Description Function DEREP_N_OVERRIDE 0 (default) 1 Description Automatic detection and processing of procession of pixel repeated modes using the AVI InfoFrame information. Enables manual setting of the pixel repetition factor as per DEREP_N[3:0]. DEREP_N[3:0], Address 68 (HDMI), Address 0x41[3:0] DEREP_N[3:0] sets the derepetition value if derepetition is overridden by setting DEREP_N_OVERRIDE. Table 57. DEREP_N[3:0] Function Description Function DEREP_N[3:0] 0000 (default) Description DEREP_N+1 indicates the pixel and clock discard factor Rev. A | Page 29 of 168 UG-907 ADV7613 Reference Manual BG_PIX_REP[3:0], Address 68 (HDMI), Address 0xEA[7:4] (Read Only) BG_PIX_REP[3:0] is the background port pixel repetition status for the background HDMI port determined by BG_MEAS_PORT_SEL[2:0]. The readback provides the pixel repetition value in AVI InfoFrame and is updated when an update request is made via the BG_MEAS_REQ control bit. This measurement is only valid when BG_PARAM_LOCK is set to 1. Table 58. BG_PIX_REP[3:0] Function Description BG_PIX_REP[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 to 1111 Description 1x 2x 3x 4x 5x 6x 7x 8x 9x 10x Reserved Following registers allow forcing YCrCb 444 and YCrCb 422 regardless of the AVI InfoFrame. This feature is useful when source switches between YCrCb 444 and YCrCb 422 modes without sending appropriate update in AVI InfoFrame. FORCE_YCRCB_444, Address 68 (HDMI), Address 0x46[4] FORCE_YCRCB_444 forces a 4:4:4 interpretation of the video contents, regardless of the description in the AVI InfoFrame. This bit carries higher priority than FORCE_YCRCB_422. Table 59. FORCE_YCRCB_444 Function Description FORCE_YCRCB_444 0 (default) 1 Description Not forced Forced FORCE_YCRCB_422, Address 68 (HDMI), Address 0x47[4] FORCE_YCRCB_422 forces a 4:2:2 interpretation of the video contents, regardless of the description in the AVI InfoFrame. This bit is only valid if FORCE_YCRCB_444 is zero. Table 60. FORCE_YCRCB_422 Function Description FORCE_YCRCB_422 0 (default) 1 Description Not forced Forced HDCP SUPPORT HDCP Decryption Engine The HDCP decryption engine allows the reception and decryption of HDCP content-protected video and audio data. In the HDCP authentication protocol, the transmitter authenticates the receiver by accessing the HDCP registers of the ADV7613 over the DDC bus. Once the authentication is initiated, the HDCP decryption integrated in the ADV7613 computes and updates a decryption mask for every video frame. This mask is applied to the incoming data at every clock cycle to yield decrypted video and audio data. HDCP_A0, Address 68 (HDMI), Address 0x00[7] HDCP_A0 is a control to set the second LSB of the HDCP port I2C address. Table 61. HDCP_A0 Function Description HDCP_A0 0 (default) 1 Description I2C address for HDCP port is 0x74. Used for single-link mode or first receiver in dual-link mode. I2C address for HDCP port is 0x76. Used only for a second receiver in dual-link mode. Rev. A | Page 30 of 168 ADV7613 Reference Manual UG-907 HDMI_CONTENT_ENCRYPTED, Address 68 (HDMI), Address 0x05[6] (Read Only) This bit is a readback to indicate the use of HDCP encryption. Table 62. HDMI_CONTENT_ENCRYPTED Function Description HDMI_CONTENT_ENCRYPTED 0 (default) 1 Description The input stream processed by the HDMI core is not HDCP encrypted. The input stream processed by the HDMI core is HDCP encrypted. HDMI_ENCRPT_x_RAW reports the encryption status of the data present on each individual HDMI port (where x is A or B). Note that these bits are reset to 0 if an HDMI packet detection reset occurs (see the HDMI Packet Detection Flag Reset section). HDMI_ENCRPT_A_RAW, IO, Address 0x6F[2] (Read Only) This bit is the raw status of Port A encryption detection signal. Table 63. HDMI_ENCRPT_A_RAW Function Description HDMI_ENCRPT_A_RAW 0 (default) 1 Description Current frame in Port A is not encrypted. Current frame in Port A is encrypted. The ADV7613 supports the 1.1_FEATURES, FAST_REAUTHENTICATION, and FAST_I2C speed HDCP features. The BCAPS register must be initialized appropriately if these features are to be supported by the application integrating the ADV7613. For example, set BCAPS[0] to 1 to support FAST_REAUTHENTICATION. It is recommended to set BCAPS[7:0], Bit 7 to 1 if the ADV7613 is used as the front end of an HDMI receiver. This bit must be set to 0 for DVI applications. Internal HDCP Key OTP ROM The ADV7613 features an on-chip nonvolatile memory that is preprogrammed with a set of HDCP keys. HDCP Keys Access Flags The ADV7613 accesses the internal HDCP key, one-time programmable (OTP) ROM (also referred to as HDCP ROM) on two different occasions: • • After a power up, the ADV7613 reads the KSV from the internal HDCP ROM (see Figure 8). After a KSV update from an HDCP transmitter, the ADV7613 reads the KSV and all keys to carry out the link verification response (see Figure 9). The host processor can read the HDCP_KEYS_READ and HDCP_KEY_ERROR flags to check that the ADV7613 has accessed the HDCP ROM. HDCP_KEYS_READ, Address 68 (HDMI), Address 0x04[5] (Read Only) HDCP_KEYS_READ is a readback to indicate a successful read of the HDCP keys and/or KSV from the internal HDCP Key OTP ROM. A logic high is returned when the read is successful. Table 64. HDCP_KEYS_READ Function Description HDCP_KEYS_READ 0 (default) 1 Description HDCP keys and/or KSV not yet read HDCP keys and/or KSV HDCP keys read HDCP_KEY_ERROR, Address 68 (HDMI), Address 0x04[4] (Read Only) HDCP_KEY_ERROR is a readback to indicate if a checksum error occurred while reading the HDCP and/or KSV from the HDCP key ROM Returns 1 when HDCP Key master encounters an error while reading the HDCP key OTP ROM. Table 65. HDCP_KEY_ERROR Function Description HDCP_KEY_ERROR 0 (default) 1 Description No error occurred while reading HDCP keys HDCP keys read error Rev. A | Page 31 of 168 UG-907 ADV7613 Reference Manual START (AFTER POWER-UP) HDCP_KEY_READ = 0 HDCP_KEY_ERROR = 0 READ KSV AND CHECKSUM CS1 FROM HDCP OTP ROM DERIVE CHECKSUM CS1' FROM KSV CS1 = CS1' NO HDCP_KEY_ERROR = 1 YES SET BKSV (HDCP REGISTER ADDRESS 0x00 BKSV = KSV 13807-008 HDCP_KEY_READ = 1 HDCP_KEY_ERROR = 0 END Figure 8. HDCP ROM Access After Power-Up Rev. A | Page 32 of 168 ADV7613 Reference Manual UG-907 START (AKSV UPDATE FROM TRANSMITTER) HDCP_KEY_READ = 0 HDCP_KEY_ERROR = 0 READ KSV, HDCP KEYS AND CHECKSUM CS2 FROM HDCP PROM DERIVE CHECKSUM CS2' FROM KSV AND HDCP KEYS CS1 = CS1' NO HDCP_KEY_ERROR = 1 YES DERIVE LINK VERIFICATION Ri' UPDATE BKSV AND Ri' IN HDCP RESGISTERS 13807-009 HDCP_KEY_READ = 1 END HDCP_KEY_ERROR = 0 END Figure 9. HDCP ROM Access After KSV Update from the Transmitter After the device has powered up, it is recommended to wait for 1 ms before checking the HDCP_KEYS_READ and HDCP_KEY_ERROR flag bits. This ensures that the ADV7613 had sufficient time to access the internal HDCP ROM and set the HDCP_KEYS_READ and HDCP_KEY_ERROR flag bits. After an HDCP transmitter key selection vector (AKSV) update from the transmitter, it is recommended to wait for 2 ms before checking the HDCP_KEYS_READ and HDCP_KEY_ERROR flag bits. This ensures that the ADV7613 had sufficient time to access the internal HDCP ROM, and set the HDCP_KEYS_READ and HDCP_KEY_ERROR flag bits. When the ADV7613 successfully retrieves the HDCP keys and/or KSV from the internal HDCP ROM, the HDCP_KEYS_READ flag bit is set to 1 and the HDCP_KEY_ERROR flag bit is set to 0. The I2C controllers for the main I2C lines and the HDCP lines are independent of each other. It is, therefore, possible to access the internal registers of the ADV7613 while it reads the HDCP keys and/or the KSV from the internal HDCP ROM. A hardware reset (that is, reset via the reset pin) does not lead the ADV7613 to read the KSV or the keys from the HDCP ROM. The ADV7613 takes 1.8 ms to read the keys from the HDCP ROM. HDCP Ri Expired The following register allows early detection of HDMI transmitter (Tx) failure. See also the interrupt status control, RI_EXPIRED_A_ST. HDCP_RI_EXPIRED, Address 68 (HDMI), Address 0x04[3] (Read Only) This bit reads back high when a calculated Ri has not been read by the source Tx on the active port. It remains high until the next AKSV update. Table 66. HDCP_RI_EXPIRED Function Description HDCP_RI_EXPIRED 0 (default) 1 Description Calculated Ri has been read by the source Tx Calculated Ri has not been read by the source Tx Rev. A | Page 33 of 168 UG-907 ADV7613 Reference Manual HDMI SYNCHRONIZATION PARAMETERS The ADV7613 contains the logic required to measure the details of the incoming video resolution. The HDMI synchronization parameters readback registers from the HDMI map can be used, in addition to the STDI registers from the CP (see the Standard Detection and Identification section), to estimate the video resolution of the incoming HDMI stream. Note that the synchronization parameters are valid if the part is configured in HDMI mode via PRIM_MODE[3:0]. Also note that the HDMI synchronization filter readback parameters are valid even while the part free runs (see the Free Run Mode section) on the condition that the measurement filters have locked. Horizontal Filter and Measurements The HDMI horizontal filter performs measurements on the data enable (DE) and horizontal synchronization (HSYNC) of the HDMI stream on the selected port. The ADV7613 also performs horizontal measurements on the background port as selected by BG_MEAS_PORT_SEL[2:0]. These measurements are available in the HDMI map and can be used to determine the resolution of the incoming video data streams. Primary Port Horizontal Filter Measurements The HDMI horizontal filter performs the measurements described in this section on the HDMI port selected by HDMI_PORT_SELECT. The horizontal measurements are valid only if DE_REGEN_LCK_RAW is set to 1. The HDMI horizontal filter is used solely to measure the horizontal synchronization signals decoded from the HDMI stream. The HDMI horizontal filter is not in the main path of the synchronization processed by the part and does not delay the overall HDMI data into video data out latency. The unit for horizontal filter measurement is a pixel, that is, the actual element of the picture content encapsulated in the HDMI/DVI stream, which the ADV7613 processes. A pixel has a duration TPIXEL, which is provided in Equation 2, unit time of horizontal filter measurements. TPIXEL = TFTMDS × DEEP_COLOR_RATIO × (PIXEL_REPETITION + 1) (2) where: TFTMDS is the TMDS frequency. DEEP_COLOR_RATIO = 1 for 24-bit deep color. PIXEL_REPETITION is the number of repeated pixels in the input HDMI stream. DE_REGEN_FILTER_LOCKED, Address 68 (HDMI), Address 0x07[5] (Read Only) This bit shows the DE regeneration filter lock status. It indicates that the DE regeneration section has locked to the received DE and horizontal synchronization parameter measurements are valid for readback. Table 67. DE_REGEN_FILTER_LOCKED Function Description DE_REGEN_FILTER_LOCKED 0 (default) 1 Description DE regeneration not locked DE regeneration locked to incoming DE DE_REGEN_LCK_RAW, IO, Address 0x6A[0] (Read Only) This bit is the raw status of the DE regeneration lock signal. Table 68. DE_REGEN_LCK_RAW Function Description DE_REGEN_LCK_RAW 0 (default) 1 Description DE regeneration block has not been locked. DE regeneration block has been locked to the incoming DE signal. TOTAL_LINE_WIDTH[13:0], Address 68 (HDMI), Address 0x1E[5:0]; Address 0x1F[7:0] (Read Only) TOTAL_LINE_WIDTH[13:0] is the total line width is a horizontal synchronization measurement. This gives the total number of pixels per line. This measurement is valid only when the DE regeneration filter has locked. Table 69. TOTAL_LINE_WIDTH[13:0] Function Description TOTAL_LINE_WIDTH[13:0] xxxxxxxxxxxxx Description Total number of pixels per line Rev. A | Page 34 of 168 ADV7613 Reference Manual UG-907 LINE_WIDTH[12:0], Address 68 (HDMI), Address 0x07[4:0]; Address 0x08[7:0] (Read Only) Line width is a horizontal synchronization measurement, which gives the number of active pixels in a line. This measurement is only valid when the DE regeneration filter is locked. Table 70. LINE_WIDTH[12:0] Function Description LINE_WIDTH[12:0] 00000000000 (default) xxxxxxxxxxx Description Total number of active pixels per line Total number of active pixels per line HSYNC_FRONT_PORCH[12:0], Address 68 (HDMI), Address 0x20[4:0]; Address 0x21[7:0] (Read Only) HSYNC front porch width is a horizontal synchronization measurement. The unit of this measurement is unique pixels. This measurement is valid only when the DE regeneration filter has locked. Table 71. HSYNC_FRONT_PORCH[12:0] Function Description HSYNC_FRONT_PORCH[12:0] xxxxxxxxxxx Description Total number of pixels in the front porch HSYNC_PULSE_WIDTH[12:0], Address 68 (HDMI), Address 0x22[4:0]; Address 0x23[7:0] (Read Only) HSYNC pulse width is a horizontal synchronization measurement. The unit of this measurement is unique pixels. This measurement is valid only when the DE regeneration filter has locked. Table 72. HSYNC_PULSE_WIDTH[12:0] Function Description HSYNC_PULSE_WIDTH[12:0] xxxxxxxxxxx Description Total number of pixels in the HSYNC pulse HSYNC_BACK_PORCH[12:0], Address 68 (HDMI), Address 0x24[4:0]; Address 0x25[7:0] (Read Only) HSYNC back porch width is a horizontal synchronization measurement. The unit of this measurement is unique pixels. This measurement is valid only when the DE regeneration filter has locked. Table 73. HSYNC_BACK_PORCH[12:0] Function Description HSYNC_BACK_PORCH[12:0] xxxxxxxxxxx Description Total number of pixels in the back porch DVI_HSYNC_POLARITY, Address 68 (HDMI), Address 0x05[5] (Read Only) This bit is a readback to indicate the polarity of the HSYNC encoded in the input stream. Table 74. DVI_HSYNC_POLARITY Function Description Description The HSYNC is active low. The HSYNC is active high. A DATA ENABLE B D C E HSYNC NOTE: A TOTAL NUMBER OF PIXELS PER LINE B ACTIVE NUMBER OF PIXELS PER LINE C HSYNC FRONT PORCH WIDTH IN PIXEL UNIT D HSYNC WIDTH IN PIXEL UNIT E HSYNC BACK PORCH WIDTH IN PIXEL UNIT Figure 10. Horizontal Timing Parameters Rev. A | Page 35 of 168 13807-010 DVI_HSYNC_POLARITY 0 (default) 1 UG-907 ADV7613 Reference Manual Background Port Horizontal Filter Measurements The HDMI horizontal filter performs the measurements described in this section on the HDMI port selected by BG_MEAS_PORT_SEL[2:0]. Note that BG_PARAM_LOCK must be high for background horizontal and vertical measurements to be valid. BG_PARAM_LOCK, Address 68 (HDMI), Address 0xEA[1] (Read Only) This bit is a flag to indicate that vertical and horizontal parameters have been locked during a background measurement. Table 75. BG_PARAM_LOCK Function Description BG_PARAM_LOCK 0 (default) 1 Description Horizontal and vertical were not locked when measurement for select background HDMI port were taken. Horizontal and vertical were locked when measurement for select background HDMI port were taken. BG_TOTAL_LINE_WIDTH[13:0], Address 68 (HDMI), Address 0xE4[5:0]; Address 0xE5[7:0] (Read Only) Background port total line width, a horizontal synchronization measurement for the background HDMI Port determined by BG_MEAS_PORT_SEL[2:0]. The value represents the total number of pixels in a line and is updated when a update request is made via the BG_MEAS_REQ control bit. This measurement is only valid when BG_PARAM_LOCK is set to 1. Table 76. BG_TOTAL_LINE_WIDTH[13:0] Function Description BG_TOTAL_LINE_WIDTH[13:0] xxxxxxxxxxxxx Description The total number of pixels per line on the background measurement port BG_LINE_WIDTH[12:0], Address 68 (HDMI), Address 0xE2[4:0]; Address 0xE3[7:0] (Read Only) Background port line width, a horizontal synchronization measurement for the background HDMI Port determined by BG_MEAS_PORT_SEL[2:0]. The value represents the number of active pixels in a line and is updated when a update request is made via the BG_MEAS_REQ control bit. Table 77. BG_LINE_WIDTH[12:0] Function Description BG_LINE_WIDTH[12:0] 0000000000000 (default) xxxxxxxxxxxxx Description The number of active pixels per line on the background measurement port. The number of active pixels per line on the background measurement port. Horizontal Filter Locking Mechanism The locking/unlocking mechanism of the HDMI horizontal filter is as follows. The HDMI horizontal filter locks if the following two conditions are met: • • The DE transitions occur at the exact same pixel count for eight consecutive video lines. The HSYNC transitions occur at the exact same pixel count for eight consecutive video lines. The HDMI horizontal filter unlocks if either of the two following conditions are met: • • The DE transitions occur on different pixels count for 15 consecutive video lines. The HSYNC transitions occur on different pixels count for 15 consecutive video lines. Vertical Filters and Measurements The ADV7613 integrates an HDMI vertical filter that performs measurements on the vertical synchronization (VSYNC) of the HDMI stream on the selected port. The ADV7613 also performs vertical measurements on the background port as selected by BG_MEAS_PORT_SEL[2:0].These measurements are available in the HDMI map and can be used to determine the resolution of the incoming video data streams. Primary Port Vertical Filter Measurements The HDMI vertical filter performs the measurements on the HDMI port selected by HDMI_PORT_SELECT. The Field 0 measurements are adequate to determine the standard of incoming progressive modes. Use a combination of Field 0 and Field 1 measurements to determine the standard of interlaced modes. Rev. A | Page 36 of 168 ADV7613 Reference Manual UG-907 Note that the vertical measurements are valid only if V_LOCKED_RAW is set to 1. The HDMI vertical filter is used solely to measure the vertical synchronization signals decoded from the HDMI stream. This filter is not in the main path of the synchronization processed by the part and does not delay the overall HDMI data into video data out latency. VERT_FILTER_LOCKED, Address 68 (HDMI), Address 0x07[7] (Read Only) VERT_FILTER_LOCKED is the vertical filter lock status. Indicates whether the vertical filter is locked and vertical synchronization parameter measurements are valid for readback. Table 78. VERT_FILTER_LOCKED Function Description VERT_FILTER_LOCKED 0 1 Description Vertical filter has not locked. Vertical filter has locked. V_LOCKED_RAW, IO, Address 0x6A[1] (Read Only) V_LOCKED_RAW is the raw status of the vertical sync filter locked signal. Table 79. V_LOCKED_RAW Function Description V_LOCKED_RAW 0 1 Description Vertical sync filter has not locked and vertical sync parameters are not valid Vertical sync filter has locked and vertical sync parameters are valid Note that Field 0 measurements are used to determine the video modes that are progressive. FIELD0_TOTAL_HEIGHT[13:0], Address 68 (HDMI), Address 0x26[5:0]; Address 0x27[7:0] (Read Only) Field 0 total height is a vertical synchronization measurement. This readback gives the total number of half lines in Field 0. This measurement is valid only when the vertical filter has locked. Table 80. FIELD0_TOTAL_HEIGHT[13:0] Function Description FIELD0_TOTAL_HEIGHT[13:0] xxxxxxxxxxxxxx Description The total number of half lines in Field 0 (divide readback by 2 to get number of lines) FIELD0_HEIGHT[12:0], Address 68 (HDMI), Address 0x09[4:0]; Address 0x0A[7:0] (Read Only) Field 0 height is a vertical filter measurement. This readback gives the number of active lines in Field 0. This measurement is valid only when the vertical filter has locked. Table 81. FIELD0_HEIGHT[12:0] Function Description FIELD0_HEIGHT[12:0] xxxxxxxxxxxxx Description The number of active lines in Field 0 FIELD0_VS_FRONT_PORCH[13:0], Address 68 (HDMI), Address 0x2A[5:0]; Address 0x2B[7:0] (Read Only) Field 0 VSYNC front porch width is a vertical synchronization measurement. The unit of this measurement is half lines. This measurement is valid only when the vertical filter has locked. Table 82. FIELD0_VS_FRONT_PORCH[13:0] Function Description FIELD0_VS_FRONT_PORCH[13:0] xxxxxxxxxxxxxx Description The total number of half lines in the VSYNC front porch of Field 0 (divide readback by 2 to get number of lines) FIELD0_VS_PULSE_WIDTH[13:0], Address 68 (HDMI), Address 0x2E[5:0]; Address 0x2F[7:0] (Read Only) Field 0 VSYNC width is a vertical synchronization measurement. The unit for this measurement is half lines. This measurement is valid only when the vertical filter has locked. Table 83. FIELD0_VS_PULSE_WIDTH[13:0] Function Description FIELD0_VS_PULSE_WIDTH[13:0] xxxxxxxxxxxxxx Description The total number of half lines in the VSYNC pulse of Field 0 (divide readback by 2 to get number of lines) Rev. A | Page 37 of 168 UG-907 ADV7613 Reference Manual FIELD0_VS_BACK_PORCH[13:0], Address 68 (HDMI), Address 0x32[5:0]; Address 0x33[7:0] (Read Only) Field 0 VSYNC back porch width is a vertical synchronization measurement. The unit for this measurement is half lines. Table 84. FIELD0_VS_BACK_PORCH[13:0] Function Description FIELD0_VS_BACK_PORCH[13:0] xxxxxxxxxxxxxx Description The total number of half lines in the VSYNC back porch of Field 0 (divide readback by 2 to get number of lines) DVI_VSYNC_POLARITY, Address 68 (HDMI), Address 0x05[4] (Read Only) DVI_VSYNC_POLARITY is a readback to indicate the polarity of the VSYNC encoded in the input stream. Table 85. DVI_VSYNC_POLARITY Function Description DVI_VSYNC_POLARITY 0 1 Description The VSYNC is active low. The VSYNC is active high. A B DATA ENABLE HSYNC C D E NOTE: A TOTAL NUMBER OF LINES IN FIELD 0. UNIT IS IN HALF LINES. B ACTIVES NUMBER OF LINES IN FIELD 0. UNIT IS IN HALF LINES. C VSYNC FRONT PORCH WIDTH IN FIELD 0. UNIT IS IN HALF LINES. D VSYNC PULSE WIDTH IN FIELD 0. UNIT IS IN HALF LINES. E VSYNC BACK PORCH WIDTH IN FIELD 0. UNIT IS IN HALF LINES. 13807-011 VSYNC Figure 11. Vertical Parameters for FIELD 0 Note that Field 1 measurements must not be used for progressive video modes. FIELD1_TOTAL_HEIGHT[13:0], Address 68 (HDMI), Address 0x28[5:0]; Address 0x29[7:0] (Read Only) Field 1 total height is a vertical synchronization measurement. This readback gives the total number of half lines in Field 1. This measurement is valid only when the vertical filter has locked. Field 1 measurements are valid when HDMI_INTERLACED is set to 1. Table 86. FIELD1_TOTAL_HEIGHT[13:0] Function Description FIELD1_TOTAL_HEIGHT[13:0] xxxxxxxxxxxxxx Description The total number of half lines in Field 1 (divide readback by 2 to get number of lines) FIELD1_HEIGHT[12:0], Address 68 (HDMI), Address 0x0B[4:0]; Address 0x0C[7:0] (Read Only) Field 1 height is a vertical filter measurement. This readback gives the number of active lines in field. This measurement is valid only when the vertical filter has locked. Field 1 measurements are only valid when HDMI_INTERLACED is set to 1. Table 87. FIELD1_HEIGHT[12:0] Function Description FIELD1_HEIGHT[12:0] xxxxxxxxxxxxx Description The number of active lines in Field 1 FIELD1_VS_FRONT_PORCH[13:0], Address 68 (HDMI), Address 0x2C[5:0]; Address 0x2D[7:0] (Read Only) Field 1 VSYNC front porch width is a vertical synchronization measurement. The unit of this measurement is half lines. This measurement is valid only when the vertical filter has locked. Field 1 measurements are valid when HDMI_INTERLACED is set to 1. Table 88. FIELD1_VS_FRONT_PORCH[13:0] Function Description FIELD1_VS_FRONT_PORCH[13:0] xxxxxxxxxxxxxx Description The total number of half lines in the VSYNC front porch of Field 1 (divide readback by 2 to get number of lines) Rev. A | Page 38 of 168 ADV7613 Reference Manual UG-907 FIELD1_VS_PULSE_WIDTH[13:0], Address 68 (HDMI), Address 0x30[5:0]; Address 0x31[7:0] (Read Only) Field 1 VSYNC width is a vertical synchronization measurement. The unit for this measurement is half lines. This measurement is valid only when the vertical filter has locked. Field 1 measurements are valid when HDMI_INTERLACED is set to 1. Table 89. FIELD1_VS_PULSE_WIDTH[13:0] Function Description FIELD1_VS_PULSE_WIDTH[13:0] xxxxxxxxxxxxxx Description The total number of half lines in the VSYNC pulse of Field 1 (divide readback by 2 to get number of lines) FIELD1_VS_BACK_PORCH[13:0], Address 68 (HDMI), Address 0x34[5:0]; Address 0x35[7:0] (Read Only) Field 1 VSYNC back porch width is a vertical synchronization measurement. The unit for this measurement is half lines. This measurement is valid only when the vertical filter has locked. Field 1 measurements are valid when HDMI_INTERLACED is set to 1. Table 90. FIELD1_VS_BACK_PORCH[13:0] Function Description FIELD1_VS_BACK_PORCH[13:0] xxxxxxxxxxxxx Description The number of half lines in the VSYNC back porch of Field 1 (divide readback by 2 to get number of lines) A B DATA ENABLE HSYNC C D E NOTE: A TOTAL NUMBER OF LINES IN FIELD 1. UNIT IS IN HALF LINES. B ACTIVES NUMBER OF LINES IN FIELD 1. UNIT IS IN HALF LINES. C VSYNC FRONT PORCH WIDTH IN FIELD 1. UNIT IS IN HALF LINES. D VSYNC PULSE WIDTH IN FIELD 1. UNIT IS IN HALF LINES. E VSYNC BACK PORCH WIDTH IN FIELD 1. UNIT IS IN HALF LINES. 13807-012 VSYNC Figure 12. Vertical Parameters for Field 1 The vertical filter provides the interlaced status of the video stream. The interlaced status HDMI_INTERLACED is valid only if the vertical filter is locked and V_LOCKED_RAW is set to 1. HDMI_INTERLACED, Address 68 (HDMI), Address 0x0B[5] (Read Only) This bit is the HDMI input interlace status, a vertical filter measurement. Table 91. HDMI_INTERLACED Function Description HDMI_INTERLACED 0 1 Description Progressive Input Interlaced Input Background Port Vertical Filter Measurements The HDMI vertical filter performs the measurements described in this section on the HDMI port selected by BG_MEAS_PORT_SEL[2:0]. Note that BG_PARAM_LOCK must be high for background horizontal and vertical measurements to be valid. BG_TOTAL_FIELD_HEIGHT[12:0], Address 68 (HDMI), Address 0xE8[4:0]; Address 0xE9[7:0] (Read Only) Background port total field height is a vertical synchronization measurement for the background HDMI port determined by BG_MEAS_PORT_SEL[2:0]. The value represents the total number of lines in a field and is updated when an update request is made via the BG_MEAS_REQ control bit. Table 92. BG_TOTAL_FIELD_HEIGHT[12:0] Function Description BG_TOTAL_FIELD_HEIGHT[12:0] 0000000000000 Description The total number of lines in a field on the background measurement port Rev. A | Page 39 of 168 UG-907 ADV7613 Reference Manual BG_FIELD_HEIGHT[12:0], Address 68 (HDMI), Address 0xE6[4:0]; Address 0xE7[7:0] (Read Only) Background port field height is a vertical synchronization measurement for a background HDMI port determined by BG_MEAS_PORT_SEL[2:0]. The value represents the number of active lines in a field and is updated when an update request is made via the BG_MEAS_REQ control bit. Table 93. BG_FIELD_HEIGHT[12:0] Function Description BG_FIELD_HEIGHT[12:0] 0000000000000 Description The number of active lines in a Field on the background measurement port BG_HDMI_INTERLACED, Address 68 (HDMI), Address 0xEA[0] (Read Only) Background port HDMI input interlace status is a vertical filter measurement for a background HDMI port determined by BG_MEAS_PORT_SEL[2:0]. The status readback is updated when a update request is made via the BG_MEAS_REQ control bit. This measurement is only valid when BG_PARAM_LOCK is set to 1. Table 94. BG_HDMI_INTERLACED Function Description BG_HDMI_INTERLACED 0 1 Description Progressive Input Interlaced Input Vertical Filter Locking Mechanism The HDMI vertical filter locks if the input VSYNC comes at exactly the same line count for two consecutive frames. The HDMI vertical filter unlocks if the VSYNC comes at a different pixels count for two consecutive frames. Low Frequency Formats To process the low frame rate video formats such as 720p24, 720p25, 720p30, 1080p23, 1080p24, and 1080p30, the NEW_VS_PARAM bit must be set (see Figure 13). DE_REGEN_RAW INDICATES A CHANGE IN HSYNC CALCULATE TOTAL HORIZONTAL BLANKING (HSYNC FRONT PORCH + HSYNC PULSE WIDTH + HSYNC BACK PORCH) SET NEW_VS_PARAM TO 0 SET NEW_VS_PARAM TO 1 13807-013 IF TOTAL HORIZONTAL BLANKING IS GREATER THAN TOTAL LINE LENGTH Figure 13. Low Frame Rate Algorithm NEW_VS_PARAM, HDMI, Address 0x4C[2] Enables a new version of vertical parameter extraction for evaluation purposes. That is the version in the background port measurement blocks. Table 95. NEW_VS_PARAM Function Description NEW_VS_PARAM 0 1 Description NEW_VS_PARAM disabled NEW_VS_PARAM enabled Rev. A | Page 40 of 168 ADV7613 Reference Manual UG-907 AUDIO CONTROL AND CONFIGURATION The ADV7613 extracts a pulse coded modulated (L-PCM), IEC 61937 compressed DSD, or HBR audio data stream from their corresponding audio packets (that is, audio sample, DSD, or HBR) encapsulated inside the HDMI data stream. The ADV7613 also regenerates an audio master clock along with the extraction of the audio data. The clock regeneration is performed by an integrated DPLL. The regenerated clock is used to output audio data from the 64 stereo sample depth FIFO to the audio interface configuration pins. Important The ADV7613 supports the extraction of stereo audio data (noncompressed or compressed) at audio sampling frequency up to 192 kHz. The ADV7613 supports the extraction of multichannel audio data. TMDS CLOCK N AUDIO DPLL MCLK CTS AUDIO FIFO AUDIO DATA TMDS CLOCK DELAY LINE RAMPED MUTE/UNMUTE PACKET PROCESSOR (DISPATCH BLOCK) DATA FROM HDCP ENGINE/MASK VIDEO DATA TO DPP BLOCK AUDIO RECONSTRUCTION, SERIALIZATION AND MUXING AP0 AP1 AP2 AP3 AP4 AP5 SCLK CHANNEL STATUS BITS COLLECTION 13807-014 128fs ACR PACKET DATA Figure 14. Audio Processor Block Diagram Audio DPLL The audio DPLL generates an internal audio master clock with a frequency of 128 times the audio sampling frequency, usually called fS. The audio master clock is used to clock the audio processing section. Locking Mechanism When the upstream HDMI transmitter outputs a stable TMDS frequency and consistent audio clock regeneration values, the audio DPLL locks within two cycles of the audio master clock after the following two conditions are met: • • TMDS PLL is locked (see the TMDS_PLL_LOCKED description in Table 45) ADV7613 has received an ACR packet with N and CTS parameters within a valid range The audio DPLL lock status can be monitored via AUDIO_PLL_LOCKED. AUDIO_PLL_LOCKED, Address 68 (HDMI), Address 0x04[0] (Read Only) A readback to indicate the Audio DPLL lock status. Table 96. AUDIO_PLL_LOCKED Function Description AUDIO_PLL_LOCKED 0 (default) 1 Description The audio DPLL is not locked. The audio DPLL is locked. Rev. A | Page 41 of 168 UG-907 ADV7613 Reference Manual ACR Parameters Loading Method The N and CTS parameters from the ACR packets are used to regenerate the audio clock and are reloaded into the DPLL anytime they change. The self clearing FORCE_N_UPDATE bit provides a means to reset the audio DPLL by forcing a reload of the N and CTS parameters from the ACR packet into the audio DPLL. FORCE_N_UPDATE, Address 68 (HDMI), Address 0x5A[0] (Self Clearing) FORCE_N_UPDATE is a control to force an N and CTS value update to the audio DPLL. The audio DPLL regenerates the audio clock. Table 97. FORCE_N_UPDATE Function Description FORCE_N_UPDATE 0 (default) 1 Description No effect Forces an update on the N and CTS values for audio clock regeneration Audio DPLL Coast Feature The audio DPLL incorporates a coast feature that allows it to indefinitely output a stable audio master clock when selectable events occur. The coast feature allows the audio DPLL to provide an audio master clock when the audio processor mutes the audio following a mute condition (see the Audio Muting section). The events that cause the audio DPLL to coast are selected via the coasts masks listed in Table 98. Table 98. Selectable Coast Conditions Bit Name AC_MSK_VCLK_CHNG HDMI Map Address 0x13[6] AC_MSK_VPLL_UNLOCK 0x13[5] AC_MSK_NEW_CTS 0x13[3] AC_MSK_NEW_N 0x13[2] When set to 1, audio DPLL coasts if CTS changes by more than the threshold set in CTS_CHANGE_THRESHOLD[5:0] (see Table 150) When set to 1, audio DPLL coasts if N changes AC_MSK_CHNG_PORT 0x13[1] When set to 1, audio DPLL coasts if active port is changed AC_MSK_VCLK_DET 0x13[0] When set to 1, audio DPLL coasts if no TMDS clock is detected on the active port Description When set to 1, audio DPLL coasts if TMDS clock has any irregular/missing pulses When set to 1, audio DPLL coasts if TMDS PLL unlocks Rev. A | Page 42 of 168 Corresponding Status Register(s) VCLK_CHNG_RAW (see Table 221) TMDS_PLL_LOCKED (see Table 45) CTS_PASS_THRSH_RAW (see Table 149) CHANGE_N_RAW (see Table 148) HDMI_PORT_SELECT (see Table 34) TMDS_CLK_A_RAW (see Table 35) ADV7613 Reference Manual UG-907 AUDIO FIFO The audio FIFO can store up to 128 audio stereo data from the audio sample, DSD or HBR packets. Stereo audio data are added into the FIFO from the audio packet received. Stereo audio data are retrieved from the FIFO at a rate corresponding to 128 times the audio sampling frequency, fS. The status of the audio FIFO can be monitored through the following status flags: FIFO_UNDERFLO_RAW, FIFO_OVERFLO_RAW, FIFO_NEAR_OVFL_RAW, and FIFO_NEAR_UFLO_RAW. ADDRESS ORDER EMPTY ADDRESS 63 … … … EMPTY STEREO DATA N – 1 STEREO DATA N – 2 WRITE POINTER ADDRESS N + 2 ADDRESS N + 1 ADDRESS N … … … STEREO DATA 1 ADDRESS 3 STEREO DATA 0 ADDRESS 2 EMPTY ADDRESS 1 EMPTY ADDRESS 0 13807-015 READ POINTER Figure 15. Audio FIFO FIFO_UNDERFLO_RAW, IO, Address 0x7E[6] (Read Only) FIFO_UNDERFLO_RAW is the status of audio FIFO underflow interrupt signal. When set to 1, it indicates the audio FIFO read pointer has reached the write pointer causing the audio FIFO to underflow. Once set, this bit remains high until it is cleared via AUDIO_FIFO_UNDERFLO_CLR. Table 99. FIFO_UNDERFLO_RAW Function Description FIFO_UNDERFLO_RAW 0 (default) 1 Description Audio FIFO has not underflowed. Audio FIFO has underflowed. FIFO_OVERFLO_RAW, IO, Address 0x7E[5] (Read Only) FIFO_OVERFLO_RAW is the status of audio FIFO overflow interrupt signal. When set to 1, it indicates audio FIFO write pointer has reached the read pointer causing the audio FIFO to overflow. Once set, this bit remains high until it is cleared via AUDIO_FIFO_OVERFLO_CLR. Table 100. FIFO_OVERFLO_RAW Function Description FIFO_OVERFLO_RAW 0 (default) 1 Description Audio FIFO has not overflowed. Audio FIFO has overflowed. Rev. A | Page 43 of 168 UG-907 ADV7613 Reference Manual FIFO_NEAR_UFLO_RAW, IO, Address 0x83[0] (Read Only) FIFO_NEAR_UFLO_RAW is the status of audio FIFO near underflow interrupt signal. When set to 1, it indicates the audio FIFO is near underflow as the number of FIFO registers containing stereo data is less or equal to value set in AUDIO_FIFO_ALMOST_EMPTY_ THRESHOLD. Once set, this bit remains high until it is cleared via FIFO_NEAR_UFLO_CLR. Table 101. FIFO_NEAR_UFLO_RAW Function Description FIFO_NEAR_UFLO_RAW 0 (default) 1 Description Audio FIFO has not reached low threshold defined in AUDIO_FIFO_ALMOST_EMPTY_THRESHOLD [5:0]. Audio FIFO has reached low threshold defined in AUDIO_FIFO_ALMOST_EMPTY_THRESHOLD [5:0]. FIFO_NEAR_OVFL_RAW, IO, Address 0x7E[7] (Read Only) FIFO_NEAR_OVFL_RAW is the status of audio FIFO near overflow interrupt signal. When set to 1, it indicates the audio FIFO is near overflow as the number FIFO registers containing stereo data is greater or equal to value set in AUDIO_FIFO_ALMOST_FULL_ THRESHOLD. Once set, this bit remains high until it is cleared via FIFO_NEAR_OVFL_CLR. Table 102. FIFO_NEAR_OVFL_RAW Function Description FIFO_NEAR_OVFL_RAW 0 (default) 1 Description Audio FIFO has not reached high threshold defined in AUDIO_FIFO_ALMOST_FULL_THRESHOLD [5:0] Audio FIFO has reached high threshold defined in AUDIO_FIFO_ALMOST_FULL_THRESHOLD [5:0] AUDIO_FIFO_ALMOST_EMPTY_THRESHOLD[6:0], Address 68 (HDMI), Address 0x12[6:0] This bitfield sets the threshold used for FIFO_NEAR_UFLO_RAW. The FIFO_NEAR_UFLO_ST interrupt is triggered if audio FIFO goes below this level. Table 103. AUDIO_FIFO_ALMOST_EMPTY_THRESHOLD[6:0] Function Description AUDIO_FIFO_ALMOST_EMPTY_THRESHOLD[6:0] 0x02 (default) Description Default value AUDIO_FIFO_ALMOST_FULL_THRESHOLD[6:0], Address 68 (HDMI), Address 0x11[6:0] This bitfield ets the threshold used for FIFO_NEAR_OVRFL_RAW. FIFO_NEAR_OVRFL_ST interrupt is triggered if audio FIFO reaches this level. Table 104. AUDIO_FIFO_ALMOST_FULL_THRESHOLD[6:0] Function Description AUDIO_FIFO_ALMOST_FULL_THRESHOLD[6:0] 0x7D (default) Description Default value Rev. A | Page 44 of 168 ADV7613 Reference Manual UG-907 AUDIO PACKET TYPE FLAGS The ADV7613 can receive the following audio packets: • • • • Audio sample packets (receive and process) HBR packets (receive and process) DSD packets (receive and process) DST packets (detection only) The following flags are provided to monitor the type of audio packets received by the ADV7613. Figure 16 shows the algorithm that can be implemented to monitor the type of audio packet processed by the ADV7613. AUDIO_MODE_CHNG_RAW, IO, Address 0x83[5] (Read Only) This bit is the status of audio mode change interrupt signal. When set to 1, it indicates that the type of audio packet received has changed. The following are considered audio modes, no audio packets, audio sample packet, DSD packet, HBR packet or DST packet. Once set, this bit remains high until it is cleared via AUDIO_MODE_CHNG_CLR. Table 105. AUDIO_MODE_CHNG_RAW Function Description AUDIO_MODE_CHNG_RAW 0 (default) 1 Description Audio mode has not changed. Audio mode has changed. AUDIO_SAMPLE_PCKT_DET, Address 68 (HDMI), Address 0x18[0] (Read Only) This is the audio sample packet detection bit. This bit resets to zero on the 11th HSYNC leading edge following an audio packet if a subsequent audio sample packet has not been received or if a DSD, DST, or HBR audio packet sample packet has been received. Table 106. AUDIO_SAMPLE_PCKT_DET Function Description AUDIO_SAMPLE_PCKT_DET 0 (default) 1 Description No L_PCM or IEC 61937 compressed audio sample packet received within the last 10 HSYNCs L_PCM or IEC 61937 compressed audio sample packet received within the last 10 HSYNCs DSD_PACKET_DET, Address 68 (HDMI), Address 0x18[1] (Read Only) This is the DSD audio packet detection bit. This bit resets to zero on the 11th HSYNC leading edge following a DSD packet or if an audio, DST, or HBR packet sample packet has been received or after an HDMI reset condition. Table 107. DSD_PACKET_DET Function Description DSD_PACKET_DET 0 (default) 1 Description No DSD packet received within the last 10 HSYNCs DSD packet received within the last 10 HSYNCs DST_AUDIO_PCKT_DET, Address 68 (HDMI), Address 0x18[2] (Read Only) This is the DST audio packet detection bit. This bit resets to zero on the 11th HSYNC leading edge following a DST packet if a subsequent DST has not been received. Or if an audio, DSD, or HBR packet sample packet has been received or after an HDMI reset condition. Table 108. DST_AUDIO_PCKT_DET Function Description DST_AUDIO_PCKT_DET 0 (default) 1 Description No DST packet received within the last 10 HSYNCs DST packet received within the last 10 HSYNCs Rev. A | Page 45 of 168 UG-907 ADV7613 Reference Manual HBR_AUDIO_PCKT_DET, Address 68 (HDMI), Address 0x18[3] (Read Only) This is the HBR packet detection bit. This bit resets to zero on the 11th HSYNC leading edge following an HBR packet if a subsequent HBR packet has not been detected. It also resets if an Audio, DSD or DST packet sample packet has been received and after an HDMI reset condition. Table 109. HBR_AUDIO_PCKT_DET Function Description HBR_AUDIO_PCKT_DET 0 (default) 1 Description No HBR audio packet received within the last 10 HSYNCs HBR audio packet received within the last 10 HSYNCs Note that the ADV7613 processes only one type of audio packet at a time, and processes the latest type of audio packet that it received. AUDIO_SAMPL_PCKT_DET, DSD_PACKET_DET, DST_AUDIO_PCKT_DET, and HBR_AUDIO_PCKT_DET are reset to 0 when a HDMI packet detect reset condition occurs. A corresponding interrupt can be enabled for AUDIO_MODE_CHNG_RAW by setting the mask AUDIO_MODE_CHNG_MB1 or AUDIO_MODE_CHNG_MB2. See the Interrupts section for additional information on the interrupt feature. START ENABLE THE AUDIO_MODE_CHNG_ST INTERRUPT YES AUDIO_MODE_CH NG_ST INTERRUPT? NO AUDIO SAMPLE PACKETS ARE BEING RECEIVED NO IS AUDIO_SAMPLE PCKT_DET? YES AUDIO SAMPLE PACKETS ARE BEING RECEIVED NO DSD PACKETS ARE BEING RECEIVED NO IS DSD_PACKET_DET? YES DSD PACKETS ARE BEING RECEIVED NO DST PACKETS ARE BEING RECEIVED NO IS DST_PACKET_DET? YES DST PACKETS ARE BEING RECEIVED NO HBR PACKETS ARE BEING RECEIVED NO IS HBR_PACKET_DET? YES HBR PACKETS ARE BEING RECEIVED Figure 16. Monitoring Audio Packet Type Processed by ADV7613 Rev. A | Page 46 of 168 13807-016 SET AUDIO_MODE_CHNG_CLR TO 1 ADV7613 Reference Manual UG-907 AUDIO OUTPUT INTERFACE The ADV7613 has a dedicated three-pin audio output interface. The output pin names and descriptions are shown in Table 110. Table 110. Audio Outputs and Clocks Output Pixel Port AP0 AP1 AP2 AP3 AP4 AP5 SCLK/INT2 MCLK/INT2 Description Audio Output Port 0 Audio Output Port 1 Audio Output Port 2 Audio Output Port 3 Audio Output Port 4 Audio Output Port 5 Bit Clock Audio Master Clock Table 111 shows the default configurations for the various possible output interfaces. Table 111. Default Audio Output Pixel Port Mapping Output Pixel Port AP0 AP1 AP2 AP3 AP4 AP5 I2S/SPDIF Interface SPDIF0 I2S0/SDPIF0 I2S1/SDPIF1 I2S2/SPDIF2 I2S3/SPDIF3 LRCLK DSD Interface DSD0A DSD0B DSD1A DSD1B DSD2A DSD2B Note that it is possible to tristate the audio pins using the global controls, as described in the Tristate Audio Output Drivers section. It is possible to output an AP0 signal (SPDIF0) to the AP1 pin using MUX_SPDIF_TO_I2S_ENABLE. MUX_SPDIF_TO_I2S_ENABLE, Address 68 (HDMI), Address 0x6E[3] This bit enables muxing SPDF data into the I2S pins (AP1). Table 112. MUX_SPDIF_TO_I2S_ENABLE Function Description MUX_SPDIF_TO_I2S_ENABLE 0 (default) 1 Description Do not modify I2S outputs Mux SPDIF into I2S pins I2S/SPDIF Audio Interface and Output Controls Two controls are provided to change the mapping between the audio output ports and the I2S and SPDIF (IEC60958) signals. I2S_SPDIF_MAP_ROT[1:0], Address 68 (HDMI), Address 0x6D[5:4] I2S_SPDIF_MAP_ROT[1:0] is a control to select the arrangement of the I2S/SPDIF interface on the audio output port pins. Table 113. I2S_SPDIF_MAP_ROT[1:0] Function Description I2S_SPDIF_MAP_ROT[1:0] 00 (default) 01 10 Description I2S0/SPDIF0 on AP1 I2S1/SPDIF1 on AP2 I2S2/SPDIF2 on AP3 I2S3/SPDIF3 on AP4 I2S3/SPDIF3 on AP1 I2S0/SPDIF0 on AP2 I2S1/SPDIF1 on AP3 I2S2/SPDIF2 on AP4 I2S2/SPDIF2 on AP1 I2S3/SPDIF3 on AP2 I2S0/SPDIF0 on AP3 I2S1/SPDIF1 on AP4 Rev. A | Page 47 of 168 UG-907 I2S_SPDIF_MAP_ROT[1:0] 11 ADV7613 Reference Manual Description I2S1/SPDIF1 on AP1 I2S2/SPDIF2 on AP2 I2S3/SPDIF3 on AP3 I2S0/SPDIF0 on AP4 I2S_SPDIF_MAP_INV, Address 68 (HDMI), Address 0x6D[6] I2S_SPDIF_MAP_INV is a control to invert the arrangement of the I2S/SPDIF interface on the audio output port pins. Note that the arrangement of the I2S/SPDIF interface on the audio output port pins is determined by I2S_SPDIF_MAP_ROT. Table 114. I2S_SPDIF_MAP_INV Function Description I2S_SPDIF_MAP_INV 0 (default) 1 Description Do not invert arrangement of I2S/SPDIF channels in audio output port pins Invert arrangement of I2S/SPDIF channels in audio output port pins I2S_SPDIF_MAP_ROT[1:0] and I2S_SPDIF_MAP_INV are independent controls. Any combination of values is therefore allowed for I2S_SPDIF_MAP_ROT[1:0] and I2S_SPDIF_MAP_INV. Table 115 and Table 116 show examples of mappings for the I2S/SPDIF signals. Table 115. Audio Mappings for I2S_SPDIF_MAP_ROT = 00, I2S_SPDIF_MAP_INV = 0 (Default) Output Audio Port AP1 AP2 AP3 AP4 I2S/SPDIF Interface I2S0/SDPIF0 I2S1/SDPIF1 I2S2/SDPIF2 I2S3/SDPIF3 Table 116. Audio Mappings for I2S_SPDIF_MAP_ROT = 00, I2S_SPDIF_MAP_INV = 1 Output Audio Port AP1 AP2 AP3 AP4 I2S/SPDIF Interface I2S3/SDPIF3 I2S2/SDPIF2 I2S1/SDPIF1 I2S0/SDPIF0 I2SBITWIDTH[4:0], Address 68 (HDMI), Address 0x03[4:0] I2SBITWIDTH[4:0] is a control to adjust the bit width for right justified mode on the I2S interface. Table 117. I2SBITWIDTH[4:0] Function Description I2SBITWIDTH[4:0] 00000 00001 00010 … 11000 (default) 11110 11111 Description 0 bit 1 bit 2 bits … 24 bits 30 bits 31 bits I2SOUTMODE[1:0], Address 68 (HDMI), Address 0x03[6:5] I2SOUTMODE[1:0] is a control to configure the I2S output interface. Table 118. I2SOUTMODE[1:0] Function Description I2SOUTMODE[1:0] 00 (default) 01 10 11 Description I2S mode Right justified Left justified Raw SPDIF (IEC60958) mode Rev. A | Page 48 of 168 ADV7613 Reference Manual UG-907 I2SOUTMODE[1:0] is effective when the ADV7613 is configured to output I2S streams or AES3 streams, as in the following cases: • • • The ADV7613 receives audio sample packets. The ADV7613 receives HBR packets, OVR_MUX_HBR is set to 1, and MUX_HBR_OUT is set to 2’b00, 2’b01, 2’b10, or 2’b11. In HBR mode, it is required that the part outputs four SPDIF, I2S, or raw IEC60958 streams encapsulating a 24-bit audio sample word. Therefore, I2SBITSWIDTH[4:0] must always be set to 0b11000. The following audio formats can be output when the ADV7613 receives audio sample packets: • • • • • Linear L-PCM audio data is output on the audio output pins if the part received audio sample packets with L-PCM encoded audio data. Each audio output pin carries stereo data that can be output in I2S, right justified, or left justified mode (see Figure 17, Figure 18, and Figure 19). The I2SOUTMODE[1:0] control must be set to 0x0, 0x01, or 0x2 to output I2S, right justified, and left justified respectively on the audio output pins. A stream conforming to the IEC60958 specification when the part receives audio sample packets with L-PCM encoded data (see Figure 20). An AES3 stream if the I2SOUTMODE[1:0] control is set to 0x3 (see Figure 21 and Figure 22). Note that AES3 is also referred to as raw SPDIF. Each AES3 stream may encapsulate stereo L-PCM audio data or multichannel non L-PCM audio data (for example, 5.1 Dolby Digital). Binary stream on the audio output pins when the part receives audio sample packets with non L-PCM encoded audio data (that is, AC-3 compressed audio) and if the following configuration is used: • I2SOUTMODE must be set to 0x0, 0x01, or 0x2 for I2S, right justified, and left justified format, respectively (see Figure 17, Figure 18, and Figure 19). • MT_MSK_COMPRS_AUD is set to 0. • Note that no audio flags are output by the part in that configuration. Each binary stream output by the part may encapsulate stereo L-PCM audio data or multichannel non L-PCM audio data (for example, 5.1 Dolby Digital). A stream conforming to the IEC61937 specification when the part receives audio sample packets with non L-PCM encoded audio data (for example, AC-3 compressed audio). The audio outputs can carry an audio stream that may be stereo or multichannel audio (for example, 5.1 Dolby Digital). Table 119. I2S/SPDIF Interface Description I2S/SPDIF Interface IO SPDIF0 I2S0/SPDIF0 I2S1/SPDIF1 I2S2/SPDIF2 I2S3/SPDIF3 SCLK LRCLK MCLKOUT LRCLK Function SPDIF audio output I2S audio (Channel 1, Channel 2)/SPDIF0 I2S audio (Channel 3, Channel 4)/SPDIF1 I2S audio (Channel 5, Channel 6)/SPDIF2 I2S audio (Channel 7, Channel 8)/SPDIF3 Bit clock Data output clock for left and right channel Audio master clock output LEFT RIGHT SCLK MSB LSB MSB 32 CLOCK SLOTS LSB 32 CLOCK SLOTS Figure 17. Timing Audio Data Output in I2S Mode Rev. A | Page 49 of 168 13807-017 ISx UG-907 ADV7613 Reference Manual LEFT RIGHT MSB MSB MSB MSB – 1 LSB MSB MSB EXTENDED MSB MSB MSB LSB MSB – 1 MSB EXTENDED 32 CLOCK SLOTS 13807-018 MSB 32 CLOCK SLOTS Figure 18. Timing Audio Data Output in Right Justified Mode RIGHT MSB LSB MSB LSB 32 CLOCK SLOTS 13807-019 LEFT 32 CLOCK SLOTS Figure 19. Timing Audio Data Output in Left Justified Mode 0 3 4 SYNC PREAMBLE 27 28 L S B M S B AUDIO SAMPLE WORD V 31 U C P VALIDITY FLAG USER DATA 13807-020 CHANNEL STATUS PARITY BIT Figure 20. IEC 60958 Subframe Timing Diagram 0 23 24 L S B M S B V DATA VALIDITY FLAG 27 U C B 31 0 0 0 0 ZERO PADDING CHANNEL STATUS BLOCK START FLAG Figure 21. AES3 Subframe Timing Diagram Rev. A | Page 50 of 168 13807-021 USER DATA ADV7613 Reference Manual UG-907 CHANNEL A MSB V U C LSB B 32 CLOCK SLOTS MSB V U C B 32 CLOCK SLOTS FRAME N FRAME N + 1 13807-022 LSB CHANNEL B Figure 22. AES3 Stream Timing Diagram DSD Audio Interface and Output Controls The ADV7613 incorporates a 6-DSD channel interface used to output the audio stream extracted from DSD packets. Each of the DSD channels carries an oversampled 1-bit representation of the audio signal as delivered on super audio CDs (SACDs). Table 120. DSD Interface Description DSD Interface IO DSD0A DSD0B DSD1A DSD1B DSD2A DSD2B SCLK MCLKOUT Function First DSD data channel Second DSD data channel Third DSD data channel Fourth DSD data channel Fifth DSD data channel Sixth DSD data channel Bit clock Audio master clock output Two controls are provided to change the mapping between the audio output ports and DSD signals. DSD_MAP_ROT[2:0], Address 68 (HDMI), Address 0x6D[2:0] DSD_MAP_ROT[2:0] is a control to select the arrangement of the DSD interface on the audio output port pins. Table 121. DSD_MAP_ROT[2:0] Function Description DSD_MAP_ROT[2:0] 000 (default) 001 010 Description DSD0A on AP0 DSD0B on AP1 DSD1A on AP2 DSD1B on AP3 DSD2A on AP4 DSD2B on AP5 DSD2B on AP0 DSD0A on AP1 DSD0B on AP2 DSD1A on AP3 DSD1B on AP4 DSD2A on AP5 DSD2A on AP0 DSD2B on AP1 DSD0A on AP2 DSD0B on AP3 DSD1A on AP4 DSD1B on AP5 Rev. A | Page 51 of 168 UG-907 DSD_MAP_ROT[2:0] 011 100 101 110 111 ADV7613 Reference Manual Description DSD1B on AP0 DSD2A on AP1 DSD2B on AP2 DSD0A on AP3 DSD0B on AP4 DSD1A on AP5 DSD1A on AP0 DSD1B on AP1 DSD2A on AP2 DSD2B on AP3 DSD0A on AP4 DSD0B on AP5 DSD0B on AP0 DSD1A on AP1 DSD1B on AP2 DSD2A on AP3 DSD2B on AP4 DSD0A on AP5 Reserved Reserved DSD_MAP_INV, Address 68 (HDMI), Address 0x6D[3] This bit is control to invert the arrangement of the DSD interface on the audio output port pins. Note the arrangement of the DSD interface on the audio output port pins is determined by DSD_MAP_ROT[2:0]. Table 122. DSD_MAP_INV Function Description DSD_MAP_INV 0 (default) 1 Description Do not invert arrangement of the DSD channels on the audio output port pins Invert arrangement of the DSD channels on the audio output port pins DSD_MAP_ROT[2:0]and DSD_MAP_INV are independent controls. Any combination of values is therefore allowed for DSD_MAP_ROT[2:0] and DSD_MAP_INV. Table 123 and Table 124 show examples of mappings for the DSD signals. Table 123. Audio Mapping for DSD_MAP_ROT = 00, DSD_MAP_INV = 0 (Default) Output Pixel Port Name AP0 AP1 AP2 AP3 AP4 AP5 DSD Interface DSD0A DSD0B DSD1A DSD1B DSD2A DSD2B Table 124. Audio Mapping for DSD_MAP_ROT = 00, DSD_MAP_INV = 1 Output Pixel Port Name AP0 AP1 AP2 AP3 AP4 AP5 DSD Interface DSD2B DSD2A DSD1B DSD1A DSD0B DSD0A Note that the DSD0A and DSD0B output must be used when in stereo mode only. DSD0A and DSD0B always carry the main twochannel audio data. DSD1A, DSD1B, DSD2A, and DSD2B are the surround channels. Rev. A | Page 52 of 168 ADV7613 Reference Manual UG-907 DSDxx 1 1WHERE xx IS A CHANNEL, SUCH AS 0A, 0B. 13807-023 SCLK Figure 23. DSD Timing Diagram By default, the ADV7613 automatically enables the DSD interface if it receives DSD packets. The ADV7613 also automatically enables the I2S interface if it receives audio sample packets or if it does not receive any audio packets. However, it is possible to override the audio interface that is used via the OVR_AUTO_MUX_DSD_OUT and MUX_DSD_OUT controls. OVR_AUTO_MUX_DSD_OUT, Address 68 (HDMI), Address 0x01[3] OVR_AUTO_MUX_DSD_OUT is the DSD/DST override control. In automatic control, DSD or I2S interface is selected according to the type of packet received. The DSD/DST interface is enabled if the device receives DSD or DST audio sample packet. The I2S interface is enabled when the device receives audio sample packets or when no packet is received. In manual mode, MUX_DSD_OUT selects the output interface. Table 125. OVR_AUTO_MUX_DSD_OUT Function Description Function OVR_AUTO_MUX_DSD_OUT 0 (default) 1 Description Automatic DSD/DST output control Override DSD/DST output control MUX_DSD_OUT, Address 68 (HDMI), Address 0x01[4] MUX_DSD_OUT is an override control for the DSD output. Table 126. MUX_DSD_OUT Function Description Function MUX_DSD_OUT 0 1 Description Override by outputting I2S data Override by outputting DSD/DST data HBR Interface and Output Controls The ADV7613 can receive HBR audio stream packets. The ADV7613 outputs HBR data over four of the audio output pins in any of the three following formats. The ADV7613 can output HBR data as an SDPIF stream conforming to the IEC60958 specification (see Figure 20). One of the following configurations is required to output an SPDIF stream on the HBR output pins: • • OVR_MUX_HBR is set to 0. OVR_MUX_HBR is set to 1 and MUX_HBR_OUT is set to 1. The ADV7613 can output HBR data as a binary stream, if one of the following configurations is used (note that no audio flags are output by the device in these configurations): • • • OVR_MUX_HBR is set to 1, MUX_HBR_OUT is set to 0, and I2SOUTMODE[1:0] is set to 0x0 for an I2S mode binary stream (see Figure 17). OVR_MUX_HBR is set to 1, MUX_HBR_OUT is set to 0, and I2SOUTMODE[1:0] is set to 0x1 for a right justified stream (see Figure 18). OVR_MUX_HBR is set to 1, MUX_HBR_OUT is set to 0, and I2SOUTMODE[1:0] is set to 0x2 for a left justified stream (see Figure 19). The ADV7613 can output HBR data as an AES3 stream on each HBR interface output pin (see Figure 21 and Figure 22). The following configuration is required to output AES3 streams: • • OVR_MUX_HBR is set to 1. I2SOUTMODE[1:0] is set to 0b11. It is important to note that each of the four HBR outputs carry one of four consecutive blocks of the HBR stream, and the four streams on the four HBR pin are output at one quarter of the audio sample rate, fS. Rev. A | Page 53 of 168 UG-907 ADV7613 Reference Manual Table 127. HBR Interface Description HBR Interface IO AP1 AP2 AP3 AP4 SCLK LRCLK MCLKOUT Function First block of HBR stream. Second block of HBR stream Third block of HBR stream Fourth block of HBR stream Bit clock Data output clock for left and right channel Audio master clock output Note that the audio output mapping controls, I2S_SPDIF_MAP_ROT[1:0] and I2S_SPDIF_MAP_INV, also apply to the HBR output signals. Also note that the audio output interface pin AP0 also carries the SPDIF0 output, regardless of I2S_SPDIF_MAP_ROT[1:0] and I2S_SPDIF_MAP_INV. OVR_MUX_HBR, Address 68 (HDMI), Address 0x01[2] OVR_MUX_HBR is a control to select automatic or manual configuration for HBR outputs. HBR outputs are automatically encoded as SPDIF streams. In manual mode, MUX_HBR_OUT selects the audio output interface. Table 128. OVR_MUX_HBR Function Description OVR_MUX_HBR 0 (default) 1 Description Automatic HBR output control Manual HBR output control MUX_HBR_OUT, Address 68 (HDMI), Address 0x01[1] MUX_HBR_OUT is a control to manually select the audio output interface for HBR data. It is valid when OVR_MUX_HBR is set to 1. Table 129. MUX_HBR_OUT Function Description MUX_HBR_OUT 0 (default) 1 Description Override by outputting I2S data Override by outputting SPDIF data MCLKOUT SETTING The frequency of audio master clock MCLKOUT is set using the MCLK_FS_N[2:0] register, as shown in Equation 3, in the relationship between MCLKOUT, MCLKFS_N, and fS. MCLKOUT = (MCLKFS_N[2:0] + 1) × 128 × fS (3) MCLK_FS_N[2:0], Address 4C (DPLL), Address 0xB5[2:0] MCLK_FS_N[2:0] selects the frequency of MCLK out as multiple of 128 fS. Table 130. MCLK_FS_N[2:0] Function Description MCLK_FS_N[2:0] 000 001 (default) 010 011 100 101 110 111 Description 128 fS 256 fS 384 fS 512 fS 640 fS 768 fS Not valid Not valid Rev. A | Page 54 of 168 ADV7613 Reference Manual UG-907 AUDIO CHANNEL MODE AUDIO_CH_MD_RAW indicates if 2-channel audio data or multichannel audio data is received. AUDIO_CH_MD_RAW, IO, Address 0x65[4] (Read Only) This bit is the raw status signal indicating the layout value of the audio packets that were last received. Table 131. AUDIO_CH_MD_RAW Function Description AUDIO_CH_MD_RAW 0 1 Description The last audio packets received have a layout value of 1. (For example, Layout 1 corresponds to 2-channel audio when audio sample packets are received.) The last audio packets received have a layout value of 0. (For example, Layout 0 corresponds to 8-channel audio when audio sample packets are received.) Note that the audio CH_MD_RAW flag is valid for audio sample packets and DSD packets. AUDIO_CHANNEL_MODE, Address 68 (HDMI), Address 0x07[6] (Read Only) This bit flags stereo or multichannel audio packets. Note that stereo packets can carry compressed multichannel audio. Table 132. AUDIO_CHANNEL_MODE Function Description AUDIO_CHANNEL_MODE 0 1 Description Stereo audio (may be compressed multichannel) Multichannel uncompressed audio detected (Channel 3 to Channel 8). AUDIO MUTING The ADV7613 integrates an advanced audio mute function that is designed to remove all extraneous noise and pops from a 2-channel L-PCM audio stream at sample frequencies up to 48 kHz. The hardware for audio mute function is composed of the following three blocks: • • • Audio delay line that delays Channel 1 and Channel 2 by 512 stereo samples. Audio mute controller takes in event detection signals that can be used to determine when an audio mute is needed. The controller generates a mute signal to the ramped audio block and a coast signal to the digital PLL generating the audio clock. Ramped audio mute block that can mute the audio over the course of 512 stereo samples. Note that the ADV7613 mutes only the noncompressed data from the audio sample packets output through the I2S and the SPDIF interface. The audio delay line is automatically bypassed when the ADV7613 receives multichannel audio or when it receives DSD packets or HBR packets. The ramped audio mute block is always bypassed when the device receives compressed audio or when it receives DSD packets or HBR packets. Delay Line Control The audio delay line must be enabled when the ADV7613 is configured for automatic mute. The audio delay line is controlled by the MAN_AUDIO_DL_BYPASS and AUDIO_DELAY_LINE_BYPASS bits. MAN_AUDIO_DL_BYPASS, Address 68 (HDMI), Address 0x0F[7] This bit is the audio delay bypass manual enable. The audio delay line is automatically active for stereo samples and bypassed for multichannel samples. By setting MAN_AUDIO_DL_BYPASS to 1, the audio delay bypass configuration can be set by the user with the AUDIO_DELAY_LINE_BYPASS control. Table 133. MAN_AUDIO_DL_BYPASS Function Description MAN_AUDIO_DL_BYPASS 0 (default) 1 Description Audio delay line is automatically bypassed if multichannel audio is received. The audio delay line is automatically enabled if stereo audio is received. Overrides automatic bypass of audio delay line. Audio delay line is applied depending on the AUDIO_DELAY_LINE_BYPASS control. Rev. A | Page 55 of 168 UG-907 ADV7613 Reference Manual AUDIO_DELAY_LINE_BYPASS, Address 68 (HDMI), Address 0x0F[6] This bit is the manual bypass control for the audio delay line. It is only valid if MAN_AUDIO_DL_BYPASS is set to 1. Table 134. AUDIO_DELAY_LINE_BYPASS Function Description AUDIO_DELAY_LINE_BYPASS 0 (default) 1 Description Enables the audio delay line Bypasses the audio delay line Audio Mute Configuration The ADV7613 can be configured to automatically mute an L-PCM audio stream when selectable mute conditions occur. Configure the audio muting as follows: • • • • Set the audio muting speed via AUDIO_MUTE_SPEED[4:0]. Set NOT_AUTO_UNMUTE as follows: • Set NOT_AUDIO_UNMUTE[2:0] to 0 if the audio must be unmuted automatically after a delay set in WAIT_UNMUTE[2:0] after all selected mute conditions have become inactive. • Set NOT_AUTO_UNMUTE to 1 if the audio must be unmuted manually (for example, by an external controller) when all selected mute conditions have become inactive. • Select the mute conditions that trigger an audio mute (see Table 139). Select the Audio PLL coast conditions (see the Audio DPLL Coast Feature section). Set WAIT_UNMUTE[2:0] to configure the audio counter that triggers the audio unmute when it has timed out after all selected mute conditions have become inactive. The ADV7613 internally unmutes the audio if the following three conditions (listed in order of priority) are met: • • • Mute conditions are inactive. NOT_AUTO_UNMUTE is set to 0. Audio unmute counter has finished counting down or is disabled. Note that both Table 98 and Table 139 provide a column with the heading, Corresponding Status Register(s). This column lists the status registers that convey information related to their corresponding audio mute masks or coast masks. The ADV7613 also mutes the DSD stream when one of the selected mute conditions occurs (see Table 139) by outputting the DSD mute pattern 0101010101… A DSD decoder receiving this stream outputs a 0 V mean analog stream. The ADV7613 can mute the audio data with compressed audio data or HBR packets. In these cases, mute outputs a constant stream of 0. For the best audio muting performance, it is recommended to set AUDIO_MUTE_SPEED to 1 when the ADV7613 receives multichannel sample packets. For best audio muting performance, the following settings are recommended when the audio sampling frequency of the audio stream is greater than 48 kHz: • • • Set AUDIO_MUTE_SPEED to 1 Set MAN_AUDIO_DL_BYPASS to 1 Set AUDIO_DELAY_LINE_BYPASS to 1 For best audio muting performance, the following settings are recommended when the audio sampling frequency of the audio stream is equal to or lower than 48 kHz: • • Set AUDIO_MUTE_SPEED to 0x1F Set MAN_AUDIO_DL_BYPASS to 0 MUTE_AUDIO, Address 68 (HDMI), Address 0x1A[4] MUTE_AUDIO is a control to force an internal mute independently of the mute mask conditions. Table 135. MUTE_AUDIO Function Description MUTE_AUDIO 0 (default) 1 Description Audio in normal operation Force audio mute Rev. A | Page 56 of 168 ADV7613 Reference Manual UG-907 AUDIO_MUTE_SPEED[4:0], Address 68 (HDMI), Address 0x0F[4:0] AUDIO_MUTE_SPEED[4:0] is the number of samples between each volume change of 1.5 dB when muting and unmuting. Table 136. AUDIO_MUTE_SPEED[4:0] Function Description AUDIO_MUTE_SPEED[4:0] 0x1F (default) Description Default value NOT_AUTO_UNMUTE, Address 68 (HDMI), Address 0x1A[0] NOT_AUTO_UNMUTE is a control to disable the automatic unmute feature. When set to 1, audio can be unmuted manually if all mute conditions are inactive by setting NOT_AUTO_UNMUTE to 0 and then back to 1. Table 137. NOT_AUTO_UNMUTE Function Description NOT_AUTO_UNMUTE 0 (default) 1 Description Audio unmutes following a delay set by WAIT_UNMUTE after all mute conditions have become inactive Prevents audio from unmuting automatically WAIT_UNMUTE[2:0], Address 68 (HDMI), Address 0x1A[3:1] WAIT_UNMUTE[2:0] is a control to delay audio unmute. Once all mute conditions are inactive, WAIT_UNMUTE[2:0] can specify a further delay time before unmuting. NOT_AUTO_UNMUTE must be set to 0 for this control to be effective. Table 138. WAIT_UNMUTE[2:0] Function Description WAIT_UNMUTE[2:0] 000 (default) 001 010 011 100 Description Disables/cancels delayed unmute. Audio unmutes directly after all mute conditions become inactive. Unmutes 250 ms after all mute conditions become inactive. Unmutes 500 ms after all mute conditions become inactive. Unmutes 750 ms after all mute conditions become inactive. Unmutes 1 sec after all mute conditions become inactive. Table 139. Selectable Mute Conditions Bit Name MT_MSK_COMPRS_AUD MT_MSK_AUD_MODE_CHNG HDMI Map Address 0x14[5] 0x14[4] MT_MSK_PARITY_ERR 0x14[1] MT_MSK_VCLK_CHNG 0x14[0] MT_MSK_APLL_UNLOCK MT_MSK_VPLL_UNLOCK MT_MSK_ACR_NOT_DET 0x15[7] 0x15[6] 0x15[5] MT_MSK_FLATLINE_DET MT_MSK_FIFO_UNDERFLOW MT_MSK_FIFO_OVERFLOW MT_MSK_AVMUTE 0x15[3] 0x15[1] 0x15[0] 0x16[7] MT_MSK_NOT_HDMIMODE MT_MSK_NEW_CTS 0x16[6] 0x16[5] MT_MSK_NEW_N MT_MSK_CHMODE_CHNG 0x16[4] 0x16[3] MT_MSK_APCKT_ECC_ERR 0x16[2] Description Causes audio mute if audio is compressed Causes audio mute if audio mode changes between PCM, DSD, DST, or HBR formats Causes audio mute if parity bits in audio samples are not correct Causes audio mute if TMDS clock has irregular/missing pulses Causes audio mute if audio PLL unlocks Causes audio mute if TMDS PLL unlocks Causes audio mute if ACR packets are not received within one VSYNC Causes audio mute if flatline bit in audio packets is set Causes audio mute if audio FIFO underflows Causes audio mute if audio FIFO overflows Causes audio mute if AVMUTE is set in the general control packet Causes audio mute if HDMI_MODE bit goes low Causes audio mute if CTS changes by more than the threshold set in CTS_CHANGE_THRESHOLD[5:0] Causes audio mute if N changes Causes audio mute if the channel mode changes from stereo to multichannel, or vice versa Causes audio mute if uncorrectable error is detected in the audio packets by the ECC block Rev. A | Page 57 of 168 Corresponding Status Register(s) CS_DATA[1] AUDIO_SAMPLE_PCKT_DET PARITY_ERROR_RAW VCLK_CHNG_RAW AUDIO_PLL_LOCKED TMDS_PLL_LOCKED AUDIO_C_PCKT_RAW AUDIO_FLT_LINE_RAW FIFO_UNDERFLO_RAW FIFO_OVERFLO_RAW AV_MUTE_RAW HDMI_MODE CTS_PASS_THRSH_RAW CHANGE_N_RAW AUDIO_MODE_CHNG_RAW AUDIO_PCKT_ERR_RAW UG-907 Bit Name MT_MSK_CHNG_PORT MT_MSK_VCLK_DET ADV7613 Reference Manual HDMI Map Address 0x16[1] 0x16[0] Description Causes audio mute if HDMI port is changed Causes audio mute if TMDS clock is not detected Corresponding Status Register(s) HDMI_PORT_SELECT TMDS_CLK_A_RAW Internal Mute Status The internal mute status is provided through the INTERNAL_MUTE_RAW bit. INTERNAL_MUTE_RAW, IO, Address 0x65[6] (Read Only) This bit is the raw status signal of internal mute signal. Table 140. INTERNAL_MUTE_RAW Function Description INTERNAL_MUTE_RAW 0 (default) 1 Description Audio is not muted Audio is muted AV Mute Status AV_MUTE, Address 68 (HDMI), Address 0x04[6] (Read Only) This bit is the readback of the AVMUTE status received in the last general control packet received. Table 141. AV_MUTE Function Description AV_MUTE 0 (default) 1 Description AVMUTE not set AVMUTE set Audio Mute Signal The ADV7613 can output an audio mute signal that can be used to control the muting in a back end audio device processing the audio data output by the ADV7613 (for example, DSP). The audio mute signal is output on the INT1 pin by setting EN_UMASK_RAW_INTRQ to 1. The mute signal is active high. It is important to note that the ADV7613 may interface with an audio processor (for example, DSP) in which the muting of the audio is implemented. In this case, the audio processor typically features a delay line followed by a mute block for audio mute and unmuting purposes. The following hardware and software configuration is recommended for optimum muting performance of the ADV7613 and audio processor system: • • Connect the mute signal of the ADV7613 to the audio processor mute input. The ADV7613 mute signal can now drive the muting/unmuting of the audio data inside the audio processor. Bypass the audio delay line of the ADV7613 with the following settings: • Set MAN_AUDIO_DL_BYPASS to 1. • Set AUDIO_DELAY_LINE_BYPASS to 1. • Configure the ADV7613 to mute the audio over one audio sample clock. Set AUDIO_MUTE_SPEED[4:0] to 1, which ensures that the ADV7613 never outputs invalid audio data out to the audio processor. EN_UMASK_RAW_INTRQ, IO Map, Address 0x40[3] This bit is a control to apply the audio mute signal on INT1 interrupt pin. Table 142. EN_UMASK_RAW_INTRQ Function Description EN_UMASK_OUT_INTRQ 0 (default) 1 Description Does not output raw interrupt flag on INT1 Outputs raw interrupt flag on INT1 Rev. A | Page 58 of 168 ADV7613 Reference Manual UG-907 Audio Stream with Incorrect Parity Error The ADV7613 discards audio sample packets that have an incorrect parity bit. When these samples are received, the ADV7613 repeats the previous audio sample with a valid parity bit. The audio stream out of the ADV7613 can be muted in this situation if the audio mute mask MT_MSK_PARITY_ERR is set. It is possible to configure the ADV7613 so that it processes audio sample packets that have an incorrect parity bit and corrects the parity bit. The ADV7613 can then output an audio stream even when the parity bits from the audio sample packet are invalid. This configuration is activated by setting MT_MSK_PARITY_ERR 0 and IGNORE_PARITY_ERR to 1. IGNORE_PARITY_ERR, Address 68 (HDMI), Address 0x1A[6] This bit is a control to select the processing of audio samples even when they have a parity error. Table 143. IGNORE_PARITY_ERR Function Description IGNORE_PARITY_ERR 0 (default) 1 Description Discard audio sample packets that have an invalid parity bit Process audio sample packets that have an invalid parity bit MT_MSK_PARITY_ERR, Address 68 (HDMI), Address 0x14[1] MT_MSK_PARITY_ERR is the audio mute mask for a parity error. It sets the audio mutes if an audio sample packet is received with an incorrect parity bit. Table 144. MT_MSK_PARITY_ERR Function Description MT_MSK_PARITY_ERR 1 (default) Description Audio mute occurs if an audio sample packet is received with an incorrect parity bit AUDIO CLOCK REGENERATION PARAMETERS The ADV7613 recreates an internal audio master clock using audio clock regeneration (ACR) values transmitted by the HDMI source. ACR Parameters Readbacks The N and CTS registers can be read back from the HDMI map. CTS[19:0], Address 68 (HDMI), Address 0x5B[7:0]; Address 0x5C[7:0]; Address 0x5D[7:4] (Read Only) CTS[19:0] is a readback for the CTS value received in the HDMI data stream. Table 145. CTS[19:0] Function Description CTS[19:0] 00000000000000000000 (default) xxxxxxxxxxxxxxxxxxxx Description Default CTS value readback from HDMI stream CTS value readback from HDMI stream N[19:0], Address 68 (HDMI), Address 0x5D[3:0]; Address 0x5E[7:0]; Address 0x5F[7:0] (Read Only) N[19:0] is a readback for the N value received in the HDMI data stream. Table 146. N[19:0] Function Description N[19:0] 00000000000000000000 (default) xxxxxxxxxxxxxxxxxxxx Description Default N value readback from HDMI stream N value readback from HDMI stream Note that a buffer is implemented for the N and CTS readback registers. After a read of the HDMI map, Address 0x5B updates the buffer that stores the N and CTS readback registers. The buffer implemented for N and CTS readback allows the reading of both the N and CTS registers within an I2C block read. Rev. A | Page 59 of 168 UG-907 ADV7613 Reference Manual Monitoring ACR Parameters The reception of ACR packets can be notified via the AUDIO_C_PCKT_RAW flag. Changes in N and CTS can be monitored via the CHANGE_N_RAW and CTS_PASS_THRSH_RAW flags, as described in this section. AUDIO_C_PCKT_RAW, IO, Address 0x65[1] (Read Only) AUDIO_C_PCKT_RAW is the raw status signal of audio clock regeneration packet detection signal. Table 147. AUDIO_C_PCKT_RAW Function Description AUDIO_C_PCKT_RAW 0 (default) 1 Description No audio clock regeneration packets received since the last HDMI reset condition Audio clock regeneration packets received CHANGE_N_RAW, IO, Address 0x7E[3] (Read Only) CHANGE_N_RAW is the status of the ACR N value changed interrupt signal. When set to 1, it indicates that the N value of the ACR packets has changed. Once set, this bit remains high until it is cleared via CHANGE_N_CLR. Table 148. CHANGE_N_RAW Function Description CHANGE_N_RAW 0 (default) 1 Description Audio clock regeneration N value has not changed. Audio clock regeneration N value has changed. CTS_PASS_THRSH_RAW, IO, Address 0x7E[4] (Read Only) CTS_PASS_THRSH_RAW is the status of the ACR CTS value exceed threshold interrupt signal. When set to 1, it indicates that the CTS value of the ACR packets has exceeded the threshold set by CTS_CHANGE_THRESHOLD. Once set, this bit remains high until it is cleared via CTS_PASS_THRSH_CLR. Table 149. CTS_PASS_THRSH_RAW Function Description CTS_PASS_THRSH_RAW 0 (default) 1 Description Audio clock regeneration CTS value has not passed the threshold. Audio clock regeneration CTS value has changed more than threshold. CTS_CHANGE_THRESHOLD[5:0], Address 68 (HDMI), Address 0x10[5:0] CTS_CHANGE_THRESHOLD[5:0] sets the tolerance for change in the CTS value. This tolerance is used for the audio mute mask MT_MSK_NEW_CTS and the HDMI status bit CTS_PASS_THRSH_RAW and the HDMI interrupt status bit CTS_PASS_THRSH_ST. This register controls the amounts of LSBs that the CTS can change before an audio mute, status change, or interrupt is triggered. Table 150. CTS_CHANGE_THRESHOLD[5:0] Function Description CTS_CHANGE_THRESHOLD[5:0] 100101 (default) xxxxxx Description Tolerance of CTS value for CTS_PASS_THRSH_RAW and MT_MSK_NEW_CTS Tolerance of CTS value for CTS_PASS_THRSH_RAW and MT_MSK_NEW_CTS Rev. A | Page 60 of 168 ADV7613 Reference Manual UG-907 CHANNEL STATUS Channel status bits are extracted from the HDMI audio packets of the first audio channel (that is, Channel 0) and stored in the CHANNEL_STATUS_DATA_x registers of the HDMI map (where x = 1, 2, 3, 4, and 5). Validity Status Flag The channel status readback described in the Channel Status section must be considered valid if CS_DATA_VALID_RAW is set to 1. Figure 24 shows the algorithm that can be implemented to monitor the read valid channel status bit using the CS_DATA_VALID_RAW flag. CS_DATA_VALID_RAW, IO, Address 0x65[7] (Read Only) This bit is the raw status signal of the channel status data valid signal. Table 151. CS_DATA_VALID_RAW Function Description CS_DATA_VALID_RAW 0 (default) 1 Description Channel status data is not valid. Channel status data is valid. START ENABLE THE CS_DATA_VALID_ST INTERRUPT INITIALIZATION NO CHECK IF THE CS_DATA_VALID INTERRUPT HAS TRIGGERED IS CS_DATA_VALID_S T SET TO 1? NO SET CS_DATA_VALID_CLR TO 1 IS CS_DATA_VALID_R AW SET TO 1? YES READ THE CHANNEL STATUS BITS IN HDMI MAP 0x36 TO 0x3A THE CHANNEL STATUS BITS PREVIOUSLY READ ARE NOT VALID IS CS_DATA_VALID_S T SET TO 1? YES READ THE CHANNEL STATUS BITS AND DECIDE IF THEY ARE VALID THE CHANNEL STATUS BITS PREVIOUSLY READ ARE VALID 13807-024 NO Figure 24. Reading Valid Channel Status Flags Note that CS_DATA_VALID_RAW indicates that the first 40 of the channel status bits sent by the upstream transmitter have been correctly collected. This bit does not indicate if the content of the channel status bit is corrupted as this is indeterminable. A corresponding interrupt can be enabled for CS_DATA_VALID_RAW by setting the mask CS_DATA_VALID_MB1 or CS_DATA_VALID_MB2. See the Interrupts section for additional information on the interrupt feature. Rev. A | Page 61 of 168 UG-907 ADV7613 Reference Manual General Control and Mode Information The general control and mode information are specified in Byte 0 of the channel status. For more information, see the IEC60958 standards. CS_DATA[0], Consumer/Professional Application, HDMI Map, Address 0x36[0] Table 152. CS_DATA[0] Function Description CS_DATA[0] 0 (default) 1 Description Consumer application Professional application CS_DATA[1], PCM/non-PCM Audio Sample, HDMI Map, Address 0x36[1] Table 153. CS_DATA[1] Function Description CS_DATA[1] 0 (default) 1 Description Audio sample word represents linear PCM samples Audio sample word used for other purposes CS_DATA[2], Copyright, HDMI Map, Address 0x36[2] Table 154. CS_DATA[2] Function Description CS_DATA[2] 0 (default) 1 Description Software for which copyright is asserted Software for which no copyright is asserted CS_DATA[5:3], Emphasis, HDMI Map, Address 0x36[5:3] Table 155. CS_DATA[5:3] Function Description CS_DATA[5:3]1 000 (default) 001 1 Description Two audio channels without pre-emphasis Two audio channels with 50/15 pre-emphasis Unspecified values are reserved. CS_DATA[7:6], Channel Status Mode, HDMI Map, Address 0x36[7:6] Table 156. CS_DATA[7:6] Function Description CS_DATA[7:6]1 00 (default) 1 Description Mode 0 Unspecified values are reserved. Category Code The category code is specified in Byte 1 of the channel status. The category code indicates the type of equipment that generates the digital audio interface signal. For more information, refer to the IEC60958 standards. CS_DATA[15:8], Category Code, HDMI Map, Address 0x37[7:0] Table 157. CS_DATA[15:8] Function Description CS_DATA[15:8] xxxx xxxx 0000 0000 (default) 1 Description Category code1 Reset value Refer to the IEC60958-3 standards. Rev. A | Page 62 of 168 ADV7613 Reference Manual UG-907 Source Number and Channel Number CS_DATA[19:16], Source Number, HDMI Map, Address 0x38[3:0] Table 158. CS_DATA[19:16] Function Description CS_DATA[19:16] xxxx 0000 (default) 1 Description Source number1 Reset value Refer to the IEC60958-3 standards. CS_DATA[23:20], Channel Number, HDMI Map, Address 0x38[7:4] Table 159. CS_DATA[23:20] Function Description CS_DATA[23:20] xxxxx 00000 (default) 1 Description Channel number1 Reset value Refer to the IEC60958-3 standards. Sampling and Frequency Accuracy The sampling frequency and clock accuracy are specified by Byte 3 of the channel status. For additional information, refer to the IEC60958 standards. CS_DATA[27:24], Sampling Frequency, HDMI Map, Address 0x39[3:0] Table 160. CS_DATA[27:24] Function Description CS_DATA[27:24]1 0000 (default) 0010 0011 1000 1001 1010 1100 1110 1 Description 44.1 kHz 48 kHz 32 kHz 88.2 kHz 768 kHz 96 kHz 176 kHz 192 kHz Unspecified values are reserved. CS_DATA[29:28], Clock Accuracy, HDMI Map, Address 0x39[5:4] Table 161. CS_DATA[29:28] Function Description CS_DATA[29:28] 00 (default) 01 10 11 Description Level II, ±1000 ppm Level I, ±50 ppm Level III, variable pitch shifted Reserved CS_DATA[31:30], Reserved Register, HDMI Map, Address 0x39[7:6] Table 162. CS_DATA[31:30] Function Description CS_DATA[31:30] xx 00 (default) Description Reserved Reset value Rev. A | Page 63 of 168 UG-907 ADV7613 Reference Manual Word Length Word length information is specified in Byte 4 of the channel status bit. For more information, refer to the IEC60958 standards. CS_DATA[32], Maximum Word Length Size, HDMI Map, Address 0x3A[0] Table 163. CS_DATA[32] Function Description CS_DATA[32] 0 (default) 1 Description Maximum audio sample word length is 20 bits. Maximum audio sample word length is 24 bits. CS_DATA[35:33], Word Length, HDMI Map, Address 0x3A[3:1] Table 164. CS_DATA[35:33] Function Description CS_DATA[35:33]1 000 (default) 001 010 100 101 110 1 Description Audio Sample Word Length if Maximum Length is Audio Sample Word Length if Maximum Length is 24 as Indicated by CS_DATA_[32] 20 as Indicated by CS_DATA_[32] Word length not indicated Word length not indicated 20 bits 16 bits 22 bits 18 bits 23 bits 19 bits 24 bits 20 bits 21 bits 21 bits Unspecified values are reserved. Channel Status Copyright Value Assertion It is possible to overwrite the copyright value of the channel status bit that is passed to the SPDIF output. This is done via the CS_COPYRIGHT_MANUAL and CS_COPYRIGHT_VALUE controls. CS_COPYRIGHT_MANUAL, Address 68 (HDMI), Address 0x50[1] This bit is a control to select automatic or manual setting of the copyright value of the channel status bit that is passed to the SPDIF output. Manual control is set with the CS_COPYRIGHT_VALUE bit. Table 165. CS_COPYRIGHT_MANUAL Function Description CS_COPYRIGHT_MANUAL 0 (default) 1 Description Automatic CS copyright control. Manual CS copyright control. Manual value is set by CS_COPYRIGHT_VALUE. CS_COPYRIGHT_VALUE, Address 68 (HDMI), Address 0x50[0] This bit is a control to set the CS copyright value when in manual configuration of the CS copyright bit that is passed to the SPDIF output. Table 166. CS_COPYRIGHT_VALUE Function Description CS_COPYRIGHT_VALUE 0 (default) 1 Description Copyright value of channel status bit is 0. Valid only if CS_COPYRIGHT_MANUAL is set to 1. Copyright value of channel status bit is 1. Valid only if CS_COPYRIGHT_MANUAL is set to 1. Monitoring Change of Audio Sampling Frequency The ADV7613 features the NEW_SAMP_RT_RAW flag to monitor changes in the audio sampling frequency field of the channel status bits. NEW_SAMP_RT_RAW, IO, Address 0x83[3] (Read Only) This bit is the status of the new sampling rate interrupt signal. When set to 1, it indicates that the audio sampling frequency field in channel status data has changed. Once set, this bit remains high until it is cleared via NEW_SAMP_RT_CLR. Table 167. NEW_SAMP_RT_RAW Function Description NEW_SAMP_RT_RAW 0 (default) 1 Description Sampling rate bits of the channel status data on audio Channel 0 have not changed. Sampling rate bits of the channel status data on audio Channel 0 have changed. It is important to note that the NEW_SAMP_RT_RAW flag does not trigger if CS_DATA_VALID_RAW is set to 0. This prevents the notification of a change from a valid to an invalid audio sampling frequency readback in the channel status bits, and vice versa. Rev. A | Page 64 of 168 ADV7613 Reference Manual UG-907 PACKETS AND INFOFRAMES REGISTERS In HDMI, auxiliary data is carried across the digital link using a series of packets. The ADV7613 automatically detects and stores the following HDMI packets: • • • • InfoFrames Audio content protection (ACP) International standard recording code (ISRC) Gamut metadata When the ADV7613 receives one of these packets, it computes the packet checksum and compares it with the checksum available in the packet. If these checksums are the same, the packets are stored in the corresponding registers. If the checksums are not the same, the packets are discarded. Refer to the EIA/CEA-861D specifications for more information on the packets fields. InfoFrames Registers The ADV7613 can store the following InfoFrames: • • • • Auxiliary video information (AVI) InfoFrame Source production descriptor (SPD) InfoFrame Audio InfoFrame Moving picture expert group (MPEG) source InfoFrame InfoFrame Collection Mode The ADV7613 has two modes for storing the InfoFrame packet sent from the source into the internal memory. By default, the ADV7613 only stores the InfoFrame packets received if the checksum is correct for each InfoFrame. The ADV7613 also provides a mode to store every InfoFrame sent from the source, regardless of a InfoFrame packet checksum error. ALWAYS_STORE_INF, Address 68 (HDMI), Address 0x47[0] This bit is a control to force InfoFrames with checksum errors to be stored. Table 168. ALWAYS_STORE_INF Function Description ALWAYS_STORE_INF 0 (default) 1 Description Stores data from received InfoFrames only if their checksum is correct Always store the data from received InfoFrame regardless of their checksum InfoFrame Checksum Error Flags The following checksum error status registers flag when the last InfoFrame received has a checksum error. Once set, these bits remain high until the interrupt is cleared via their corresponding clear bits. AVI_INF_CKS_ERR_RAW, IO, Address 0x88[4] (Read Only) This bit is the status of the AVI InfoFrame checksum error interrupt signal. When set to 1, it indicates that a checksum error has been detected for an AVI InfoFrame. Once set, this bit remains high until it is cleared via AVI_INF_CKS_ERR_CLR. Table 169. AVI_INF_CKS_ERR_RAW Function Description AVI_INF_CKS_ERR_RAW 0 (default) 1 Description No AVI InfoFrame checksum error has occurred. An AVI InfoFrame checksum error has occurred. AUD_INF_CKS_ERR_RAW, IO, Address 0x88[5] (Read Only) This bit is the status of the audio InfoFrame checksum error interrupt signal. When set to 1, it indicates that a checksum error has been detected for an audio InfoFrame. Once set, this bit remains high until it is cleared via AUDIO_INF_CKS_ERR_CLR. Table 170. AUD_INF_CKS_ERR_RAW Function Description AUD_INF_CKS_ERR_RAW 0 (default) 1 Description No audio InfoFrame checksum error has occurred. An audio InfoFrame checksum error has occurred. Rev. A | Page 65 of 168 UG-907 ADV7613 Reference Manual SPD_INF_CKS_ERR_RAW, IO, Address 0x88[6] (Read Only) This bit is the status of SPD InfoFrame checksum error interrupt signal. When set to 1, it indicates that a checksum error has been detected for an SPD InfoFrame. Once set, this bit remains high until it is cleared via ASPD_INF_CKS_ERR_CLR. Table 171. SPD_INF_CKS_ERR_RAW Function Description SPD_INF_CKS_ERR_RAW 0 (default) 1 Description No SPD InfoFrame checksum error has occurred. An SPD InfoFrame checksum error has occurred. MS_INF_CKS_ERR_RAW, IO, Address 0x88[7] (Read Only) This bit is the status of MPEG source InfoFrame checksum error interrupt signal. When set to 1. it indicates that a checksum error has been detected for an MPEG source InfoFrame. Once set, this bit remains high until it is cleared via MS_INF_CKS_ERR_CLR. Table 172. MS_INF_CKS_ERR_RAW Function Description MS_INF_CKS_ERR_RAW 0 (default) 1 Description No MPEG source InfoFrame checksum error has occurred. An MPEG source InfoFrame checksum error has occurred. VS_INF_CKS_ERR_RAW, IO, Address 0x8D[0] (Read Only) This bit is the status of vendor specific InfoFrame checksum error interrupt signal. When set to 1, it indicates that a checksum error has been detected for an Vendor Specific InfoFrame. Once set, this bit remains high until it is cleared via VS_INF_CKS_ERR_CLR. Table 173. VS_INF_CKS_ERR_RAW Function Description VS_INF_CKS_ERR_RAW 0 (default) 1 Description No VS InfoFrame checksum error has occurred A VS InfoFrame checksum error has occurred AVI InfoFrame Registers Table 174 provides a list of readback registers for the AVI InfoFrame data. Refer to the EIA/CEA-861D specifications for a detailed explanation of the AVI InfoFrame fields. Table 174. AVI InfoFrame Registers InfoFrame Map Address 0xE0 0xE1 0xE2 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 Access Type1 R/W R R R R R R R R R R R R R R R R R R R R Register Name AVI_PACKET_ID[7:0] AVI_INF_VER AVI_INF_LEN AVI_INF_PB_0_1 AVI_INF_PB_0_2 AVI_INF_PB_0_3 AVI_INF_PB_0_4 AVI_INF_PB_0_5 AVI_INF_PB_0_6 AVI_INF_PB_0_7 AVI_INF_PB_0_8 AVI_INF_PB_0_9 AVI_INF_PB_0_10 AVI_INF_PB_0_11 AVI_INF_PB_0_12 AVI_INF_PB_0_13 AVI_INF_PB_0_14 AVI_INF_PB_0_15 AVI_INF_PB_0_16 AVI_INF_PB_0_17 AVI_INF_PB_0_18 Rev. A | Page 66 of 168 Byte Name2 Packet type value InfoFrame version number InfoFrame length Checksum Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Data Byte 8 Data Byte 9 Data Byte 10 Data Byte 11 Data Byte 12 Data Byte 13 Data Byte 14 Data Byte 15 Data Byte 16 Data Byte 17 ADV7613 Reference Manual InfoFrame Map Address 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 1 2 Access Type1 R R R R R R R R R R UG-907 Register Name AVI_INF_PB_0_19 AVI_INF_PB_0_20 AVI_INF_PB_0_21 AVI_INF_PB_0_22 AVI_INF_PB_0_23 AVI_INF_PB_0_24 AVI_INF_PB_0_25 AVI_INF_PB_0_26 AVI_INF_PB_0_27 AVI_INF_PB_0_28 Byte Name2 Data Byte 18 Data Byte 19 Data Byte 20 Data Byte 21 Data Byte 22 Data Byte 23 Data Byte 24 Data Byte 25 Data Byte 26 Data Byte 27 R/W means memory location has read and write access. R means memory location is read access only; a read always returns 0, unless otherwise specified. As defined by the EIA/CEA-861D specifications. The AVI InfoFrame registers are considered valid if the following two conditions are met: AVI_INFO_RAW is 1, and AVI_INF_CKS_ERR_RAW is 0 (this condition applies only if ALWAYS_STORE_INF is set to 1). AVI_INFO_RAW is described in the Interrupt Architecture Overview section. Audio InfoFrame Registers Table 175 provides the list of readback registers available for the Audio InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the audio InfoFrame fields. Table 175. Audio InfoFrame Registers InfoFrame Map Address 0xE3 0xE4 0xE5 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 1 2 Access Type1 R/W R R R R R R R R R R R R R R R R Register Name AUD_PACKET_ID[7:0] AUD_INF_VERS AUD_INF_LEN AUD_INF_PB_0_1 AUD_INF_PB_0_2 AUD_INF_PB_0_3 AUD_INF_PB_0_4 AUD_INF_PB_0_5 AUD_INF_PB_0_6 AUD_INF_PB_0_7 AUD_INF_PB_0_8 AUD_INF_PB_0_9 AUD_INF_PB_0_10 AUD_INF_PB_0_11 AUD_INF_PB_0_12 AUD_INF_PB_0_13 AUD_INF_PB_0_14 Byte Name2 Packet type value InfoFrame version number InfoFrame length Checksum Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Data Byte 8 Data Byte 9 Data Byte 10 Data Byte 11 Data Byte 12 Data Byte 13 R/W means memory location has read and write access. R means memory location is read access only; a read always returns 0, unless otherwise specified. As defined by the EIA/CEA-861D specifications. The audio InfoFrame registers are considered valid if the following two conditions are met: AUDIO_INFO_RAW is 1, and AUD_INF_CKS_ERR_RAW is 0 (this condition applies only if ALWAYS_STORE_INF is set to 1). AUDIO_INFO_RAW, IO, Address 0x60[1] (Read Only) This bit is the raw status of the audio InfoFrame detected signal. Table 176. AUDIO_INFO_RAW Function Description AUDIO_INFO_RAW 0 (default) 1 Description No AVI InfoFrame were received within the last three VSYNCs or since the last HDMI packet detection reset. An audio InfoFrame was received within the last three VSYNCs. This bit resets to zero on the fourth VSYNC leading edge following an audio InfoFrame, after an HDMI packet detection reset or upon writing to AUD_PACKET_ID. Rev. A | Page 67 of 168 UG-907 ADV7613 Reference Manual SPD InfoFrame Registers Table 177 provides a list of readback registers available for the SPD InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the SPD InfoFrame fields. Table 177. SPD InfoFrame Registers InfoFrame Map Address 0xE6 0xE7 0xE8 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 1 2 Access Type1 R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Register Name SPD_PACKET_ID[7:0] SPD_INF_VER SPD_INF_LEN SPD_INF_PB_0_1 SPD_INF_PB_0_2 SPD_INF_PB_0_3 SPD_INF_PB_0_4 SPD_INF_PB_0_5 SPD_INF_PB_0_6 SPD_INF_PB_0_7 SPD_INF_PB_0_8 SPD_INF_PB_0_9 SPD_INF_PB_0_10 SPD_INF_PB_0_11 SPD_INF_PB_0_12 SPD_INF_PB_0_13 SPD_INF_PB_0_14 SPD_INF_PB_0_15 SPD_INF_PB_0_16 SPD_INF_PB_0_17 SPD_INF_PB_0_18 SPD_INF_PB_0_19 SPD_INF_PB_0_20 SPD_INF_PB_0_21 SPD_INF_PB_0_22 SPD_INF_PB_0_23 SPD_INF_PB_0_24 SPD_INF_PB_0_25 SPD_INF_PB_0_26 SPD_INF_PB_0_27 SPD_INF_PB_0_28 Byte Name2 Packet type value InfoFrame version number InfoFrame length Checksum Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Data Byte 8 Data Byte 9 Data Byte 10 Data Byte 11 Data Byte 12 Data Byte 13 Data Byte 14 Data Byte 15 Data Byte 16 Data Byte 17 Data Byte 18 Data Byte 19 Data Byte 20 Data Byte 21 Data Byte 22 Data Byte 23 Data Byte 24 Data Byte 25 Data Byte 26 Data Byte 27 R/W means memory location has read and write access. R means memory location is read access only; a read always returns 0, unless otherwise specified. As defined by the EIA/CEA-861D specifications. The source product descriptor InfoFrame registers are considered valid if the following two conditions are met: SPD_INFO_RAW is 1, and SPD_INF_CKS_ERR_RAW is 0 (this condition only applies if ALWAYS_STORE_INF is set to 1). SPD_INFO_RAW, IO, Address 0x60[2] (Read Only) This bit is the raw status of the SPD InfoFrame detected signal. Table 178. SPD_INFO_RAW Function Description SPD_INFO_RAW 0 (default) 1 Description No source product description InfoFrame received since the last HDMI packet detection reset. Source product description InfoFrame received. This bit resets to zero after an HDMI packet detection reset or upon writing to SPD_PACKET_ID. Rev. A | Page 68 of 168 ADV7613 Reference Manual UG-907 MPEG Source InfoFrame Registers Table 179 provides a list of readback registers available for the MPEG InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the MPEG InfoFrame fields. Table 179. MPEG InfoFrame Registers InfoFrame Map Address 0xE9 0xEA 0xEB 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 1 2 Access Type1 R/W R R R R R R R R R R R R R R R R Register Name MS_PACKET_ID[7:0] MS_INF_VERS MS_INF_LEN MS_INF_PB_0_1 MS_INF_PB_0_2 MS_INF_PB_0_3 MS_INF_PB_0_4 MS_INF_PB_0_5 MS_INF_PB_0_6 MS_INF_PB_0_7 MS_INF_PB_0_8 MS_INF_PB_0_9 MS_INF_PB_0_10 MS_INF_PB_0_11 MS_INF_PB_0_12 MS_INF_PB_0_13 MS_INF_PB_0_14 Byte Name2 Packet type value InfoFrame version number InfoFrame length Checksum Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Data Byte 8 Data Byte 9 Data Byte 10 Data Byte 11 Data Byte 12 Data Byte 13 R/W means memory location has read and write access. R means memory location is read access only; a read always returns 0, unless otherwise specified. As defined by the EIA/CEA-861D specifications. The MPEG InfoFrame registers are considered valid if the following two conditions are met: MS_INFO_RAW is 1, and MS_INF_CKS_ERR_RAW is 0 (this condition applies only if ALWAYS_STORE_INF is set to 1). MS_INFO_RAW, IO, Address 0x60[3] (Read Only) This bit is the raw status signal of the MPEG source InfoFrame detection signal. Table 180. MS_INFO_RAW Function Description MS_INFO_RAW 0 (default) 1 Description No source product description InfoFrame received within the last three VSYNCs or since the last HDMI packet detection reset. MPEG Source InfoFrame received. This bit resets to zero after an HDMI packet detection reset or upon writing to MS_PACKET_ID. Rev. A | Page 69 of 168 UG-907 ADV7613 Reference Manual Vendor Specific InfoFrame Registers Table 181 provides a list of readback registers available for the vendor specific InfoFrame. Table 181. VS InfoFrame Registers InfoFrame Map Address 0xEC 0xED 0xEE 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 1 Access Type1 R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Register Name VS_PACKET_ID[7:0] VS_INF_VERS VS_INF_LEN VS_INF_PB_0_1 VS_INF_PB_0_2 VS_INF_PB_0_3 VS_INF_PB_0_4 VS_INF_PB_0_5 VS_INF_PB_0_6 VS_INF_PB_0_7 VS_INF_PB_0_8 VS_INF_PB_0_9 VS_INF_PB_0_10 VS_INF_PB_0_11 VS_INF_PB_0_12 VS_INF_PB_0_13 VS_INF_PB_0_14 VS_INF_PB_0_15 VS_INF_PB_0_16 VS_INF_PB_0_17 VS_INF_PB_0_18 VS_INF_PB_0_19 VS_INF_PB_0_20 VS_INF_PB_0_21 VS_INF_PB_0_22 VS_INF_PB_0_23 VS_INF_PB_0_24 VS_INF_PB_0_25 VS_INF_PB_0_26 VS_INF_PB_0_27 VS_INF_PB_0_28 Byte Name Packet type value InfoFrame version number InfoFrame length Checksum Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Data Byte 8 Data Byte 9 Data Byte 10 Data Byte 11 Data Byte 12 Data Byte 13 Data Byte 14 Data Byte 15 Data Byte 16 Data Byte 17 Data Byte 18 Data Byte 19 Data Byte 20 Data Byte 21 Data Byte 22 Data Byte 23 Data Byte 24 Data Byte 25 Data Byte 26 Data Byte 27 R means memory location is read access only; a read always returns 0, unless otherwise specified. The vendor specific InfoFrame registers are considered valid if the following two conditions are met: VS_INFO_RAW is 1, and VS_INF_CKS_ERR_RAW is 0 (this condition applies only if ALWAYS_STORE_INF is set to 1). VS_INFO_RAW, IO, Address 0x60[4] (Read Only) This bit is the raw status signal of the vendor specific InfoFrame detection signal. Table 182. VS_INFO_RAW Function Description VS_INFO_RAW 0 (default) 1 Description No new VS InfoFrame has been received since the last HDMI packet detection reset. A new VS InfoFrame has been received. This bit resets to zero after an HDMI packet detection reset or upon writing to VS_PACKET_ID. Rev. A | Page 70 of 168 ADV7613 Reference Manual UG-907 PACKET REGISTERS ACP Packet Registers Table 183 provides the list of readback registers available for the ACP packets. Refer to the HDMI 1.3 specifications for a detailed explanation of the ACP packet fields. Table 183. ACP Packet Registers InfoFrame Map Address 0xEF 0xF0 0xF1 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 1 2 Access Type1 R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Register Name ACP_PACKET_ID[7:0] ACP_TYPE ACP_HEADER2 ACP_PB_0_1 ACP_PB_0_2 ACP_PB_0_3 ACP_PB_0_4 ACP_PB_0_5 ACP_PB_0_6 ACP_PB_0_7 ACP_PB_0_8 ACP_PB_0_9 ACP_PB_0_10 ACP_PB_0_11 ACP_PB_0_12 ACP_PB_0_13 ACP_PB_0_14 ACP_PB_0_15 ACP_PB_0_16 ACP_PB_0_17 ACP_PB_0_18 ACP_PB_0_19 ACP_PB_0_20 ACP_PB_0_21 ACP_PB_0_22 ACP_PB_0_23 ACP_PB_0_24 ACP_PB_0_25 ACP_PB_0_26 ACP_PB_0_27 ACP_PB_0_28 Packet Byte No.2 Packet type value HB1 HB2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 R/W means memory location has read and write access. R means memory location is read access only; a read always returns 0, unless otherwise specified. As defined by the HDMI 1.3 specifications. The ACP InfoFrame registers are considered valid if ACP_PCKT_RAW is set to 1. ACP_PCKT_RAW, IO, Address 0x60[5] (Read Only) This bit is the raw status signal of the audio content protection packet detection signal. Table 184. ACP_PCKT_RAW Function Description ACP_PCKT_RAW 0 (default) 1 Description No ACP packet received within the last 600 ms or since the last HDMI packet detection reset. ACP packets have been received within the last 600 ms. This bit resets to zero after an HDMI packet detection reset or upon writing to ACP_PACKET_ID. Rev. A | Page 71 of 168 UG-907 ADV7613 Reference Manual ISRC Packet Registers Table 185 and Table 187 provide lists of readback registers available for the ISRC packets. Refer to the HDMI 1.3 specifications for a detailed explanation of the ISRC packet fields. Table 185. ISRC1 Packet Registers InfoFrame Map Address 0xF2 0xF3 0xF4 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 1 2 Access Type1 R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Register Name ISRC1_PACKET_ID[7:0] ISRC1_HEADER1 ISRC1_HEADER2 ISRC1_PB_0_1 ISRC1_PB_0_2 ISRC1_PB_0_3 ISRC1_PB_0_4 ISRC1_PB_0_5 ISRC1_PB_0_6 ISRC1_PB_0_7 ISRC1_PB_0_8 ISRC1_PB_0_9 ISRC1_PB_0_10 ISRC1_PB_0_11 ISRC1_PB_0_12 ISRC1_PB_0_13 ISRC1_PB_0_14 ISRC1_PB_0_15 ISRC1_PB_0_16 ISRC1_PB_0_17 ISRC1_PB_0_18 ISRC1_PB_0_19 ISRC1_PB_0_20 ISRC1_PB_0_21 ISRC1_PB_0_22 ISRC1_PB_0_23 ISRC1_PB_0_24 ISRC1_PB_0_25 ISRC1_PB_0_26 ISRC1_PB_0_27 ISRC1_PB_0_28 Packet Byte No.2 Packet type value HB1 HB2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 R/W means memory location has read and write access. R means memory location is read access only; a read always returns 0, unless otherwise specified. As defined by the HDMI specifications. The ISRC1 packet registers are considered valid if ISRC1_PCKT_RAW is set to 1. ISRC1_PCKT_RAW, IO, Address 0x60[6] (Read Only) This bit is the raw status signal of International Standard Recording Code 1 (ISRC1) packet detection signal. Table 186. ISRC1_PCKT_RAW Function Description ISRC1_PCKT_RAW 0 (default) 1 Description No ISRC1 packets received since the last HDMI packet detection reset. ISRC1 packets have been received. This bit resets to zero after an HDMI packet detection reset or upon writing to ISRC1_PACKET_ID. Rev. A | Page 72 of 168 ADV7613 Reference Manual UG-907 Table 187. ISRC2 Packet Registers InfoFrame Map Address 0xF5 0xF6 0xF7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 1 2 Access Type1 R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Register Name ISRC2_PACKET_ID[7:0] ISRC2_HEADER1 ISRC2_HEADER2 ISRC2_PB_0_1 ISRC2_PB_0_2 ISRC2_PB_0_3 ISRC2_PB_0_4 ISRC2_PB_0_5 ISRC2_PB_0_6 ISRC2_PB_0_7 ISRC2_PB_0_8 ISRC2_PB_0_9 ISRC2_PB_0_10 ISRC2_PB_0_11 ISRC2_PB_0_12 ISRC2_PB_0_13 ISRC2_PB_0_14 ISRC2_PB_0_15 ISRC2_PB_0_16 ISRC2_PB_0_17 ISRC2_PB_0_18 ISRC2_PB_0_19 ISRC2_PB_0_20 ISRC2_PB_0_21 ISRC2_PB_0_22 ISRC2_PB_0_23 ISRC2_PB_0_24 ISRC2_PB_0_25 ISRC2_PB_0_26 ISRC2_PB_0_27 ISRC2_PB_0_28 Packet Byte No.2 Packet type value HB1 HB2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 R/W means memory location has read and write access. R means memory location is read access only; a read always returns 0, unless otherwise specified. As defined by the HDMI 1.3 specifications. The ISRC2 packet registers are considered valid if, and only, if ISRC1_PCKT_RAW is set to 1. ISRC2_PCKT_RAW, IO, Address 0x60[7] (Read Only) This bit is the raw status signal of International Standard Recording Code 2 (ISRC2) packet detection signal. Table 188. ISRC2_PCKT_RAW Function Description ISRC2_PCKT_RAW 0 (default) 1 Description No ISRC2 packets received since the last HDMI packet detection reset. ISRC2 packets have been received. This bit resets to zero after an HDMI packet detection reset or upon writing to ISRC2_PACKET_ID. Rev. A | Page 73 of 168 UG-907 ADV7613 Reference Manual Gamut Metadata Packets Refer to the HDMI specifications for a detailed explanation of the gamut metadata packet fields. Table 189. Gamut Metadata Packet Registers HDMI Map Address 0xF8 0xF9 0xFA 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 1 2 Access Type1 R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Register Name GAMUT_PACKET_ID[7:0] GAMUT_HEADER1 GAMUT_HEADER2 GAMUT_MDATA_PB_0_1 GAMUT_MDATA_PB_0_2 GAMUT_MDATA_PB_0_3 GAMUT_MDATA_PB_0_4 GAMUT_MDATA_PB_0_5 GAMUT_MDATA_PB_0_6 GAMUT_MDATA_PB_0_7 GAMUT_MDATA_PB_0_8 GAMUT_MDATA_PB_0_9 GAMUT_MDATA_PB_0_10 GAMUT_MDATA_PB_0_11 GAMUT_MDATA_PB_0_12 GAMUT_MDATA_PB_0_13 GAMUT_MDATA_PB_0_14 GAMUT_MDATA_PB_0_15 GAMUT_MDATA_PB_0_16 GAMUT_MDATA_PB_0_17 GAMUT_MDATA_PB_0_18 GAMUT_MDATA_PB_0_19 GAMUT_MDATA_PB_0_20 GAMUT_MDATA_PB_0_21 GAMUT_MDATA_PB_0_22 GAMUT_MDATA_PB_0_23 GAMUT_MDATA_PB_0_24 GAMUT_MDATA_PB_0_25 GAMUT_MDATA_PB_0_26 GAMUT_MDATA_PB_0_27 GAMUT_MDATA_PB_0_28 Packet Byte No.2 Packet type value HB1 HB2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 R/W means memory location has read and write access. R means memory location is read access only; a read always returns 0, unless otherwise specified. As defined by the HDMI specifications. The gamut metadata packet registers are considered valid if GAMUT_MDATA_RAW is set to 1. GAMUT_MDATA_RAW, IO, Address 0x65[0] (Read Only) This bit is the raw status signal of gamut metadata packet detection signal. Table 190. GAMUT_MDATA_RAW Function Description GAMUT_MDATA_RAW 0 (default) 1 Description No gamut metadata packet has been received in the last video frame or since the last HDMI packet detection reset. A gamut metadata packet has been received in the last video frame. This bit resets to zero after an HDMI packet detection reset or upon writing to GAMUT_PACKET_ID. GAMUT_IRQ_NEXT_FIELD, Address 68 (HDMI), Address 0x50[4] This bit is a control to set the NEW_GAMUT_MDATA_RAW interrupt to detect when the new contents are applicable to next field or to indicate that the gamut packet is new, by using the header information of the gamut packet. Table 191. GAMUT_IRQ_NEXT_FIELD Function Description GAMUT_IRQ_NEXT_FIELD 0 (default) 1 Description Interrupt flag indicates that gamut packet is new. Interrupt flag indicates that gamut packet is to be applied next field. Rev. A | Page 74 of 168 ADV7613 Reference Manual UG-907 CUSTOMIZING PACKET/INFOFRAME STORAGE REGISTERS The packet type value of each set of packet and InfoFrame registers in the InfoFrame map is programmable. This allows the user to configure the ADV7613 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the selected HDMI port. Note that writing to any of the nine following packet ID registers also clears the corresponding raw InfoFrame/packet detection bit. For example, writing 0x82, or any other value, to AVI_PACKET_ID clears AVI_INFO_RAW. AVI_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xE0[7:0] AVI_PACKET_ID[7:0] is the AVI InfoFrame ID. Table 192. AVI_PACKET_ID[7:0] Function Description AVI_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0x00 to Address 0x1B Packet type value of InfoFrame stored in InfoFrame map, Address 0x00 to Address 0x1B AUD_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xE3[7:0] AUD_PACKET_ID[7:0] is the audio InfoFrame ID. Table 193. AUD_PACKET_ID[7:0] Function Description AUD_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0x1C to Address 0x29 Packet type value of InfoFrame stored in InfoFrame map, Address 0x1C to Address 0x29 SPD_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xE6[7:0] SPD_PACKET_ID[7:0] is the source prod InfoFrame ID. Table 194. SPD_PACKET_ID[7:0] Function Description SPD_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0x2A to Address 0x45 Packet type value of InfoFrame stored in InfoFrame map, Address 0x2A to Address 0x45 MS_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xE9[7:0] MS_PACKET_ID[7:0] is the MPEG source InfoFrame ID. Table 195. MS_PACKET_ID[7:0] Function Description MS_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0x46 to Address 0x53 Packet type value of InfoFrame stored in InfoFrame map, Address 0x46 to Address 0x53 VS_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xEC[7:0] VS_PACKET_ID[7:0] is the vendor specific InfoFrame ID. Table 196. VS_PACKET_ID[7:0] Function Description VS_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0x54 to Address 0x6F Packet type value of packet stored in InfoFrame map, Address 0x54 to Address 0x6F ACP_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xEF[7:0] ACP_PACKET_ID[7:0] is the ACP InfoFrame ID. Table 197. ACP_PACKET_ID[7:0] Function Description ACP_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0x70 to Address 0x8B Packet type value of InfoFrame stored in InfoFrame map, Address 0x70 to Address 0x8B Rev. A | Page 75 of 168 UG-907 ADV7613 Reference Manual ISRC1_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xF2[7:0] ISRC1_PACKET_ID[7:0] is the ISRC1 InfoFrame ID. Table 198. ISRC1_PACKET_ID[7:0] Function Description ISRC1_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0x8C to Address 0xA7 Packet type value of InfoFrame stored in InfoFrame map, Address 0x8C to Address 0xA7 ISRC2_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xF5[7:0] ISRC2_PACKET_ID[7:0] is the ISRC2 InfoFrame ID. Table 199. ISRC2_PACKET_ID[7:0] Function Description ISRC2_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0xA8 to Address 0xC3 Packet type value of InfoFrame stored in InfoFrame map, Address 0xA8 to Address 0xC3 GAMUT_PACKET_ID[7:0], Address 7C (InfoFrame), Address 0xF8[7:0] GAMUT_PACKET_ID[7:0] is the Gamut InfoFrame ID. Table 200. GAMUT_PACKET_ID[7:0] Function Description GAMUT_PACKET_ID[7:0] 0xxxxxxx 1xxxxxxx Description Packet type value of packet stored in InfoFrame map, Address 0xC4 to Address 0xDF Packet type value of InfoFrame stored in InfoFrame map, Address 0xC4 to Address 0xDF Note that the packet type values and corresponding packets must not be programmed in the packet type values registers. These packets are always processed internally and cannot be stored in the packet/InfoFrame registers in the InfoFrame map. • • • • • • 0x01: audio clock regeneration packet 0x02: audio sample packet 0x03: general control packet 0x07: DSD audio sample packet 0x08: DST audio packet 0x09: HBR audio stream packet Rev. A | Page 76 of 168 ADV7613 Reference Manual UG-907 REPEATER SUPPORT The ADV7613 incorporates an EDID/repeater controller that provides all the features required for a receiver front end of a fully HDCP 1.4compliant repeater system. The ADV7613 has a RAM that can store up to 127 KSVs, which allows it to handle up to 127 downstream devices in repeater mode (see Table 210). The ADV7613 features a set of HDCP registers, defined in the HDCP specifications, which are accessible through the DDC bus (see the DDC Ports section) of the selected port. A subset of the HDCP registers (defined in the following subsections) are also available in the Repeater map and are accessible through the main I2C port (see the Main I2C Port section). Repeater Routines Performed by the EDID/Repeater Controller Power Up A power-on reset circuitry on the DVDD supply is used to reset the EDID/repeater controller when the ADV7613 is powered up. When the EDID/repeater controller reboots after reset, it resets all the KSV registers listed in Table 210 to 0x00. AKSV Update The EDID/repeater controller resets automatically the BCAPS [5] bit to 0 when an HDCP transmitter writes its AKSV into the ADV7613 HDCP registers through the DDC bus of the HDMI port. Note that writing a value in the AKSV[39:32] triggers an AKSV update and AKSV_UPDATE_ST interrupt if AKSV_UPDATE_MB1 or AKSV_UPDATE_MB2 has been set to 1 This triggers the EDID/repeater controller to reset the BCAPS [5] bit back to 0. KSV List Ready The KSV_LIST_READY bit is set by an external controller driving the ADV7613. This notifies the ADV7613 on-chip EDID/repeater controller that the KSV list registers have been updated with the KSV’s of the attached and active downstream HDCP devices. When KSV_LIST_READY is set to 1, the EDID/repeater controller computes the SHA-1 (refer to the HDCP documentation) hash value V’, updates the corresponding V’ registers (see Table 211), and sets the READY bit (that is, BCAPS[5]) to 1. This indicates to the transmitter attached to the ADV7613 that the KSV FIFO and SHA-1 hash value V’ are ready to be read. KSV_LIST_READY, Address 64 (Repeater), Address 0x71[7] The system sets this bit to indicate that the KSV list has been read from the Tx IC(s) and written into the repeater map. The system must also set Bits[11:0] of BSTATUS before setting this bit. Table 201. KSV_LIST_READY Function Description KSV_LIST_READY 0 (default) 1 Description Not ready Ready Note that the SHA-1 hash value is computed if the bit KSV_LIST_READY is set after the device receives an AKSV update from the upstream source. The external controller must therefore set KSV_LST_READY to 1 only after the device has received an AKSV update from the upstream source. The ADV7613 does not automatically clear KSV_LIST_READY to 0, after it has finished computing the SHA-1 value. Therefore, the external controller needs to clear KSV_LIST_READY. HDMI Mode The BSTATUS[12]bit is updated automatically by the ADV7613 and follows the HDMI mode status of the HDMI/DVI stream input on the active HDMI port. BSTATUS [12] is set to 1 if the ADV7613 receives an HDMI stream, and set to 0 if the ADV7613 receives a DVI stream. Repeater Actions Required by External Controller The external controller must set the BCAPS register and notify the ADV7613 when the KSV list is updated, as described in the following sections: the Repeater Bit section, the KSV FIFO Read from HDCP Registers section, and the First AKSV Update section. Note that many more routines must be implemented into the external controller driving the ADV7613 to implement a full repeater. Such routines are described in the HDCP and HDMI specifications (for example, copying InfoFrame and packet data image from the HDMI receiver into the HDMI transmitter, momentarily deasserting the hot plug detect and disabling the clock termination on a change of downstream topology, and so on). Rev. A | Page 77 of 168 UG-907 ADV7613 Reference Manual Repeater Bit The repeater bit (that is, BCAPS[6]) must be set to 1 by the external controller in the routine that initializes the ADV7613. The repeater bit must be left as such as long as the ADV7613 is configured as the front end of a repeater system. Note that the registers in the KSV list (see Table 210) must always be set to 0x0 if the repeater bit is set to 0. The firmware running on the external controller, therefore, always sets the registers in the KSV list to 0x0 if the repeater bit is changed from 1 to 0. KSV FIFO Read from HDCP Registers The KSV FIFO read at Address 0x43 through the HDCP port of the selected HDMI port is dependent on the value of the repeater bit (that is, BCAPS[6]). When the repeater bit is set to 0, the KSV FIFO read from the HDCP port always returns 0x0. When the repeater bit is set to 1, the KSV FIFO read from the HDCP port matches the KSV list which is set in the Repeater map at Address 0x80 to Address 0xF7 (see Table 210). First AKSV Update When the upstream transmitter writes its AKSV for the first time into the ADV7613 HDCP registers, the external controller driving the ADV7613 must perform the following tasks: • • • • Update BSTATUS[11:0] according to the topology of the downstream device attached to the repeater. Update the KSV list (refer to Table 210) with the KSV from the transmitter on the back end of the repeater as well as the KSV from all the downstream devices connected to the repeater. Set KSV_LIST_READY to 1. The external controller can monitor the AKSV_UPDATE_A_RAW bits to be notified when the transmitter writes its AKSV into the HDCP registers of the ADV7613. AKSV_UPDATE_A_RAW, IO, Address 0x88[0] (Read Only) This bit is the status of the Port A AKSV update interrupt signal. When set to 1, it indicates that thetransmitter has written its AKSV into the HDCP registers for Port A. Once set, this bit remains high until it is cleared via AKSV_UPDATE_A_CLR. Table 202. AKSV_UPDATE_A_RAW Function Description AKSV_UPDATE_A_RAW 0 (default) 1 Description No AKSV updates on Port A Detected a write access to the AKSV register on Port A Second and Subsequent AKSV Updates When the upstream transmitter writes its AKSV for the second time or more into the ADV7613 HDCP registers, the external controller driving the ADV7613 must set KSV_LIST_READY to 1. HDCP Registers Available in Repeater Map To enable fast switching of the HDCP encrypted HDMI ports, Register 0x00 to Register 0x42 in the repeater map are replicated for each port. AUTO_HDCP_MAP_ENABLE and HDCP_MAP_SELECT determine which port is currently visible to the user. AUTO_HDCP_MAP_ENABLE, Address 64 (Repeater), Address 0x79[3] This bit selects which port is accessed for HDCP addresses: the HDMI active port (selected by HDMI_PORT_SELECT, HDMI map) or the one selected in HDCP_MAP_SELECT. Table 203. AUTO_HDCP_MAP_ENABLE Function Description AUTO_HDCP_MAP_ENABLE 0 1 (default) Description HDCP data read from port given by HDCP_MAP_SELECT HDCP data read from the active HDMI port HDCP_MAP_SELECT, Address 64 (Repeater), Address 0x79[0] This bit selects which port is accessed for HDCP addresses (0x00 to 0x42 in repeater map). This only takes effect when AUTO_HDCP_MAP_ENABLE is 0. Table 204. HDCP_MAP_SELECT Function Description HDCP_MAP_SELECT[0] 000 (default) Description Select Port A Rev. A | Page 78 of 168 ADV7613 Reference Manual UG-907 BKSV[39:0], Address 64 (Repeater), Address 0x04[7:0]; Address 0x03[7:0]; Address 0x02[7:0]; Address 0x01[7:0]; Address 0x00[7:0] (Read Only) The receiver key selection vector (BKSV) can be read back once the device has accessed the HDCP ROM. The following registers contain the BKSV read from the EEPROM. Table 205. BKSV[39:0] Function Description BKSV[39:0] 0x00[7:0] 0x01[7:0] 0x02[7:0 ] 0x03[7:0] 0x04[7:0] Description BKSV[7:0] BKSV[15:8] BKSV[23:16] BKSV[31:24] BKSV[39:32] AKSV[39:0], Address 64 (Repeater), Address 0x14[7:0]; Address 0x13[7:0]; Address 0x12[7:0]; Address 0x11[7:0]; Address 0x10[7:0] The AKSV of the transmitter attached to the active HDMI port can be read back after an AKSV update. The following registers contain the AKSV written by the Tx. Table 206. AKSV[39:0] Function Description AKSV[39:0] 0x10[7:0] 0x11[7:0] 0x12[7:0] 0x13[7:0] 0x14[7:0] Description AKSV[7:0] AKSV[15:8] AKSV[23:16] AKSV[31:24] AKSV[39:32] BCAPS[7:0], Address 64 (Repeater), Address 0x40[7:0] This is the BCAPS register presented to the Tx attached to the active HDMI port. Table 207. BCAPS[7:0] Function Description BCAPS[7:0] 10000011 (default) xxxxxxxx Description Default BCAPS register value presented to the Tx BCAPS register value presented to the Tx BSTATUS[15:0], Address 64 (Repeater), Address 0x42[7:0]; Address 0x41[7:0] These registers contain the BSTATUS information presented to the Tx attached to the active HDMI port. Bits [11:0] must be set by the system software acting as a repeater. Table 208. BSTATUS[15:0] Function Description BSTATUS[15:0] xxxxxxxxxxxxxxxx 0000000000000000 (default) 0x41[7:0] 0x42[7:0] Description BSTATUS register presented to Tx. Reset value. BSTATUS register is reset only after power up. BSTATUS[7:0]. BSTATUS[15:8]. The KSV registers are stored consecutively in RAM, which is split into 5x128 bytes bank maps. The maps are accessible through KSV_BYTE_0 to KSV_BYTE_127. The proper segment can be selected via the KSV_MAP_SELECT[2:0] register, as shown in Figure 25. Rev. A | Page 79 of 168 UG-907 ADV7613 Reference Manual 0x00 0x00 TO 0x04 KSV0 0x05 TO 0x09 KSV1 0x0A TO 0x0E KSV2 0x80 KSV_BYTE_0 KSV_MAP_SELECT = 0 KSV_MAP_SELECT = 0 … 0x7D TO 0x81 KSV25 0x79 0x82 TO 0x86 KSV26 0x80 … 0xFF KSV_BYTE_127 KSV_MAP_SELECT = 1 0xF5 TO 0xF9 KSV49 0xFA TO 0xFE KSV50 0xFF 0xFF TO 0x103 KSV51 … 0x100 KSV_MAP_SELECT = 2 0x17C TO 0x180 KSV76 0x17F 0x181 TO 0x185 KSV77 0x186 TO 0x18A KSV78 … 0x180 KSV_MAP_SELECT = 3 0x1FE TO 0x202 KSV102 0x200 0x203 TO 0x207 KSV103 0x208 TO 0x20C KSV104 0x201 0x276 TO 0x27A KSV126 13807-025 KSV_MAP_SELECT = 4 … 0x27A Figure 25. Addressing Block Using KSV_MAP_SELECT and Register KSV_BYTE_0 to Register KSV_BYTE_127 KSV_MAP_SELECT[2:0], Address 64 (Repeater), Address 0x79[6:4] KSV_MAP_SELECT[2:0] selects which 128 bytes of KSV list are accessed when reading or writing to Address 0x80 to Address 0xFF in this map. Values from 5 and upwards are not valid. Table 209. KSV_MAP_SELECT[2:0] Function Description KSV_MAP_SELECT[2:0] 000 (default) 001 010 011 100 101 110 111 Description KSV Map 0 selected KSV Map 1 selected KSV Map 2 selected KSV Map 3 selected KSV Map 4 selected Reserved Reserved Reserved Table 210. KSV Byte Registers Location KSV Byte Number 0 1 2 3 4 5 6 7 8 9 10 Register Name KSV_BYTE_0[7:0] KSV_BYTE_1[7:0] KSV_BYTE_2[7:0] KSV_BYTE_3[7:0] KSV_BYTE_4[7:0] KSV_BYTE_5[7:0] KSV_BYTE_6[7:0] KSV_BYTE_7[7:0] KSV_BYTE_8[7:0] KSV_BYTE_9[7:0] KSV_BYTE_10[7:0] Rev. A | Page 80 of 168 Register Addresses1 0x80[7:0] 0x81[7:0] 0x82[7:0] 0x83[7:0] 0x84[7:0] 0x85[7:0] 0x86[7:0] 0x87[7:0] 0x88[7:0] 0x89[7:0] 0x8A[7:0] ADV7613 Reference Manual KSV Byte Number 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 UG-907 Register Name KSV_BYTE_11[7:0] KSV_BYTE_12[7:0] KSV_BYTE_13[7:0] KSV_BYTE_14[7:0] KSV_BYTE_15[7:0] KSV_BYTE_16[7:0] KSV_BYTE_17[7:0] KSV_BYTE_18[7:0] KSV_BYTE_19[7:0] KSV_BYTE_20[7:0] KSV_BYTE_21[7:0] KSV_BYTE_22[7:0] KSV_BYTE_23[7:0] KSV_BYTE_24[7:0] KSV_BYTE_25[7:0] KSV_BYTE_26[7:0] KSV_BYTE_27[7:0] KSV_BYTE_28[7:0] KSV_BYTE_29[7:0] KSV_BYTE_30[7:0] KSV_BYTE_31[7:0] KSV_BYTE_32[7:0] KSV_BYTE_33[7:0] KSV_BYTE_34[7:0] KSV_BYTE_35[7:0] KSV_BYTE_36[7:0] KSV_BYTE_37[7:0] KSV_BYTE_38[7:0] KSV_BYTE_39[7:0] KSV_BYTE_40[7:0] KSV_BYTE_41[7:0] KSV_BYTE_42[7:0] KSV_BYTE_43[7:0] KSV_BYTE_44[7:0] KSV_BYTE_45[7:0] KSV_BYTE_46[7:0] KSV_BYTE_47[7:0] KSV_BYTE_48[7:0] KSV_BYTE_49[7:0] KSV_BYTE_50[7:0] KSV_BYTE_51[7:0] KSV_BYTE_52[7:0] KSV_BYTE_53[7:0] KSV_BYTE_54[7:0] KSV_BYTE_55[7:0] KSV_BYTE_56[7:0] KSV_BYTE_57[7:0] KSV_BYTE_58[7:0] KSV_BYTE_59[7:0] KSV_BYTE_60[7:0] KSV_BYTE_61[7:0] KSV_BYTE_62[7:0] KSV_BYTE_63[7:0] Rev. A | Page 81 of 168 Register Addresses1 0x8B[7:0] 0x8C[7:0] 0x8D[7:0] 0x8E[7:0] 0x8F[7:0] 0x90[7:0] 0x91[7:0] 0x92[7:0] 0x93[7:0] 0x94[7:0] 0x95[7:0] 0x96[7:0] 0x97[7:0] 0x98[7:0] 0x99[7:0] 0x9A[7:0] 0x9B[7:0] 0x9C[7:0] 0x9D[7:0] 0x9E[7:0] 0x9F[7:0] 0xA0[7:0] 0xA1[7:0] 0xA2[7:0] 0xA3[7:0] 0xA4[7:0] 0xA5[7:0] 0xA6[7:0] 0xA7[7:0] 0xA8[7:0] 0xA9[7:0] 0xAA[7:0] 0xAB[7:0] 0xAC[7:0] 0xAD[7:0] 0xAE[7:0] 0xAF[7:0] 0xB0[7:0] 0xB1[7:0] 0xB2[7:0] 0xB3[7:0] 0xB4[7:0] 0xB5[7:0] 0xB6[7:0] 0xB7[7:0] 0xB8[7:0] 0xB9[7:0] 0xBA[7:0] 0xBB[7:0] 0xBC[7:0] 0xBD[7:0] 0xBE[7:0] 0xBF[7:0] UG-907 KSV Byte Number 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 ADV7613 Reference Manual Register Name KSV_BYTE_64[7:0] KSV_BYTE_65[7:0] KSV_BYTE_66[7:0] KSV_BYTE_67[7:0] KSV_BYTE_68[7:0] KSV_BYTE_69[7:0] KSV_BYTE_70[7:0] KSV_BYTE_71[7:0] KSV_BYTE_72[7:0] KSV_BYTE_73[7:0] KSV_BYTE_74[7:0] KSV_BYTE_75[7:0] KSV_BYTE_76[7:0] KSV_BYTE_77[7:0] KSV_BYTE_78[7:0] KSV_BYTE_79[7:0] KSV_BYTE_80[7:0] KSV_BYTE_81[7:0] KSV_BYTE_82[7:0] KSV_BYTE_83[7:0] KSV_BYTE_84[7:0] KSV_BYTE_85[7:0] KSV_BYTE_86[7:0] KSV_BYTE_87[7:0] KSV_BYTE_88[7:0] KSV_BYTE_89[7:0] KSV_BYTE_90[7:0] KSV_BYTE_91[7:0] KSV_BYTE_92[7:0] KSV_BYTE_93[7:0] KSV_BYTE_94[7:0] KSV_BYTE_95[7:0] KSV_BYTE_96[7:0] KSV_BYTE_97[7:0] KSV_BYTE_98[7:0] KSV_BYTE_99[7:0] KSV_BYTE_100[7:0] KSV_BYTE_101[7:0] KSV_BYTE_102[7:0] KSV_BYTE_103[7:0] KSV_BYTE_104[7:0] KSV_BYTE_105[7:0] KSV_BYTE_106[7:0] KSV_BYTE_107[7:0] KSV_BYTE_108[7:0] KSV_BYTE_109[7:0] KSV_BYTE_110[7:0] KSV_BYTE_111[7:0] KSV_BYTE_112[7:0] KSV_BYTE_113[7:0] KSV_BYTE_114[7:0] KSV_BYTE_115[7:0] KSV_BYTE_116[7:0] Rev. A | Page 82 of 168 Register Addresses1 0xC0[7:0] 0xC1[7:0] 0xC2[7:0] 0xC3[7:0] 0xC4[7:0] 0xC5[7:0] 0xC6[7:0] 0xC7[7:0] 0xC8[7:0] 0xC9[7:0] 0xCA[7:0] 0xCB[7:0] 0xCC[7:0] 0xCD[7:0] 0xCE[7:0] 0xCF[7:0] 0xD0[7:0] 0xD1[7:0] 0xD2[7:0] 0xD3[7:0] 0xD4[7:0] 0xD5[7:0] 0xD6[7:0] 0xD7[7:0] 0xD8[7:0] 0xD9[7:0] 0xDA[7:0] 0xDB[7:0] 0xDC[7:0] 0xDD[7:0] 0xDE[7:0] 0xDF[7:0] 0xE0[7:0] 0xE1[7:0] 0xE2[7:0] 0xE3[7:0] 0xE4[7:0] 0xE5[7:0] 0xE6[7:0] 0xE7[7:0] 0xE8[7:0] 0xE9[7:0] 0xEA[7:0] 0xEB[7:0] 0xEC[7:0] 0xED[7:0] 0xEE[7:0] 0xEF[7:0] 0xF0[7:0] 0xF1[7:0] 0xF2[7:0] 0xF3[7:0] 0xF4[7:0] ADV7613 Reference Manual KSV Byte Number 117 118 119 120 121 122 123 124 125 126 127 1 UG-907 Register Name KSV_BYTE_117[7:0] KSV_BYTE_118[7:0] KSV_BYTE_119[7:0] KSV_BYTE_120[7:0] KSV_BYTE_121[7:0] KSV_BYTE_122[7:0] KSV_BYTE_123[7:0] KSV_BYTE_124[7:0] KSV_BYTE_125[7:0] KSV_BYTE_126[7:0] KSV_BYTE_127[7:0] Register Addresses1 0xF5[7:0] 0xF6[7:0] 0xF7[7:0] 0xF8[7:0] 0xF9[7:0] 0xFA[7:0] 0xFB[7:0] 0xFC[7:0] 0xFD[7:0] 0xFE[7:0] 0xFF[7:0] All KSVs are located in the repeater map. Table 211. Registers Location for SHA-1 Hash Value V’ Register Name SHA_A[31:0] Function H0 part of SHA-1 hash value V’. Register also called (V’.H1)2. SHA_B[31:0] H1 part of SHA-1 hash value V’. Register also called (V’.H1)2. SHA_C[31:0] H2 part of SHA-1 hash value V’. Register also called (V’.H2)2. SHA_D[31:0] H3 part of SHA-1 hash value V’. Register also called (V’.H3)2. SHA_E[31:0] H4 part of SHA-1 hash value V’. Register also called (V’.H4)2. 1 2 Address Location1 0x20[7:0]: SHA_A[7:0] 0x21[7:0]: SHA_A[15:8] 0x22[7:0]: SHA_A[23:16] 0x23[7:0]: SHA_A[31:24] 0x24[7:0]: SHA_B[7:0] 0x25[7:0]: SHA_B[15:8] 0x26[7:0]: SHA_B[23:16] 0x27[7:0]: SHA_B[31:24] 0x28[7:0]: SHA_C[7:0] 0x29[7:0]: SHA_C[15:8] 0x2A[7:0]: SHA_C[23:16] 0x2B[7:0]: SHA_C[31:24] 0x2C[7:0]: SHA_D[7:0] 0x2D[7:0]: SHA_D[15:8] 0x2E[7:0]: SHA_D[23:16] 0x2F[7:0]: SHA_D[31:24] 0x30[7:0]: SHA_E[7:0] 0x31[7:0]: SHA_E[15:8] 0x32[7:0]: SHA_E[23:16] 0x33[7:0]: SHA_E[31:24] All registers specified in Table 211 are located in the repeater map. Refer to HDCP protection system Standards. INTERFACE TO DPP SECTION The video data below 2.25 Gbps from the HDMI section is sent to the CP section via the DPP block. The video data output by the HDMI section is always in a 4:4:4 format with 36 bits per pixel. This is irrespective of the encoding format of the video data encapsulated in the HDMI/DVI stream input to the HDMI receiver section (that is, 4:2:2 or 4:4:4). • • • • If the HDMI section receives a stream with video encoded in a 4:4:4 format, it passes the video data to the DPP section. If the HDMI section receives a stream with video encoded in a 4:2:2 format (see Figure 26), the HDMI section upconverts the video data into a 4:4:4 format, according to the UP_CONVERSION_MODE bit, and passes the upconverted video data to the DPP section (see Figure 27). If the HDMI receiver receives video data with fewer than 12 bits used per channel, the valid bits are left-shifted on each component channel with zeroes padding the bit below the LSB, before being sent to the DPP section. If the HDMI receiver receives video data above 2.25 Gbps, data must be send directly to the video output formatter, bypassing the DPP and CP core, where it is output using two video buses running at half pixel clock frequency Rev. A | Page 83 of 168 UG-907 ADV7613 Reference Manual Y0/Cb0 Y1/Cr0 Y2/Cb2 Y3/Cr2 Y4/Cb2 … BITS[3:0] Y0 BITS[3:0] Y1 BITS[3:0] Y2 BITS[3:0] Y3 BITS[3:0] Y4 BITS[3:0] … BITS[7:4] Cb0 BITS[3:0] Cr0 BITS[3:0] Cb2 BITS[3:0] Cr2 BITS[3:0] Cb4 BITS[3:0] … 1 BITS[7:0] Y0 BITS[11:4] Y1 BITS[11:4] Y2 BITS[11:4] Y3 BITS[11:4] Y4 BITS[11:4] … 2 BITS[7:0] Cb0 BITS[11:4] Cr0 BITS[11:4] Cb2 BITS[11:4] Cr2 BITS[11:4] Cb4 BITS[11:4] … 0 13807-026 TMDS CHANNEL Figure 26. YCbCr 4:2:2 Video Data Encapsulated in HDMI Stream Y0/Cb0/Cr0 Y1/CR0/CR0 Y2/Cb2/Cr2 Y3/Cb2/Cr2 Y4/Cb4/Cr4 … Y BITS[12:0] Y0 Y1 Y2 Y3 Y4 … Cb BITS[12:0] Cb0 Cb0 Cb2 Cb2 Cb4 … Cr BITS[12:0] Cr0 Cr0 Cr2 Cr2 Cr4 … 13807-027 COMPONENT CHANNEL Figure 27. Video Stream Output by HDMI Core for YCbCr 4:2:2 Input and UP_CONVERSION = 0 UP_CONVERSION_MODE, Address 68 (HDMI), Address 0x1D[5] This bit is a control to select linear or interpolated 4:2:2 to 4:4:4 conversion. A 4:2:2 incoming stream is upconverted to a 4:4:4 stream before being sent to the CP. Table 212. UP_CONVERSION_MODE Function Description UP_CONVERSION_MODE 0 (default) 1 Description Cr and Cb samples are repeated in their respective channel Interpolate Cr and Cb values Note that when the ADV7613 pixel output format is set to 4:2:2, the DPP section downconverts the 4:4:4 stream from the HDMI section according to DS_WITHOUT_FILTER. For a 4:4:4 HDMI input stream to the ADV7613, the DPP section filters and downsamples the video data from 4:4:4 to 4:2:2 format if DS_WITHOUT_FILTER is set to 0. The DPP section only downsamples, without filtering, the video data from the HDMI section if DS_WITHOUT_FILTER is set to 1. For a 4:2:2 HDMI input stream, the functionality of DS_WITHOUT_FILTER is reversed. This inversion ensures that for a 4:2:2 HDMI input stream no filtering is applied if DS_WITHOUT_FILTER is left to its default value of 0. When a 4:2:2 HDMI input stream is input to the ADV7613, the DPP section downsamples, without filtering, the video data from 4:4:4 to 4:2:2 format if DS_WITHOUT_FILTER is set to 0. If DS_WITHOUT_FILTER is set to 1, the DPP filters and downsamples the video data from 4:4:4 to 4:2:2 format. DS_WITHOUT_FILTER, Address 40 (IO), Address 0xE0[7] This bit disables the chroma filters on Channel B and Channel C while keeping the downsampler functional. Table 213. DS_WITHOUT_FILTER Function Description DS_WITHOUT_FILTER 0 (default) 1 Description Filters and downsamples Downsamples only (no filtering) COLOR SPACE INFORMATION SENT TO THE DPP AND CP SECTIONS The HDMI section sends information regarding the color space of the video it outputs to the DPP and the CP sections. This color space information is derived from the DVI/HDMI status of the input stream the HDMI stection processes and from the AVI InfoFrame that the HDMI section decodes from the input stream. The color space information sent by the HDMI section to the DDP and CP sections can be read via HDMI_COLORSPACE[3:0]. Rev. A | Page 84 of 168 ADV7613 Reference Manual UG-907 HDMI_COLORSPACE[3:0], Address 68 (HDMI), Address 0x53[3:0] (Read Only) HDMI_COLORSPACE[3:0] is a readback of the HDMI input color space decoded from several fields in the AVI InfoFrame. Table 214. HDMI_COLORSPACE[3:0] Function Description HDMI_COLORSPACE[3:0] 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Description RGB_LIMITED RGB_FULL YUV_601 YUV_709 XVYCC_601 XVYCC_709 YUV_601_FULL YUV_709_FULL sYCC 601 Adobe YCC 601 Adobe RGB STATUS REGISTERS Many status bit are available throughout the IO and HDMI maps. These status bits are listed in Table 215 to Table 224. Table 215. HDMI Flags in IO Map Register 0x60 Bit Name AVI_INFO_RAW Bit Position 0 (LSB) AUDIO_INFO_RAW 1 SPD_INFO_RAW 2 MS_INFO_RAW 3 VS_INFO_RAW 4 ACP_PCKT_RAW 5 ISRC1_PCKT_RAW 6 ISRC2_PCKT_RAW 7 (MSB) Description Returns 1 if an AVI InfoFrame was received within last seven VSYNCs. For additional information, see the Interrupt Architecture Overview section. Returns 1 if an AVI InfoFrame was received within last three VSYNCs. For additional information, see the Audio InfoFrame Registers section. Returns 1 if a source product descriptor InfoFrame has been received. For additional information, see the SPD InfoFrame Registers section. Returns 1 if a MPEG InfoFrame was received within the last three VSYNCs. For additional information, see the MPEG Source InfoFrame Registers section. Returns 1 if a vendor specific InfoFrame has been received. For additional information, see the Vendor Specific InfoFrame Registers section. Returns 1 if an ACP packet was received within last 600 ms. For additional information, see the ACP Packet Registers section. Returns 1 if an ISRC1 packet was received. For additional information, see the ISRC Packet Registers section. Returns 1 if an ISRC2 packet was received. For additional information, see the ISRC Packet Registers section. Table 216. HDMI Flags in IO Map Register 0x65 Bit Name GAMUT_MDATA_RAW AUDIO_C_PCKT_RAW Bit Position 0 (LSB) 1 GEN_CTL_PCKT_RAW 2 HDMI_MODE_RAW 3 AUDIO_CH_MD_RAW 4 AV_MUTE_RAW 5 INTERNAL_MUTE_RAW 6 CS_DATA_VALID_RAW 7 (MSB) Description Returns 1 if a gamut metadata packet was received. Returns 1 if an audio clock regeneration packet has been received. Reset to 0 following a packet detection flag reset condition. Returns 1 if general control packet has been received. Reset to 0 following a packet detection flag reset condition. Returns 1 if a HDMI stream is being received. For additional information, see HDMI/DVI Status Bits section. Returns 1 if the audio channel mode is multichannel (2-, 4-, 6-, or 8-channel) audio. Reset to 0 following a packet detection flag reset condition. For additional information, see the Audio Channel Mode section. Returns 1 if the latest general control packet received has AV_MUTE asserted. Reset to 0 following packet detection flag reset condition. Returns 1 if ADV7613 has internally muted the audio data. For additional information, see the Internal Mute Status section. Returns 1 if channel status bit readback registers in HDMI map, Address 0x36 to 0x3A are valid. For additional information, see the Validity Status Flag section. Rev. A | Page 85 of 168 UG-907 ADV7613 Reference Manual Table 217. HDMI Flags in IO Map Register 0x6A Bit Name DE_REGEN_LCK_RAW V_LOCKED_RAW VIDEO_3D_RAW TMDS_CLK_A_RAW TMDSPLL_LCK_A_RAW Bit Position 0 (LSB) 1 2 4 6 Description Description available in the Primary Port Horizontal Filter Measurements section. Description available in the Primary Port Horizontal Filter Measurements section. Raw interrupt status of 3D video detection flag (refer to VIDEO_3D_ST in Table 384). Description available in the TMDS Clock Activity Detection section Description available in the TMDS Measurement After TMDS PLL section Table 218. HDMI Flags in IO Map Register 0x6F Bit Name CABLE_DET_A_RAW HDMI_ENCRPT_A_RAW Bit Position 0 2 Description Description available in the +5 V Cable Detect section. Description available in the HDCP Decryption Engine section. Table 219. HDMI Flags in IO Map Register 0x79 Bit Name NEW_AVI_INFO_RAW NEW_AUDIO_INFO_RAW NEW_SPD_INFO_RAW NEW_MS_INFO_RAW NEW_VS_INFO_RAW NEW_ACP_PCKT_RAW NEW_ISRC1_PCKT_RAW NEW_ISRC2_PCKT_RAW Bit Position 0 (LSB) 1 2 3 4 5 6 7 (MSB) Table 220. HDMI Flags in IO Map Register 0x7E Bit Name NEW_GAMUT_MDATA_RAW Bit Position 0 (LSB) AUDIO_PCKT_ERR_RAW 1 PACKET_ERROR_RAW 2 CHANGE_N_RAW 3 CTS_PASS_THRSH_RAW 4 FIFO_OVERFLO_RAW 5 FIFO_UNDERFLO_RAW 6 FIFO_NEAR_OVFL_RAW 7 (MSB) Description When set to 1 indicates that a gamut metadata packet with new content has been received. Once set, this bit remains high until the interrupt is cleared via NEW_GAMUT_MDATA_PCKT_CLR (IO Map 0x80[0]). When set to 1 indicates that an uncorrectable error was detected in the body of an audio packet. Once set, this bit remains high until the interrupt is cleared via AUDIO_PCKT_ERR_CLR (IO Map 0x80[1]). When set to 1 it indicates an uncorrectable EEC error was detected in the body or header of any packet. Once set, this bit remains high until the interrupt is cleared via PACKET_ERROR_CLR (IO Map 0x80[2]). When set to 1 it indicates the N value of the ACR packets has changed. Once set, this bit remains high until the interrupt is cleared via CHANGE_N_CLR (IO Map 0x80 [3]). When set to 1 it indicates the CTS value of the ACR packets has exceeded the threshold set by CTS_CHANGE_THRESHOLD. Once set, this bit remains high until the interrupt is cleared via CTS_PASS_THRSH_CLR (IO Map 0x80[4]). When set to 1 it indicates the audio FIFO write pointer has reached the read pointer causing the audio FIFO to overflow. Once set, this bit remains high until the interrupt is cleared via FIFO_OVERFLO_CLR (IO Map 0x80[5]). When set to 1 it indicates the audio FIFO read pointer has reached the write pointer causing the audio FIFO to underflow. Once set, this bit remains high until the interrupt is cleared via FIFO_UNDERFLO_CLR (IO Map 0x80[6]). When set to 1 it indicates the audio FIFO is near overflow as the number FIFO registers containing stereo data is greater or equal to value set in AUDIO_FIFO_ALMOST_FULL_ THRESHOLD. Once set, this bit remains high until the interrupt is cleared via FIFO_NEAR_OVFL_CLR (IO Map 0x80[7]). Rev. A | Page 86 of 168 ADV7613 Reference Manual UG-907 Table 221. HDMI Flags in IO Map Register 0x83 Bit Name FIFO_NEAR_UFLO_RAW Bit Position 0 (LSB) NEW_TMDS_FRQ_RAW 1 AUDIO_FLT_LINE_RAW 2 NEW_SAMP_RT_RAW 3 PARITY_ERROR_RAW 4 AUDIO_MODE_CHNG_RAW 5 VCLK_CHNG_RAW 6 DEEP_COLOR_CHNG_RAW 7 (MSB) Description When set to 1 it indicates the audio FIFO is near underflow as the number of FIFO registers containing stereo data is less or equal to value set in AUDIO_FIFO_ALMOST_EMPTY_ THRESHOLD. Once set, this bit remains high until the interrupt is cleared via FIFO_NEAR_UFLO_CLR (IO Map 0x85[0]). When set to 1 it indicates the TMDS frequency has changed by more than the tolerance set in FREQTOLERANCE[3:0] Once set, this bit remains high until the interrupt is cleared via NEW_TMDS_FREQ_CLR (IO Map 0x85[1]). When set to 1 it indicates audio sample packet has been received with the flat line bit set to 1. Once set, this bit remains high until the interrupt is cleared via AUDIO_FLT_LINE_CLR (IO Map 0x85[2]). When set to 1 it indicates that audio sampling frequency field in channel status data has changed. Once set, this bit remains high until the interrupt is cleared via NEW_SAMP_ RT_CLR (IO Map 0x85[3]). When set to 1 it indicates an audio sample packet has been received with parity error. Once set, this bit remains high until the interrupt is cleared via PARITY_ERROR_CLR (IO Map 0x85 [4]). When set to 1 it indicates that the type of audio packet received has changed. The following are considered audio modes, no audio, PCM, DSD, HBR, or DST. AUDIO_SAMPL_PCKT_DET, DSD_PACKET_DET, DST_AUDIO_PCKT_DET, and HBR_AUDIO_PCKT_DET used identify type of audio packet currently received. Once set, this bit remains high until the interrupt is cleared via AUDIO_MODE_CHNG_CLR (IO Map 0x85[5]). When set to 1 it indicates that irregular or missing pulses are detected in the TMDS clock. Once set, this bit remains high until the interrupt is cleared via VCLK_CHNG_CLR (IO Map 0x85[6]). When set to 1 it indicates a change in the deep color mode has been detected. Once set, this bit remains high until the interrupt is cleared via DEEP_COLOR_CHNG_CLR (IO Map 0x85[7]). Table 222. HDMI InfoFrame Checksum Error Flags in IO Map Bit Name AVI_INF_CKS_ERR_RAW AUD_INF_CKS_ERR_RAW SPD_INF_CKS_ERR_RAW MS_INF_CKS_ERR_RAW VS_INF_CKS_ERR_RAW IO Map Location 0x88[4] 0x88[5] 0x88[6] 0x88[7] 0x8D[0] Description Description available in the InfoFrame Checksum Error Flags section. Description available in the InfoFrame Checksum Error Flags section. Description available in the InfoFrame Checksum Error Flags section. Description available in the InfoFrame Checksum Error Flags section. Description available in the InfoFrame Checksum Error Flags section. Table 223. AKSV Update Flags and RI Expired Flag in IO Map Register 0x88 Bit Name AKSV_UPDATE_A_RAW Bit Position 0 RI_EXPIRED_A_RAW 2 Description When set to 1 it indicates that transmitter has written its AKSV into HDCP registers for Port A. When set, this bit remains high until the interrupt is cleared via AKSV_UPDATE_A_CLR (IO Map, Address 0x8A[0]). Status of Port A Ri expired interrupt signal. When set to 1, it indicates that HDCP cipher Ri value for Port A is expired. Once set, this bit remains high until it is cleared via RI_EXPIRED_A_CLR (HDMI map, Address 0x8A[2]). Table 224. HDMI Flags in HDMI Map Bit Name AUDIO_PLL_LOCKED AUDIO_SAMPLE_PCKT_DET DSD_PACKET_DET DST_AUDIO_PCKT_DET HBR_AUDIO_PCKT_DET DCFIFO_LOCKED HDMI Map Location 0x04[0] 0x18[0] 0x18[1] 0x18[2] 0x18[3] 0x1C[3] Description Description available in the Locking Mechanism section. Description available in the Audio Packet Type Flags section. Description available in the Audio Packet Type Flags section. Description available in the Audio Packet Type Flags section. Description available in the Audio Packet Type Flags section. Description available in the Video FIFO section. Rev. A | Page 87 of 168 UG-907 ADV7613 Reference Manual HDMI SECTION RESET STRATEGY The reset strategy implemented for the HDMI section is as follows. A global chip reset is triggered by asserting the reset pin to a low level. The HDMI section, excluding the EDID/repeater controller, is reset when a global reset is triggered. A loss of TMDS clock or 5 V signal on the HDMI port selected via HDMI_PORT_SELECT resets the entire HDMI section except for the EDID/repeater controller and the audio section. The loss of a 5 V signal condition is discarded if DIS_CABLE_DET_RST is set high. For a DVI mode reset, the packet processing block, including InfoFrame memory is held in reset when the HDMI section processes a DVI stream. For a EDID/repeater controller reset, the EDID/repeater controller is reset when the DVDD supplies go low or when HDCP_REPT_ EDID_RESET is set high. HDMI PACKET DETECTION FLAG RESET A packet detection flag reset is triggered when any of the following events occur: • • • • The ADV7613 is powered up. The ADV7613 is reset. A TMDS clock is detected, after a period of no clock activity, on the selected HDMI port. The selected HDMI port is changed. The signal from the 5 V input pin of the HDMI port selected through HDMI_PORT_SELECT transitions to a high. This condition is discarded if DIS_CABLE_DET_RST is set high. Rev. A | Page 88 of 168 ADV7613 Reference Manual UG-907 DATA PREPROCESSOR, COLOR SPACE CONVERSION, AND COLOR CONTROLS COLOR SPACE CONVERSION MATRIX The ADV7613 provides any-to-any color space support. It supports formats such as RGB, YUV, YCbCr, and many other color spaces. The data preprocessor (DPP) and component processor (CP) run at speeds of up to 170 MHz. The ADV7613 features a 3×3 color space conversion matrix (CSC) in the CP block (CP CSC), as shown in Figure 28. The CP CSC also provides color controls for brightness, contrast, saturation, and hue adjustments. The DPP block features an automatic CSC. The ADV7613 automatically configures the DPP CSC depending on the input and output formats and the use of the color control feature. DATA PRE-PROCESSOR (DPP) FIRST STAGE DECIMATION FILTER COMPONENT PROCESSOR (CP) SECOND STAGE DECIMATION FILTER CP COLOR SPACE CONVERSION MATRIX (CP CSC) 13807-028 DPP COLOR SPACE CONVERSION MATRIX (DPP CSC) Figure 28. DPP/CP CSC Block Diagram The configuration of the color space conversion using the CP CSC block and a description of the adjustable register bits are provided in Figure 29. CSC_COEFF_SEL MANUAL CSC MODE CSC_SCALE A1-A4[12:0] B1-B4[12:0] C1-C4[12:0] 0000 AUTOMATIC CSC MODE RGB_OUT INP_COLOR_SPACE ALT_GAMMA 1111 CHANNEL A, B, AND C FROM DPP CHANNEL A, B, AND C TO CP CORE CP COLOR CONTROL CP COLOR SPACE CONVERSION MATRIX (CP CSC) CP_BRIGHTNESS CP_SATURATION CP_CONTRAST CP_HUE 1 VID_ADJ_EN 13807-029 0 Figure 29. Configuring CP CSC Block CP CSC Selection MAN_CP_CSC_EN, Address 44 (CP), Address 0x69[4] MAN_CP_CSC_EN is a control to manually enable the CP CSC. By default, the CP CSC is automatically enabled if either a color-space conversion or video adjustments (hue, saturation, contrast, brightness) are determined to be required due to other I2C settings. If MAN_CP_CSC_EN is set to 1, the CP CSC is forced into the enabled state. Table 225. MAN_CP_CSC_EN Function Description MAN_CP_CSC_EN 0 (default) 1 Description CP CSC is automatically enabled if required, for example, if either a color space conversion or video adjustment (hue, saturation, contrast, brightness) is determined to be required due to other I2C settings. Manual override to force CP CSC to be enabled. Rev. A | Page 89 of 168 UG-907 ADV7613 Reference Manual Selecting Automatic or Manual CP CSC Conversion Mode The ADV7613 CP CSC provides two modes for the CSC configuration: automatic CSC mode and manual CSC mode. In automatic CSC mode, the user is required to program the input color space and the output color space for the correct operation of the CSC matrix. Manual CSC mode allows the user to program all the color space conversion by manually programming CSC coefficients. CSC_COEFF_SEL[3:0], Address 44 (CP), Address 0x68[7:4] CSC_COEFF_SEL[3:0] is a control to select the mode the CP CSC operates in. Table 226. CSC_COEFF_SEL[3:0] Function Description CSC_COEFF_SEL[3:0] 0000 1111 (default) xxxx Description CP CSC configuration in manual mode CP CSC configured in automatic mode Reserved The selection of the CSC is automated in the ADV7613. Automatic or manual CSC mode can be selected by setting the CSC_COEFF_SEL[3:0] bits. When CSC_COEFF_SEL[3:0] is set to 0b1111, the CSC mode is automatically selected, based on the input color space and output color space required and set through the INP_COLOR_SPACE[3:0], RGB_OUT, and ALT_GAMMA registers. Automatic Color Space Conversion Matrix The CSC matrix, automatic gain control (AGC) target gain values, and offset values can be configured automatically via the INP_COLOR_SPACE[3:0], RGB_OUT, ALT_GAMMA, and OP_656_RANGE_SEL registers. INP_COLOR_SPACE[3:0], IO, Address 0x02[7:4] INP_COLOR_SPACE[3:0] is a control to set the color space of the input video. It is used in conjunction with ALT_GAMMA and RGB_OUT to configure the color space converter. A value of 4'b1111 selects automatic setting of the input color space based on the primary mode and video standard settings. Setting 1000 to Setting 1110 are undefined. Table 227. INP_COLOR_SPACE[3:0] Function Description INP_COLOR_SPACE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1111 (default) Description Forces RGB (range 16 to 235) input Forces RGB (range 0 to 255) input Forces YCrCb input (601 color space) (range 16 to 235) Forces YCrCb input (709 color space) (range 16 to 235) Forces XVYCC 601 Forces XVYCC 709 Forces YCrCb input (601 color space) (range 0 to 255) Forces YCrCb input (709 color space) (range 0 to 255) Input color space depends on color space reported by HDMI block. Table 228. Automatic Input Color Space Selection PRIM_MODE[3:0] 0101 VID_STD[5:0] xxxx Input Color Space Dependent on AVI InfoFrame 0110 xxxx Dependent on AVI InfoFrame Input Range 0:255 for YUV Dependent on AVI InfoFrame for RGB 0:255 for YUV Dependent on AVI InfoFrame for RGB Comments HDMI component modes HDMI graphic modes RGB_OUT, IO, Address 0x02[1] RGB_OUT is a control to select output color space and the correct digital blank level and offsets on the RGB or YPrPb outputs. It is used in conjunction with the INP_COLOR_SPACE[3:0] and ALT_GAMMA bits to select the applied CSC. Table 229. RGB_OUT Function Description RGB_OUT 0 (default) 1 Description YPbPr color space output RGB color space output Rev. A | Page 90 of 168 ADV7613 Reference Manual UG-907 ALT_GAMMA, IO, Address 0x02[3] ALT_GAMMA is a control to set the color space of the input video. It is used in conjunction with ALT_GAMMA and RGB_OUT to configure the color space converter. A value of 4'b1111 selects automatic setting of the input color space based on the primary mode and video standard settings. Setting 1000 to Setting 1110 are undefined. Table 230. ALT_GAMMA Function Description ALT_GAMMA 0 (default) 1 Description No conversion. YUV601 to YUV709 conversion applied if input is YUV601. YUV709 to YUV601 conversion applied if input is YUV709. Table 231. Automatic CSC Selection INP_COLOR_SPACE[3:0] (Input Color Space) 00 = RGB 01 = (YCbCr /YUV 601) 10 = (YCbCr /YUV 709) RGB_OUT 0 1 0 1 0 1 CSC Mode Used (Output) ALT_GAMMA = 0 ALT_GAMMA = 1 YCbCr 601 YCbCr 709 RGB RGB YCbCr 601 YCbCr 709 RGB RGB YCbCr 709 YCbCr 601 RGB RGB CSC_COEFF_SEL_RB[3:0], Address 44 (CP), Address 0xF4[7:4] (Read Only) CSC_COEFF_SEL_RB[3:0] is the readback of the CP CSC conversion when configured in automatic mode. Table 232. CSC_COEFF_SEL_RB[3:0] Function Description CSC_COEFF_SEL_RB[3:0] 0000 (default) 0001 0011 0101 0111 1001 1010 1111 xxxx Description CSC is bypassed YPbPr 601 to RGB YPbPr 709 to RGB RGB to YPbPr 601 RGB to YPbPr 709 YPbPr 709 to YPbPr 601 YPbPr 601 to YPbPr 709 CSC in manual mode Reserved Table 233. CSC Configuration for All CSC Modes Reported by CSC_COEFF_SEL_RB CSC Mode 0b0000 0b0001 0b0011 0b0101 0b0111 0b1001 0b1010 CSC_ SCALE [1:0] 0b01 0b01 0b00 0b00 0b01 0b01 A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 CSC in bypass mode. In this mode the CSC effectively performs a color conversion based on the CSC coefficients set in registers CSC_SCALE, A1, A2, A3, A4, B1, B2, B3, B4, C1, C2, C3, and C4. 0x0800 0x1A6A 0x1D50 0x0423 0x0800 0x0AF8 0x0000 0x1A84 0x0800 0x0000 0x0DDB 0x0800 0x1C54 0x1E89 0x0291 0x0800 0x0C52 0x0000 0x19D7 0x0800 0x0000 0x0E87 0x0964 0x04C9 0x01D3 0x0000 0x1927 0x082D 0x1EAC 0x0800 0x1A93 0x1D3F 0x082D 0x0B71 0x0368 0x0127 0x0000 0x1893 0x082D 0x1F3F 0x0800 0x19B2 0x1E21 0x082D 0x0800 0x0188 0x00CB 0x1ED7 0x0000 0x07DE 0x1F6C 0x005B 0x0000 0x1F1D 0x07EB 0x0800 0x1E56 0x1F14 0x014A 0x0000 0x0834 0x009A 0x1F9A 0x0000 0x00EB 0x0826 Rev. A | Page 91 of 168 C4 0x1912 0x18BC 0x0800 0x0800 0x007B 0x1F78 UG-907 ADV7613 Reference Manual HDMI Automatic CSC Operation In HDMI mode, the ADV7613 provides an automatic CSC function based on the AVI InfoFrame sent from the source. The flowchart in Figure 30 shows the mechanism of the ADV7613 automatic CSC functionality in HDMI mode. Note that in the following flowcharts, a dashed line represents a state that is undefined according to the CEA-861D specification, and therefore must never happen. In the event that it does somehow occur, the ADV7613 retains the previous colorimetry. START Y[1:0] = 00b RGB MODE Y[1:0] = 01b YCbCr MODE Y[1:0] = 10b YCbCr MODE Y[1:0] = 11b YCbCr MODE 13807-030 DETECT YCbCr/RGB Y[1:0] = xxb? Figure 30. HDMI Automatic CSC Flowchart Y[1:0] = 00b RGB MODE START DETECT QUANTIZATION RANGE Q[1:0] = xxb? Q[1:0] = 01b Q[1:0] = 00b Q[1:0] = 10b Q[1:0] = 11b REMAIN CURRENT CS OR RGB LIMITED RANGE RGB LIMITED RANGE CHECK ITC IN AVI (ITC = 1?) TRUE RGB FULL RANGE Figure 31. HDMI Automatic CSC Flowchart (Case RGB) Rev. A | Page 92 of 168 13807-031 FALSE ADV7613 Reference Manual UG-907 Y[1:0] = 01b, 10b, 11b YCbCr MODE START YCbCr COLORIMETRY C[1:0] = xxb? C[1:0] = 10b C[1:0] = 10b C[1:0] = 00b C[1:0] = 11b YUV709 YUV601 EC[2:0] = 001b xvYCC709 EC[2:0] = 000b xvYCC601 EC[2:0] ≠ (001 OR 000) REMAIN CURRENT STATUS Figure 32. HDMI Automatic CSC Flowchart (Case YCbCr-1) YCbCr COLORIMETRY C[1:0] = 00b VIDEO FORMAT IDENTIFICATION CODE CHECK VIC[6:0] VALUES IN AVI INFOFRAME VIC[6:0] == 0d VIC[6:0] == 1d VIC[6:0] == 4d VIC[6:0] == 5d VIC[6:0] == 16d VIC[6:0] == 19d VIC[6:0] == 20d VIC[6:0] == 31d VIC[6:0] == 32d VIC[6:0] == 33d VIC[6:0] == 34d VIC[6:0] == 39d VIC[6:0] == 40d VIC[6:0] == 46d VIC[6:0] == 47d VIC[6:0] >= 60d FALSE YUV601 13807-033 TRUE YUV709 Figure 33. HDMI Automatic CSC Flowchart (Case YCbCr-2) Rev. A | Page 93 of 168 13807-032 EXTENDED COLORIMETRY EC[2:0] = xxxb? UG-907 ADV7613 Reference Manual In the RGB case (see Figure 34), the ADV7613 has the programmability to control manually the RGB limited/full range regardless of the ITC bit. Y[1:0] = 00b RGB START 4:4:4 MODE DETECT QUANTIZATION RANGE Q[1:0] = xxb? Q[1:0] = 01b Q[1:0] = 10b QZERO_RGB_FULL = 1 1-BIT CONTROL TO SELECT FULL/LIMITED RGB/RANGE RGB FULL RANGE RGB LIMITED RANGE 13807-034 QZERO_RGB_FULL = 0 (DEFAULT) Q[1:0] = 00b Figure 34. Manual RGB Range Control Flowchart for Automatic CSC (Case RGB) QZERO_ITC_DIS, Address 68 (HDMI), Address 0x47[2] QZERO_ITC_DIS is a control to select manual control of the RGB colorimetry when the AVI InfoFrame field Q[1:0] = 00. It is used in conjunction with QZERO_RGB_FULL. Table 234. QZERO_ITC_DIS Function Description QZERO_ITC_DIS 0 (default) 1 Description AVI InfoFrame ITC bit decides RGB-full or limited range in case Q[1:0] = 00 Manual RGB range as per QZERO_RGB_FULL QZERO_RGB_FULL, Address 68 (HDMI), Address 0x47[1] QZERO_RGB_FULL is a control to manually select the HDMI colorimetry when AVI InfoFrame field Q[1:0] = 00. It is valid only when QZERO_ITC_DIS is set to 1. Table 235. QZERO_RGB_FULL Function Description QZERO_RGB_FULL 0 (default) 1 Description RGB-limited range when Q[1:0] = 00 RGB-full when Q[1:0] = 00 Rev. A | Page 94 of 168 ADV7613 Reference Manual UG-907 Manual Color Space Conversion Matrix The CP CSC matrix in the ADV7613 is a 3 × 3 matrix with full programmability of all coefficients in the matrix in manual mode. Each coefficient is 12 bits wide to ensure signal integrity is maintained in the CP CSC section. The CP CSC contains three identical processing channels, one of which is shown in Figure 35. The main inputs labeled In_A, In_B, and In_C come from the 36-bit digital input from the HDMI section. Each input to the individual channels to the CSC is multiplied by a separate coefficient for each channel. In Figure 35, these coefficients are marked A1, A2 and A3. The variable labeled A4 is used as an offset control for Channel A in the CSC. There is also a further CP CSC control bit labeled CSC_SCALE[1:0]; this control can be used to accommodate coefficients that extend the supported range. The functional diagram for a single channel in the CP CSC as per Figure 35 is repeated for the other two remaining channels, Channel B and Channel C. The coefficients for these channels are called B1, B2, B3, B4, C1, C2, C3, and C4. CSC_SCALE A1[12:0] A4[12:0] ×2 IN_A[11:0] 1 OUT_A[11:0] × + + + 0 A2[12:0] IN_B[11:0] × IN_C[11:0] 13807-035 A3[12:0] × Figure 35. Single CSC Channel The coefficients mentioned previously are detailed in Table 236 along with the default values for these coefficients. Table 236. CSC Coefficients Function Bit A1[12:0] A2[12:0] A3[12:0] B1[12:0] B2[12:0] B3[12:0] C1[12:0] C2[12:0] C3[12:0] CSC_SCALE[1:0] A4[12:0] B4[12:0] C4[12:0] CP Map Address 0x57[4:0], 0x58[7:0] 0x55[1:0], 0x56[7:0], 0x57[7:5] 0x54[6:0], 0x55[7:2] 0x5E[4:0], 0x5F[7:0] 0x5C[1:0], 0x5D[7:0], 0x5E[7:5] 0x5B[6:0], 0x5C[7:2] 0x65[4:0], 0x66[7:0] 0x63[1:0], 0x64[7:0], 0x65[7:5] 0x62[6:0], 0x63[7:2] 0x52[7:6] 0x52[4:0], 0x53[7:0] 0x59[4:0], 0x5A[7:0] 0x60[4:0], 0x61[7:0] Reset Value (Hex) 0x800 0x000 0x000 0x000 0x800 0x000 0x000 0x000 0x800 0x01 0x000 0x000 0x000 CSC_SCALE[1:0], Address 44 (CP), Address 0x52[7:6] CSC_SCALE[1:0] is a control to set the CSC coefficient scaler. Table 237. CSC_SCALE[1:0] Function Description CSC_SCALE[1:0] 00 01 (default) 10 11 Description CSC scaler set to 1. CSC scaler set to 2. Reserved. Do not use. Reserved. Do not use. Rev. A | Page 95 of 168 Description Coefficient for Channel A Coefficient for Channel A Coefficient for Channel A Coefficient for Channel B Coefficient for Channel B Coefficient for Channel B Coefficient for Channel C Coefficient for Channel C Coefficient for Channel C Scaling for CSC formula Offset for Channel A Offset for Channel B Offset for Channel C UG-907 ADV7613 Reference Manual CSC Manual Programming The equations performed by the CP CSC are as follows. For CSC Channel A, A1[12:0] A2[12:0] A3[12:0]   Out _ A   In _ A   In _ B   In _ C   A4[12:0]   2CSC _ SCALE 4096 4096 4096   (4) For CSC Channel B, B1[12:0] B2[12:0] B3[12:0]   Out _ B   In _ A   In _ B   In _ C   B4[12:0]   2CSC _ SCALE 4096 4096 4096   (5) For CSC Channel C, C1[12:0] C2[12:0] C3[12:0]   Out _ C   In _ A   In _ B   In _ C   C4[12:0]   2CSC _ SCALE 4096 4096 4096   (6) As can be seen from Equation 4, Equation 5, and Equation 6, the A1, A2, A3; B1, B2, B3, and C1, C2, C3 coefficients are used to scale the primary inputs. The values of A4, B4, and C4 are added as offsets. The CSC_SCALE[1:0] bits allow the user to implement a conversion formula in which the coefficients exceed the standard range of [−4095/4096 ... 4095/4096]. The overall range of the CSC is [0 … 1] for unipolar signals (for example, Y, R, G, and B) and [−0.5 … +0.5] for bipolar signals (for example, Pr and Pb). Note that the bipolar signals must be offset to midrange, for example, 2048. To arrive at programming values from typical formulas, perform the following steps: 1. 2. 3. 4. 5. 6. 7. 8. 9. Determine the dynamic range of the equation. The dynamic range of the CSC is [0 … 1] or [−0.5 … +0.5]. Equations with a gain larger than 1 need to be scaled back. Errors in the gain can be compensated for in the gain stages of the follow on blocks. Scale the equations, if necessary. Check the value of each coefficient. The coefficients can only be programmed in the range [−0.99 … +0.99]. To support larger coefficients, use the CSC_SCALE[1:0] function. Determine the setting for CSC_SCALE[1:0] and adjust coefficients, if necessary. Program the coefficient values. Convert the float point coefficients into 12-bit fixed decimal format. Convert into binary format, using twos complement for negative values. Program A1 to A3, B1 to B3, and C1 to C3. Program the offset values. Depending on the type of CSC, offsets may have to be used. Program A4, B4, and C4. CSC Example The following set of equations gives an example of a conversion from a gamma corrected RGB signal into a YCbCr color space signal. A1[12:0] A2[12:0] A3[12:0]   Out _ A   In _ A   In _ B   In _ C   A4[12:0]   2CSC _ SCALE 4096 4096 4096   B1[12:0] B2[12:0] B3[12:0]   Out _ B   In _ A   In _ B   In _ C   B4[12:0]   2CSC _ SCALE 4096 4096 4096   C1[12:0] C2[12:0] C3[12:0]   Out _ C   In _ A   In _ B   In _ C   C4[12:0]   2CSC _ SCALE 4096 4096 4096   Note that the original equations give offset values of 128 for the Pr and Pb components. The value of 128 equates to half the range on an 8-bit system. It must be noted that the CSC operates on a 12-bit range. The offsets, therefore, must be changed from 128 to half the range of a 12-bit system, which equates to 2048. The maximum range for each equation, that is, each output data path, can only be [0 ... 1] or [−0.5 ... +0.5]. Equations with a larger gain must be scaled back into range. The gain error can be compensated for in the gain stage of the follow on blocks. The ranges of the three equations are shown in Table 238. Rev. A | Page 96 of 168 ADV7613 Reference Manual UG-907 Table 238. Equation Ranges Equation Y Pb Pr Minimum Value 0+0+0=0 (−0.34) + (−0.17) = −0.51 (−0.43) + (−0.08) = −0.51 Maximum Value 0.59 + 0.3 + 0.11 = 1 0.51 0.51 Range [0 … 1] = 1 [−0.51 …+ 0.51] = 1.02 [−0.51 … +0.51] = 1.02 As can be seen from Table 238, the range for the Y component fits into the CSC operating range. However, the Pb and Pr ranges slightly exceed the range. To bring all equations back into the supported range, they must be scaled back by 1/1.02. If equations fall outside the supported range, overflow or underflow can occur and undesirable wrap around effects (large number overflowing to small ones) can occur. Y 0.59 0.3 0.11 G  R  B  0.58  G  0.29  R  0.11  B 1.02 1.02 1.02 Pb  0.34 0.17 0.51 G  R  B  2048  0.33  G  0.17  R  0.5  B  2048 1.02 1.02 1.02 Pr  0.43 0.51 0.08 G  R  B  2048  0.42  G  0.5  R  0.08  B  2048 1.02 1.02 1.02 Note that the scaling of the dynamic range does not affect the static offset. Check the Value of Each Coefficient The maximum value for each coefficient on its own can only be within the range of −4096/+4096 to 4095/4096, which equals [1 … +0.999755859375]. Values outside this range do not fit into the 12-bit fixed point format used to program the coefficients. If the value of one or more coefficients after scaling of the overall equation exceeds the supported coefficient range, CSC_SCALE[1:0] must be set. With CSC_SCALE[1:0] set high, all coefficients must be scaled by half, which makes them fit into the given coefficient range. The overall outputs of the CSC are gained up by a fixed value of two, thus compensating for the scaled down coefficients. In the preceding example, each coefficient on its own is within the range of 4095 4095  Coefficient  4096 4096 Therefore, all coefficients can be programmed directly and the CSC_SCALE[1:0] bit must be set to 0. Note that, to achieve a coefficient value of 1.0 for any given coefficient, CSC_SCALE must be set high and the coefficient must actually be programmed to a value of 0.5. Otherwise, the largest value is 4095/4096 = 0.9997, which is not exactly 1. Although this value can be interpreted as a 1, it is recommended to use the value of 0.5 and the CSC_SCALE bit for maximum accuracy. For very large coefficient values (for example, 2.58), use a combination of CSC_SCALE[1:0] and equation scaling. Set CSC_SCALE high (2.58/2 = 1.29) and scale the overall equation by slightly more than 1.28 (coefficient falls within the supported range of [−0.999 … +0.999]). CSC in Pass-Through Mode It is possible to configure the CP CSC in a pass-through mode. In this mode, the CP CSC is used but does not alter the data it processes. The CP CSC pass-through mode is obtained using the following settings: 1. 2. 3. Set MAN_CP_CSC_EN to 1’b1. Set CSC_COEFF_SEL[3:0] to 4’b0000. Leave the following registers from the CP map at the default:  CSC_SCALE = 1 (default value)  A4 = A3 = A2 = 0x000 (default value)  B4 = B3 = B1 = 0x000 (default value)  C4 = C2 = C1 = 0x000 (default value)  A1 = B2 = C3 = 0x800 (default value) Note that the DPP CSC is always in pass-through mode unless the ADV7613 is processing an RGB input, outputting this input in the RGB color space and VID_ADJ_EN is enabled. Rev. A | Page 97 of 168 UG-907 ADV7613 Reference Manual COLOR CONTROLS The ADV7613 has a color control feature that can adjust the brightness, contrast, saturation, and hue properties. VID_ADJ_EN, Address 44 (CP), Address 0x3E[7] This bit is the video adjustment enable. This control selects whether or not the color controls feature is enabled. The color controls feature is configured via the CP_CONTRAST[7:0], CP_SATURATION[7:0], CP_BRIGHTNESS[7:0], and CP_HUE[7:0] parameters. The CP CSC must also be enabled for the color controls to be effective. Table 239. VID_ADJ_EN Function Description VID_ADJ_EN 0 (default) 1 Description Disable color controls Enable color controls CP_CONTRAST[7:0], Address 44 (CP), Address 0x3A[7:0] CP_CONTRAST[7:0] is a control to set the contrast. This field is a unsigned value represented in a 1.7 binary format. The MSB represents the integer part of the contrast value, which is either 0 or 1. The seven LSBs represent the fractional part of the contrast value. The fractional part has the range [0 to 0.99]. This control is functional if VID_ADJ_EN is set to 1. Table 240. CP_CONTRAST[7:0] Function Description CP_CONTRAST[7:0] 00000000 10000000 (default) 11111111 Description Contrast set to minimum Default Contrast set to maximum CP_SATURATION[7:0], Address 44 (CP), Address 0x3B[7:0] CP_SATURATION[7:0] is a control to set the saturation. This field is an unsigned value represented in a 1.7 binary format. The MSB represents the integer part of the contrast value, which is either 0 or 1. The seven LSBs represent the fractional part of the saturation value. The fractional part has a [0 to 0.99] range. This control is functional if VID_ADJ_EN is set to 1. Table 241. CP_SATURATION[7:0] Function Description CP_SATURATION[7:0] 00000000 10000000 (default) 11111111 Description Saturation set to minimum Default Saturation set to maximum CP_BRIGHTNESS[7:0], Address 44 (CP), Address 0x3C[7:0] CP_BRIGHTNESS[7:0] is a control to set the brightness. This field is a signed value. The effective brightness value applied to the luma is obtained by multiplying the programmed value CP_BRIGHTNESS with a gain of 4. The brightness applied to the luma has a range of [−512 to +508]. This control is functional if VID_ADJ_EN is set to 1. Table 242. CP_BRIGHTNESS[7:0] Function Description CP_BRIGHTNESS[7:0] 00000000 (default) 01111111 11111111 Description The offset applied to the luma is 0. The offset applied to the luma is 508d. This value corresponds to the brightness setting. The offset applied to the luma is −512d. This value corresponds to the darkest setting. Rev. A | Page 98 of 168 ADV7613 Reference Manual UG-907 CP_HUE[7:0], Address 44 (CP), Address 0x3D[7:0] CP_HUE[7:0] is a control to set the hue. This register a represent an unsigned value which provides hue adjustment. Following control processes, Cb and Cr stream as follows: Cb_out = Cb × cos(hue) + Cr × sin(hue) Cr_out = Cr × cos(hue) − Cb × sin(hue) It allows rotating of the hue by any angle