EVAL-CN0269-SDPZ

Circuit Note CN-0269 Devices Connected/Referenced AD7984 18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN AD8475 Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system AD8065 integration to help solve today’s analog, mixed-signal, ADG5208 and RF design challenges. For more information and/or support, visit www.analog.com/CN0269. ADG5236 Precision, Selectable Gain, Fully Differential Funnel Amp High Performance, 145 MHz FastFET Op Amps High Voltage, Latch-Up Proof, 8-Channel Multiplexers High Voltage Latch-Up Proof, Dual SPDT Switches Ultralow Noise, 4.096 V, LDO XFET Voltage References with Current Sink and Source ADR444 18-Bit, 1.33 MSPS, 16-Channel Data Acquisition System EVALUATION AND DESIGN SUPPORT A single channel can be sampled at up to 1.33 MSPS with 18-bit resolution. A channel-to-channel switching rate of 250 kHz between all input channels provides 16-bit performance. Circuit Evaluation Boards CN-0269 Circuit Evaluation Board (EVAL-CN0269-SDPZ) System Demonstration Platform (EVAL-SDP-CB1Z) Design and Integration Files Schematics, Layout Files, Bill of Materials The signal processing circuit combined with a simple 4-bit updown binary counter provides a simple and cost effective way to realize channel-to-channel switching without an FPGA, CPLD, or high speed processor. The counter can be programmed to count up or count down for sequentially sampling multiple channels, or can be loaded with a fixed binary word for sampling a single channel. CIRCUIT FUNCTION AND BENEFITS The circuit shown in Figure 1 is a high performance industrial signal level multichannel data acquisition circuit that has been optimized for fast channel-to-channel switching. It can process 16-channels of single-ended inputs or 8-channels of differential inputs with up to 18-bit resolution. +5V +12V VDD AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 S1 S2 S3 S4 S5 S6 S7 S8 AI0+ AI1+ AI2+ AI3+ AI4+ AI5+ AI6+ AI7+ –12V VSS GND P4 D AGND +12V –12V EN A0 A1 A2 VDD GND S1A VSS D1 –12V IN1 S2A 1kΩ NC_1 NC_2 NC_3 +12V VDD DIFFERENTIAL VSS GND D NC_4 NC_5 ADG5236 1.25kΩ 2 –IN_0.4* 1kΩ S1B 0.1µF +12V –12V 0Ω VCOM JP3 1 +12V +IN_0.8* 2 +IN_0.4* 1 JP4 1.25kΩ 1kΩ +VS NC 1kΩ 1.25kΩ +OUT 3 –IN_0.8* VCOM 3 IN2 –12V 0.1µF 50V 22µF 6.3V +5V AD8065 S2B AI0– AI1– AI2– AI3– AI4– AI5– AI6– AI7– 0.1µF 50V DGND 1kΩ D2 AI8 AI9 AI10 AI11 AI12 AI13 AI14 AI15 +2.5V +4.096V TP_2 NC_2 VOUT TRIM ADR444 ADG5208 S1 S2 S3 S4 S5 S6 S7 S8 TP_1 VIN NC_1 GND 0.1µF 50V 1.25kΩ –OUT VIO 10kΩ 10Ω 2.2nF REF VDD IN+ 2.2nF IN– VIO SDI SCK SDO CNV 33Ω 33Ω 33Ω TCLKBF DATA TFS GND 10Ω AD7984 –VS AD8475 +3.3V AD8065 CH0 CH1 CH2 CH3 33Ω 33Ω 33Ω EN A0 A1 A2 SPORT 33Ω 33Ω 33Ω Q0 Q1 Q2 Q3 B Y 74LVC1G00 A VCC GND CEP CET TC 15Ω GPIO CP PE U/D PL U/D P0 P1 P2 P3 P0 P1 P2 P3 74LVC169 ADG5208 S_D EN 10563-001 SINGLE ENDED Figure 1. Multichannel Data Acquisition Circuit (Simplified Schematic: All Components, Connections, and Decoupling Not Shown) Rev. 0 Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved. CN-0269 Circuit Note signals by modern low voltage differential input ADCs, the attenuation and level shifting stage is necessary. This circuit is an ideal solution for a multichannel data acquisition card for many industrial applications including process control, and power line monitoring. The AD8475, fully differential, attenuating (funnel) amplifier with integrated precision gain resistors provides precision attenuation (by 0.4× or 0.8×), common-mode level shifting, and singleended-to-differential conversion along with input overvoltage protection. Fast settling time (50 ns to 0.001%), and low noise performance (10 nV/√Hz) make the AD8475 well suited to drive 18-bit differential input ADCs at sampling rates up to 4 MSPS. CIRCUIT DESCRIPTION The circuit shown in Figure 1 is a classic multichannel nonsynchronous data acquisition signal chain consisting of a multiplexer, amplifiers, and an ADC. The architecture allows fast sampling of multiple channels using a single ADC, providing low cost and excellent channel-tochannel matching. The AD7984, 18-bit, PulSAR® ADC selected in this circuit provides 18-bit resolution at 1.33 MSPS when sampling a single channel. However, the settling time of various components in the signal chain limit the overall accuracy when sequentially switching between channels. For example, 16-bit performance is achieved when switching between channels at a 250 kHz rate. Channel-to-channel switching speed is limited by the settling time of the various components following the multiplexer in the signal chain, because the multiplexer can present a full-scale step voltage output to the downstream amplifier and ADC. The components in this circuit have been specifically chosen to minimize the settling time and maximize channel-to-channel switching speed. Timing Analysis When the circuit shown in Figure 1 is operating in the continuous switching mode, all the 16-channel signal-ended or 8-channel differential signal streams are merged into a time-division multiplexed signal by the two stage multiplexer comprised of the ADG5208 and the ADG5236. The multiplexed signal drives the buffer circuit (AD8065) and the attenuation and level shift circuit (AD8475). The output signal of the AD8475 drives the differential input ADC through an RC filter (2.2 nF, 10 Ω). Component Selection The ADG5208 multiplexer switches one of eight inputs to a common output, as determined by the 3-bit binary address lines. The ADG5236 contains two independently selectable single-pole/double throw (SPDT) switches. Two ADG5208 switches, combined with one ADG5236, allow 16 single-ended channels or 8 true differential channels to be connected to the rest of the signal chain using a 4-bit digital control signal. The multiplexed input signal typically consists of large voltage steps when switching between channels. In the worst case, one channel is at negative full scale, while the next channel is at positive full scale. Therefore, the step can be as large as the full range of input signal, in this case, 20 V. It is a tremendous challenge for the analog signal chain to settle to high precision from such a large step signal level in a short time. The timing of the circuit must be carefully examined to determine the amount of settling time available at various sampling rates and the settling time required by the circuits in the signal chain. The 4-bit digital signal is generated by a 4-bit binary up/down counter triggered by the same signal used for the convert (CNV) input to the 18-bit, 1.33 MSPS AD7984 ADC. The AD8065 JFET input op amp has a 145 MHz bandwidth and is configured as a unity-gain buffer to provide excellent settling time performance and extremely high input impedance. The AD8065 also provides very low impedance output to drive the AD8475 funnel amp attenuation stage. Figure 2 shows the basic timing diagram of the system, and this is where the analysis starts. The advantages of fully differential signal chain are good common-mode rejection and reduction in second-order distortion products. In order to process ±10 V industrial level tS CNV tCONV [CH3 TO CH0] VOUT_SW CONVERSION ACQUISITION [0000] ACQUISITION [0001] SETTLING TO CH0 SETTLING TO CH1 tDD tMD tSETTLE Figure 2. Multichannel Data Acquisition Circuit Timing Rev. 0 | Page 2 of 12 10563-002 STATUS tACQ Circuit Note CN-0269 Digital Delay So tMD is calculated using the equation: In the circuit shown in Figure 1, the ADC and multiplexer are both triggered by the rising edge of CNV signal from digital controller. At this point, the SAR ADC has completed the acquisition of the sample and starts the conversion cycle. tMD = tTRANSITION − tSETTLE (90%) The maximum settling time left for analog signal chain at a sampling rate of 𝑓𝑠 can be estimated by the equation: tSETTLE(fs) = 1/fS – tDD − tMD Ideally, the signal chain has one full sampling period to settle to the next channel, but there are delays in the digital circuits that decrease the available settling time. In Figure 2, tDD is the sum of the delay through the NAND gate and the counter CLK-toOUT delay. This digital delay can be found from the data sheet of each component, and is approximately 8 ns total. The time for switch to settle to within a % error can be calculated by the equation below. See the AN-1024 Application Note, “How to Calculate the Settling Time and Sampling Rate of a Multiplexer” for more details. The test circuit for measuring the transition delay with a load of 300 Ω||35 pF is shown in Figure 3. Under this test configuration, the settling time can be estimated by Equation 3. Since the ADG5208 and ADG5236 are switched simultaneously in this circuit, the tMD marked in Figure 2 is equal to the delay generated by the slower one, which is the ADG5208.  % error t SETTLE = – ln   100 The transition time delay of multiplexer is easy to find in the data sheet. However, the transition delay on the data sheet is the delay time between the 50% of the digital input and the 90% point of the digital output as shown in Figure 3. 3V 50% 50% tr < 20ns tf < 20ns VDD VSS VDD VSS   R ON R L     R ON + R L   (C + C L  D  A0 S1 0V VIN tMD A1 50Ω VS1 S2 TO S7 A2 tTRANSITION (2) A good first order approximation for estimating multiplexer settling time is to treat the multiplexer in the on state as a simple RC circuit with time constant of RON × CD. The time shown as tMD in Figure 2 is the delay through the two stage multiplexer measured from the 50% point of the digital input to the point that the analog output signal starts to settle. ADDRESS DRIVE (VIN) (1) tTRANSITION S8 90% ADG5208 2.0V OUTPUT D EN GND VS8 OUTPUT 300Ω 35pF 10563-003 90% Figure 3. ADG5208 Transition Delay Test Circuit Rev. 0 | Page 3 of 12 ) (3) CN-0269 Circuit Note Actually, this digital delay of 147 ns due to the digital control circuit and part of the transition delay from multiplexer can be compensated by delaying the rising edge of the convert signal with respect to the multiplexer update signal by an amount of time equal to tDD + tMD. However, both tDD and tMD are a function of temperature, power supply voltage, and normal variations from part to part. The time margin must be enough to account for the variation and drift. For example, under this configuration with 147 ns digital delay, switching the multiplexer 100 ns to 120 ns ahead of the ADC convert signal (tAHEAD) increases the available settling time by the same amount. For the ADG5208, RON is 160 Ω, and CD is 52 pF. The transition delay of ADG5208 is 160 ns. So, the 90% settling time of the ADG5208 is  10   (160 || 300 Ω )( 52 pF + 35 pF ) = 21 ns t SETTLE ( 90%) = – ln    100  From Equation 1, tMD = tTRANSITION – tSETTLE(90%) = 160 ns – 21 ns = 139 ns Therefore, under this circuit configuration with the ADG5208 and the ADG5236, the total extra time delay due to the digital circuits is The optimized timing is shown in Figure 4, but was not implemented in the actual circuit in order to minimize complexity. tDD + tMD = 8 ns + 139 ns = 147 ns tS tAHEAD tCONV tACQ CONVERSION ACQUISITION CNV STATUS MUX CTRL [0000] VOUT_SW TO CH0 [0001] SETTLING TO CH1 tDD tMD tSETTLE Figure 4. Optimized Timing of Multichannel Data Acquisition Circuit Rev. 0 | Page 4 of 12 10563-004 [CH3:CH0] Circuit Note CN-0269 Settling Time Analysis Settling Time for the Multiplexer Stage When the circuit shown in Figure 1 is operating in the continuous switching mode, all the 16-channel signal-ended or 8-channel differential signal streams are merged into a timedivision multiplexed signal by the two stage multiplexer, the ADG5208 and ADG5236. The signal is then buffered by the AD8065 that has a high impedance, low capacitance input. The equivalent circuit for a CMOS switch can be approximated as an ideal switch in series with a resistor (RON) and in parallel with two capacitors (CS, CD). The multiplexer stage and associated filters can therefore be modeled as shown in Figure 6. PART 3 PART 4 ATTENUATION RC + ADC ADG5208 ADG5236 AD8065 AD8475 AD7984 tS_MUX tS_BUF tS_ATN tS_RC 2 2 CD VSS VSS VSS CIN VSS The RS is the 1 kΩ resistor in series with non-inverting input of the AD8065, and CIN is the input capacitance of AD8065. The input impedance of AD8065 is 1 GΩ||2.2 pF, and the 1 GΩ resistance can be ignored. Then the total settling time is estimated to be the root sum square (rss) of settling time of each stage 2 CS The pre-filter in front of multiplexer is not shown in Figure 1. This pre-filter is used for noise suppression. Also, the RP resistor combined with protection diodes and the TVS provides additional transient and over-voltage protection for hostile environments. The protection components are shown in the complete circuit schematic contained in the CN-0269 Design Support Package. Figure 5. Sub-Stage Block Diagram for Settling Time Analysis t S _ ALL = t S _ MUX + t S _ BUF + t S _ ATN + t S _ RC CS VSS RS CD Note that the ADG5236 model does not show the series switch because it only switches when changing from single-ended to differential mode inputs. 10563-005 PART 2 BUFFER CP VSS RON SW2 AD8065 Figure 6. First-Order Model for Input Pre-Filter, Multiplexer, and AD8065 Input For the purposes of calculating settling time, the circuit can be divided into four parts as shown in Figure 5. MUX VSS RP RON D CS CP VSS AI 2 ADG5236 RON SW1 10563-006 AI 1 Then the low impedance output of AD8065 buffer drives the AD8475 stage that attenuates, level shifts, and performs the single-ended to differential conversion. An RC (10 Ω, 2.2 nF) filter is placed at the input of the AD7984 ADC in order to limit out-of-band noise and attenuate the kickback from the switched capacitor input of the ADC. The −3 dB bandwidth of the filter is 7.2 MHz. (See Front-End Amplifier and RC Filter Design for a Precision SAR Analog-to-Digital Converters, Analog Dialogue 46-12, December 2012). PART 1 ADG5208 PRE-FILTER RP The circuit in Figure 6 was simulated using NI Multisim™ as shown in Figure 7, with the following component values: 2 Pre-filter: RP = 300 Ω; CP = 120 pF; In order to settle to within a specific error band at a sampling rate, fS , the relationship below must be satisfied. ADG5208: RON =160 Ω; CS = 5.5 pF; CD = 52 pF; tS_ALL + tDD + tMD < 1/fS ADG5236: RON =160 Ω; CS = 2.5 pF; CD = 12 pF; Or, fS