SDP User Guide
UG-277
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
SDP-B Controller Board
INTRODUCTION
This user guide describes the EVAL-SDP-CB1Z system
demonstration platform—Blackfin® (SDP-B) controller board
from Analog Devices, Inc. The SDP-B controller board is part
of the Analog Devices system demonstration platform (SDP).
The SDP consists of a series of controller boards, interposer
boards, and daughter boards.
SDP controller boards provide a means of communicating with
the PC from the system under evaluation. Interposer boards
route signals between two connectors. Daughter boards are a
collection of product evaluation boards and Circuits from the
Lab™ reference circuit boards. The SDP-B is used as part of the
evaluation system for many Analog Devices components and
reference circuits. The primary audience for this user guide is a
system engineer who seeks to understand how to set up the
SDP-B board and begin USB communications to the PC.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
The SDP-B board is designed to be used in conjunction with
various Analog Devices component evaluation boards and
Circuits from the Lab reference circuits as part of a customer
evaluation environment. The SDP-B provides USB connectivity
through a USB 2.0 high speed connection to the computer
allowing users to evaluate components on this platform from a
PC application. The SDP-B is based on ADSP-BF527 Blackfin
processor, with the Blackfin processor peripheral communication lines available to the component daughter board through
two identical 120-pin small footprint connectors.
The SDP-B user guide provides instructions for installing the
SDP-B hardware (EVAL-SDP-CB1Z board) and software onto
your computer. The necessary installation files are provided
with the evaluation daughter board package. The Getting
Started section provides software and hardware installation
procedures, PC system requirements, and basic board information. The Hardware Description section provides information
on the EVAL-SDP-CB1Z components. The EVAL-SDP-CB1Z
schematics are provided in the Schematics section.
Rev. B | Page 1 of 24
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SDP User Guide
TABLE OF CONTENTS
Introduction ...................................................................................... 1
USB Installation .............................................................................4
Revision History ............................................................................... 2
Powering Up/Powering Down the SDP .....................................4
Product Overview............................................................................. 3
Hardware Description.......................................................................5
Technical or Customer Support.................................................. 3
LEDs ................................................................................................5
Product Information .................................................................... 3
Connector Details .........................................................................5
Regulatory Compliance ............................................................... 3
Power............................................................................................ 10
Getting Started .................................................................................. 4
Daughter Board Design Guidelines ......................................... 10
Package Contents .......................................................................... 4
Mechanical Specifications ......................................................... 12
PC Configuration ......................................................................... 4
Schematics ....................................................................................... 13
REVISION HISTORY
12/11—Rev. A to Rev. B
Changes to Figure 7 ........................................................................ 14
Changes to Figure 8 ........................................................................ 15
Changes to Figure 9 ........................................................................ 16
Changes to Figure 10 ...................................................................... 17
Changes to Figure 11 ...................................................................... 18
Changes to Figure 12 ...................................................................... 19
Changes to Figure 13 ...................................................................... 20
10/11—Rev. 0 to Rev. A
Change to Product Overview Section............................................ 3
Replaced Hardware Description Section ..................................... 15
Replaced Schematics Section ........................................................ 13
6/11—Revision 0: Initial Version
Rev. B | Page 2 of 24
SDP User Guide
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PRODUCT OVERVIEW
The SDP-B board features
PRODUCT INFORMATION
•
•
•
•
•
•
Product information can be obtained from the Analog Devices
website.
•
•
•
Analog Devices ADSP-BF527 Blackfin processor
Core performance up to 600 MHz
208-ball CSP-BGA package
24 MHz CLKIN oscillator
5 Mb of internal RAM memory
32 Mb flash memory
• Numonyx M29W320EB or
• Numonyx M25P32
SDRAM memory
• Micron MT48LC16M16A2P-6A - 16 Mb x 16 bits
(256 Mb/32 MB)
3 × 120-pin small foot print connectors
• Hirose FX8-120P-SV1(91), 120-pin header
Blackfin processor peripherals exposed
• SPI
• SPORT
• TWI/I2C
• GPIO
• PPI
• Asynchronous parallel
• Timers
Analog Devices Web Site
The Analog Devices website, www.analog.com, provides
information about a broad range of products—analog
integrated circuits, amplifiers, converters, and digital signal
processors.
Note that MyAnalog.com is a free feature of the Analog Devices
website that allows customization of a web page to display only
the latest information about products of interest to you. You can
choose to receive weekly email notifications containing updates
to the web pages that meet your interests, including
documentation errata against all documents. MyAnalog.com
provides access to books, application notes, data sheets, code
examples, and more.
Visit MyAnalog.com to sign up. If you are a registered user, just
log on. Your user name is your email address.
REGULATORY COMPLIANCE
For more information, go to http://www.analog.com/sdp.
TECHNICAL OR CUSTOMER SUPPORT
You can reach Analog Devices customer support in the
following ways:
•
•
•
•
•
Visit the SDP website at
http://www.analog.com/sdp
Email processor questions to
• processor.support@analog.com (worldwide support)
• processor.europe@analog.com (Europe support)
• processor.china@analog.com (China support)
Phone questions to
1-800-ANALOGD
Contact your Analog Devices local sales office or
authorized distributor.
Send questions by mail to
Analog Devices, Inc.
Three Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
The EVAL-SDP-CB1Z is designed to be used solely in a laboratory environment. The board is not intended for use as a
consumer end product or as a portion of a consumer end
product. The board is an open system design, which does not
include a shielded enclosure and therefore may cause interference to other electrical devices in close proximity. This board
should not be used in or near any medical equipment or
RF devices. Store unused boards in the protective shipping
package.
The EVAL-SDP-CB1Z board has been certified to comply with
the essential requirements of the European EMC directive
89/36/EC amended by 93/68/EEC and therefore carries the
CE mark.
Rev. B | Page 3 of 24
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SDP User Guide
GETTING STARTED
Verifying Driver Installation
This section provides specific information to assist you with
using the SDP-B board as part of your evaluation system.
Before using the SDP-B board, verify the driver software has
installed properly.
The following topics are covered:
•
•
•
•
Open the Windows Device Manager and verify the SDP board
appears under ADI Development Tools as shown in Figure 1.
Package contents
PC configuration
USB installation
Powering up/powering down the SDP
PACKAGE CONTENTS
Your EVAL-SDP-CB1Z board package contains the following:
•
•
EVAL-SDP-CB1Z board
1 m USB Standard-A to Mini-B cable
Contact the vendor where you purchased your SDP-B board or
contact Analog Devices if anything is missing.
PC CONFIGURATION
For correct operation of the SDP board, your computer must
have the following minimum configuration:
•
•
Windows XP Service Pack 2 or Windows Vista®
USB 2.0 port
09865-001
When removing the SDP-B board from the package, handle the
board carefully to avoid the discharge of static electricity, which
can damage some components.
USB INSTALLATION
Figure 1. Device Manager
Perform the following tasks to safely install the SDP-B board
onto the computer. There are two stages in the software
application installation procedure. The first stage installs the
application software. The second stage installs the .NET
Framework 3.5 and the necessary drivers.
POWERING UP/POWERING DOWN THE SDP
The following sections describe how to safely power up and
power down the SDP-B.
Powering Up the SDP-B Board
Installing the Software
1.
2.
Run the application install provided. The first stage installs
the applications GUI and the necessary support files onto
the computer
Immediately following the application install, the .NET
Framework 3.5 and the driver package for the SDP board is
installed. If the .NET Framework 3.5 is already preinstalled
on the computer in question, this stage is skipped and Step
2 will consist of a driver package installation only
Connecting the SDP-B Board to the PC
Attach the SDP-B board to a USB 2.0 port on the computer via
the Standard-A to Mini-B cable provided.
1.
2.
3.
Connect the SDP-B board to the daughter evaluation board
through the 120-pin mating connectors.
Power the daughter board.
Connect the USB port on the computer to the SDP-B
board.
Powering Down the SDP-B Board
1.
2.
3.
Rev. B | Page 4 of 24
Power down the daughter evaluation board.
Disconnect the USB port on the computer from the SDP-B
board.
Disconnect the SDP-B board from the daughter evaluation
board.
SDP User Guide
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HARDWARE DESCRIPTION
This section describes the hardware design of the EVAL-SDPCB1Z board.
The following topics are covered:
•
•
•
•
•
LEDs—This section describes the SDP on-board LEDs.
Connector Details—This section details the pin
assignments on the 120-pin connectors.
Power—This section lists power requirements of the SDP
and identifies connector power inputs and output pins.
Daughter board design guidelines—This section provides
guidelines on how to design daughter boards for use with
the SDP.
Mechanical specifications—This section provides
dimensional information.
LEDS
There are two LEDs located on the SDP-B board (see Figure 2).
POWER LED
The green power LED indicates that the SDP-B board is
powered. This is not an indication of USB connectivity between
the SDP-B and the PC.
STATUS LED
The orange status LED is an LED used as a diagnostic tool for
evaluation application developers. When there are two or more
identical SDP controller board and daughter board combinations connected to the PC simultaneously, the status LED
flashes during the connect routine to help the user identify
which board they will communicate with.
CONNECTOR DETAILS
The SDP-B board contains three Hirose FX8-120P-SV1(91),
120-pin header connectors. Connector A and Connector B share
identical pinouts and through these connectors, the peripheral
communication interfaces of ADSP-BF527 Blackfin processor are
exposed. The exposed peripherals are
•
•
•
•
•
•
•
•
SPI
SPORT
I2C/TWI
GPIO
Asynchronous parallel
PPI
UART
Timers
CON A
In addition, included on the connector specification are input
and output power pins, ground pins, and pins reserved for
future use. For further details on the peripheral interfaces,
including timing diagrams, see the ADSP-BF52x Blackfin
Processor Hardware Reference.
LED
Connector C exposes the entire Blackfin memory space, but is
not used as part of the SDP platform.
POWER
Connector Pin Assignments
LED
CON B
STATUS
Figure 2. SDP-B Board LEDs
09865-002
CON C
The connector pin assignments for Connector A and
Connector B have been defined independently of the any
internal pin sharing that occurs on the Blackfin processor.
Table 1 lists the connector pins and identifies the functionality
assigned to each connector pin for Connector A and
Connector B on the SDP-B board.
Rev. B | Page 5 of 24
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SDP User Guide
Table 1. 120-Pin Connector Pin Assignments
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Pin Name
VIN
NC
GND
GND
USB_VBUS
GND
PAR_D23
PAR_D21
PAR_D19
PAR_D17
GND
PAR_D14
PAR_D13
PAR_D11
PAR_D9
PAR_D7
GND
PAR_D5
PAR_D3
PAR_D1
PAR_RD
PAR_CS
GND
PAR_A3
PAR_A1
PAR_FS3
PAR_FS1
GND
SPORT_TDV0
SPORT_TDV1
SPORT_DR1
SPORT_DT1
SPI_D2
SPI_D3
SERIAL_INT
GND
SPI_SEL_B
SPI_SEL_C
SPI_SEL1/SPI_SS
40
41
42
43
44
45
46
47
48
49
50
GND
SDA_1
SCL_1
GPIO0
GPIO2
GPIO4
GND
GPIO6
TMR_A
TMR_C
NC
Description
Power to SDP Board. Requires 200 mA at 5 V.
No Connect. Leave this pin unconnected. Do not ground.
Connect to ground plane of board.
Connect to ground plane of board.
Connected directly to the USB +5 V supply.
Connect to ground plane of board.
Parallel Data Bus Bit 23. (No connect.)1
Parallel Data Bus Bit 21. (No connect.)1
Parallel Data Bus Bit 19. (No connect.)1
Parallel Data Bus Bit 17. (No connect.)1
Connect to ground plane of board.
Parallel Data Bus Bit 14.
Parallel Data Bus Bit 13.
Parallel Data Bus Bit 11.
Parallel Data Bus Bit 9.
Parallel Data Bus Bit 7.
Connect to ground plane of board.
Parallel Data Bus Bit 5.
Parallel Data Bus Bit 3.
Parallel Data Bus Bit 1.
Asynchronous Parallel Read Strobe.
Asynchronous Parallel Chip Select.
Connect to ground plane of board.
Parallel Address Bus Bit 3.
Parallel Address Bus Bit 1.
Synchronous (PPI) Parallel Frame Sync 3.
Synchronous (PPI) Parallel Frame Sync 1.
Connect to ground plane of board.
SPI Data Line 3. (No connect.)1
SPI Data Line 2. (No connect.)1
SPORT Data Receive 1. Secondary SPORT data into processor.
SPORT Data Transmit 1. Secondary SPORT data from processor.
SPORT Data Line. (No connect.)1
SPORT Data Line. (No connect.)1
Serial Interrupt. Used to trigger a nonperiodic serial event.
Connect to ground plane of board.
SPI Chip Select B. Use this to control a second device on the SPI bus.
SPI Chip Select C. Use this for a third device on the SPI bus.
SPI Chip Select 1.2 Used to connect to SPI boot flash, if required. Also used as chip select when Blackfin
processor is operating as SPI slave.
Connect to ground plane of board.
I2C Data 1.
I2C Data 1.2
General-Purpose Input/Output.
General-Purpose Input/Output.
General-Purpose Input/Output.
Connect to ground plane of board.
General-Purpose Input/Output.2
Timer A Flag Pin. Use as first timer, if required.
Timer C Flag Pin.1 (No connect.)
No Connect. Leave this pin unconnected. Do not ground.
Rev. B | Page 6 of 24
SDP User Guide
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Pin Name
NC
GND
NC
NC
NC
EEPROM_A0
RESET_OUT
GND
UART_RX
RESET_IN
BMODE1
UART_TX
GND
SLEEP
WAKE
NC
NC
NC
GND
NC
CLKOUT
TMR_D
TMR_B
GPIO7
GND
GPIO5
GPIO3
GPIO1
SCL_0
SDA_0
GND
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_SEL_A
GND
SPORT_TSCLK
SPORT_DT0
SPORT_TFS
SPORT_RFS
SPORT_DR0
SPORT_RSCLK
GND
PAR_CLK
PAR_FS2
PAR_A0
PAR_A2
GND
PAR_INT
PAR_WR
PAR_D0
PAR_D2
PAR_D4
UG-277
Description
No Connect. Leave this pin unconnected. Do not ground.
Connect to ground plane of board.
No Connect. Leave this pin unconnected. Do not ground.
No Connect. Leave this pin unconnected. Do not ground.
No Connect. Leave this pin unconnected. Do not ground.
EEPROM A0. Connect to A0 address line of the EEPROM.
Active low reset signal from processor board.
Connect to ground plane of board.
UART Receive Data.2
Active low pin to reset controller board.
Boot Mode 1. Pull up with 10 kΩ resistor to set SDP to boot from SPI Flash. Enabled on Connector A only.
UART Transmit Data2.
Connect to ground plane of board.
Active low sleep from processor board.
External wake up to processor board.
No Connect. Leave this pin unconnected. Do not ground.
No Connect. Leave this pin unconnected. Do not ground.
No Connect. Leave this pin unconnected. Do not ground.
Connect to ground plane of board.
No Connect. Leave this pin unconnected. Do not ground.
CLKOUT from processor.
Timer D Flag Pin.2
Timer B Flag Pin. Use as second timer, if required.
General-Purpose Input/Output.
Connect to ground plane of board.
General-Purpose Input/Output.
General-Purpose Input/Output.
General-Purpose Input/Output.
I2C Clock 0. Daughter board EEPROM must be connected to this bus.
I2C Data 0. Daughter board EEPROM must be connected to this bus.
Connect to ground plane of board.
SPI Clock.
SPI Master In, Slave Out Data.
SPI Master Out, Slave In Data.
SPI Chip Select A. Use this to control the first device on the SPI bus.
Connect to ground plane of board.
SPORT Transmit Clock.
SPORT Data Transmit 0. Primary SPORT data from processor.
SPORT Transmit Frame Sync.
SPORT Receive Frame Sync.
SPORT Data Receive 0. Primary SPORT data into processor.
SPORT Receive Clock.
Connect to ground plane of board.
Clock for Synchronous Parallel Interface (PPI).
Synchronous (PPI) Parallel Frame Sync 2.
Parallel Address Bus Bit 0.
Parallel Address Bus Bit 2.
Connect to ground plane of board.
Parallel Interrupt. Used to trigger a nonperiodic parallel event.
Asynchronous Parallel Write Strobe.
Parallel Data Bus Bit 0.
Parallel Data Bus Bit 2.
Parallel Data Bus Bit 4.
Rev. B | Page 7 of 24
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Pin No.
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
1
2
Pin Name
GND
PAR_D6
PAR_D8
PAR_D10
PAR_D12
GND
PAR_D15
PAR_D16
PAR_D18
PAR_D20
PAR_D22
GND
VIO (+3.3 V)
GND
GND
NC
NC
SDP User Guide
Description
Connect to ground plane of board.
Parallel Data Bus Bit 6.
Parallel Data Bus Bit 8.
Parallel Data Bus Bit 10.
Parallel Data Bus Bit 12.
Connect to ground plane of board.
Parallel Data Bus Bit 15.
Parallel Data Bus Bit 16.1 (No connect.)1
Parallel Data Bus Bit 18.1 (No connect.)1
Parallel Data Bus Bit 20.1 (No connect.)1
Parallel Data Bus Bit 22. (No connect.)1
Connect to ground plane of board.
+3.3 V Output. 20 mA maximum current available to power IO voltage on daughter board.
Connect to ground plane of board.
Connect to ground plane of board.
No Connect. Leave this pin unconnected. Do not ground.
No Connect. Leave this pin unconnected. Do not ground.
Functionality not implemented on the SDP board.
Shared across both connectors.
Each interface provided by the SDP-B is available on unique pins of the SDP-B 120-pin connector. The connector pin numbering scheme
is outlined in Figure 3.
Rev. B | Page 8 of 24
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60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESET_IN
UART_RX
GND
RESET_OUT
SDP
EEPROM_A0
STANDARD
NC
CONNECTOR
NC
NC
GND
NC
NC
TMR_C *
TIMERS
TMR_A
GPIO6
GND
GENERAL
GPIO4
INPUT/OUTPUT
GPIO2
GPIO0
SCL_1
I2C
SDA_1
GND
SPI_SEL1/SPI_SS
SPI_SEL_C
SPI
SPI_SEL_B
BMODE1
UART_TX
GND
SLEEP
WAKE
NC
NC
NC
GND
NC
NC
TMR_D
TMR_B
GPIO7
GND
GPIO5
GPIO3
GPIO1
SCL_0
SDA_0
GND
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_SEL_A
GND
GND
SERIAL_INT
SPORT_TSCLK
SPI_D3 *
SPORT_DT0
SPI_D2 *
SPORT
SPORT_TFS
SPORT_DT1
SPORT_RFS
SPORT_DR1
SPORT_DR0
SPORT_TDV1 *
SPORT_RSCLK
SPORT_TDV0 *
GND
GND
PAR_CLK
PAR_FS1
PAR_FS2
PAR_FS3
PAR_A0
PAR_A1
PAR_A2
PAR_A3
GND
GND
PAR_INT
PAR_CS
PAR_WR
PAR_RD
PAR_D0
PAR_D1
PARALLEL
PAR_D2
PAR_D3
PORT
PAR_D4
PAR_D5
GND
GND
PAR_D6
PAR_D7
PAR_D8
PAR_D9
PAR_D10
PAR_D11
PAR_D12
PAR_D13
GND
PAR_D14
PAR_D15
GND
* PAR_D16
PAR_D17 *
* PAR_D18
PAR_D19 *
* PAR_D20
PAR_D21 *
* PAR_D22
PAR_D23 *
GND
GND
VIO(+3.3V)
USB_VBUS
GND
GND
GND
GND
NC
NC
*NC ON BLACKFIN SDP
NC
VIN
Figure 3. 120-Pin Connector Outline
Rev. B | Page 9 of 24
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
09865-003
SDP User Guide
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SDP User Guide
Pin Sharing
POWER
Two types of pin sharing occur on the SDP-B board and must
be considered when using two or more of the connector’s
peripheral interfaces between a daughter board and the SDP
board. The first type is pin sharing that occurs internally in the
Blackfin processor. The second type is pin sharing that occurs
when a single Blackfin processor output pin is shared across
both Connector A and Connector B.
The SDP-B board requires that any daughter board connected
to the SDP-B board provides the SDP-B board with 5 V at 200
mA. This supply should be made available on Pin 1 (VIN) of
the 120-pin connector. This supply is required to power the
Blackfin processor, the memory, and the other components on
the SDP-B board. The SDP board also provides 3.3 V at 20 mA
on Pin 116 (VIO_3.3) to connected daughter boards as the VIO
voltage for the daughter board. Pin 5 (USB_VBUS) is connected
to the +5 V line of the USB connector, providing 5 V ±10% as
an output of the SDP board.
Internal Blackfin processor pin sharing can restrict the
simultaneous availability of peripheral interfaces on a single
connector or across both connectors. The Blackfin processor's
internal design has multiple signals physically sharing each
single output pin. As mentioned previously, the pins on the 120pin connector were defined independently of this pin sharing.
This has the effect of limiting the peripherals, which can be
used simultaneously on the SDP. A system designer must
consult the ADSP-BF52x Blackfin Processor Hardware
Reference for the ADSP-BF527 processor to ensure the selected
peripherals are available simultaneously and their signals do not
share Blackfin processor output pins. An example of this
sharing is that the SPORT and PPI peripherals physically share
the same Blackfin processor pins. Therefore, these two
interfaces cannot be utilized in a single application. Pin sharing
also occurs from certain Blackfin processor output pins to both
Connector A and Connector B. The following signals are
connected from a single Blackfin processor output pin to both
Connector A and Connector B:
•
•
•
•
•
I2C Bus 1, Pin 41 and Pin 42
SCL 0 on I2C Bus 0, Pin 79
GPIO 6 and GPIO 7, Pin 47 and Pin 67
Timer D, Pin 72
UART, Pin 59 and Pin 62
DAUGHTER BOARD DESIGN GUIDELINES
The daughter board design guidelines specify the layout,
connector position, keep out areas, and dimensions of potential
daughter boards. This guidance is to ensure that a daughter
board can connect off either Connector A or Connector B of
the SDP-B board. Following these guidelines ensures that both
connectors on the SDP can have any one of the catalogue of
daughter boards physically attached to the connectors
simultaneously.
Connector Location
The daughter board connector and securing screw holes are to
be located in the top left hand corner. This arrangement can
be seen for Daughter Board A in Figure 4. Note that Daughter
Board B is the same as Daughter Board A rotated clockwise
through 90°. The exact location of the connector from the
board's edge is important in order to allow both boards connect
at the same time. As seen in Figure 4, if either board exceeds
these dimensions, it is not possible to connect the other. Every
effort was made to extend the 5.9 mm dimension as large as
possible in order to allow space for vias between the connector
and the edge of the board. These are absolute maximum
dimensions and should not be exceeded.
Rev. B | Page 10 of 24
SDP User Guide
UG-277
5.9mm
3.3mm
DAUGHTERBOARD B
3.3mm
5.9mm
09865-004
DAUGHTERBOARD A
Figure 4. Maximum Board Dimensions for Connector Placement
The full specification drawing for the connector location on the daughter board can be seen in Figure 5.
1.75mm
5.90mm
NO RIGHT-ANGLED CONNECTORS ALLOWED ALONG THIS EDGE
ORIGIN (0,0)
3.30mm
x = 5.9mm, y = –3.3mm
5.15mm
60
61
D3.10mm
x = 5.95mm, y = –28.55mm (CENTER OF CONNECTOR)
50.50mm
1
120
EVAL-xxxxx-DB
Rev. D
x = 5.95mm, y = –53.8mm
PLACEMENT KEEPOUT FOR COMPONENTS
OVER 3mm IN HEIGHT
(EXTENDS DOWN ENTIRE HEIGHT OF LEFT HAND SIDE OF PCB)
12.65mm
Figure 5. Connector Placement on Compatible Daughter Boards
Rev. B | Page 11 of 24
09865-005
D3.10mm
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SDP User Guide
The mating daughter board 120-pin connector is the Hirose
FX8-120S-SV(21), 120-pin receptacle, FEC 132-4660, Digi-Key
H1219-ND. Consult the connector's data sheet for full details
on the connector. Note that Pin 1 to Pin 60 are placed on the
left side of the connector and Pin 61 to Pin 120 are placed on
the right side of the connector.
on the top and left edges of the daughter boards and (if
required) should be placed on the right or bottom edges. The
phrase "right angle connector" is used to describe any connector
that requires the connection to protrude over the edge of the
board (for example, right angle SMB or screw terminal)
MECHANICAL SPECIFICATIONS
Keep Out Area
The mechanical specifications of the SDP-B board are 2.75" ×
2.25" (69.85 mm × 27.15 mm). The height of the 120-pin connectors from the bottom of the board is approximately 0.152"
(3.86 mm). The tallest component on the top is approximately
0.125" (3.175 mm), and the tallest components on the bottoms
are the connectors at approximately 0.152" (3.86 mm). Refer to
Figure 6.
In order to allow the greatest flexibility for future controller
boards, a keep out area is established for components higher
that 3 mm. The keep out area is 12.65 mm wide and extends
down the entire left side of the daughter board.
Restriction on Right Angle Connectors
Due to the close proximity of the edges of the A and B daughter
boards (seen in Figure 4) right angle connectors are not allowed
CON A
2.75”
69.85mm
LED
2.25”
57.15mm
POWER
CON C
LED
CON B
STATUS
0.125”/3.17mm
CON B
A
CON A
0.152”/8.86mm
0.21875”/5.54mm
CON B
Figure 6. SDP-B Board Mechanical Specifications
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CON C
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SCHEMATICS
This section provides the schematic drawings for the EVAL-SDP-CB1Z board. The schematic pages include
•
•
•
•
•
•
•
SDP-B—Power
SDP-B—Memory
SDP-B—Clocks_USB
SDP-B—Blackfin_I/O
SDP-B—Connector A
SDP-B—Connector B
SDP-B—Connector C
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Figure 7. SDP-B —Power
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Figure 8. SDP-B —Memory
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Figure 9. SDP-B —Clocks_USB
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Figure 10. SDP-B —Blackfin_I/O
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Figure 11. SDP-B —Connector A
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Figure 12. SDP-B —Connector B
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Figure 13. SDP-B —Connector C
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NOTES
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NOTES
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NOTES
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NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
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AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
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registered trademarks are the property of their respective owners.
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