31 W, Filterless, Class-D Digital Input
Audio Amplifier
SSM3515
Data Sheet
FEATURES
GENERAL DESCRIPTION
Filterless digital input, mono Class-D amplifier
Operates from a single 4.5 V to 17 V supply
31.3 W output power, 17 V supply, and 4 Ω load at 1% THD + N
107 dB A-weighted signal-to-noise ratio
93.3% efficiency into 8 Ω load at 12 V
I2C control with up to 4 pin selectable slots/addresses
Supports multiple serial data formats up to TDM16
Digital interface supports sample rates from 8 kHz to 192 kHz
Flexible digital and analog gain adjustment
Flexible supply monitoring AGC function
6.55 mA quiescent current with single 17 V PVDD supply
Short-circuit and thermal protection, thermal warning
20-ball, 1.8 mm × 2.2 mm, 0.4 mm pitch WLCSP
Pop and click suppression
User selectable ultralow EMI emissions mode
Power-on reset
The SSM3515 is a fully integrated, high efficiency, mono Class-D
audio amplifier with digital inputs. The application circuit
requires a minimum of external components and can operate
from a single 4.5 V to 17 V supply. It can deliver 8.4 W of output
power into an 8 Ω load or 15.8 W into an 4 Ω load from a 12 V
power supply, or 31.3 W into an 4 Ω load from a 17 V power
supply, all with 1% THD + N.
APPLICATIONS
The digital input eliminates the need for an external digital-toanalog converter (DAC). The SSM3515 has a micropower
shutdown mode with a typical shutdown current of 39 nA at
the 12 V PVDD supply. The device also includes pop and click
suppression circuitry that minimizes voltage glitches at the
output during turn on and turn off.
The SSM3515 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. This scheme
provides high efficiency even at low output power. It operates
with 92% efficiency at 7 W into an 8 Ω load or 88% efficiency at
15 W into 4 Ω from a 12 V supply.
Spread spectrum pulse density modulation provides lower EMI
radiated emissions compared with other Class-D architectures,
particularly above 100 MHz.
Notebooks
Portable electronics
Home audio
The SSM3515 operates with or without an I2C control interface.
The SSM3515 is specified over the commercial temperature range
(−40C to +85C). It has built in thermal shutdown and output
short-circuit protection. It is available in a halide-free, 20-ball,
1.8 mm × 2.2 mm wafer-level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
1.8V
5V
VREG50/AVDD
SCL
SDA
VREG18/DVDD
AGND
I2C
TDM
I2S
INPUT
ADDR
BST+
BCLK
FSYNC
REG_EN
VOLUME
DAC
Σ-∆
CLASS-D
MODULATOR
SDATA
FULL
BRIDGE
POWER
STAGE
OUT+
OUT–
BST–
SSM3515
13327-001
PVDD PGND
Figure 1.
Rev. A
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SSM3515
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
EMI Noise.................................................................................... 24
Applications ....................................................................................... 1
Output Modulation Description .............................................. 24
General Description ......................................................................... 1
Faults and Limiter Status Reporting ........................................ 25
Functional Block Diagram .............................................................. 1
VBAT Sensing ............................................................................. 25
Revision History ............................................................................... 2
Limiter and Battery Tracking Threshold Control .................. 25
Specifications..................................................................................... 3
Layout .......................................................................................... 28
Digital Timing Characteristics ................................................... 6
Bootstrap Capacitors.................................................................. 28
Absolute Maximum Ratings............................................................ 8
Power Supply Decoupling ......................................................... 28
Thermal Resistance ...................................................................... 8
Register Summary .......................................................................... 29
ESD Caution .................................................................................. 8
Register Details ............................................................................... 30
Pin Configuration and Function Descriptions ............................. 9
Power Control Register ............................................................. 30
Typical Performance Characteristics ........................................... 10
Gain and Edge Control Register............................................... 30
Theory of Operation ...................................................................... 19
DAC Control Register................................................................ 31
Overview...................................................................................... 19
DAC Volume Control Register ................................................. 32
Power Supplies ............................................................................ 19
SAI Control 1 Register ............................................................... 33
Power-Up Sequence ................................................................... 19
SAI Control 2 Register ............................................................... 34
Power-Down Operation ............................................................ 19
Battery Voltage Output Register ............................................... 35
REG_EN Pin Setup and Control .............................................. 19
Limiter Control 1 Register ........................................................ 35
ADDR Pin Setup and Control .................................................. 20
Limiter Control 2 Register ........................................................ 36
Clocking ....................................................................................... 20
Limiter Control 3 Register ........................................................ 37
Digital Audio Serial Interface ....................................................... 21
Status Register ............................................................................. 37
Stereo (I S/Left Justified) Operating Mode ............................. 21
Fault Control Register ................................................................ 38
TDM Operating Mode ............................................................... 21
Typical Application Circuit ........................................................... 40
I C Control .................................................................................. 21
Outline Dimensions ....................................................................... 41
Analog and Digital Gain............................................................ 24
Ordering Guide .......................................................................... 41
2
2
Pop and Click Suppression ........................................................ 24
REVISION HISTORY
1/2017—Rev. 0 to Rev. A
Changes to Figure 2 and Table 5 ..................................................... 6
6/2015—Revision 0: Initial Version
Rev. A| Page 2 of 41
Data Sheet
SSM3515
SPECIFICATIONS
PVDD = 12 V, VREG50/AVDD = 5 V (internal), VREG18/DVDD = 1.8 V (external), RL = 8 Ω + 33 μH, BCLK = 3.072 MHz and FSYNC =
48 kHz, TA = −40°C to +85°C, unless otherwise noted. The measurements are with a 20 kHz AES17 low-pass filter. The other load
impedances used are 4 Ω + 15 μH and 3 Ω +10 μH. Measurements are with a 20 kHz AES17 low-pass filter, unless otherwise noted.
The sine wave output powers above 20 W in 4 Ω cannot be continuous and may invoke the thermal limit indicator based on the power
dissipation capability of the board.
Table 1.
Parameter
DEVICE CHARACTERISTICS
Output Power/Channel
RL = 8 Ω
Symbol
Test Conditions/Comments
POUT
f = 1 kHz
THD + N = 1%, PVDD = 17 V
THD + N = 1%, PVDD = 12 V
THD + N = 1%, PVDD = 7 V
THD + N = 1%, PVDD = 5 V
THD + N = 10%, PVDD = 17 V
THD + N = 10%, PVDD = 12 V
THD + N = 10%, PVDD = 7 V
THD + N = 10%, PVDD = 5 V
THD + N = 1%, PVDD = 17 V
THD + N = 1%, PVDD = 12 V
THD + N = 1%, PVDD = 7 V
THD + N = 1%, PVDD = 5 V
THD + N = 10%, PVDD = 17 V
THD + N = 10%, PVDD = 12 V
THD + N = 10%, PVDD = 7 V
THD + N = 10%, PVDD = 5 V
POUT = 9 W, RL = 8 Ω, PVDD = 12 V
POUT = 9 W, RL = 8 Ω, PVDD = 12 V (low EMI mode)
POUT = 30 W, RL = 4 Ω, PVDD = 17 V
POUT = 30 W, RL = 4 Ω, PVDD = 17 V (low EMI mode)
POUT = 5 W into RL = 8 Ω, f = 1 kHz, PVDD = 16 V
RL = 4 Ω
Efficiency
η
Total Harmonic
Distortion + Noise
Load Resistance
Load Inductance
Output FET On Resistance
Overcurrent Protection
Trip Point
Average Switching
Frequency
Differential Output DC
Offset Voltage
THD + N
POWER SUPPLIES
Supply Voltage Range
AC Power Supply
Rejection Ratio
GAIN CONTROL
Output Voltage Peak
Min
3
5
RON
I OC
Typ
Max
16
8.4
2.8
1.4
19.7
10.5
3.5
1.8
31.3
15.8
5.4
2.8
39.3
19.7
6.7
3.4
93.3
93.2
88
87.8
0.004
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
%
%
%
%
%
10
110
Ω
μH
mΩ
A peak
300
kHz
5.8
fSW
VOOS
Gain = 12.6 V
PVDD
VREG50/AVDD
VREG18/DVDD
PSRRAC
Guaranteed from PSRR test
Internal
Internal or external
VRIPPLE = 1 V rms at 1 kHz
Measured with 0 dBFS input at 1 kHz
Analog gain setting = 8.4 V/V with PVDD = 17 V
Analog gain setting = 12.6 V/V with PVDD = 17 V
Analog gain setting = 14.0 V/V with PVDD = 17 V
Analog gain setting = 15.0 V/V with PVDD = 17 V
Rev. A| Page 3 of 41
4.5
4.5
1.62
Unit
±1
±5.0
mV
5.0
1.80
87
17
5.5
1.98
73
V
V
V
dB
8.4
12.6
14
15
V peak
V peak
V peak
V peak
SSM3515
Parameter
SHUTDOWN CONTROL 1
Turn On Time, Volume
Ramp Disabled
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
Turn On Time, Volume
Ramp Enabled
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
Turn Off Time, Volume
Ramp Disabled
Turn Off Time, Volume
Ramp Enabled
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
Output Impedance
NOISE PERFORMANCE 2
Output Voltage Noise
Signal-to-Noise Ratio
PVDD ADC PERFORMANCE
PVDD Sense Full-Scale
Range
PVDD Sense Absolute
Accuracy
Resolution
DIE TEMPERATURE
Overtemperature
Warning
Overtemperature
Protection
1
2
Data Sheet
Symbol
Test Conditions/Comments
t WU
Time from SPWDN = 0 to output switching,
DAC_HV = 1 or DAC_MUTE = 1, t WU = 4 FSYNC
cycles to 7 FSYNC cycles + 7.68 ms
t WUR
t SD
t SDR
Time from SPWDN = 0 to full volume output
switching, DAC_HV = 0 and DAC_MUTE = 0,
VOL = 0x40
t WUR = t WU + 15.83 ms
t WUR = t WU + 15.83 ms
t WUR = t WU + 15.83 ms
t WUR = t WU + 7.92 ms
t WUR = t WU + 0.99 ms
Time from SPWDN = 1 to full power-down,
DAC_HV = 1 or DAC_MUTE = 1
Time from SPWDN = 1 to full power-down,
DAC_HV = 0 and DAC_MUTE = 0, VOL = 0x40
Min
Max
Unit
8.01
7.84
7.76
7.72
7.70
8.27
7.98
7.83
7.76
7.72
ms
ms
ms
ms
ms
23.84
23.67
23.59
15.64
8.69
24.10
23.81
23.66
15.68
8.71
ms
ms
ms
ms
ms
µs
100
t SDR = t SD + 15.83 ms
t SDR = t SD + 15.83 ms
t SDR = t SD + 15.83 ms
t SDR = t SD + 7.92 ms
t SDR = t SD + 0.99 ms
ZOUT
en
SNR
Typ
15.932
15.932
15.932
8.016
1.09
ms
ms
ms
ms
ms
kΩ
37.5
48
107
107
µV rms
µV rms
dB
dB
100
f = 20 Hz to 20 kHz, A-weighted, PVDD = 12 V
f = 20 Hz to 20 kHz, A-weighted, PVDD = 17 V
POUT = 8.2 W, RL = 8 Ω, A-weighted, PVDD = 12 V
POUT = 31 W, RL = 4 Ω, A-weighted, PVDD = 17 V
PVDD with full-scale ADC out
3.8
16.2
V
PVDD = 15 V
−8
+8
LSB
PVDD = 5 V
Unsigned 8-bit output with 3.8 V offset
−6
+6
8
LSB
Bits
117
°C
145
°C
Guaranteed by design.
Noise performance is based on the bench data for TA = −40°C to +85°C.
Rev. A| Page 4 of 41
Data Sheet
SSM3515
Software master power-down indicates that the clocks are turned off. Auto power-down indicates that there is no dither or zero input
signal with clocks on; the device enters soft power-down after 2048 cycles of zero input values. Quiescent indicates triangular dither with
zero input signal. All specifications are typical, with a 48 kHz sample rate, unless otherwise noted.
Table 2. Power Supply Current Consumption 1
Edge Rate
Control
Mode
REG_EN Pin
Normal
Low
PVDD
Low EMI
Low
PVDD
1
Test Conditions
PVDD
Software master
power-down
Auto power-down
Quiescent
Software master
power-down
Auto power-down
Quiescent
Software master
power-down
Auto power-down
Quiescent
Software master
power-down
Auto power-down
Quiescent
5V
0.01
No Load
IPVDD
12 V 17 V
0.03
0.03
IREG18
1.8 V
7
5V
0.01
4 Ω + 15 µH
IPVDD
12 V 17 V
0.03
0.03
IREG18
1.8 V
7
0.01
4.10
0.01
0.03
5.00
0.03
0.03
5.60
0.03
310
4.64
0.01
310
5.60
0.03
0.01
4.00
0.01
310
4.60
5V
0.01
8 Ω + 33 µH
IPVDD
12 V 17 V
0.03
0.03
IREG18
1.8 V
7
μA
54
0.48
N/A
0.01
4.10
0.01
0.03
5.12
0.03
0.03
5.90
0.03
54
0.48
N/A
0.01
4.10
0.01
0.03
5.10
0.03
0.03
5.80
0.03
54
0.48
N/A
μA
mA
μA
316
6.26
0.03
N/A
N/A
7
310
4.74
0.01
310
5.85
0.03
316
6.55
0.03
N/A
N/A
7
310
4.74
0.01
310
5.85
0.03
316
6.55
0.03
N/A
N/A
7
μA
mA
μA
0.03
4.95
0.03
0.03
5.54
0.03
54
0.48
N/A
0.01
4.70
0.01
0.03
3.99
0.03
0.03
5.59
0.03
54
0.48
N/A
0.01
4.02
0.01
0.03
4.98
0.03
0.03
5.63
0.03
54
0.48
N/A
μA
mA
μA
310
5.60
316
6.17
N/A
N/A
310
4.60
310
5.65
316
6.35
N/A
N/A
310
4.60
310
5.60
316
6.40
N/A
N/A
μA
mA
Min
Typ
Max
Unit
27
30
30
38
39
39
7
95
100
152
27
nA
nA
nA
μA
Unit
N/A means not applicable.
Table 3. Power-Down Current
Parameter
POWER-DOWN CURRENT
Symbol
I PVDD
I DVDD
Test Conditions/Comments
VREG18/DVDD = 1.8 V external, software master power-down, no BCLK/FSYNC
PVDD = 5 V
PVDD = 12 V
PVDD = 17 V
VREG18/DVDD = 1.8 V external
Table 4. Digital Input/Output
Parameter
INPUT VOLTAGE 1
High (VIH)
BCLK, FSYNC, SCL, SDA
SDATA, ADDR
Low (VIL)
BCLK, FSYNC, SDATA, SCL, SDA
ADDR
INPUT LEAKAGE
High (I IH)
Low (I IL)
INPUT CAPACITANCE
OUTPUT VOLTAGE (SDATA)
High (VOH)
Low (VOL)
OUTPUT DRIVE STRENGTH1
SDA
SDATA
BCLK Frequency (BCLK)
Sample Rate (FSYNC)
1
Min
Typ
Max
Unit
1.13
0.7 × VREG18/DVDD
5.5
1.98
V
V
−0.3
−0.3
+0.54
+1.98
V
V
1
1
5
µA
µA
pF
0.45
V
V
5
24
24.576
192
mA
mA
MHz
kHz
1.17
3
2
2.048
8
Test Comments/Comments
The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.
Rev. A| Page 5 of 41
SSM3515
Data Sheet
DIGITAL TIMING CHARACTERISTICS
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 5. I 2 C Port Timing
Parameter
I 2 C PORT
fSCL
t SCLH
t SCLL
t SCS
t SCH
t DS
t SCR
t SCF
tR
tF
t BFT
t HOLD
Min
Limit
Max
400
0.6
1.3
0.6
0.6
100
300
300
300
300
0.6
140
0
Unit
Description
kHz
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
ns
ns
SCL frequency
SCL high
SCL low
Setup time; relevant for repeated start condition
Hold time; after this period, the first clock is generated
Data setup time
SCL rise time
SCL fall time
SDA rise time, not shown in Figure 2
SDA fall time, not shown in Figure 2
Bus-free time (time between stop and start)
SCL falling to SDA rising
SCL falling to SDA falling
Table 6. Digital Input Timing
Parameter
SERIAL PORT
t BIL
t BIH
t SIS
t SIH
t LIS
t LIH
t BP
TMIN
Limit
TMAX
15
15
6
6
10
5
40
Unit
Description
ns
ns
ns
ns
ns
ns
ns
BCLK low pulse width
BCLK high pulse width
SDATA setup, time to BCLK rising
SDATA hold, time from BCLK rising
FSYNC setup time to BCLK rising
FSYNC hold time to BCLK rising
Minimum BCLK period
Digital Timing Diagrams
tDS
tSCH
tSCH
SDA
tSCR
tSCLH
tSCS
tSCLL
START
CONDITION
tSCF
tBFT
STOP
CONDITION
tHOLD
Figure 2. I2C Port Timing
Rev. A| Page 6 of 41
13327-005
SCL
Data Sheet
SSM3515
tBIH
tBP
BCLK
tBIL
tLIH
tLIS
FSYNC
SDATA
LEFT-JUSTIFIED
MODE
tSIS
MSB – 1
MSB
tSIH
SDATA
I2C-JUSTIFIED
MODE
tSIS
MSB
tSIH
tSIS
MSB
LSB
tSIH
tSIH
Figure 3. Serial Input Port Timing
PVDD
tWU
PVDD/2
OUTPUT
0V
13327-161
I2C POWER-UP COMMAND
Figure 4. Turn On Hard Volume
tSD
PVDD
OUTPUT
I2C POWER-DOWN COMMAND
Figure 5. Turn Off Hard Volume
Rev. A| Page 7 of 41
13327-162
0V
13327-002
tSIS
SDATA
RIGHT-JUSTIFIED
MODE
SSM3515
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at TA = 25°C, unless otherwise
noted.
Table 7.
Parameter
PVDD Supply Voltage
VREG18/DVDD Supply Voltage
VREG50/AVDD Supply Voltage
PGND and AGND Differential
ADDR, SDATA Input Voltage
SCL, SDA, BCLK, FSYNC Input Voltage
REG_EN Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature Range
(Soldering, 60 sec)
Rating
−0.3 V to +18 V
−0.3 V to +1.98 V
−0.3 V to +5.5 V
±0.3 V
−0.3 V to +1.98 V
−0.3 V to +5.5 V
−0.3 V to +18 V
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
THERMAL RESISTANCE
θJA (junction to air) is specified for worst case conditions, that is,
a device soldered in a circuit board for surface-mount packages. θJA
and θJB are determined according to JESD51-9 on a 4-layer
printed circuit board (PCB) with natural convection cooling.
Table 8. Thermal Resistance
Package Type
20-Ball, 1.8 mm × 2.2 mm WLCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A| Page 8 of 41
θJA
55.5
Unit
°C/W
Data Sheet
SSM3515
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
3
4
A
VREG50/
AVDD
AGND
PGND
BST–
B
SDA
ADDR
OUT–
OUT–
C
SCL
REG_EN
PVDD
PVDD
D
VREG18/
DVDD
FSYNC
OUT+
OUT+
E
SDATA
BCLK
PGND
BST+
13327-006
1
Figure 6. Pin Configuration (Top Side View)
Table 9. Pin Function Descriptions
Pin No.
A1
A2
A3
Mnemonic
VREG50/AVDD
AGND
PGND
Type1
AOUT
PWR
PWR
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
BST−
SDA
ADDR
OUT−
OUT−
SCL
REG_EN
PVDD
PVDD
VREG18/DVDD
FSYNC
OUT+
OUT+
SDATA
BCLK
PGND
AIN
DIO
DIN
AOUT
AOUT
DIN
AIN
PWR
PWR
PWR
DIN
AOUT
AOUT
DIO
DIN
PWR
E4
BST+
AIN
1
Description
5 V Regulator Output.
Analog Ground. It is recommended to connect the AGND pin to a single ground plane on the board.
Power Stage Ground. The PGND pin is shorted internally. It is recommended to connect PGND to a
single ground plane on the board.
Bootstrap Capacitor for OUT−.
I2C Serial Data.
I2C Address Selection.
Power Stage Inverting Output.
Power Stage Inverting Output.
I2C Clock.
Regulator Enable Tie to PVDD to Enable Regulators.
Power Stage Supply.
Power Stage Supply.
1.8 V Regulator Output/DVDD Input.
TDM Frame Sync Input.
Power Stage Noninverting Output.
Power Stage Noninverting Output.
Serial Data Input to DAC.
TDM Bit Clock Input.
Power Stage Ground. The PGND pin is shorted internally. It is recommended to connect PGND to a
single ground plane on the board.
Bootstrap Capacitor for OUT+.
AOUT is analog output; PWR is power supply or ground pin; AIN is analog input; DIO is digital input/output; DIN is digital input.
Rev. A| Page 9 of 41
SSM3515
Data Sheet
10k
AMPLITUDE (dBV)
AMPLITUDE (dBV)
1k
10k
FREQUENCY (Hz)
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
AMPLITUDE (dBV)
AMPLITUDE (dBV)
1k
10k
FREQUENCY (Hz)
1k
10k
Figure 11. FFT, No Signal, Analog Gain = 8.4, RL = 4 Ω
13327-103
100
100
FREQUENCY (Hz)
Figure 8. FFT, 60 dBFS Input, Analog Gain = 12.6, RL = 4 Ω
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
10k
Figure 10. FFT, 60 dBFS Input, Analog Gain = 15, RL = 4 Ω
13327-102
100
1k
FREQUENCY (Hz)
Figure 7. Fast Fourier Transform (FFT), 60 dBFS Input, Analog Gain = 8.4,
RL = 4 Ω
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
100
13327-105
1k
FREQUENCY (Hz)
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
100
1k
10k
FREQUENCY (Hz)
Figure 9. FFT, 60 dBFS Analog Gain = 14, RL = 4 Ω
Figure 12. FFT, No Signal, Analog Gain =12.6, RL = 4 Ω
Rev. A| Page 10 of 41
13327-106
100
13327-104
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
AMPLITUDE (dBV)
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
13327-101
AMPLITUDE (dBV)
TYPICAL PERFORMANCE CHARACTERISTICS
1
100mW
1W
5W
0.1
THD + N (%)
0.01
100
20
1k
10k
FREQUENCY (Hz)
0.001
20
10k
Figure 16. THD + N vs. Frequency, RL = 4 Ω, PVDD = 12 V
1
100mW
1W
10W
THD + N (%)
0.1
100
20
1k
10k
FREQUENCY (Hz)
0.001
20
100
1k
10k
FREQUENCY (Hz)
Figure 14. FFT, No Signal, Analog Gain = 15, RL = 4 Ω
13327-009
0.01
13327-108
Figure 17. THD + N vs. Frequency, RL = 4 Ω, PVDD = 17 V
1
1
100mW
1W
100mW
1W
0.1
THD + N (%)
THD + N (%)
0.1
0.01
0.001
20
100
1k
10k
FREQUENCY (Hz)
13327-007
0.01
Figure 15. THD + N vs. Frequency into RL = 4 Ω, PVDD = 4.5 V
0.001
20
100
1k
10k
FREQUENCY (Hz)
Figure 18. THD + N vs. Frequency, RL = 8 Ω, PVDD = 4.5 V
Rev. A| Page 11 of 41
13327-010
AMPLITUDE (dBV)
1k
FREQUENCY (Hz)
Figure 13. FFT, No Signal, Analog Gain = 14, RL = 4 Ω
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
100
13327-008
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
SSM3515
13327-107
AMPLITUDE (dBV)
Data Sheet
SSM3515
Data Sheet
1
10
100mW
1W
5W
4.5V
12V
17V
1
THD + N (%)
THD + N (%)
0.1
0.1
0.01
100
1k
10k
FREQUENCY (Hz)
Figure 19. THD + N vs. Frequency, RL = 8 Ω, PVDD = 12 V
0.001
10µ
100µ
1m
10m
100m
1
10
POWER (W)
13327-014
0.001
20
13327-011
0.01
Figure 22. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 12.6
10
1
100mW
1W
5W
4.5V
14V
17V
1
THD + N (%)
THD + N (%)
0.1
0.1
0.01
100
10k
1k
FREQUENCY (Hz)
0.001
10µ
10m
100m
1
10
Figure 23. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 14
10
10
8V
4.5V
17V
1
4.5V
15V
17V
1
THD + N (%)
0.1
0.01
0.1
100µ
1m
10m
100m
1
10
POWER (W)
13327-013
0.01
Figure 21. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 8.4
0.001
10µ
100µ
1m
10m
100m
1
10
POWER (W)
Figure 24. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 15
Rev. A| Page 12 of 41
13327-016
THD + N (%)
1m
POWER (W)
Figure 20. THD + N vs. Frequency, RL = 8 Ω, PVDD = 17 V
0.001
10µ
100µ
13327-015
0.001
20
13327-012
0.01
Data Sheet
10
4.5V
14V
17V
1
THD + N (%)
THD + N (%)
1
0.1
1m
10m
100m
1
10
0.001
10µ
13327-017
100µ
POWER (W)
1m
10m
100m
1
10
Figure 28. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 15
14
4.5V
12V
14V
POUT 10%, 8V GAIN
POUT 1%, 8V GAIN
12
1
10
POWER (W)
THD + N (%)
100µ
POWER (W)
Figure 25. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 8.4
10
0.1
0.01
0.01
0.001
10µ
4.5V
15V
17V
13327-020
10
SSM3515
0.1
8
6
4
0.01
100µ
1m
10m
100m
1
10
POWER (W)
0
6
7
8
9
10
11
12
13
14
PVDD (V)
Figure 26. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 12.6
10
5
13327-021
0.001
10µ
13327-018
2
Figure 29. Output Power vs. PVDD Supply Voltage (PVDD), RL = 4 Ω,
Analog Gain = 8.4
30
4.5V
14V
16V
POUT 10%
POUT 1%
25
1
POWER (W)
THD + N (%)
20
0.1
15
10
0.01
100µ
1m
10m
100m
1
10
POWER (W)
0
5
6
7
8
9
10
11
12
13
14
15
16
17
PVDD (V)
Figure 30. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 12.6
Figure 27. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 14
Rev. A| Page 13 of 41
13327-022
0.001
10µ
13327-019
5
SSM3515
35
Data Sheet
100
POUT 10%
POUT 1%
30
90
80
70
EFFICIENCY (%)
POWER (W)
25
20
15
60
50
40
30
10
20
5
6
7
8
9
10
11
12
13
14
15
16
17
PVDD (V)
0
13327-023
0
10
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 34. Efficiency vs. POUT, RL = 4 Ω, FB and 220 pF Capacitor, PVDD = 5 V,
Analog Gain = 8.4
100
POUT 10%
POUT 1%
35
0
POUT (W)
Figure 31. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 14
40
5V FB NORMAL
5V FB LOW
13327-026
5
90
80
30
EFFICIENCY (%)
POWER (W)
70
25
20
15
60
50
40
30
10
20
6
7
8
9
10
11
12
13
14
15
16
17
PVDD (V)
80
80
70
70
EFFICIENCY (%)
90
60
50
40
20
10
5V NO FB NORMAL
5V NO FB LOW
1.5
2.0
2.5
POUT (W)
3.0
3.5
4.0
4.5
5.0
20
25
40
20
1.0
15
50
30
0.5
10
60
30
0
13327-025
EFFICIENCY (%)
100
90
0
5
Figure 35. Efficiency vs. POUT, RL = 4 Ω, No FB and 220 pF, PVDD = 12 V,
Analog Gain = 12.6
100
0
0
POUT (W)
Figure 32. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 15
10
12V NO FB NORMAL
12V NO FB LOW
Figure 33. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)
and 220 pF Capacitor, PVDD = 5 V, Analog Gain = 8.4
12V FB NORMAL
12V FB LOW
0
5
10
15
POUT (W)
20
25
13327-028
5
0
13327-024
0
10
13327-027
5
Figure 36. Efficiency vs. POUT, RL = 4 Ω, FB and 220 pF Capacitor, PVDD = 12 V,
Analog Gain = 12.6
Rev. A| Page 14 of 41
SSM3515
0.010
90
0.009
80
0.008
70
0.007
60
0.006
IPVDD (A)
100
50
40
0.004
30
0.003
20
0.002
0.001
17V FB NORMAL
17V FB LOW
0
0
5
10
15
20
25
30
35
40
POUT (W)
0
5
7
9
11
13
15
17
13327-032
10
4Ω + 15µH FB 220pF LOW MODE
4Ω + 15µH FB 220pF NORMAL MODE
0.005
13327-029
EFFICIENCY (%)
Data Sheet
19
PVDD (V)
Figure 37. Efficiency vs. POUT, RL = 4 Ω, FB and 220 pF Capacitor, PVDD = 17 V,
Analog Gain = 14
Figure 40. Quiescent Current, RL = 4 Ω, FB and 220 pF Capacitor,
Analog Gain = 12
100
7
POUT 10%
POUT 1%
90
6
80
5
POWER (W)
EFFICIENCY (%)
70
60
50
40
30
4
3
2
20
17V NO FB NORMAL
17V NO FB LOW
0
5
10
15
20
25
30
35
40
45
POUT (W)
0
13327-030
0
5
7
8
9
10
11
12
13
14
PVDD (V)
Figure 38. Efficiency vs. POUT, RL = 4 Ω, No FB and 220 pF Capacitor, PVDD = 17 V,
Analog Gain = 14
Figure 41. Output Power vs. PVDD, RL = 8 Ω, Analog Gain = 8
14
0.007
POUT 10%
POUT 1%
NO LOAD NO FB NORMAL MODE
NO LOAD NO FB LOW MODE
12
0.005
10
0.004
0.003
8
6
0.002
4
0.001
2
0
5
7
9
11
13
15
17
PVDD (V)
Figure 39. Quiescent Current, RL = 4 Ω, No FB and 220 pF Capacitor,
Analog Gain = 12
0
5.0
7.5
10
12.5
PVDD (V)
Figure 42. Output Power vs. PVDD, RL = 8 Ω, Analog Gain = 12
Rev. A| Page 15 of 41
13327-034
POWER (W)
0.006
13327-031
IPVDD (AMP)
6
13327-033
1
10
SSM3515
18
Data Sheet
100
POUT 10%
POUT 1%
16
90
80
14
70
EFFICIENCY (%)
10
8
6
60
50
40
30
20
2
10
0
0
5
10
13327-035
4
15
PVDD (V)
Figure 43. Output Power vs. PVDD, RL = 8 Ω, Analog Gain = 14
NORMAL NO FB/220pF
LOW NO FB/220pF
0
2
4
6
8
10
12
POUT (W)
13327-038
POWER (W)
12
Figure 46. Efficiency vs. POUT, RL = 8 Ω, No FB and 220 pF Capacitor,
PVDD = 12 V, Analog Gain = 12.6
20
100
17V NO FB NORMAL
17V NO FB LOW
POUT 10%
POUT 1%
80
EFFICIENCY (%)
POWER (W)
15
10
60
40
5
5
15
10
0
13327-036
0
PVDD (V)
Figure 44. Output Power vs. PVDD, RL = 8 Ω, Analog Gain = 15
0
5
10
15
20
POUT (W)
13327-041
20
Figure 47. Efficiency vs. POUT, RL = 8 Ω, No FB and 220 pF Capacitor,
PVDD = 17 V, Analog Gain = 14
100
100
5V NO FB NORMAL
5V NO FB LOW
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
70
60
40
60
50
40
30
20
0
2
1
POUT (W)
3
13327-037
10
0
Figure 45. Efficiency vs. POUT, RL = 8 Ω, No FB and 220 pF Capacitor,
PVDD = 5 V, Analog Gain = 8.4
5V NO FB NORMAL
5V NO FB LOW
0
0
2
1
3
POUT (W)
Figure 48. Efficiency vs. POUT, RL = 8 Ω, FB and 220 pF Capacitor,
PVDD = 5 V, Analog Gain = 8.4
Rev. A| Page 16 of 41
13327-040
20
Data Sheet
SSM3515
100
100
12V NO FB NORMAL
12V NO FB LOW
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
70
60
50
40
60
40
30
20
20
10
0
2
4
6
8
10
12
14
POUT (W)
0
30
100
17V FB LOW
17V FB NORMAL
17V NO FB NORMAL
17V NO FB LOW
80
EFFICIENCY (%)
60
40
60
40
20
20
10
5
15
20
POUT (W)
0
13327-042
0
0
5
10
15
20
25
30
35
40
45
50
POUT (W)
Figure 50. Efficiency vs. POUT, RL = 8 Ω, FB and 220 pF Capacitor, PVDD = 17 V,
Analog Gain = 14
13327-047
EFFICIENCY (%)
20
Figure 52. Efficiency vs. POUT, RL = 3 Ω, No FB and 220 pF Capacitor,
PVDD = 12 V, Analog Gain = 12.6
80
0
10
POUT (W)
Figure 49. Efficiency vs. POUT, RL = 8 Ω, FB and 220 pF Capacitor,
PVDD = 12 V, Analog Gain = 12.6
100
0
13327-046
NORMAL FB/220pF
LOW FB/220pF
13327-039
0
Figure 53. Efficiency vs. POUT, RL = 3 Ω, No FB and 220 pF Capacitor,
PVDD = 17 V, Analog Gain = 14
100
100
5V FB NORMAL
5V FB LOW
80
EFFICIENCY (%)
60
40
20
40
20
5V NO FB NORMAL
5V NO FB LOW
0
4
2
POUT (W)
6
0
13327-045
0
60
Figure 51. Efficiency vs. POUT, RL = 3 Ω, No FB and 220 pF Capacitor,
PVDD = 5 V, Analog Gain = 8.4
0
4
2
POUT (W)
6
13327-048
EFFICIENCY (%)
80
Figure 54. Efficiency vs. POUT, RL = 3 Ω, FB and 220 pF Capacitor, PVDD = 5 V,
Analog Gain = 8.4
Rev. A| Page 17 of 41
SSM3515
Data Sheet
40
100
12V FB NORMAL
12V FB LOW
POUT 10%
POUT 1%
35
80
POWER (W)
EFFICIENCY (%)
30
60
40
25
20
15
10
20
0
10
20
30
POUT (W)
0
13327-049
8
PVDD (V)
Figure 55. Efficiency vs. POUT, RL = 3 Ω, FB and 220 pF Capacitor, PVDD = 12 V,
Analog Gain = 12.6
Figure 58. Output Power vs. PVDD, RL = 3 Ω, Analog Gain = 12.6
100
50
17V FB LOW
17V FB NORMAL
POUT 10%
POUT 1%
40
POWER (W)
EFFICIENCY (%)
80
60
40
20
30
20
10
0
5
10
15
30
25
20
35
40
45
50
POUT (W)
0
13327-050
0
14
12
10
15
Figure 59. Output Power vs. PVDD, RL = 3 Ω, Analog Gain = 14
50
POUT 10%
POUT 1%
16
10
PVDD (V)
Figure 56. Efficiency vs. POUT,, RL = 3 Ω, FB and 220 pF Capacitor, PVDD = 17 V,
Analog Gain = 14
18
5
13327-053
0
13327-052
5
POUT 10%
POUT 1%
40
14
POWER (W)
10
8
30
20
6
4
10
0
5
6
7
8
9
10
11
12
13
14
PVDD (V)
Figure 57. Output Power vs. PVDD, RL = 3 Ω, Analog Gain = 8.4
0
5
10
15
PVDD (V)
Figure 60. Output Power vs. PVDD, RL = 3 Ω, Analog Gain = 15
Rev. A| Page 18 of 41
13327-054
2
13327-051
POWER (W)
12
Data Sheet
SSM3515
THEORY OF OPERATION
OVERVIEW
POWER-UP SEQUENCE
The SSM3515 Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and reducing system cost. The
SSM3515 does not require an output filter; it relies on the
inherent inductance of the speaker coil and the natural filtering
of the speaker and human ear to recover the audio component
of the square wave output.
If the REG_EN pin is tied to PVDD, the power-up sequence is
performed internally. As the PVDD voltage ramps up, the
VREG18/DVDD voltage (generated internally) also ramps up.
The typical wait time before the I2C commands can be sent to
the device depends on the PVDD supply ramp-up time.
Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM3515 uses Σ-Δ modulation to
determine the switching pattern of the output devices, resulting
in a number of important benefits. Σ-Δ modulators do not produce
a sharp peak with many harmonics in the AM broadcast band, as
pulse-width modulators often do. Σ-Δ modulation reduces the
amplitude of spectral components at high frequencies, reducing
EMI emission that may otherwise be radiated by speakers and
long cable traces. Due to the inherent spread spectrum nature of
Σ-Δ modulation, the need for oscillator synchronization is eliminated for designs incorporating multiple SSM3515 amplifiers.
The SSM3515 also integrates overcurrent and temperature
protection and a thermal warning with optional programmable
gain reduction.
POWER SUPPLIES
The power supply pins on the SSM3515 are PVDD, VREG50/
AVDD, and VREG18/DVDD.
PVDD, the battery supply, is used for the output stage and also
supplies power to the 5 V regulator. In addition, it can be used
to supply power to the 1.8 V regulator. This pin must be
decoupled to ground using a 100 nF capacitor in parallel with a
1 µF MLCC capacitor to ground as close as possible to the
respective pins. In addition, a bulk electrolytic capacitor may be
required depending on the output power to supply the current at
low frequency output. Typically, 220 µF and 25 V is
recommended. This must be sized according to the power
supply regulation in the system.
VREG50/AVDD (5 V) is the analog supply used for the input
stage, modulator, power stage driver, and other blocks. It uses
the VREG50/AVDD pin. It is generated internally by the
integrated 5 V linear regulator. This pin must be decoupled to
ground using the 100 nF and 10 µF capacitor.
VREG18/DVDD (1.8 V) is the supply for the digital circuitry. It
uses the VREG18/DVDD pin. It can be generated internally
using an integrated 1.8 V linear regulator. Alternatively, an
external 1.8 V supply can be used to save the power dissipation.
The VREG18/DVDD pin must be decoupled to ground using
100 nF and 10 µF MLCC capacitors close to the pin.
If the REG_EN pin is tied low, ensure that 1.8 V is supplied
externally and that PVDD is greater than 4.5 V before sending
I2C commands to enable the device.
POWER-DOWN OPERATION
The SSM3515 offers several power down options via I2C.
Register 0x00 provides multiple options for setting the various
power-down modes.
Set the SPWDN bit to 1 to fully power down the device. Only
the I2C, 1.8 V regulator is kept alive.
The SSM3515 monitors both the BCLK and FSYNC pins for clock
presence when in 2-wire mode. When no BCLK or FSYNC signals
are present, the device automatically powers down all internal
circuitry to its lowest power state. When a BCLK or FSYNC
signal returns, the device automatically powers up following
its usual power up sequence.
When enabled, the APWDN_EN bit (auto power down),
activates a low power state as soon as 2048 consecutive zero
input samples are received. Only the I2C and digital audio input
blocks are kept active.
REG_EN PIN SETUP AND CONTROL
The REG_EN (regulator enable) pin enables or disables the
internal 1.8 V regulator.
Table 10. Regulator Enable Pin Function
REG_EN
Ground
PVDD
1.8 V Regulator
Disabled
Enabled
Comment
External 1.8 V
Internal 1.8 V
The status of the REG_EN pin determines if the 1.8 V supply is
generated internally or if it must be provided externally. If the
REG_EN pin is tied to PVDD, the internal 1.8 V regulator is
enabled. If the REG_EN pin is tied to ground, a 1.8 V supply
must be supplied externally to the VREG18/DVDD pin for the
device to operate. For the device to respond to I2C commands,
the 1.8 V supply must be stable.
Rev. A| Page 19 of 41
SSM3515
Data Sheet
ADDR PIN SETUP AND CONTROL
The ADDR pin sets the device I2C address. See Table 11 for details.
CLOCKING
In 3-wire mode (BCLK, FSYNC, SDATA), a BCLK signal must
be provided to the SSM3515 for correct operation. The BCLK
signal must have a minimum frequency of 2.048 MHz. The BCLK
signal is used for internal clocking of the device. The BCLK rate
is detected automatically, but the sampling frequency must be
known to the device. The supported BCLK rates at 32 kHz to 48
kHz are 50, 64, 100, 128, 192, 200, 256, 384, 400, and 512 times
the sample rate.
Table 11. Pin Setup List
ADDR Pin
Connected to Ground Using a 47 kΩ Resistor
Open (No Connection)
Connected to 1.8 V Using a 47 kΩ Resistor
Connected to 1.8 V
SCL Pin
SCL
SCL
SCL
SCL
SDA Pin
Control Mode
7-Bit I2C Address
TDM Slot
SDA
SDA
SDA
SDA
I2C
0x14
0x15
0x16
0x17
1
2
3
4
I2C
I2C
I2C
Rev. A| Page 20 of 41
Data Sheet
SSM3515
DIGITAL AUDIO SERIAL INTERFACE
The SSM3515 includes a standard serial audio interface that is
slave only. The interface is capable of receiving I2S, left justified,
PCM, or TDM formatted data.
The serial interface has three main operating modes, listed in
Table 12.
Table 12. Operating Modes
Mode
2-Channel (Stereo)
Format
I 2 S/left justified
Multichannel TDM
I 2 S/left justified
Comments
Register control
using I 2 C port
Register control
using I 2 C port
I2C CONTROL
The SSM3515 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the SSM3515 and the system I2C master controller. The
SSM3515 is always a slave on the bus, meaning it cannot initiate
a data transfer. Each slave device is recognized by a unique address.
Using the ADDR pin provides the four device addresses, which are
listed in Table 11. The address byte format is shown in Table 13.
The address resides in the first seven bits of the I2C write. The
LSB of this byte sets either a read or write operation. Logic Level 1
corresponds to a read operation, and Logic Level 0 corresponds
to a write operation.
Stereo modes, typically I2S or left justified, are used when there
is one or two devices on the interface bus. Standard multichannel TDM modes are more flexible and offer the ability to
have multiple devices on the bus. In both of these cases, the
register control uses an I2C port.
Connect 2.2 kΩ pull-up resistors on the lines connected to the
SDA and SCL pins. The voltage on these signal lines must not
be more than 5 V.
STEREO (I2S/LEFT JUSTIFIED) OPERATING MODE
Addressing
Stereo modes use both edges of FSYNC to determine placement
of data. Stereo mode is enabled when SAI_MODE = 0 and the
data format is determined by the SDATA_FMT register setting.
Initially, each device on the I2C bus is in an idle state, monitoring
the SDA and SCL lines for a start condition and the proper
address. The I2C master initiates a data transfer by establishing a
start condition, defined by a high to low transition on SDA while
SCL remains high. This indicates that an address or data stream
follows. All devices on the bus respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/W bit)
MSB first. The device that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This ninth bit is an acknowledge bit. All other devices
withdraw from the bus at this point and return to the idle condition. The device address for the SSM3515 is determined by the
state of the ADDR pin. See Table 11 for four available addresses.
The I2S or left justified interface formats accept any number of
BCLK cycles per FSYNC cycle. Sample rates from 8 kHz to
192 kHz are accepted. The maximum BCLK rate is 24.576 MHz.
TDM OPERATING MODE
The TDM operating mode allows multiple chips to use a single
serial interface bus for audio data.
The FSYNC signal operates at the desired sample rate. A rising
edge of the FSYNC signal indicates the start of a new frame. For
proper operation, this signal must be one BCLK cycle wide,
transitioning on a falling BCLK edge. The MSB of data must be
present on the SDATA one BCLK cycle later. The SDATA signal
latches on the rising edge of BCLK.
Each chip on the TDM bus can occupy 16, 24, 32, 48, or 64 BCLK
cycles. This is set with the TDM_BCLKS bits and all devices on
the bus must have the same setting. Up to 16 SSM3515 devices can
be used on a single TDM bus, but only 4 unique I2C device
addresses are available. The SSM3515 automatically determines
how many possible devices can be placed on the bus from the
BCLK rate. There is no limit to the total number of BCLK cycles
per FSYNC pulse.
Which chip slot each SSM3515 uses is determined by the ADDR
pin settings (see Table 11 for details), or by the TDM_SLOT bits
in Register 0x05.
The input data width to the DAC can be either 16-bit or 24-bit.
The R/W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means the master writes information to
the peripheral, whereas a Logic 1 means the master reads
information from the peripheral after writing the subaddress
and repeating the start address. A data transfer occurs until a
stop condition is encountered. A stop condition occurs when
SDA transitions from low to high while SCL is held high. The
timing for the I2C port is shown in Figure 61.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the SSM3515 immediately
jumps to the idle condition. During a given SCL high period,
the user must issue only one start condition, one stop condition, or
a single stop condition followed by a single start condition. If
the user issues an invalid subaddress, the SSM3515 does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while in auto-increment mode,
one of two actions is taken.
Rev. A| Page 21 of 41
SSM3515
Data Sheet
In read mode, the SSM3515 outputs the highest subaddress register
contents until the master device issues a no acknowledge, indicating the end of a read. A no acknowledge condition is when the
SDA line is not pulled low on the ninth clock pulse on SCL. If the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register,
a no acknowledge is issued by the SSM3515, and the device
returns to the idle condition.
I 2C Read and Write Operations
Figure 62 shows the timing of a single-word write operation.
Every ninth clock, the SSM3515 issues an acknowledge (ACK)
by pulling SDA low.
every byte because the requested subaddress corresponds to a
register or memory area with a byte word length.
The timing of a single word read operation is shown in Figure 64.
Note that the first R/W bit is 0, indicating a write operation.
This is because the subaddress still must be written to set up the
internal address. After the SSM3515 acknowledges the receipt of
the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W set to 1 (read).
This causes the SSM3515 SDA to reverse and begin driving data
back to the master. The master then responds every ninth pulse
with an acknowledge pulse to the SSM3515. See Table 15 for a
list of abbreviations in Figure 62 through Figure 65.
Figure 63 shows the timing of a burst mode write sequence. This
figure shows an example in which the target destination registers
are two bytes. The SSM3515 increments its subaddress register
Table 13. I 2 C Device Address Byte Format Using the ADDR Pin1
Bit 0
0
1
Bit 1
0
Bit 2
1
Bit 3
0
Bit 4
1
Bit 5
X
Bit 6
X
X means don’t care.
Table 14. ADDR Pin to I 2 C Device Address Mapping
ADDR Pin
GND
Pull-Down 47 kΩ Resistor
Open
Pull-Up 47 kΩ Resistor
DVDD
I2C Address Bit 5
Not applicable
0
0
1
1
ADDR Voltage
GND
0.25 × VREG18/DVDD
0.5 × VREG18/DVDD
0.75 × VREG18/DVDD
DVDD
Table 15. Abbreviations for Figure 62 Through Figure 65
Symbol
Meaning
S
P
AM
AS
Start bit
Stop bit
Acknowledge by master
Acknowledge by slave
Rev. A| Page 22 of 41
I2C Address Bit 6
Not applicable
0
1
0
1
Bit 7
R/W
Data Sheet
SSM3515
SCK
SDA
START BY
MASTER
ACK
ACK
R/W
FRAME 2
SUBADDRESS BYTE
FRAME 1
CHIP ADDRESS BYTE
SCK
(CONTINUED)
ACK
ACK
STOP BY
MASTER
FRAME 4
DATA BYTE 2
FRAME 3
DATA BYTE 1
2
START
BIT
I2C ADDRESS
(7 BITS)
R/W = 0
SUBADDRESS
(8 BITS)
ACK BY
SLAVE
DATA BYTE 1
(8 BITS)
ACK BY
SLAVE
STOP
BIT
13327-067
Figure 61. I C Read/Write Timing
S
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS
AS
DATA
WORD 1
AS
DATA
WORD 2
AS
…
P
13327-068
Figure 62. Single Word I2C Write Format
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS
AS
S
CHIP ADDRESS,
R/W = 1
AS
DATA
BYTE 1
AM
DATA
BYTE N
P
13327-069
S
DATA
WORD 1
AM
…
P
13327-070
Figure 63. Burst Mode I2C Write Format
Figure 64. Single Word I2C Read Format
S
CHIP ADDRESS,
R/W = 0
AS
SUBADDRESS
AS
S
CHIP ADDRESS,
R/W = 1
AS
Figure 65. Burst Mode I2C Read Format
Rev. A| Page 23 of 41
13327-066
SDA
(CONTINUED)
SSM3515
Data Sheet
ANALOG AND DIGITAL GAIN
EMI NOISE
Several selectable settings are available for the analog gain of the
system. These provide optimal gain settings at various PVDD supply
voltages. The ANA_GAIN bits are available in Register 0x01,
Bits[1:0].
The SSM3515 uses a proprietary modulation and spread
spectrum technology to minimize EMI emissions from the
device. The SSM3515 can pass FCC Class B emissions testing
with an unshielded 20-inch cable using ferrite bead-based
filtering. For applications that have difficulty passing FCC Class B
emission tests, the SSM3515 includes a modulation select pin
(ultralow EMI emission mode) that significantly reduces the
radiated emissions at the Class-D outputs, particularly above
100 MHz. Note that reducing the supply voltage greatly reduces
radiated emissions.
The available options are as shown in Table 16.
Table 16. Analog Gain Options
PVDD
5 V to 9 V
9 V to 13 V
13 V to 14 V
14 V to 16 V
ANA_GAIN
00
01
10
11
Amplifier Analog Gain
Selection
8.4 V full-scale gain mapping
12.6 V full-scale gain mapping
14 V full-scale gain mapping
15 V full-scale gain mapping
OUTPUT MODULATION DESCRIPTION
POP AND CLICK SUPPRESSION
The SSM3515 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to PVDD and vice versa. Ideally, when
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present.
Voltage transients at the output of audio amplifiers may occur
when shutdown is activated or deactivated. Voltage transients
as small as 10 mV can be heard as an audible pop in the speaker.
Clicks and pops are defined as undesirable audible transients
generated by the amplifier system that do not come from the
system input signal.
Due to this constant presence of noise, a differential pulse is
occasionally generated in response to this stimulus. A small
amount of current flows into the inductive load when the
differential pulse is generated. However, most of the time, the
output differential voltage is 0 V. This feature ensures that the
current flowing through the inductive load is small.
Such transients may be generated when the amplifier system
changes its operating mode. For example, system power-up and
power-down can be sources of audible transients.
When the user sends an input signal, an output pulse is generated
to follow the input voltage. The differential pulse density is
increased by raising the input signal level. Figure 66 depicts
three-level, Σ-Δ output modulation with and without input
stimulus.
There is also a digital gain or volume control that provides fine
control in 0.375 dB steps from −70 dB to +24 dB.
The SSM3515 has a pop and click suppression architecture that
reduces these output transients, resulting in noiseless activation and
deactivation.
Either mute or power-down must be set before the BCLK is
removed to ensure a pop free power-down.
OUTPUT = 0V
+5V
OUT+
0V
+5V
OUT–
0V
+5V
VOUT
0V
–5V
OUTPUT > 0V
+5V
OUT+
0V
+5V
OUT–
0V
+5V
VOUT
0V
OUTPUT < 0V
+5V
OUT+
0V
+5V
OUT–
0V
–5V
NOTES
1. VOUT = (OUT+) – (OUT−) MEASURED ACROSS THE LOAD.
13327-071
0V
Figure 66. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
Rev. A| Page 24 of 41
Data Sheet
SSM3515
FAULTS AND LIMITER STATUS REPORTING
VBAT SENSING
The SSM3515 offers comprehensive protections against the
faults at the outputs and reporting to help with system design.
The faults listed in Table 17 are reported using the status registers.
The SSM3515 contains an 8-bit ADC that measures the voltage
of the battery voltage (VBAT) supply. The battery voltage
information is stored in Register 0x06 as an 8-bit unsigned format.
The ADC input range is fixed internally as 3.8 V to 16.2 V. To
convert the hexidecimal (hex) value to the voltage value, use the
following steps:
Table 17. Register 0x0A, Faults
Fault Type
5 V Regulator UV
Flag Set Condition
5 V regulator voltage at
VREG50/AVDD < 3.6 V
Limiter engaged
Limiter/Gain Reduction
Engage
Clipping
DAC clipping
Output Overcurrent
(OC)
Die Overtemperature
(OT)
Die Overtemperature
Warning (OTW)
Battery Voltage >
VBAT_INF
Output current > 6 A
peak
Die temperature >
145°C
Die temperature >
117°C
Battery voltage PVDD >
VBAT_INF
Status Reported
Register
Register 0x0A,
Bit 6, UVLO_VREG
Register 0x0A,
Bit 5, LIM_EG
Register 0x0A,
Bit 4, CLIP
Register 0x0A,
Bit 3, AMP_OC
Register 0x0A,
Bit 2, OTF
Register 0x0A,
Bit 4, OTW
Register 0x0A,
Bit 0, BAT_WARN
The faults listed in Table 17 are reported in Register 0x0A and
can be read via I2C by the microcontroller in the system.
In the event of a fault occurrence, how the device reacts to the
faults can be controlled by using Register 0x0B.
Table 18. Register 0x0B, Fault Recovery
Fault Type
OTW
Manual
Recovery
Autorecovery
Attempts
UV
Die OT
OC
Flag Set Condition
The amount of gain
reduction applied if there
is an OTW
Use to attempt manual
recovery in case of a fault
event
When autorecovery from
faults is used, set the
number of attempts using
this bit
Recovery can be automatic
or manual
Recovery can be automatic
or manual
Recovery can be automatic
or manual
Status Reported
Register
Register 0x0B,
Bits[7:6], OTW_GAIN
Register 0x0B, Bit 5,
MRCV
Register 0x0B,
Bits[4:3], MAX_AR
Register 0x0B, Bit 2,
ARCV_UV
Register 0x0B, Bit 1,
ARCV_OT
Register 0x0B, Bit 0,
ARCV_OC
When the automatic recovery mode is set, the device attempts
to recover itself after the fault event and, in case the fault
persists, then the device sets the fault again. This process
repeats until the fault is resolved.
1.
2.
Convert the hex value to decimal. For example, if the hex
value is 0xA9, the decimal value = 169.
Calculate the voltage using the following equation:
Voltage = 3.8 V + 12.4 V × Decimal Value/255
With a decimal value of 169,
Voltage = 3.8 V + 12.4 V × 169/255 = 12.02 V
LIMITER AND BATTERY TRACKING THRESHOLD
CONTROL
The SSM3515 contains an output limiter that can be used limit
the peak output voltage of the amplifier. The limiter works on
the rms and peak value of the signal. The limiter threshold,
slope, attack rate, and release rate are programmable using
Register 0x07, Register 0x08, and Register 0x09. The limiter can
be enabled or disabled using LIM_EN, Bits[1:0] in Register 0x07.
The threshold at which the output is limited is determined by
the LIM_THRES register setting, in Register 0x08, Bits[7:3].
When the ouput signal level exceeds the set therhold level, the
limiter activates and limits the signal level to the set limit. Below
the set threshold, the output level is not affected. The limiter
threshold can be set from 1 V peak to 15 V peak.
The limiter threshold can be set above the maximum output
voltage of the amplifier. In this case, the limiter allows maximum
peak output; in other words, the output may clip depending on
the power supply voltage and not the limiter.
The limiter threshold can be set as fixed or to vary with the
battery voltage via the VBAT_TRACK bit (Register 0x07, Bit 2).
When set to fixed, the limiter threshold is fixed and does not
vary with battery voltage. The threshold can be set from 1 V peak
to 15 V peak using the LIM_THRES bit (see Figure 68).
When set to a variable threshold, the SSM3515 monitors the
VBAT supply and automatically adjusts the limiter threshold
based on the VBAT supply voltage.
The VBAT supply voltage at which the limiter threshold level
begins to decrease the output level is determined by the VBAT
inflection point, the VBAT_INF bits (Register 0x09, Bits[7:0]).
When the manual recovery mode is used, the device shuts down
and the recovery must be attempted using the system
microcontroller.
Rev. A| Page 25 of 41
SSM3515
Data Sheet
The limiter, when active, reduces the gain of the amplifier. The rate
of gain reduction or attack rate is determined by the LIM_ATR bits
(Register 0x07, Bits[5:4]). Similarly, when the signal level drops
below the limiter threshold, the gain is restored. The gain release
rate is determined by the LIM_RRT bits (Register 0x07, Bits[7:6]).
LIM_EN = 00
VBAT_TRACK = 0
AMPLIFIER CLIPPING LEVEL
Voltage = 3.8 + 12.4 × Decimal Value/255
Convert the decimal value to an 8-bit hex value and use it to set
the VBAT_INF bits.
The rate at which the limiter threshold is lowered relative to
the amount change in VBAT below the VBAT_INF point is
determined by the slope bits (Register 0x08, Bits[1:0]).
The slope is the ratio of the limiter threshold reduction to the
VBAT voltage reduction.
INPUT LEVEL
Slope = ΔLimiter Threshold/ΔVBAT
Figure 67. Limiter Example (LIM_EN = 0b0, VBAT_TRACK = 0bx)
LIMITER THRESHOLD FIXED AT SET VALUE
AND DOES NOT TRACK VBAT
LIM_THRES
The limiter offers various active modes which can be set using the
LIM_EN bits (Register 0x07, Bits[1:0]) and the VBAT_TRACK bit,
as shown in Table 19.
When LIM_EN = 01, the limiter is enabled. When LIM_EN = 10,
the limiter mutes the output if VBAT falls below VBAT_INF. When
LIM_EN = 11, the limiter engages only when the battery voltage
is lower than VBAT_INF. When VBAT is above VBAT_INF, no
limiting occurs. Note that there is hysteresis on VBAT_INF for the
limiter disengaging.
VBAT
Figure 68. Limiter Fixed (LIM_EN = 0b01, VBAT_TRACK = 0b0)
Table 19. Limiter Modes
VBAT_TRACK
0/1
0
1
0/1
0
1
Limiter
No
Fixed
Variable
Fixed
Fixed
Variable
VBAT < VBAT_INF
Not applicable
Use the set threshold
Lowers the threshold
Mutes the output
Use the set threshold
Lowers the threshold
VBAT > VBAT_INF
Not applicable
Use the set threshold
Use the set threshold
Use the set threshold
No limiting
No limiting
Rev. A| Page 26 of 41
Comments
See Figure 67
See Figure 68
See Figure 69 and Figure 70
See Figure 71 and Figure 72
See Figure 73 and Figure 74
13327-080
LIMITER THRESHOLD
The slope ratio can be set from 1:1 to 4:1. This function is useful
to prevent early shutdown under low battery conditions. As the
VBAT voltage falls, the limiter threshold is lowered. This results in
the lower output level and therefore helps to reduce the current
drawn from the battery and in turn helps prevent early shutdown
due to low VBAT.
LIM_EN
00
01
01
10
11
11
13327-078
PEAK OUTPUT LEVEL
The VBAT_INF point is defined as the battery voltage at which
the limiter either activates or deactivates depending on the
LIM_EN mode (see Table 19). When the battery voltage is
greater than VBAT_INF, the limiter is not active. When it
battery voltage is less than VBAT_INF, the limiter is activated.
The VBAT_INF bits can be set from 3.8 V to 16.2 V. The 8-bit
value for the voltage can be calculated using the following
equation.
Data Sheet
SSM3515
LIM_EN = 01
VBAT_TRACK = 1
LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF
13327-081
CHANGE IN LIM THRESHOLD = N × (VBAT_INF – VBAT)
WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x08
INPUT LEVEL
13327-182
LIMITER THRESHOLD
PEAK OUTPUT LEVEL
LIMITER THRESHOLD FIXED AT SET VALUE
AND DOES NOT TRACK VBAT
LIM_THRES
VBAT > VBAT_INF LIMITER
LIMITER THRESHOLD SETTING
VBAT
Figure 69. Limiter Fixed (LIM_EN = 0b01, VBAT_TRACK = 0b1)
Figure 72. Limiter Fixed (LIM_EN = 0b11, VBAT_TRACK = 0b0)
LIM_EN = 11
VBAT_TRACK = 1
LIMITER THRESHOLD STAYS AT
THE SET VALUE FOR VBAT > VBAT_INF
VBAT > VBAT_INF LIMITER IS NOT ACTIVE
AMPLIFIER CLIPPING LEVEL
VBAT_INF
PEAK OUTPUT LEVEL
LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF
LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF
CHANGE IN LIM THRESHOLD = N × (VBAT_INF – VBAT)
WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x08
VBAT
INPUT LEVEL
Figure 70. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN = 0b01,
VBAT_TRACK = 0b1)
Figure 73. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0b1)
LIM_EN = 11
VBAT_TRACK = 0
LIMITER THRESHOLD INACTIVE FOR VBAT > VBAT_INF
LIMITER THRESHOLD
SET LIM_THRES
INPUT LEVEL
Figure 71. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0)
13327-082
LIMITER THRESHOLD SETTING
NO CHANGE IN LIM THRESHOLD PER VBAT
VBAT_INF
SLOPE
LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF
VBAT
Figure 74. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN = 0b11,
VBAT_TRACK = 0b1)
Rev. A| Page 27 of 41
13327-183
AMPLIFIER CLIPPING LEVEL
PEAK OUTPUT LEVEL
13327-083
SLOPE
LIMITER THRESHOLD SETTING
13327-181
LIMITER THRESHOLD
LIM_THRES
SSM3515
Data Sheet
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply; a poor layout increases voltage drops, consequently
decreasing efficiency. A good practice is to use short, wide PCB
tracks to decrease voltage drops and minimize inductance. For
lowest dc resistance (DCR) and minimum inductance, ensure
that track widths are at least 200 mil for every inch of length
and use 1 oz or 2 oz copper. Use large traces for the power supply
inputs and amplifier outputs. Proper grounding guidelines
improve audio performance, minimize crosstalk between
channels, and prevent switching noise from coupling into the
audio signal.
To maintain high output swing and high peak output power, the
PCB traces that connect the output pins to the load and supply
pins must be as wide as possible to maintain the minimum trace
resistances. It is also recommended that a large ground plane be
used for minimum impedances. In addition, good PCB layout
isolates critical analog paths from sources of high interference.
Separate high frequency circuits (analog and digital) from low
frequency circuits.
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
If the system has separate analog and digital ground and power
planes, the analog ground plane must be directly beneath the
analog power plane, and, similarly, the digital ground plane must
be directly beneath the digital power plane. There must be no
overlap between analog and digital ground planes or between
analog and digital power planes.
BOOTSTRAP CAPACITORS
The output stage of the SSM3515 uses a high-side NMOS driver,
rather than PMOS. Therefore, a bootstrap supply is needed to
drive the high-side NMOS. To generate the boosted gate driver
voltage for the high-side NMOS, a 0.22 μF bootstrap capacitor is
used from each output pin to BST± pins. This capacitor boosts the
voltage at BST± pins when the high-side NMOS turns on and
acts as a floating power supply for that particular switching
cycle. The bootstrap capacitor is charged during the low-side
NMOS active period.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high power supply rejection ratio (PSRR), proper power
supply decoupling is necessary. Noise transients on the power
supply lines are short duration voltage spikes. These spikes can
contain frequency components that extend into the hundreds of
megahertz. The power supply input must be decoupled with a
good quality, low ESL, low ESR bulk capacitor larger than
220 µF. This capacitor bypasses low frequency noises to the
ground plane.
For high frequency transient noises, place 1 µF capacitors as
close as possible to the PVDD pins of the device.
Rev. A| Page 28 of 41
Data Sheet
SSM3515
REGISTER SUMMARY
Table 20. Register Summary
Reg.
Name
Bits
Bit 7
Bit 6
0x00
Power Control
[7:0]
APWDN_
EN
BSNS_
PWDN
0x01
Gain and Edge
Control
[7:0]
0x02
DAC Control
[7:0]
0x03
DAC Volume
Control
[7:0]
0x04
SAI Control 1
[7:0]
DAC_POL
0x05
SAI Control 2
[7:0]
DATA_
WIDTH
0x06
Battery Voltage
Output
[7:0]
0x07
Limiter Control 1
[7:0]
0x08
Limiter Control 2
[7:0]
0x09
Limiter Control 3
[7:0]
0x0A
Status
[7:0]
0x0B
Fault Control
[7:0]
Bit 5
Bit 4
RESERVED
DAC_HV
Bit 3
Bit 2
RESERVED
DAC_MUTE
EDGE
DAC_HPF
Bit 1
Bit 0
Reset
RW
S_RST
SPWDN
0x81
R/W
0x01
R/W
0x32
R/W
0x40
R/W
0x11
R/W
0x00
R/W
0x00
R
RESERVED
DAC_LPM
ANA_GAIN
RESERVED
DAC_FS
VOL
BCLK_POL
TDM_BCLKS
RESERVED
FSYNC_
MODE
AUTO_
SLOT
SDATA_
FMT
SAI_MODE
TDM_SLOT
VBAT
LIM_RRT
LIM_ATR
RESERVED
LIM_THRES
VBAT_
TRACK
LIM_EN
0xA4
R/W
RESERVED
SLOPE
0x51
R/W
VBAT_INF
RESERVED
UVLO_VREG
OTW_GAIN
LIM_EG
MRCV
CLIP
AMP_OC
MAX_AR
Rev. A| Page 29 of 41
0x22
R/W
OTF
OTW
BAT_WARN
0x00
R
ARCV_UV
ARCV_OT
ARCV_OC
0x18
R/W
SSM3515
Data Sheet
REGISTER DETAILS
POWER CONTROL REGISTER
Address: 0x00, Reset: 0x81, Name: Power Control
7
6
5
1 0
4
3
0 0
2
1
0 0
0
0 1
[7] APW DN_EN (R/W)
Auto Power-Down Enable
0: Auto Power-Down Disabled.
1: Auto Power-Down Enabled.
[0] SPW DN (R/W)
Master Software Power-Down
0: Normal Operation.
1: Software Master Power-Down.
[6] BSNS_PWDN (R/W)
Battery Voltage Sense Power-Down
0: Battery Voltage Sense Powered On.
1: Battery Voltage Sense Powered Off.
[1] S_RST (W)
Full Software Reset
0: Normal Operation.
1: Reset all blocks and I2C registers.
[5:2] RESERVED
Table 21. Bit Descriptions for Power Control
Bits
Bit Name
7
APWDN_EN
6
Settings
Description
Reset
Access
Auto Power-Down Enable. Auto power-down automatically puts the IC in a low
power state when 2048 consecutive zero input samples have been received.
0x1
R/W
0x0
R/W
0
Auto Power-Down Disabled.
1
Auto Power-Down Enabled. When APWDN_EN = 1 the device automatically
powers down when 2048 consecutive zero value input samples have been
received. The device automatically powers up when a single nonzero sample is
received.
BSNS_PWDN
Battery Voltage Sense Power-Down.
0
Battery Voltage Sense Powered On.
1
Battery Voltage Sense Powered Off.
[5:2]
RESERVED
Reserved.
0x0
R/W
1
S_RST
Full Software Reset.
0x0
W
0x1
R/W
Description
Reset
Access
Reserved.
0x0
R/W
0
0
Normal Operation.
1
Reset all Blocks and I 2 C Registers.
Master Software Power-Down. Software power-down puts all blocks except the I 2 C
interface in a low-power state.
SPWDN
0
Normal Operation.
1
Software Master Power-Down.
GAIN AND EDGE CONTROL REGISTER
Address: 0x01, Reset: 0x01, Name: Gain and Edge Control
7
6
0 0
5
4
0 0
3
2
0 0
1
0
0 1
[7:5] RESERVED
[1:0] ANA_GAIN (R/W)
Amp Analog Gain Selection
00: 8.4V Full-Scale Gain Mapping.
01: 12.6V Full-Scale Gain Mapping.
10: 14V Full-Scale Gain Mapping.
11: 15V Full-Scale Gain Mapping.
[4] EDGE (R/W)
Edge Rate Control
0: Normal Operation.
1: Low EMI Mode Operation.
[3:2] RESERVED
Table 22. Bit Descriptions for Gain and Edge Control
Bits
Bit Name
[7:5]
RESERVED
Settings
Rev. A| Page 30 of 41
Data Sheet
Bits
Bit Name
4
EDGE
[3:2]
RESERVED
[1:0]
ANA_GAIN
SSM3515
Settings
Description
Reset
Access
Edge Rate Control. This controls the edge speed of the power stage. The low EMI
operation mode reduces the edge speed, lowering EMI and power efficiency
0x0
R/W
Reserved.
0x0
R/W
Amp Analog Gain Selection.
0x1
R/W
0
Normal Operation.
1
Low EMI Mode Operation.
00
8.4 V Full-Scale Gain Mapping.
01
12.6 V Full-Scale Gain Mapping.
10
14 V Full-Scale Gain Mapping.
11
15 V Full-Scale Gain Mapping.
DAC CONTROL REGISTER
Address: 0x02, Reset: 0x32, Name: DAC Control
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
[7] DAC_HV (R/W)
DAC Hard Volume
0: Soft Volume Ramping.
1: Hard/Immediate Volume Change.
[2:0] DAC_FS (R/W)
DAC Sample Rate Selection
000: 8 kHz to 12 kHz Sample Rate.
001: 16 kHz to 24 kHz Sample Rate.
010: 32 kHz to 48 kHz Sample Rate.
011: 64 kHz to 96 kHz Sample Rate.
100: 128 kHz to 192 kHz Sample Rate.
101: 48 kHz to 72 kHz Sample Rate.
110: Reserved.
111: Reserved.
[6] DAC_MUTE (R/W)
DAC Mute Control
0: DAC Unmuted.
1: DAC Muted.
[5] DAC_HPF (R/W)
DAC High Pass Filter Enable
0: DAC High Pass Filter Off.
1: DAC High Pass Filter On.
[3] RESERVED
[4] DAC_LPM (R/W)
DAC Low Power Mode Enable
0: DAC Low Power Mode Off.
1: DAC Low Power Mode On.
Table 23. Bit Descriptions for DAC Control
Bits
Bit Name
7
DAC_HV
6
5
4
3
Settings
Reset
Access
DAC Hard Volume.
0x0
R/W
0x0
R/W
0x1
R/W
0x1
R/W
0x0
R/W
0
Soft Volume Ramping.
1
Hard/Immediate Volume Change.
DAC_MUTE
DAC Mute Control.
0
DAC Unmuted.
1
DAC Muted.
DAC_HPF
DAC High-Pass Filter Enable.
0
DAC High-Pass Filter Off.
1
DAC High-Pass Filter On.
DAC_LPM
RESERVED
Description
DAC Low Power Mode Enable.
0
DAC Low Power Mode Off.
1
DAC Low Power Mode On.
Reserved.
Rev. A| Page 31 of 41
SSM3515
Bits
Bit Name
[2:0]
DAC_FS
Data Sheet
Settings
Description
Reset
Access
DAC Sample Rate Selection.
0x2
R/W
Description
Reset
Access
Volume Control.
0x40
R/W
000
8 kHz to 12 kHz Sample Rate.
001
16 kHz to 24 kHz Sample Rate.
010
32 kHz to 48 kHz Sample Rate.
011
64 kHz to 96 kHz Sample Rate.
100
128 kHz to 192 kHz Sample Rate.
101
48 kHz to 72 kHz Sample Rate.
110
Reserved.
111
Reserved.
DAC VOLUME CONTROL REGISTER
Address: 0x03, Reset: 0x40, Name: DAC Volume Control
7
6
0
1 0
5
4
3
0 0
1
0
0 0
2
0
[7:0] VOL (R/W)
Volume Control
00000000: +24 dB.
00000001: +23.625 dB.
00000010: +23.35 dB.
...
11111101: -70.875 dB.
11111110: -71.25 dB.
11111111: Mute.
Table 24. Bit Descriptions for DAC Volume Control
Bits
Bit Name
[7:0]
VOL
Settings
00000000
+24 dB.
00000001
+23.625 dB.
00000010
+23.35 dB.
00000011
+22.875 dB.
00000100
+22.5 dB.
00000101
...
00111111
+0.375 dB.
01000000
0.
01000001
−0.375 dB.
01000010
...
11111101
−70.875 dB.
11111110
−71.25 dB.
11111111
Mute.
Rev. A| Page 32 of 41
Data Sheet
SSM3515
SAI CONTROL 1 REGISTER
Address: 0x04, Reset: 0x11, Name: SAI Control 1
7
6
0
0 0
5
4
3
1 0
1
0
0 0
2
1
[7] DAC_POL (R/W)
DAC Output Polarity
0: Normal Operation.
1: Invert the Audio Output Signal.
[0] SAI_MODE (R/W)
Serial Interface Mode Selection
0: Stereo Modes (I2S,LJ)
1: TDM/PCM Modes.
[6] BCLK_POL (R/W)
BCLK Polarity Control
0: Rising Edge of BCLK is used to register
SDATA.
1: Falling Edge of BCLK is used to register
SDATA.
[1] SDATA_FMT (R/W)
Serial Data Format
0: I2S/Delay by one from FSYNC edge.
1: Left Justified/No delay from FSYNC edge.
[2] FSYNC_MODE (R/W)
FSYNC Mode Control
0: Low FSYNC is Left Channel in Stereo
Modes or Pulsed FSYNC Mode in TDM Modes.
1: High FSYNC is Left Channel in Stereo
Modes or 50% FSYNC Mode in TDM Modes.
[5:3] TDM_BCLKS (R/W)
Number of BCLKs per chip in TDM mode
000: 16 BCLKs per chip in TDM.
001: 24 BCLKs per chip in TDM.
010: 32 BCLKs per chip in TDM.
011: 48 BCLKs per chip in TDM.
100: 64 BCLKs per chip in TDM.
Table 25. Bit Descriptions for SAI Control 1
Bits
Bit Name
7
DAC_POL
6
[5:3]
2
1
0
Settings
Description
Reset
Access
DAC Output Polarity.
0x0
R/W
0x0
R/W
0x2
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0
Normal Operation.
1
Invert the Audio Output Signal.
BCLK_POL
BCLK Polarity Control.
0
Rising Edge of BCLK is Used to Register SDATA.
1
Falling Edge of BCLK is Used to Register SDATA.
Number of BCLKs per Chip in TDM Mode. Any number of BCLK cycles per FSYNC
can be used in stereo modes (I 2 S/LJ) or in TDM mode with only one chip. When in
TDM mode and having multiple chips on the TDM bus, the number of BCLKs per
chip must be defined.
TDM_BCLKS
000
16 BCLKs per Chip in TDM.
001
24 BCLKs per Chip in TDM.
010
32 BCLKs per Chip in TDM.
011
48 BCLKs per Chip in TDM.
100
64 BCLKs per Chip in TDM.
FSYNC_MODE
FSYNC Mode Control.
0
Low FSYNC is Left Channel in Stereo Modes or Pulsed FSYNC Mode in TDM
Modes.
1
High FSYNC is Left Channel in Stereo Modes or 50% FSYNC Mode in TDM Modes.
SDATA_FMT
Serial Data Format.
0
I 2 S/Delay by
1
Left Justified/No Delay from FSYNC Edge.
SAI_MODE
One from FSYNC Edge.
Serial Interface Mode Selection.
0
Stereo Modes (I 2 S, LJ).
1
TDM/PCM Modes.
Rev. A| Page 33 of 41
SSM3515
Data Sheet
SAI CONTROL 2 REGISTER
Address: 0x05, Reset: 0x00, Name: SAI Control 2
7
6
0 0
5
4
0 0
3
2
0 0
[7] DATA_W IDTH (R/W)
Audio Data W idth
0: Audio input on SDATA is 24 bits.
1: Audio input on SDATA is 16 bits.
[6:5] RESERVED
[4] AUTO_SLOT (R/W)
Automatic TDM Slot Selection
0: TDM Slot determined by TDM_SLOT register.
1: TDM Slot determined by ADDR pin.
1
0
0 0
[3:0] TDM_SLOT (R/W)
TDM Slot Selection
0000: Chip Slot 1 Used.
0001: Chip Slot 2 Used.
0010: Chip Slot 3 Used.
...
1101: Chip Slot 14 Used.
1110: Chip Slot 15 Used.
1111: Chip Slot 16 Used.
Table 26. Bit Descriptions for SAI Control 2
Bits
Bit Name
7
DATA_WIDTH
Settings
Description
Reset
Access
Audio Data Width.
0x0
R/W
0
Audio Input on SDATA is 24 Bits.
1
Audio Input on SDATA is 16 Bits.
[6:5]
RESERVED
Reserved.
0x0
R/W
4
AUTO_SLOT
Automatic TDM Slot Selection.
0x0
R/W
0x0
R/W
[3:0]
0
TDM Slot Determined by the TDM_SLOT Register.
1
TDM Slot Determined by the ADDR Pin.
TDM_SLOT
TDM Slot Selection.
0000
Chip Slot 1 Used.
0001
Chip Slot 2 Used.
0010
Chip Slot 3 Used.
0011
Chip Slot 4 Used.
0100
Chip Slot 5 Used.
0101
Chip Slot 6 Used.
0110
Chip Slot 7 Used.
0111
Chip Slot 8 Used.
1000
Chip Slot 9 Used.
1001
Chip Slot 10 Used.
1010
Chip Slot 11 Used.
1011
Chip Slot 12 Used.
1100
Chip Slot 13 Used.
1101
Chip Slot 14 Used.
1110
Chip Slot 15 Used.
1111
Chip Slot 16 Used.
Rev. A| Page 34 of 41
Data Sheet
SSM3515
BATTERY VOLTAGE OUTPUT REGISTER
Address: 0x06, Reset: 0x00, Name: Battery Voltage Output
7
6
0 0
5
4
0 0
3
2
0 0
1
0
0 0
[7:0] VBAT (R)
8-Bit Unsigned Battery Voltage
Table 27. Bit Descriptions for Battery Voltage Output
Bits
Bit Name
[7:0]
VBAT
Settings
Description
Reset
Access
8-Bit Unsigned Battery Voltage
0x0
R
LIMITER CONTROL 1 REGISTER
Address: 0x07, Reset: 0xA4, Name: Limiter Control 1
7
6
1
0 1
5
4
3
0 0
1
0
1 0
2
0
[7:6] LIM_RRT (R/W)
Limiter Release Rate
00: 3200 ms/dB.
01: 1600 ms/dB.
10: 1200 ms/dB.
11: 800 ms/dB.
[1:0] LIM_EN (R/W)
Limiter or Mute Mode Enable
00: Limiter and Mute Mode Off.
01: Limiter On.
10: Output mutes if VBAT is below VBAT_INF.
11: Limiter On but only engages if VBAT
is below VBAT_INF.
[5:4] LIM_ATR (R/W)
Limiter Attack Rate
00: 120 us/dB.
01: 60 us/dB.
10: 30 us/dB.
11: 20 us/dB.
[2] VBAT_TRACK (R/W)
Threshold Battery Tracking Enable
0: Limiter Attack Threshold Fixed.
1: Limiter Attack Threshold Varies or gain
reduction with Battery Voltage.
[3] RESERVED
Table 28. Bit Descriptions for Limiter Control 1
Bits
Bit Name
[7:6]
LIM_RRT
[5:4]
Settings
Description
Reset
Access
Limiter Release Rate.
0x2
R/W
0x2
R/W
00
3200 ms/dB.
01
1600 ms/dB.
10
1200 ms/dB.
11
800 ms/dB.
LIM_ATR
Limiter Attack Rate.
00
120 µs/dB.
01
60 µs/dB.
10
30 µs/dB.
11
20 µs/dB.
3
RESERVED
Reserved.
0x0
R/W
2
VBAT_TRACK
Threshold Battery Tracking Enable.
0x1
R/W
0x0
R/W
[1:0]
0
Limiter Attack Threshold Fixed.
1
Limiter Attack Threshold Varies or Gain Reduction with Battery Voltage.
LIM_EN
Limiter or Mute Mode Enable.
00
Limiter and Mute Mode Off.
01
Limiter On.
10
Output Mutes if VBAT is Below VBAT_INF.
11
Limiter On But Only Engages if VBAT is Below VBAT_INF.
Rev. A| Page 35 of 41
SSM3515
Data Sheet
LIMITER CONTROL 2 REGISTER
Address: 0x08, Reset: 0x51, Name: Limiter Control 2
7
6
0
1 0
5
4
3
1 0
1
0
0 0
2
1
[7:3] LIM_THRES (R/W)
Limiter Attack Threshold
00000: 15.0 V peak Output.
00001: 14.5 V peak Output.
00010: 14.0 V peak Output.
...
11101: 2.0 V peak Output.
11110: 1.5V V peak Output.
11111: 1.0 V peak Output.
[1:0] SLOPE (R/W)
Slope of threshold reduction/battery voltage
change
00: 1:1 Threshold/Battery Reduction.
01: 2:1 Threshold/Battery Reduction.
10: 3:1 Threshold/Battery Reduction.
11: 4:1 Threshold/Battery Reduction.
[2] RESERVED
Table 29. Bit Descriptions for Limiter Control 2
Bits
Bit Name
[7:3]
LIM_THRES
Settings
Description
Reset
Access
Limiter Attack Threshold.
0xA
R/W
00000
15.0 V peak Output.
00001
14.5 V peak Output.
00010
14.0 V peak Output.
00011
13.5 V peak Output.
00100
13.0 V peak Output.
00101
12.5 V peak Output.
00110
12.0 V peak Output.
00111
11.5 V peak Output.
01000
11.0 V peak Output.
01001
10.5 V peak Output.
01010
10.0 V peak Output.
01011
9.5 V peak Output.
01100
9.0 V peak Output.
01101
8.5 V peak Output.
01110
8.25 V peak Output.
01111
8.0 V peak Output.
10000
7.75 V peak Output.
10001
7.5 V peak Output.
10010
7.25 V peak Output.
10011
7.0 V peak Output.
10100
6.5 V peak Output.
10101
6.0 V peak Output.
10110
5.5 V peak Output.
10111
5.0 V peak Output.
11000
4.5 V peak Output.
11001
4.0 V peak Output.
11010
3.5 V peak Output.
11011
3.0 V peak Output.
11100
2.5 V peak Output.
11101
2.0 V peak Output.
11110
1.5 V peak Output.
11111
1.0 V peak Output.
Rev. A| Page 36 of 41
Data Sheet
Bits
Bit Name
2
[1:0]
SSM3515
Settings
Description
Reset
Access
RESERVED
Reserved.
0x0
R/W
SLOPE
Slope of Threshold Reduction/Battery Voltage Change.
0x1
R/W
00
1:1 Threshold/Battery Reduction.
01
2:1 Threshold/Battery Reduction.
10
3:1 Threshold/Battery Reduction.
11
4:1 Threshold/Battery Reduction.
LIMITER CONTROL 3 REGISTER
Address: 0x09, Reset: 0x22, Name: Limiter Control 3
7
6
0 0
5
4
1 0
3
2
0 0
1
0
1 0
[7:0] VBAT_INF (R/W)
Battery Voltage Inflection Point
Table 30. Bit Descriptions for Limiter Control 3
Bits
[7:0]
Bit Name
Settings
VBAT_INF
Description
Reset
Access
Battery Voltage Inflection Point. This is the VBAT sense value at which the limiter either
activates or starts reducing the threshold. It corresponds to the value that can be read
in the VBAT read only status register. To calculate this value in volts, refer to the VBAT
Sensing section. Voltage = 3.8 + 12.4 × Decimal Value/255.
0x22
R/W
STATUS REGISTER
Address: 0x0A, Reset: 0x00, Name: Status
7
6
0
0 0
5
4
3
0 0
1
0
0 0
2
0
[7] RESERVED
[0] BAT_W ARN (R)
Battery Voltage W arning
0: Battery Voltage above VBAT_INF.
1: Battery Voltage at or below VBAT_INF.
[6] UVLO_VREG (R)
Regulator Undervoltage Fault Status
0: Normal Operation.
1: Voltage Regulator Fault Condition.
[1] OTW (R)
Over Temperature Warning Status
0: Normal Operation.
1: Over Temperature Warning Condition.
[5] LIM_EG (R)
Limiter/Gain Reduction Engaged
0: Normal Operation.
1: Limiter or Gain Reduction has Reduced
Gain.
[2] OTF (R)
Over Temperature Fault Status
0: Normal Operation.
1: Over Temperature Fault Condition.
[4] CLIP (R)
Clip Detector
0: Normal Operation.
1: Amplifier Clipping Detected.
[3] AMP_OC (R)
Amplifier Over-Current Fault Status
0: Normal Operation.
1: Amp Over-Current Fault Condition.
Table 31. Bit Descriptions for Status
Bits
Bit Name
7
6
5
Settings
Description
Reset
Access
RESERVED
Reserved.
0x0
R
UVLO_VREG
Regulator Undervoltage Fault Status.
0x0
R
0x0
R
0
Normal Operation.
1
Voltage Regulator Fault Condition.
LIM_EG
Limiter/Gain Reduction Engaged.
0
Normal Operation.
1
Limiter or Gain Reduction has Reduced Gain.
Rev. A| Page 37 of 41
SSM3515
Data Sheet
Bits
Bit Name
4
CLIP
3
2
1
0
Settings
Description
Reset
Access
Clip Detector.
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0
Normal Operation.
1
Amplifier Clipping Detected.
AMP_OC
Amplifier Overcurrent Fault Status.
0
Normal Operation.
1
Amp Over-Current Fault Condition.
OTF
Overtemperature Fault Status.
0
Normal Operation.
1
Overtemperature Fault Condition.
OTW
Overtemperature Warning Status.
0
Normal Operation.
1
Overtemperature Warning Condition.
BAT_WARN
Battery Voltage Warning.
0
Battery Voltage Above VBAT_INF.
1
Battery Voltage at or Below VBAT_INF.
FAULT CONTROL REGISTER
Address: 0x0B, Reset: 0x18, Name: Fault Control
7
6
0 0
5
4
0 1
3
2
1 0
1
0
0 0
[7:6] OTW_GAIN (R/W)
Over Thermal W arning Gain Reduction
00: No gain reduction in thermal warning.
01: 1.5dB gain reduction in thermal warning.
10: 3dB gain reduction in thermal warning.
11: 5.625dB gain reduction in thermal warning.
[0] ARCV_OC (R/W)
Over Current Automatic Fault Recovery Control
0: Automatic Fault Recovery for Over-Current
Fault.
1: Manual Fault Recovery for Over-Current
Fault.
[5] MRCV (W)
Manual Fault Recovery
0: Normal Operation.
1: W riting of 1 causes a manual fault
recovery attempt when ARCV=11.
[1] ARCV_OT (R/W)
Overtemperature Automatic Fault Recovery Control
0: Automatic Fault Recovery for Overtemperature
Fault.
1: Manual Fault Recovery for Overtemperature
Fault.
[4:3] MAX_AR (R/W)
Maximum Fault recovery Attempts
00: 1 Auto Recovery Attempt.
01: 3 Auto Recovery Attempts.
10: 7 Auto Recovery Attempts.
11: Unlimited Auto Recovery Attempts.
[2] ARCV_UV (R/W)
Undervoltage Automatic Fault Recovery Control
0: Automatic Fault Recovery for Undervoltage
Fault.
1: Manual Fault Recovery for Undervoltage
Fault.
Table 32. Bit Descriptions for Fault Control
Bits
Bit Name
[7:6]
OTW_GAIN
5
Settings
Description
Reset
Access
Over Thermal Warning Gain Reduction.
0x0
R/W
0x0
W
00
No Gain Reduction in Thermal Warning.
01
1.5 dB Gain Reduction in Thermal Warning.
10
3 dB Gain Reduction in Thermal Warning.
11
5.625 dB Gain Reduction in Thermal Warning.
MRCV
Manual Fault Recovery.
0
Normal Operation.
1
Writing of 1 Causes a Manual Fault Recovery Attempt when ARCV = 11.
Rev. A| Page 38 of 41
Data Sheet
Bits
Bit Name
[4:3]
MAX_AR
SSM3515
Settings
1
0
Reset
Access
Maximum Fault Recovery Attempts. The maximum autorecovery register
determines how many attempts at autorecovery are performed.
0x3
R/W
0x0
R/W
0x0
R/W
0x0
R/W
00
1 Autorecovery Attempt.
01
3 Autorecovery Attempts.
10
7 Autorecovery Attempts.
11
2
Description
ARCV_UV
Unlimited Autorecovery Attempts.
Undervoltage Automatic Fault Recovery Control.
0
Automatic Fault Recovery for Undervoltage Fault.
1
Manual Fault Recovery for Undervoltage Fault.
ARCV_OT
Overtemperature Automatic Fault Recovery Control.
0
Automatic Fault Recovery for Overtemperature Fault.
1
Manual Fault Recovery for Overtemperature Fault.
ARCV_OC
Overcurrent Automatic Fault Recovery Control.
0
Automatic Fault Recovery for Overcurrent Fault.
1
Manual Fault Recovery for Overcurrent Fault.
Rev. A| Page 39 of 41
SSM3515
Data Sheet
TYPICAL APPLICATION CIRCUIT
Figure 75 shows a typical application circuit for a single channel output.
REG_EN
R3 0Ω EXTERNAL DVDD
R4 0Ω INTERNAL DVDD
PVDD
R4
I2C
R2
2.2kΩ
SCL
SDA
REG_EN
I2C
FSYNC
SDATA
TDM
I2S
INPUT
C1
2.2µF
C4
0.1µF
VREG50/AVDD
VREG18/DVDD
PVDD
REG
REG
AVDD
DVDD
BCLK
I2S/TDM
C3
1µF
VOLUME
SSM3515
DAC
Σ-∆
CLASS-D
MODULATOR
PVDD
BST+
FULL
BRIDGE
POWER
STAGE
AGND
C5
0.22µF
OUT+
PGND
C6
0.22µF
FB1
C7
220pF
4Ω/8Ω
C8
220pF
FB1/FB2: MURATA FERRITE BEAD NFZ2MSM181
SEE THE ADDR PIN SETUP AND CONTROL SECTION
Figure 75. Typical Application Circuit for Single Channel Output
Rev. A| Page 40 of 41
OPTIONAL
FB2
OUT–
BST–
ADDR
PVDD
+4.5V TO +17V
C6
C5
10µF 470µF
13327-184
C2
0.1uF
R1
2.2kΩ
+5V (AVDD)
+1.8V (DVDD)
R3
+1.8V
Data Sheet
SSM3515
OUTLINE DIMENSIONS
1.840
1.800
1.760
4
3
2
1
A
BALL A1
IDENTIFIER
B
2.240
2.200
2.160
1.60 REF
C
D
E
0.40
BSC
BOTTOM VIEW
TOP VIEW
(BALL SIDE UP)
(BALL SIDE DOWN)
1.20 REF
SIDE VIEW
COPLANARITY
0.05
0.300
0.260
0.220
SEATING
PLANE
0.230
0.200
0.170
12-19-2012-A
0.560
0.500
0.440
Figure 76. 20-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-20-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
SSM3515CCBZ-RL
SSM3515CCBZ-R7
EVAL-SSM3515Z
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
20-Ball Wafer Level Chip Scale Package [WLCSP]
20-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13327-0-1/17(A)
Rev. A| Page 41 of 41
Package Option
CB-20-10
CB-20-10
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