EVAL-SSM4321Z

Data Sheet Mono 2.9 W Class-D Audio Amplifier with Digital Current and Voltage Output SSM4321 FEATURES Filterless Class-D amplifier with spread-spectrum Σ-Δ modulation Digitized output of output voltage, output current, and PVDD supply voltage 72 dB signal-to-noise ratio (SNR) on output current sensing and 77 dB SNR on output voltage sensing TDM or multichip I2S slave output interface Up to 4 chips supported on a single bus 8 kHz to 48 kHz operation I2S/left justified slave output interface 1 or 2 chips supported on a single bus 8 kHz to 48 kHz operation PDM output interface operates from 1 MHz to 6.144 MHz 2.2 W into 4 Ω load and 1.4 W into 8 Ω load at 5.0 V supply with 100 dB signal-to-noise ratio (SNR) High PSRR at 217 Hz: 86 dB Amplifier supply operation from 2.5 V to 5.5 V Input/output supply operation from 1.42 V to 3.6 V Flexible gain adjustment pin: 0 dB to 12 dB in 3 dB steps with fixed input impedance of 80 kΩ 0V The gain of the SSM4321 can be set from 0 dB to 12 dB in 3 dB steps using the GAIN pin and one (optional) external resistor. The external resistor is used to select the 9 dB or 12 dB gain setting (see Table 6). +5V OUT+ 0V +5V OUT– 0V +5V VOUT Table 6. Setting the Gain of the SSM4321 with the GAIN Pin GAIN Pin Configuration Tie to GND Open Tie to PVDD Tie to GND through a 47 kΩ resistor Tie to PVDD through a 47 kΩ resistor 0V OUTPUT < 0V +5V OUT+ 0V +5V OUT– 0V 0V VOUT –5V Figure 38. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus Rev. 0 | Page 14 of 24 10752-015 Gain Setting (dB) 0 3 6 9 12 0V Data Sheet SSM4321 EMI NOISE The SSM4321 uses a proprietary modulation and spread-spectrum technology to minimize EMI emissions from the device. For applications that have difficulty passing FCC Class B emission tests or experience antenna and RF sensitivity problems, the ultralow EMI architecture of the SSM4321 significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. EMI emission tests on the SSM4321 were performed in an FCCcertified EMI laboratory with a 1 kHz input signal, producing 0.5 W of output power into an 8 Ω load from a 5.0 V supply. The SSM4321 passed FCC Class B limits with 50 cm of unshielded twisted pair speaker cable. Note that reducing the power supply voltage greatly reduces radiated emissions. OUTPUT CURRENT SENSING The SSM4321 uses an external sense resistor to determine the output current flowing to the load. As shown in Figure 1, one end of the sense resistor is tied to one amplifier output pin (OUT+); the other end of the sense resistor is tied to the load, which is also connected to one sense input pin (SENSE−). The voltage across the sense resistor is proportional to the load current and is sent to an analog-to-digital converter (ADC) running nominally at 128 fS. The output of this ADC is downsampled using digital filtering. The downsampled signal is output at a rate of 8 kHz to 48 kHz on Slot 1 of the TDM bus. The 16-bit data is in signed fractional format. The current sense output is scaled so that an output current of 0.75 A (6 V/8 Ω) with a 200 mΩ sense resistor results in full-scale output from the ADC. Table 7 lists the optimal sense resistor values for commonly used output loads. Table 7. Optimal Sense Resistor for Typical Loads Load Value (Ω) 8 4 3 Peak Current (A) 0.75 1.5 2 Sense Resistor (mΩ) 200 100 75 OUTPUT VOLTAGE SENSING The output voltage level is monitored and sent to an ADC running nominally at 128 fS. The output of this ADC is downsampled using digital filtering. The downsampled signal is output at a rate of 8 kHz to 48 kHz on Slot 2 of the TDM bus. The 16-bit data is in signed fractional format. PVDD SENSING The SSM4321 contains an 8-bit ADC that measures the voltage of the PVDD supply in real time. The output of the ADC is in 8-bit unsigned format and is presented on the 8 MSBs of Slot 3 on the TDM bus. The eight LSBs are driven low. Rev. 0 | Page 15 of 24 SSM4321 Data Sheet SERIAL DATA INPUT/OUTPUT The SSM4321 includes circuitry to sense output current, output voltage, and the PVDD supply voltage. The output current, output voltage, and PVDD voltage are sent to ADCs. The output of these ADCs is available on the TDM or I2S output serial port. A direct PDM bit stream of voltage and current data (or current and PVDD data) can also be selected. TDM OPERATING MODE The digitized output current, output voltage, and PVDD sense signals can be output on a TDM serial port. This serial port is always a slave and requires a bit clock (BCLK) and a frame synchronization signal (FSYNC) to operate. The output data is driven on the SDATAO/PDM_DATA pin at the IOVDD voltage. (See the Timing Diagrams, TDM Mode section.) The FSYNC signal operates at the desired sample rate. A rising edge of the FSYNC signal indicates the start of a new frame. For proper operation, this signal should be one BCLK cycle wide, transitioning on a falling BCLK edge. The MSB of the Slot 1 data is output on the SDATAO/PDM_DATA pin one BCLK cycle later. The SDATAO signal should be latched on a rising edge of BCLK. Each slot is 64 BCLK cycles wide. The SSM4321 can drive only four slots on its output, but it can work with 8 slots, 12 slots, or 16 slots. In this way, up to four SSM4321 devices can use the same TDM bus. At startup, the number of slots used is recognized automatically by the number of BCLK cycles between FSYNC pulses. Internal clocking is automatically generated from BCLK based on the determined BCLK rate. The set of four TDM slots to be driven is determined by the configuration of the SLOT pin on the SSM4321 (see Table 8). The value of the SLOT pin must be stable at startup. Table 8. TDM Slot Selection Device Setting TDM Slot 1 to Slot 4 used TDM Slot 5 to Slot 8 used TDM Slot 9 to Slot 12 used TDM Slot 13 to Slot 16 used With a single SSM4321 operating with four slots, Slot 1 is for the output current, Slot 2 is for the output voltage, Slot 3 is for the PVDD supply, and Slot 4 is not driven. With more than four slots, this pattern is repeated. Table 9 shows an example with three SSM4321 devices and 12 TDM slots. Table 9. TDM Output Slot Example—Three SSM4321 Devices TDM Slot 1 2 3 4 5 6 7 8 9 10 11 12 Data Present Output current, Device 1 Output voltage, Device 1 PVDD voltage, Device 1 High-Z Output current, Device 2 Output voltage, Device 2 PVDD voltage, Device 2 High-Z Output current, Device 3 Output voltage, Device 3 PVDD voltage, Device 3 High-Z I2S AND LEFT JUSTIFIED OPERATING MODE An I2S or left justified output interface can be selected by reversing the pin connections for BCLK and FSYNC; that is, the I2S LRCLK is connected to Ball D3 (BCLK_TDM/PDM_CLK/LRCLK_I2S), and the I2S BCLK is connected to Ball D2 (FSYNC_TDM/ BCLK_I2S). The I2S interface requires 64 BCLK cycles per LRCLK cycle. The voltage information is sent when LRCLK is low, and the current information is sent when LRCLK is high. (See the Timing Diagrams, I2S and Left Justified Modes section.) The SLOT pin configures the I2S or left justified output as follows (see Table 10). SLOT Pin Configuration Tie to IOVDD Open Tie to GND Tie to IOVDD through a 47 kΩ resistor • • The SSM4321 sets the SDATAO/PDM_DATA pin to a high impedance state when a slot is present that is not being driven. Connect a pull-down resistor to the SDATAO/PDM_DATA pin so that it is always in a known state. • Selection of I2S or left justified mode. Output of PVDD sense information. When PVDD data is output, eight bits are appended to the 16-bit voltage sense data to create a 24-bit output. The 16 MSBs represent the voltage data; the eight LSBs represent the PVDD data. Sample rate range. The sample rate ranges from 16 kHz to 48 kHz. A range of 32 kHz to 48 kHz is also allowed in low power I2S mode. Table 10. I2S and Left Justified Slot Selection Device Setting I2S mode at 16 kHz to 48 kHz; voltage and current data only Left justified mode at 16 kHz to 48 kHz; voltage and current data only I2S mode at 16 kHz to 48 kHz; PVDD data appended to voltage data Left justified mode at 16 kHz to 48 kHz; PVDD data appended to voltage data Low power I2S mode at 32 kHz to 48 kHz; voltage and current data only Rev. 0 | Page 16 of 24 BCLK Setting 64 × fS 64 × fS 64 × fS 64 × fS 32 × fS or 64 × fS SLOT Pin Configuration Tie to IOVDD Open Tie to GND Tie to IOVDD through a 47 kΩ resistor Tie to GND through a 47 kΩ resistor Data Sheet SSM4321 MULTICHIP I2S OPERATING MODE A special multichip I2S mode is enabled when the part is wired for TDM mode (BCLK and FSYNC not reversed) but the FSYNC signal has a 50% duty cycle. If the FSYNC signal consists of oneclock-cycle pulses, TDM operating mode is active instead. The multichip I2S interface allows multiple chips to drive a single I2S bus. Each chip takes control of the bus every two or four frames (depending on the number of chips placed on the bus), allowing a maximum of four chips on the bus. The SLOT pin assignments determine the order of control. (See the Timing Diagrams, Multichip I2S Mode section.) Each frame also contains a 1-bit ID code, which is appended to the current data in the frame. This code indicates the chip that sent the data for that frame. Table 11 provides the mapping of SLOT pin assignments to ID code. Table 11. Multichip I2S Slot Selection Chip No. 1 2 3 4 ID Code 0001 0010 0100 1000 SLOT Pin Configuration Tie to IOVDD Open Tie to GND Tie to IOVDD through a 47 kΩ resistor The part is automatically configured for two-chip or four-chip operation, depending on the number of chips detected on the bus. The part starts up in four-chip operation, but after it detects that Slot 3 and Slot 4 are unused, the part switches to two-chip operation. For two-chip operation, the first and second slots must be used. If there are three chips on the bus, Slot 1 must be used along with any two other slots. Table 12 lists the FSYNC and BCLK rates that are supported in multichip I2S mode. Table 12. FSYNC and BCLK Rates in Multichip I2S Mode, fS = 16 kHz to 48 kHz Valid Slots 1 and 2 1, 2, 3, 4 FSYNC Rate 2 × fS (32 kHz to 96 kHz) 4 × fS (64 kHz to 128 kHz) BCLK Rate 128 × fS (2.048 MHz to 6.144 MHz) 256 × fS (4.096 MHz to 12.288 MHz) PDM OUTPUT MODE By connecting the SLOT pin to GND through a 47 kΩ resistor, the 1-bit PDM data from the ADCs can be output directly. In PDM mode, a 1 MHz to 6.144 MHz clock must be provided on Ball D3 (BCLK_TDM/PDM_CLK/LRCLK_I2S). PDM data is sent on both edges of the clock and is output on Ball D1 (SDATAO/ PDM_DATA). (See the Timing Diagrams, PDM Mode section.) In PDM mode, Ball D2 (FSYNC_TDM/BCLK_I2S) is used to select the information that is output on the two possible channels (see Table 13). Table 13. FSYNC_TDM Pin Settings for PDM Mode Output Data Current data on rising edge; voltage data on falling edge Current data on rising edge; PVDD data on falling edge Rev. 0 | Page 17 of 24 FSYNC_TDM Pin Tie to IOVDD Tie to GND SSM4321 Data Sheet TIMING DIAGRAMS, TDM MODE TDM Mode, One Device SLOT pin is tied to IOVDD. BCLK_TDM 64 BCLKs CURRENT SDATAO 16 BCLKs VOLTAGE PVDD 16 BCLKs 8 BCLKs 10752-016 FSYNC_TDM Figure 39. TDM Mode, One Device TDM Mode, Two Devices IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open. BCLK_TDM 128 BCLKs FSYNC_TDM 16 BCLKs CURRENT, IC 1 VOLTAGE, IC 1 8 BCLKs 16 BCLKs PVDD, IC 1 CURRENT, IC 2 16 BCLKs 8 BCLKs VOLTAGE, IC 2 64 BCLKs 10752-017 16 BCLKs SDATAO PVDD, IC 2 64 BCLKs Figure 40. TDM Mode, Two Devices TDM Mode, Three Devices IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open; IC 3: SLOT pin is tied to GND. BCLK_TDM 192 BCLKs FSYNC_TDM SDATAO 16 BCLKs 8 BCLKs CURRENT, IC 1 VOLTAGE, IC 1 PVDD, IC 1 16 BCLKs 16 BCLKs 8 BCLKs 16 BCLKs CURRENT, IC 2 VOLTAGE, IC 2 PVDD, IC 2 64 BCLKs 16 BCLKs 8 BCLKs CURRENT, IC 3 VOLTAGE, IC 3 PVDD, IC 3 64 BCLKs 64 BCLKs 10752-018 16 BCLKs Figure 41. TDM Mode, Three Devices TIMING DIAGRAMS, I2S AND LEFT JUSTIFIED MODES I2S and Left Justified Modes with Voltage, Current, and PVDD Output, 64 × fS I2S output mode: SLOT pin is tied to GND. Left justified output mode: SLOT pin is tied to IOVDD through a 47 kΩ resistor. BCLK_I2S 64 BCLKs LRCLK_I2S SDATAO LJ VOLTAGE 16 BCLKs VOLTAGE 16 BCLKs PVDD 8 BCLKs PVDD 8 BCLKs CURRENT 16 BCLKs CURRENT 16 BCLKs Figure 42. I2S and Left Justified Modes with Voltage, Current, and PVDD Output, 64 × fS Rev. 0 | Page 18 of 24 10752-019 SDATAO I2S Data Sheet SSM4321 I2S and Left Justified Modes with Voltage and Current Output Only, 64 × fS I2S output mode: SLOT pin is tied to IOVDD (or tied to GND through a 47 kΩ resistor for low power operation at 64 × fS). Left justified output mode: SLOT pin is open. BCLK_I2S 64 BCLKs LRCLK_I2S SDATAO LJ VOLTAGE 16 BCLKs CURRENT 16 BCLKs VOLTAGE 10752-020 SDATAO I2S CURRENT 16 BCLKs 16 BCLKs Figure 43. I2S and Left Justified Modes with Voltage and Current Output Only, 64 × fS I2S Low Power Mode with Voltage and Current Output Only, 32 × fS SLOT pin is tied to GND through a 47 kΩ resistor for low power operation at 32 × fS. BCLK_I2S 32 BCLKs SDATAO I2S VOLTAGE 10752-021 LRCLK_I2S CURRENT 16 BCLKs 16 BCLKs Figure 44. I2S Low Power Mode with Voltage and Current Output Only, 32 × fS TIMING DIAGRAMS, MULTICHIP I2S MODE Multichip I2S Mode with Two Devices on the Bus IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open. BCLK_TDM 64 BCLKs FSYNC_TDM SDATAO VOLTAGE, IC 1 8 BCLKs 16 BCLKs PVDD, IC 1 16 BCLKs CURRENT, IC 1 ID VOLTAGE, IC 2 8 BCLKs PVDD, IC 2 16 BCLKs CURRENT, IC 2 ID 10752-022 4 BCLKs 4 BCLKs 16 BCLKs 2 Figure 45. Multichip I S Mode with Two Devices on the Bus Multichip I2S Mode with Three or Four Devices on the Bus IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open; IC 3: SLOT pin is tied to GND; IC 4: SLOT pin is tied to IOVDD through a 47 kΩ resistor. BCLK_TDM 64 BCLKs FSYNC_TDM 4 BCLKs 4 BCLKs 16 BCLKs SDATAO VOLTAGE, IC 1 8 BCLKs PVDD, IC 1 16 BCLKs CURRENT, IC 1 16 BCLKs ID VOLTAGE, IC 2 8 BCLKs PVDD, IC 2 16 BCLKs CURRENT, IC 2 ID BCLK_TDM FSYNC_TDM SDATAO VOLTAGE, IC 3 8 BCLKs PVDD, IC 3 16 BCLKs CURRENT, IC 3 16 BCLKs ID VOLTAGE, IC 4 8 BCLKs PVDD, IC 4 Figure 46. Multichip I2S Mode with Three or Four Devices on the Bus Rev. 0 | Page 19 of 24 16 BCLKs CURRENT, IC 4 ID 10752-023 4 BCLKs 4 BCLKs 16 BCLKs SSM4321 Data Sheet TIMING DIAGRAMS, PDM MODE PDM Mode with Current and Voltage Output SLOT pin is tied to GND through a 47 kΩ resistor; FSYNC_TDM pin is tied to IOVDD. PDM_CLK PDM_DATA I V I V I V I V I V I V I V I V I V I V I V I V I 10752-024 FSYNC_TDM Figure 47. PDM Mode with Current and Voltage Output PDM Mode with Current and PVDD Output SLOT pin is tied to GND through a 47 kΩ resistor; FSYNC_TDM pin is tied to GND. PDM_CLK PDM_DATA I PVDD I PVDD I PVDD I PVDD I PVDD I PVDD I PVDD I PVDD Figure 48. PDM Mode with Current and PVDD Output Rev. 0 | Page 20 of 24 I PVDD I PVDD I PVDD I PVDD I 10752-025 FSYNC_TDM Data Sheet SSM4321 APPLICATIONS INFORMATION LAYOUT INPUT CAPACITOR SELECTION As output power increases, care must be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. The SSM4321 does not require input coupling capacitors if the input signal is biased from 1.0 V to PVDD − 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if a single-ended source is used. If high-pass filtering is needed at the input, the input capacitor (CIN) and the input impedance of the SSM4321 (80 kΩ) form a high-pass filter with a corner frequency determined by the following equation: Proper grounding helps to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load, as well as the PCB traces to the supply pins, should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. The input capacitor value and the dielectric material can significantly affect the performance of the circuit. Not using input capacitors degrades both the output offset voltage of the amplifier and the dc PSRR performance. In addition, good PCB layout isolates critical analog paths from sources of high interference. Separate high frequency circuits (analog and digital) from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be directly beneath the analog power plane, and, similarly, the digital ground plane should be directly beneath the digital power plane. There should be no overlap between the analog and digital ground planes or between the analog and digital power planes. fC = 1/(2π × 80 kΩ × CIN) POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with a good quality, low ESL, low ESR capacitor, with a minimum value of 4.7 µF. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 µF capacitor as close as possible to the PVDD pin of the device. Placing the decoupling capacitors as close as possible to the SSM4321 helps to maintain efficient performance. Rev. 0 | Page 21 of 24 SSM4321 Data Sheet OUTLINE DIMENSIONS 1.780 1.740 SQ 1.700 4 3 2 1 A BALL A1 IDENTIFIER B 1.20 REF C D 0.40 REF TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.560 0.500 0.440 SIDE VIEW 0.300 0.260 0.220 SEATING PLANE 0.230 0.200 0.170 07-13-2011-A COPLANARITY 0.05 Figure 49. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-15) Dimensions shown in millimeters ORDERING GUIDE Model1 SSM4321ACBZ-R7 SSM4321ACBZ-RL EVAL-SSM4321Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. This package option is halide free. Rev. 0 | Page 22 of 24 Package Option2 CB-16-15 CB-16-15 Branding Y4E Y4E Data Sheet SSM4321 NOTES Rev. 0 | Page 23 of 24 SSM4321 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 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