EVAL01-HMC955LC4B

HMC955LC4B v01.0322 MUX & DEMUX - SMT 32 Gbps, 1:2 DEMUX WITH PROGRAMMABLE OUTPUT VOLTAGE Typical Applications Features The HMC955LC4B is ideal for: Supports Data Rates up to 32 Gbps • SONET OC-192 660 mW Power Consumption • Broadband Test & Measurement Equipment -3.3 V or +3.3 V Operation is Available • FPGA Interfacing Circuitry Supports Single-Ended and Differential Operation • 16 G and 32 G Fiber Channel 24 Lead Ceramic 4x4 mm SMT Package: 16 mm 2 • 100 Gbit Ethernet Invert Port Allows Scrambling for SERDES Application • ADC Encoder Functional Diagram General Description The HMC955LC4B is a 1 to 2 Demux designed to support data transmission rates up to 32 Gbps. The demux uses both rising and falling edges of the half-rate clock to sample the data in sequence 01-02 and latches the data on the rising edge into the differential outputs. The demux also has high-speed clock synchronous invert input that allows for scrambling of the data. The HMC955LC4B also features an output level control pin, VR, which allows for loss compensation or for signallevel optimization. All differential inputs to the HMC955LC4B are CML and terminated on-chip with 50 Ohms to the positive supply, GND, and may be AC or DC coupled. The differential CML outputs are source terminated to 50 Ohms and may also be AC or DC coupled. Outputs can be connected directly to a 50 Ohm ground-terminated system or drive devices with CML logic input. The HMC955LC4B operates from a single -3.3 V supply and is available in a ceramic ROHS-compliant 4x4 mm SMT package. Electrical Specifications, TA = +25 ºC, Vee = -3.3 V, VR = 0 V Parameter Conditions Power Supply Voltage (Vee) 1 Min. Typ. Max -3.6 -3.3 -3.0 Units V Power Supply Current 200 mA Maximum Data Rate 32 Gbps Maximum Clock Rate 16 GHz Input Voltage Range, C and DIN -1.5 0.5 V Input Differential Range, C and DIN 0.1 2.0 Vp-p Data Input Return Loss Frequency