EVALZ-ADN2917

Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ ADN2917 Data Sheet FEATURES GENERAL DESCRIPTION Serial data input: 8.5 Gbps to 11.3 Gbps No reference clock required Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 9.2 mV p-p typical (limiting amplifier mode) Optional limiting amplifier and equalizer inputs Programmable jitter transfer bandwidth to support G.8251 OTN Programmable slice level Sample phase adjust Output polarity invert Programmable LOS threshold via I2C I2C to access optional features LOS alarm (limiting amplifier mode only) LOL indicator PRBS generator/detector Application-aware power 352 mW at 8.5 Gbps, equalizer mode, no clock output 430 mW at 11.3 Gbps, equalizer mode, no clock output Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V 4 mm × 4 mm 24-lead LFCSP The ADN2917 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 8.5 Gbps to 11.3 Gbps. The ADN2917 automatically locks to all data rates without the need for an external reference clock or programming. ADN2917 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The ADN2917 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier or equalizer at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a userprogrammable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers. The ADN2917 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2917 is available in a compact 4 mm × 4 mm, 24-lead frame chip scale package (LFCSP). All ADN2917 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted. APPLICATIONS SONET/SDH OC-192, 10GFC, and 10GE and all associated FECs XFP, line cards, clocks, routers, repeaters, instruments Any rate regenerators/repeaters FUNCTIONAL BLOCK DIAGRAM SCK SDA LOL I2C REGISTERS FREQUENCY ACQUISITION AND LOCK DETECTOR LOS THRESH SLICE ADJUST I2C_ADDR REFCLKP/ REFCLKN (OPTIONAL) PIN 2 BYPASS NIN 50Ω 50Ω I2C VCM CML TXD DDR FIFO ÷N LA DATA INPUT SAMPLER CML CLK SAMPLE PHASE ADJUST LOS DETECT CLKOUTP/ CLKOUTN DATA RATE ADN2917 LOS DATOUTP/ DATOUTN RXD DOWNSAMPLER AND LOOP FILTER ÷2 DCO RXCK EQ CLOCK I2 C PHASE SHIFTER 11778-001 VCC FLOAT Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADN2917 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Functional Description .................................................................. 20  Applications ....................................................................................... 1  Frequency Acquisition ............................................................... 20  General Description ......................................................................... 1  Limiting Amplifier ..................................................................... 20  Functional Block Diagram .............................................................. 1  Slice Adjust .................................................................................. 20  Revision History ............................................................................... 2  Edge Select................................................................................... 20  Specifications..................................................................................... 3  Loss of Signal Detector .............................................................. 22  Jitter Specifications ....................................................................... 4  Passive Equalizer ........................................................................ 22  Output and Timing Specifications ............................................. 5  0 dB EQ ........................................................................................ 23  Timing Diagrams.......................................................................... 7  Lock Detector Operation .......................................................... 23  Absolute Maximum Ratings............................................................ 8  Output Disable and Squelch ..................................................... 24  Thermal Characteristics .............................................................. 8  I2C Interface ................................................................................ 24  ESD Caution .................................................................................. 8  Reference Clock (Optional) ...................................................... 24  Pin Configuration and Function Descriptions ............................. 9  Additional Features Available via the I2C Interface ............... 26  Typical Performance Characteristics ........................................... 10  Input Configurations ................................................................. 28  I C Interface Timing and Internal Register Descriptions ......... 12  DC-Coupled Application .......................................................... 31  Register Map ............................................................................... 13  Outline Dimensions ....................................................................... 32  Theory of Operation ...................................................................... 18  Ordering Guide .......................................................................... 32  2 REVISION HISTORY 8/2017—Rev. B to Rev. C Changed CP-24-8 to CP-24-7 ...................................... Throughout Changes to DATA_SWING[3:0] Bit Description and ClOCK_SWING[3:0] Bit Description, Table 19 ........................ 17 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 2/2016—Rev. 0 to Rev. A Changes to Figure 5 ...........................................................................9 Changes to Table 7.......................................................................... 13 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 5/2014—Revision 0: Initial Version 7/2017—Rev. A to Rev. B Change to Register CTRLC, Bit D0, Table 7 ............................... 13 Changes to Bit D0 Bit Name and Bit Description, Table 11 ..... 15 Updated Outlined Dimensions ..................................................... 32 Changes to Ordering Guide .......................................................... 32 Rev. C | Page 2 of 32 Data Sheet ADN2917 SPECIFICATIONS TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern: PRBS 223 − 1, ac-coupled, I2C register default settings, unless otherwise noted. Table 1. Parameter DATA RATE SUPPORT RANGE INPUT—DC CHARACTERISTICS Peak-to-Peak Differential Input1 Input Resistance BYPASS PATH—CML INPUT Input Voltage Range Input Common-Mode Level Differential Input Sensitivity OC-192 8GFC2 LIMITING AMPLIFIER INPUT PATH Differential Input Sensitivity OC-192 8GFC2 10.3125 Gbps EQUALIZER INPUT PATH Differential Input Sensitivity 8GFC2 OC-192 INPUT—AC CHARACTERISTICS S11 LOS DETECT Loss of Signal Detect Test Conditions/Comments PIN – NIN Differential At PIN or NIN, dc-coupled, RX_TERM_FLOAT = 1 (float) DC-coupled (see Figure 32), 600 mV p-p differential, RX_TERM_FLOAT = 1 (float) DCO Frequency Error for LOL Deassert LOL Assert Response Time ACQUISITION TIME Lock to Data (LTD) Mode Optional LTR Mode4 DATA RATE READBACK ACCURACY Coarse Readback Fine Readback Typ 95 100 0.5 0.65 Max 11.3 Unit Gbps 1.0 105 V Ω VCC VCC − 0.15 V V AC-coupled, RX_TERM_FLOAT = 0 (VCM = 1.2 V), bit error rate (BER) = 1 × 10−10 Jitter tolerance scrambled pattern (JTSPAT), ac-coupled, RX_TERM_FLOAT = 0 (VCM = 1.2 V), BER = 1 × 10−12 200 mV p-p 200 mV p-p BER = 1 × 10−10 JTSPAT, BER = 1 × 10−12 JTSPAT, BER = 1 × 10−12 9.2 8.3 11.0 mV p-p mV p-p mV p-p 15-inch FR-4, 100 Ω differential transmission line, adaptive EQ on JTSPAT, BER = 1 × 10−12 BER = 1 × 10−10 115 184 mV p-p mV p-p At 7.5 GHz, differential return loss, see Figure 9 −12 dB 10 5 128 5.7 135 110 mV p-p mV p-p mV p-p dB μs μs 1000 ppm 250 25 18 ppm μs μs 0.5 0.5 0.5 6.0 ms ms ms ms ±5 ±100 % ppm Loss of signal minimum program value Loss of signal maximum program value Hysteresis (Electrical) LOS Assert Time LOS Deassert Time LOSS OF LOCK (LOL) DETECT DCO Frequency Error for LOL Assert Min 8.5 AC-coupled3 AC-coupled3 With respect to nominal, data collected in lock to reference (LTR) mode With respect to nominal, data collected in LTR mode 8.5 Gbps, JTSPAT 10 Gbps OC192 11.3 Gbps 8.5 Gbps, JTSPAT In addition to reference clock accuracy Rev. C | Page 3 of 32 ADN2917 Parameter POWER SUPPLY VOLTAGE VCC VDD VCC1 POWER SUPPLY CURRENT VCC VDD VCC1 TOTAL POWER DISSIPATION Clock Output Enabled Clock Output Disabled Data Sheet Test Conditions/Comments Min Typ Max Unit 1.14 2.97 1.62 1.2 3.3 1.8 1.26 3.63 3.63 V V V Limiting amplifier mode, clock output enabled 8GFC,2 JTSPAT OC-192 8GFC,2 JTSPAT OC-192 8GFC,2 JTSPAT OC-192 319.1 333 7.20 7.21 22.2 35.1 359.5 377.4 8.1 8.59 28.4 47.4 mA mA mA mA mA mA Limiting amplifier mode, 8.5 Gbps Limiting amplifier mode, 9.953 Gbps Equalizer mode, 8.5 Gbps Equalizer mode, 11.3 Gbps 446.6 486.5 352 430 +85 mW mW mW mW °C OPERATING TEMPERATURE RANGE −40 1 See Figure 33. Fibre Channel Physical Interface 4 standard, FC-PI-4, Rev 8.00, May 21, 2008. When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 100 Ω differential input termination of the ADN2917 input stage. 4 This typical acquisition specification applies to all selectable reference clock frequencies in the range of 11.05 MHz to 176.8 MHz. 2 3 JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern: PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer Bandwidth (BW)1 OC-192 8GFC3 Jitter Peaking OC-192 8GFC3 Jitter Generation OC-192 8GFC3 Jitter Tolerance OC-192 Test Conditions/Comments Typ Max Unit TRANBW[2:0] = 3 OTN mode,2 TRANBW[2:0] = 1 1064 294 1242 1650 529 1676 kHz kHz kHz 20 kHz to 80 MHz 20 kHz to 80 MHz 0.014 0.004 0.024 0.021 dB dB Unfiltered Unfiltered Unfiltered Unfiltered TRANBW[2:0] = 4 (default) 2000 Hz 20 kHz 400 kHz 4 MHz 80 MHz 0.0045 0.076 0.005 0.044 0.0067 UI rms UI p-p UI rms UI p-p Rev. C | Page 4 of 32 Min 0.36 0.28 4255 106 3.78 0.50 0.43 UI p-p UI p-p UI p-p UI p-p UI p-p Data Sheet Parameter 8GFC,3 JTSPAT Sinusoidal Jitter at 340 kHz Sinusoidal Jitter at 5.098 MHz Sinusoidal Jitter at 80 MHz Rx Jitter Tracking Test4 ADN2917 Test Conditions/Comments Min Typ Max Unit 6.7 0.53 0.59 UI p-p UI p-p UI p-p